1

CHAPTER 1 INTRODUCTION 1.1 FAST FOURIER TRANSFORM

A Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Transform (DFT) and its inverse. There are many distinct FFT algorithms involving a wide range of mathematics, from simple complex-num er arithmetic to group theory and num er theory. The fast Fourier Transform is a highly efficient procedure for computing the DFT of a finite series and re!uires less num er of computations than that of direct evaluation of DFT. "t reduces the computations y ta#ing advantage of the fact that the calculation of the coefficients of the DFT can e carried out iteratively. Due to this, FFT computation techni!ue is used in digital spectral analysis, filter simulation, autocorrelation and pattern recognition. The FFT is ased on decomposition and rea#ing the transform into smaller transforms and com ining them to get the total transform. FFT reduces the computation time re!uired to compute a discrete Fourier transform and improves the performance y a factor of $%% or more over direct evaluation of the DFT.

A DFT decomposes a se!uence of values into components of different fre!uencies. This operation is useful in many fields ut computing it directly from the definition is often too slow to e practical. An FFT is a way to compute the same result more !uic#ly& computing a DFT of N points in the o vious way, using the definition, ta#es '( () ) arithmetical operations, while an FFT can compute the same result in only '(N log N) operations.

The difference in speed can e su stantial, especially for long data sets where N may e in the thousands or millions*in practice, the computation time can e reduced y

2
several orders of magnitude in such cases, and the improvement is roughly proportional to N +log (N). This huge improvement made many DFT- ased algorithms practical. FFT,s are of great importance to a wide variety of applications, from digital signal processing and solving partial differential e!uations to algorithms for !uic# multiplication of large integers.

The most well #nown FFT algorithms depend upon the factori-ation of N, ut there are FFT with ' (N log N) complexity for all N, even for prime N. .any FFT algorithms only depend on the fact that is an N th primitive root of unity, and thus can e applied to analogous transforms over any finite field, such as num er-theoretic transforms. The Fast Fourier Transform algorithm exploit the two asic properties of the twiddle factor - the symmetry property and periodicity property which reduces the num er of complex multiplications re!uired to perform DFT. FFT algorithms are ased on the fundamental principle of decomposing the

computation of discrete Fourier Transform of a se!uence of length ( into successively smaller discrete Fourier transforms. There are asically two classes of FFT algorithms. A) Decimation "n Time (D"T) algorithm /) Decimation "n Fre!uency (D"F) algorithm. "n decimation-in-time, the se!uence for which we need the DFT is successively divided into smaller se!uences and the DFTs of these su se!uences are com ined in a certain pattern to o tain the re!uired DFT of the entire se!uence. "n the decimation-infre!uency approach, the fre!uency samples of the DFT are decomposed into smaller and smaller su se!uences in a similar manner. The num er of complex multiplication and addition operations re!uired y the simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier Transform ("DFT) is of order N) as there are N data points to calculate, each of which re!uires N complex arithmetic operations.

The discrete Fourier transform (DFT) is defined y the formula&

N $ X (K ) = x(n) e n=%
1here 2 is an integer ranging from % to N 3 $.

j )nK N 0

The algorithmic complexity of DFT will '(N)) and hence is not a very efficient method. "f we can4t do any etter than this then the DFT will not e very useful for the ma5ority of practical D67 application. 8owever, there are a num er of different 4Fast Fourier Transform4 (FFT) algorithms that ena le the calculation the Fourier transform of a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic# calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm which reduces the num er of computations needed for N points from '(N 2) to '(N log N) where log is the 9sinc, function (sin x) + x. The :adix-) D"T algorithm rearranges the DFT of the function xn into two parts& a sum over the even-num ered indices n ; )m and a sum over the odd-num ered indices n ; )m < $& ase-) logarithm. "f the function to e transformed is not harmonically related to the sampling fre!uency, the response of an FFT loo#s li#e a

4
'ne can factor a common multiplier out of the second sum in the

e!uation. "t is the two sums are the DFT of the even-indexed part x)m and the DFT of

odd-indexed part x)m < $ of the function xn. Denote the DFT of the Even-indexed inputs x)m y Ek and the DFT of the Odd-indexed inputs x)m < $ y Ok and we o tain&

8owever, these smaller DFTs have a length of N+), so we need compute only N+) outputs& than#s to the periodicity properties of the DFT, the outputs for (+) = # = ( from a DFT of length N+) are identical to the outputs for %= # = (+). That is, Ek < N + ) ; Ek and Ok < N + ) ; Ok. The phase factor exp> 3 )?ik + N@ called a twiddle factor which o eys the relation& exp> 3 )?i(k < N + )) + N@ ; e 3 ?iexp> 3 )?ik + N@ ; 3 exp> 3 )?ik + N@, flipping the sign of the Ok < N + ) terms. Thus, the whole DFT can e calculated as follows&

This result, expressing the DFT of length N recursively in terms of two DFTs of si-e N+), is the core of the radix-) D"T fast Fourier transform. The algorithm gains its speed y re-using the results of intermediate computations to compute multiple DFT outputs. (ote that final outputs are o tained y a <+3 com ination of Ek and Okexp( 3 )?ik + N), which is simply a si-e-) DFT0 when this is generali-ed to larger radices elow, the si-e-) DFT is replaced y a larger DFT (which itself can e evaluated with an FFT).

5
This process is an example of the general techni!ue of divide and con!uers algorithms. "n many traditional implementations, however, the explicit recursion is avoided, and instead one traverses the computational tree in readth-first fashion.

Fig 1.1 Decimation In Time FFT "n the D"T algorithm, the twiddle multiplication is performed efore the utterfly stage whereas for the D"F algorithm, the twiddle multiplication comes after the /utterfly stage.

Fig 1.2 : Decimation In Freq enc! FFT

The 4:adix )4 algorithms are useful if N is a regular power of ) (N;)p). "f we assume that algorithmic complexity provides a direct measure of execution time and that the relevant logarithm ase is ) then as shown in ta le $.$, ratio of execution times for the (DFT) vs. (:adix ) FFT) increases tremendously with increase in (.

6
The term 4FFT4 is actually slightly am iguous, ecause there are several

commonly used 4FFT4 algorithms. There are two different :adix ) algorithms, the socalled 4Decimation in Time4 (D"T) and 4Decimation in Fre!uency4 (D"F) algorithms. /oth of these rely on the recursive decomposition of an N point transform into ) (N+)) point transforms. (um er of 7oints, ( B D $C F) CB $)D Aomplex .ultiplications in Direct computations, () $C CB )EC $%)B B%GC $CFDB Aomplex .ultiplication in FFT Algorithm, ((+)) log) ( B $) F) D% $G) BBD 6peed improvement Factor B.% E.F D.% $).D )$.F FC.C

Ta"#e 1.1: Com$ari%on o& E'ec tion Time%( DFT ) Ra*i' + 2 FFT

1.2 ,UTTERF-. STRUCTURES FOR FFT

/asically FFT algorithms are developed y means of divide and con!uer method, the is depending on the decomposition of an ( point DFT in to smaller DFT,s. "f ( is factored as ( ; r$,r),rF ..rH where r$;r);I;rH;r, then rH ;(. where r is called as :adix of FFFt algorithm. "f r; ), then if is called as radix-) FFT algorithm,. The asic DFT is of si-e of ). The ( point DFT is decimated into ) point DFT y two ways such as Decimation "n Time (D"T) and Decimation "n Fre!uency (D"F) algorithm. /oth the algorithm ta#e the advantage of periodicity and symmetry property of the twiddle factor.
W nK =e N j )nK N

The radix-) decimation-in-fre!uency FFT is an important algorithm o tained y the divide and con!uers approach. The Fig. $.) elow shows the first stage of the D-point

7
D"F algorithm.

Fig. 1.1: Fir%t Stage o& / $oint Decimation in Freq enc! A#gorit0m. The decimation, however, causes shuffling in data. The entire process involves v ; log) N stages of decimation, where each stage involves N+) utterflies of the type shown in the Fig. $.F.

Fig. 1.1: , tter&#! Sc0eme.

j )nk N

8ere

k =e Wn

is the Twiddle factor.

Aonse!uently, the computation of (-point DFT via this algorithm re!uires (N+)) log) N complex multiplications. For illustrative purposes, the eight-point decimation-in fre!uency algorithm is shown in the Figure elow. 1e o serve, as previously stated, that the output se!uence occurs in it-reversed order with respect to the input. Furthermore, if we a andon the re!uirement that the computations occur in place, it is also possi le to have oth the input and output in normal order. The D point Decimation "n fre!uency algorithm is shown in Fig $.E.

Fig. 1.2: / $oint Decimation in Freq enc! A#gorit0m

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CHAPTER 2 CHAPTER 2 HARD3ATE DESCRIPTION -AN4UA4E 2.1 INTRODUCTION

8ardware Description Hanguage (8DH) is a language that can descri e the ehavior and structure of electronic system, ut it is particularly suited as a language to descri e the structure and the ehavior of the digital electronic hardware design, such as A6"As and F7JAs as well as conventional circuits. 8DH can e used to descri e electronic hardware at many different levels of a straction such as Algorithm, :egister transfer level (:TH) and Jate level. Algorithm is un synthesi-a le, :TH is the input to the synthesis, and Jate Hevel is the input from the synthesis. "t is often reported that a large num er of A6"A designs meet their specification first time, ut fail to wor# when plunged into a system. 8DH allows this issue to e addressed in two ways, a 8DH specification can e executed in order to achieve a high level of confidence in its correctness efore commencing design and may simulate one specification for a part in the wider system context(Kg&- 7rinted Aircuited /oard 6imulation). This depends upon how accurately the speciali-ation handles aspects such as timing and initiali-ation.

2.2 AD5ANTA4ES OF HDA design methodology that uses 8DHs has several fundamental advantages over traditional Jate Hevel Design .ethodology. The following are some of the advantages&

'ne can verify functionality early in the design process and immediately simulate
the design written as a 8DH description. Design simulation at this high level, efore implementation at the Jate Hevel allows testing architectural and designing decisions.

11 F7JA synthesis provides logic synthesis and optimi-ation, so one can

automatically convert a L8DH description to gate level implementation in a given technology. 8DH descriptions provide technology independent documentation of a design and its functionality. A 8DH description is more easily read and understood than a net-list or schematic description. 8DHs typically support a mixed level description where structural or net-list constructs can e mixed with ehavioral or algorithmic descriptions. 1ith this mixed level capa ilities one can descri e system architectures at a high level or gate level implementation.

2.6 5HDL8DH is a hardware description language. "t descri es the attained. ehavior of an e

electronic circuit or system, from which the physical circuit or system can then

L8DH stands for L86"A 8ardware Description Hanguage. L86"A is itself an a reviation for Lery 8igh 6peed "ntegrated Aircuits, an initiative funded y Mnited 6tates Department of Defense in the $GD%s that led to creation of L8DH. "ts first version was L8DH DN, later upgraded to the L8DH GF. L8DH was the original and first hardware description language to e standardi-ed y "nstitute of Klectrical and Klectronics Kngineers, through the "KKK $%NC standards. An additional standard, the "KKK $$CB, was later added to introduce a multi-valued logic system.

L8DH is intended for circuit synthesis as well as circuit simulation. 8owever, though L8DH is fully simulata le, not all constructs are synthesi-a le. The two main immediate applications of L8DH are in the field of 7rogramma le Hogic Devices and in the field of A6"As (Application 6pecific "ntegrated Aircuits). 'nce the L8DH code has een written, it can e used either to implement the circuit in a programma le device or

12
can e su mitted to a foundry for fa rication of an A6"A chip.

L8DH is a fairly general-purpose language, and it doesn4t re!uire a simulator on which to run the code. There are many L8DH compilers, which uild executa le inaries. "t can read and write files on the host computer, so a L8DH program can e written that generates another L8DH program to e incorporated in the design eing developed. /ecause of this general-purpose nature, it is possi le to use L8DH to write a test bench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected.

The #ey advantage of L8DH when used for systems design is that it allows the ehavior of the re!uired system to e descri ed (modeled) and verified (simulated) efore synthesis tools translate the design into real hardware (gates and wires). The L8DH statements are inherently concurrent and the statements placed in a 7:'AK66, FM(AT"'( or 7:'AKDM:K are executed se!uentially.

2.1 EDA Too#%

There are several KDA (Klectronic Design Automation) tool availa le for circuit synthesis, implementation and simulation using L8DH. 6ome tools are offered as part of a vendor,s design suite such as Altera,s Ouatus "" which allows the synthesis of L8DH code onto Altera,s A7HD+F7JA chips, or Pilinx,s "6K suite, for Pilinx,s A7HD+F7JA chips. "6KQ WebPACK design software is the industryRs only F:KK, fully featured front-toac# F7JA design solution for Hinux, 1indows P7, and 1indows Lista. "6K WebPACK is the ideal downloada le solution for F7JA and A7HD design offering 8DH synthesis and simulation, implementation, device fitting, and STAJ programming. "6K WebPACK delivers a complete, front-to- ac# design flow providing instant access to the "6K features and functionality at no cost. Pilinx has created a solution that allows convenient productivity y providing a design solution that is always up to date with error-free downloading and single file installation.

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CHAPTER 6 DESI4N OF FFT 6.1 IMP-EMENTATION OF 178POINT FFT ,-OC9S

The FFT computation is accomplished in three stages. The x(%) until x($E) varia les are denoted as the input values for FFT computation and P(%) until P($E) are denoted as the outputs. The pipeline architecture of the $C point FFT is shown in Fig B.$ consisting of utterfly schemes in it. There are two operations to complete the computation in each stage.

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Fig 6.1: Arc0itect re o& 17 $oint FFT. The upward arrow will execute addition operation while downward arrow will execute su traction operation. The su tracted value is multiplied with twiddle factor value efore eing processed into the next stage. This operation is done concurrently and is #nown as utterfly process. The implementation of FFT flow graph in the L8DH re!uires three stages, final computation is done and the result is sent to the varia le T (%) to T ($E). K!uation in each stage is used to construct scheduling diagram.

15

For stage one, computation is accomplished in three cloc# cycles denoted as 6% to 6).The operation is much simpler compared with FFT. This is ecause FFT processed oth real and imaginary value. The result from FFT is represented in real and imaginary value ecause of the multiplication of twiddle factor. Twiddle factor is a constant defined y the num er of point used in this transform. This scheduling diagram is derived from the e!uations o tain in FFT signal flow graph. The rest of the scheduling diagrams can e s#etched in the same way as shown in figure B.). Thus each stage re!uires a cloc# cycle and totally three cloc# cycles are needed. 6cheduling diagrams are a part of ehavioral modeling and 6ynthesis steps to translate the algorithmic description into :TH (register transfer level) in L8DH design.

6.2 DESI4N OF A 4ENERA- RADI:82 FFT USIN4 5HDAs we move to higher-point FFTs, the structure for computing the FFT ecomes more complex and the need for an efficient complex multiplier to e incorporated within the utterfly structure arises. 8ence we propose an algorithm for an efficient complex multiplier that overcomes the complication of using complex num ers throughout the process. A radix-) FFT can e efficiently implemented using a utterfly processor which includes, esides the utterfly itself, an additional complex multiplier for the twiddle factors. A radix-) utterfly processor consists of a complex adder, a complex su traction, and a complex multiplier for the twiddle factors. The complex multiplication with the twiddle factor is often implemented with four real multiplications and ) add + su tract operations. Norma# Com$#e' O$eration: (P<5T) (A< 56) ; AP < 56P < 5AT - T6 ; AP U T6 < 5 (6P < AT)

16
:eal 7art : ; AP U T6 "maginary 7art " ; 6P < AT Msing the twiddle factor multiplier that has een developed, it is possi le to design a utterfly processor for a radix-) Aooley-Tu#ey FFT. 8ence this asic structure of radix-) FFT can e used as a uilding loc# to construct higher (-point FFTs. This structure has een developed as an extension to provide for the computation of higher value index FFTs.

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CHAPTER 1 5HD- IMP-EMENTATION

1.1 DESI4N SOFT3ARE The implementations have een carried out using the software, Pilinx "6K G.)i. The hardware language used is the Lery 8igh 6peed "ntegrated Aircuit 8ardware Description Hanguage (L8DH). L8DH is a widely used language for register transfer level description of hardware. "t is used for design entry, compile and simulation of digital systems. 1.2 INTERFACE The architectural design consist of data inputs, control unit, cloc#s and the data output. The register may e of the array of four or eight varia le in the type of real. The FFT implementation in L8DH consists of three states such as start, load and run.

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1.6 De%ign S mmar!

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CHAPTER 2 RESU-TS
The simulation of this whole pro5ect has een done using the Pilinx "6K of version G.)i. Pilinx "6K is a simulation tool for programming VLH6"W VA6"AWs, VF7JAWs, VA7HDWs, and V6oAWs. "t provides a comprehensive simulation and de ug environment for complex A6"A and F7JA designs. 6upport is provided for multiple languages including Lerilog, 6ystemLerilog, L8DH and 6ystemA. 2.1 SIMU-ATION RESU-T O,TAINED

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21

CHAPTER 7 CONC-USION AND FUTURE SCOPE

7.1. CONC-USION This pro5ect descri es the efficient use of L8DH code for the implementation of radix ) ased FFT architecture and the wave form result of the various stages has een o tained successfully. The accuracy in o tained results has een increased with the help of efficient coding in L8DH. The accuracy in results depends upon the e!uations o tained from the utterfly diagram and then on the correct drawing of scheduling diagrams ased on these e!uations. 7.2. FUTURE SCOPE The future scopes of this pro5ect are to implement the proposed FFT architecture using Field-7rogramma le Jate Arrays (F7JAs).

The FFT (Fast Fourier Transform) processor plays a critical part in speed and power consumption of the 'rthogonal Fre!uency Division .ultiplexing ('FD.) communication system. Thus the FFT loc# can e implemented in 'FD..

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CHAPTER ; 5HD- CODE

To$ rt# + %!nt0<main.=0*
library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity synth_main is port ( data_io : in std_logic_vector(31 downto !; "inal_op : out std_logic_vector(31 downto ! ; clock_main#clock#enbl#reset#init : in std_logic! ; end synth_main ; architecture rtl o" synth_main is signal sh"t # waves : std_logic_vector(3 downto ! ;

component subtractor port ( a : in std_logic_vector (31 downto ! ; b : in std_logic_vector (31 downto ! ; clock # rst_sub # sub_en : in std_logic ; a_smaller # "in_sub # num_$ero : out std_logic ; $ero_detect : out std_logic_vector(1 downto ! ; sub : out std_logic_vector (% downto !; change : out std_logic ! ; end component ; component swap port ( a : in std_logic_vector (31 downto ! ; b : in std_logic_vector (31 downto ! ; clock : in std_logic ; rst_swap # en_swap : in std_logic ; "inish_swap : out std_logic ; d : out std_logic_vector (31 downto ! ; large_e&p : out std_logic_vector (' downto ! ; c : out std_logic_vector (3( downto ! ! ; end component ; component shi"t( port ( sub_control : in std_logic_vector (% downto c_in : in std_logic_vector (3( downto ! ;

! ;

23
shi"t_out : out std_logic_vector (31 downto ! ; clock # shi"t_en # rst_shi"t : in std_logic ; "inish_out : out std_logic ! ; end component ; component control_main port ( a_small # sign_a # sign_out # add_sub en_sub # en_swap # std_logic ; "in_sub # "in_swap in std_logic ; clock_main # clock std_logic ! ; end component ;

sign_b : in std_logic ; # reset_all : out std_logic ; en_shi"t # addpulse # normalise : out # "inish_shi"t # add_"inish # end_all : # reset # enbl # $ero_num # change : in

component summer port ( num1 # num( : in std_logic_vector (31 downto ! ; e&p : in std_logic_vector (' downto ! ; addpulse_in # addsub # rst_sum : in std_logic ; add_"inish : out std_logic ; sumout : out std_logic_vector ( 3( downto ! ! ; end component ; component normali$e port ( a # b : in std_logic_vector (31 downto ! ; numb : in std_logic_vector (3( downto ! ; e&p : in std_logic_vector (' downto ! ; signbit # addsub # clock # en_norm # rst_norm : in std_logic ; $ero_detect : in std_logic_vector(1 downto ! ; e&it_n : out std_logic ; normal_sum : out std_logic_vector (31 downto ! ! ; end component ; component but_gen port ( add_incr # add_clear # stagedone : in std_logic ; but_butter"ly : out std_logic_vector(3 downto ! ! ; end component ; component stage_gen port ( add_staged # add_clear : in std_logic ; st_stage : out std_logic_vector(1 downto end component ; component iod_staged is port (

! ! ;

24
but_"ly : in std_logic_vector(3 downto ! ; stage_no : in std_logic_vector(1 downto ! ; add_incr # io_mode : in std_logic ; add_iod # add_staged # add_""td : out std_logic ; butter"ly_iod : out std_logic_vector(3 downto ! ! ; end component ; component baseinde& port ( ind_butter"ly : in std_logic_vector(3 downto ! ; ind_stage : in std_logic_vector(1 downto ! ; add_""t : in std_logic ; ""tadd_rd : out std_logic_vector(3 downto ! ; c # c1 # c( # c3 : in std_logic ! ; end component ; component ioadd_gen port ( io_butter"ly : in std_logic_vector(3 downto ! ; add_iomode # add_ip # add_op : in std_logic ; base_ioadd : out std_logic_vector(3 downto ! ! ; end component ; component mu&_add port ( a # b : in std_logic_vector(3 downto ! ; sel : in std_logic ; ) : out std_logic_vector(3 downto ! ! ; end component ; component ram_shi"t port ( data_in : in std_logic_vector(3 downto ! ; clock_main : in std_logic ; data_out : out std_logic_vector(3 downto ! ! ; end component ; component cycles port ( clock_main # preset # c _en # cycles_clear : in std_logic ; waves : out std_logic_vector(3 downto ! ! ; end component ; component counter port ( c : out std_logic_vector(( downto ! ; disable # clock_main # reset : in std_logic! ; end component ; component mult_clock port (

25
clock_main # mult1_c # mult1_iomode # mult_clear : in std_logic ; mult1_addincr : out std_logic ! ; end component ; component cont_gen port ( con_staged # con_iod # con_""td # con_init : in std_logic ; con_ip # con_op # con_iomode # con_""t : out std_logic ; con_enbw # con_enbor # c _enable # con_preset : out std_logic ; con_clear # disable : out std_logic ; c # clock_main : in std_logic ; en_rom # en_romgen # reset_counter : out std_logic ; con_clkcount : in std_logic_vector(( downto ! ! ; end component ; component and_gates port ( waves_and : in std_logic_vector(3 downto ! ; clock_main # c _en : in std_logic ; c #c1#c(#c3 : out std_logic ; c _c1#c(_c3#c _c(#c1_c3 : out std_logic ! ; end component ; component r_block port ( data : in std_logic_vector(31 downto ! ; trigger : in std_logic ; r_out : out std_logic_vector(31 downto ! ! ; end component ; component l_block port ( data_l : in std_logic_vector(31 downto trigger_l : in std_logic ; l_out : out std_logic_vector(31 downto end component ;

! ; ! ! ;

component level_edge port ( data_edge : in std_logic_vector(31 downto trigger_edge : in std_logic ; edge_out : out std_logic_vector(31 downto end component ;

! ; ! ! ;

component mu& port ( d # d1 : in std_logic_vector(31 downto ! ; mu&_out : out std_logic_vector(31 downto ! ; choose : in std_logic ! ; end component ;

26

component negate port ( neg_in : in std_logic_vector(31 downto ! ; neg_en # clock_main : in std_logic ; neg_out : out std_logic_vector(31 downto ! ! ; end component ; component multiply port( num_mu& # num_rom : in std_logic_vector(31 downto clock : in std_logic ; mult_out : out std_logic_vector(31 downto ! ! ; end component ; component divide port ( data_in : in std_logic_vector(31 downto ! ; data_out : out std_logic_vector(31 downto ! ! ; end component ; component romadd_gen is port ( io_rom#c #c1#c(#c3 : in std_logic ; stage_rom : in std_logic_vector(1 downto ! ; butter"ly_rom : in std_logic_vector(3 downto ! ; romadd : out std_logic_vector(( downto ! ; romgen_en : in std_logic !; end component ; component reg_dpram is port ( data_""t # data_io : in std_logic_vector (31 downto ) : out std_logic_vector (31 downto !; clock # io_mode : in std_logic; we # re : in std_logic; waddress: in std_logic_vector (3 downto !; raddress: in std_logic_vector (3 downto !!; end component ; component rom is port ( clock # en_rom : in std_logic ; romadd : in std_logic_vector(( downto ! ; rom_data : out std_logic_vector(31 downto ! ! ; end component ; *+,-+./.0 print_result is -+10( clock : 2. std_logic; op : 2. std_logic; "in_res : +30 std_logic_vector(31 downto

! ;

!;

!;

27
result : 2. std_logic_vector(31 downto end component ; begin result: print_result port map (clock_main# op#"inal_op#ram_data !; but : but_gen port map (incr # clear # staged #butter"ly_iod! ; stg : stage_gen port map (staged # clear # stage! ; iod_stgd : iod_staged port map(butter"ly_iod#stage#incr#io_mode#iod#staged#""td#butter"ly! ; base : baseinde& port map (butter"ly # stage # ""t_en # ""tadd_rd # c # c1 # c( # c3! ; ioadd : ioadd_gen port map (butter"ly # io_mode # ip # op # io_add! ; ram_shi"t1 : ram_shi"t port map (""tadd_rd # clock_main # shi"t1! ; ram_shi"t( : ram_shi"t port map (shi"t1 # clock_main # sh"t! ; ram_shi"t3 : ram_shi"t port map (sh"t # clock_main # shi"t3! ; ram_shi"t4 : ram_shi"t port map (shi"t3 # clock_main #shi"t4! ; ram_shi"t4 : ram_shi"t port map (shi"t4 # clock_main # shi"t4! ; 55ram_shi"t6 : ram_shi"t port map (shi"t4 # clock_main # shi"t6! ; mult&1 : mu&_add port map (shi"t4 # io_add # io_mode # ram_wr! ; mult&( : mu&_add port map (""tadd_rd # io_add # io_mode # ram_rd! ; cyc : cycles port map (clock_main # preset # c _en # cyc_clear # waves! ; gates : and_gates port map(waves#clock_main#c _en#c #c1#c(#c3#c _c1#c(_c3#c _c(#c1_c3! ; cnt : counter port map (clk_count # disable # clock_main # reset_count! ; mu&_clock : mult_clock port map (clock_main # c # io_mode # clear # incr! ; control : cont_gen port map (staged # iod # ""td # init # ip # op # io_mode # ""t_en # enbw # enbor # c _en # preset # clear # disable # c # clock_main #rom_en#romgen_en#reset_count#clk_count! ; reg_ram : reg_dpram port map (out_data#data_io#ram_data#clock_main#io_mode#enbw#enbor#ram_wr#r am_rd! ; "1 "( "3 "4 "4 "6 "' "% "6 : : : : : : : : : r_block l_block r_block r_block r_block l_block l_block l_block r_block port port port port port port port port port map map map map map map map map map (ram_data # c # d(! ; (ram_data # c1 # d3! ; (ram_data # c( # d4! ; (ram_data # c3 # d4! ; (d% # c1_c3 # d6! ; (d% # c _c( # d1 ! ; (d1( # c3 # d13! ; (d1( # c1 # d14! ; (d1' # clock_main # d1%! ; !!;

28
"1 : r_block port map (data_rom # clock_main # rom_""! ; mu&1 : mu& port map (d( # d3 # d6 # c(_c3! ; mu&( : mu& port map (d4 # d4 # d' # c1_c3! ; mu&3 : mu& port map (d13 # d14 # d14 # c1_c3! ; neg1 : negate port map (d1 # c _c1 #clock_main # d11! ; neg( : negate port map (d14 # c _c1 #clock_main # d16! ; mult1 : multiply port map (d6 # rom_"" # clock_main # d%! ; div : divide port map (d1% # d16! ; "11 : level_edge port map (d16#clock_main#out_data! ; rom_add1 : romadd_gen port map (io_mode#c #c1#c(#c3#stage#butter"ly#rom_add#romgen_en! ; rom1 : rom port map (clock #rom_en#rom_add#data_rom! ; b11 : subtractor port map ( d16 # d' # clock # rstb # ensubb # a_smallb # "insubb # num$erob # $erodetectb # subb # changeb! ; b( : swap port map ( a78d16 # b78d' # clock78clock # rst_swap78rstb # en_swap78enswapb # "inish_swap78"inswapb # d78swap_num(b # large_e&p78e&pb # c78swap_num1b ! ; b4 : shi"t( port map (sub_control78subb # c_in78swap_num1b # shi"t_out78shi"t_outb # clock78clock # shi"t_en78enshi"tb# rst_shi"t78rstb # "inish_out78"inshi"tb ! ; b4 : control_main port map ( a_smallb # d16(31! # d'(31! # signbitb # addsubb # rstb # ensubb # enswapb # enshi"tb # addpulseb # normaliseb # "insubb # "inswapb # "inshi"tb #"inish_sumb # end_allb # clock_main # clock # reset # enbl # num$erob # changeb ! ; b6 : summer port map ( shi"t_outb # swap_num(b # e&pb # addpulseb # addsubb # rstb # "inish_sumb # sum_outb ! ; b' : normali$e port map (d16 # d' # sum_outb # e&pb # signbitb # addsubb # clock # normaliseb # rstb # $erodetectb # end_allb # d1'! ; a1 : subtractor port map ( d6 # d11 # clock # rst # ensub # a_small # "insub # num$ero # $erodetect # suba # changea! ; a( : swap port map (d6 #d11 #clock #rst #enswap # "inswap #swap_num( # e&p # swap_num1 ! ; a4 : shi"t( port map (suba #swap_num1 #shi"t_outa #clock # enshi"t # rst # "inshi"t ! ; a4 : control_main port map ( a_small # d6(31! # d11(31! # signbit # addsub # rst # ensub # enswap # enshi"t # addpulse # normalise # "insub # "inswap # "inshi"t #"inish_sum # end_all # clock_main # clock # reset # enbl # num$ero # changea ! ; a6 : summer port map ( shi"t_outa # swap_num( # e&p # addpulse # addsub # rst # "inish_sum # sum_out ! ; a' : normali$e port map (d6 # d11 # sum_out # e&p # signbit # addsub # clock # normalise # rst # $erodetect # end_all # d1(! ; end rtl ;

29
Te%t"enc0 &i#e + %!nt0<te%t.=0*
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.butter_lib.all; 39/ 2///.90:_;+<2*_0/=02+.>;;; 39/ 90:.0/=02+.>;;; /.020? tb 29 /.: tb; >1*@20/*031/ testbench_arch +A tb 29 A2;/ 1/93;09: 0/=0 +-/. B120/_,+:/ 29 Cresults.t&tC; *+,-+./.0 synth_main -+10 ( data_io : 2n std_logic_vector (31 :own0o !; "inal_op : +ut std_logic_vector (31 :own0o !; clock_main : 2n std_logic; clock : 2n std_logic; enbl : 2n std_logic; reset : 2n std_logic; init : 2n std_logic !; /.: *+,-+./.0; C C 92<.>; data_io : std_logic_vector (31 :own0o ! :7 C; 92<.>; "inal_op : std_logic_vector (31 :own0o ! :7 C; 92<.>; clock_main : std_logic :7 D D; 92<.>; clock : std_logic :7 D D; 92<.>; enbl : std_logic :7 D D; 92<.>; reset : std_logic :7 D D; 92<.>; init : std_logic :7 D D; constant constant constant constant constant constant -/12+:_clock : time :7 ( ns; :30?_*?*;/_clock : real :7 .4; +AA9/0_clock : time :7 1 ns; -/12+:_clock_main : time :7 ( ns; :30?_*?*;/_clock_main : real :7 .4; +AA9/0_clock_main : time :7 ns;

E/<2. 330 : synth_main -+10 ,>- ( data_io 78 data_io# "inal_op 78 "inal_op# clock_main 78 clock_main#

30
clock 78 clock# enbl 78 enbl# reset 78 reset# init 78 init !; process variable i : integer :7 begin "or i in 1 to 1 loop clock F7 D1D ; wait "or 4 ns ; clock F7 D D ; wait "or 4 ns ; end loop ; end process ; process variable G : integer :7 begin "or G in 1 to 1 loop clock_main F7 D1D ; wait "or ( ns ; clock_main F7 D D ; wait "or ( ns ; end loop ; end process ; ;

process "ile vector_"ile : te&t open read_mode is C<:H=ilin&6(iHproGectsHproG_""t_22Hrom_ram.vhdC ; variable l # l( : line ; variable ) # p : integer :7 ; variable count : integer ; variable t_a # t_b : std_logic_vector (31 downto ! ; variable space : character ; begin while not end"ile(vector_"ile! loop 55"or count in 1 to 16 loop ) :7 31 ; readline(vector_"ile # l(! ; "or p in 1 to 3( loop 55 data "rom 1>, read(l( # t_b()!! ; ) :7 ) 5 1 ; end loop ; ) :7 31 ; data_io F7 t_b(31 downto ! ; wait "or 4 end loop ; ns ;

31
wait "or % ms ; 55wait "or 64 ns ; end process; 55 process to reset process begin reset F7 D1D ; enbl F7 D1D ; wait "or 1 ns ; reset F7 D D ; wait ; end process ; process begin init F7 D1D wait "or 14 init F7 D D wait ; end process

; ns ; ; ;

/.: testbench_arch;

32
%>a$.=0*
55 9B>- 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity swap is port ( a : in std_logic_vector (31 downto ! ; b : in std_logic_vector (31 downto ! ; clock : in std_logic ; rst_swap # en_swap : in std_logic ; "inish_swap : out std_logic ; d : out std_logic_vector (31 downto ! ; large_e&p : out std_logic_vector (' downto ! ; c : out std_logic_vector (3( downto ! ! ; end swap ; architecture rtl o" swap is begin process (a # b # clock # rst_swap # en_swap! variable & # y : std_logic_vector (' downto ! ; variable p # ) : std_logic_vector ((( downto ! ; begin i"(rst_swap 7 D1D ! then c F7 D D I a((( downto ! I C C ; "inish_swap F7 D D ; elsi"(rst_swap 7 D D! then i"(en_swap 7 D1D! then & :7 a (3 downto (3! ; y :7 b (3 downto (3! ; p :7 a ((( downto ! ; ) :7 b ((( downto ! ; i" (clock 7 D1D! then i" (& F y! then c F7 D1D I a ((( downto ! I C C ; 55 D1D "or checking d F7 D1D I b ((( downto ! I C C ; 55 D1D "or implicit one large_e&p F7 b (3 downto (3! ; "inish_swap F7 D1D ; elsi" (y F &! then c F7 D1D I b ((( downto ! I C d F7 D1D I a ((( downto ! I C large_e&p F7 a (3 downto (3! ; "inish_swap F7 D1D ; elsi" ( (&7y! and (p F )!! then c F7 D1D I a ((( downto ! I C d F7 D1D I b ((( downto ! I C C ; C ; 55 D1D "or implicit 1.

C ; 55 D1D "or checking C ; 55 D1D "or implicit one

33
large_e&p F7 b (3 downto (3! ; "inish_swap F7 D1D ; else c F7 D1D I b ((( downto ! I C d F7 D1D I a ((( downto ! I C large_e&p F7 a (3 downto (3! ; "inish_swap F7 D1D ; end end end end end end i" ; i" ; i" ; i" ; process; rtl; C ; C ; 55 D1D "or implicit 1.

34
% mmer.=0*
55 93,,/1 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity summer is port ( num1 # num( : in std_logic_vector (31 downto ! ; e&p : in std_logic_vector (' downto ! ; addpulse_in # addsub # rst_sum : in std_logic ; add_"inish : out std_logic ; sumout : out std_logic_vector ( 3( downto ! ! ; end summer ; architecture rtl o" summer is begin process (num1 # num( # addpulse_in # rst_sum! variable temp_num1 # temp_sum # temp_num( # temp_sum( # res : std_logic_vector (3( downto !; variable temp_e&p : std_logic_vector (' downto ! ; begin i" (rst_sum 7 D D! then i" (addpulse_in 7 D1D! then temp_num1 :7 D D I num1 (31 downto ! ; 55 to "ind whether normalisation is re)uired. temp_num( :7 D D I num( (31 downto ! ; 55i" re)uired ,9E will be 1 a"ter addition i" (addsub 7 D1D! then temp_sum :7 temp_num1 J temp_num( ; sumout F7 temp_sum ; add_"inish F7 D1D ; else temp_sum :7 temp_num( 5 temp_num1 ; 55res :7 temp_sum J temp_num1 ; sumout F7 temp_sum ; add_"inish F7 D1D ; end i" ; end i" ; elsi" (rst_sum 7 D1D! then add_"inish F7 D D; end i" ; end process ; end rtl ;

35
% "tractor.=0*
55 93E01>*0+1 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity subtractor is port ( a : in std_logic_vector (31 downto ! ; b : in std_logic_vector (31 downto ! ; clock # rst_sub # sub_en : in std_logic ; a_smaller # "in_sub # num_$ero : out std_logic ; $ero_detect : out std_logic_vector(1 downto ! ; sub : out std_logic_vector (% downto ! ; change : out std_logic ! ; end subtractor ; architecture rtl o" subtractor is begin process (a # b # clock # rst_sub # sub_en! variable temp #c # d : std_logic_vector (' downto variable e # " : std_logic_vector ((( downto ! ; begin i" (rst_sub 7 D D! then c :7 a (3 downto (3! ; d :7 b (3 downto (3! ; e :7 a ((( downto ! ; " :7 b ((( downto ! ; i"(sub_en 7 D1D! then i" (clock 7 D1D! then i" ((c7 !! then $ero_detect F7 C 1C ; num_$ero F7 D1D ; elsi" ((d7 !! then $ero_detect F7 C1 C ; num_$ero F7 D1D ; elsi" (c F d ! then temp :7 d 5 c ; a_smaller F7 D1D ; sub F7 D1D I temp (' downto "in_sub F7 D1D ; $ero_detect F7 C C ; num_$ero F7 D D ; elsi" (d F c! then temp :7 c 5 d ;

! ;

! ;

36
a_smaller F7 D D ; sub F7 D1D I temp (' downto "in_sub F7 D1D ; $ero_detect F7 C C ; num_$ero F7 D D ; elsi"((c7d! and e F "! then a_smaller F7 D1D ; temp:7 c5d ; sub F7 D1D I temp (' downto "in_sub F7 D1D ; $ero_detect F7 C C ; num_$ero F7 D D ;

! ;

! ;

elsi" ((c7d! and e 8 "! then a_smaller F7 D D ; temp :7 c5d ; sub F7 D1D I temp (' downto ! ; $ero_detect F7 C C ; num_$ero F7 D D ; "in_sub F7 D1D ; elsi" ((c7d! and (e 7 "!! then temp :7 c5d ; a_smaller F7 D D ; sub F7 D1D I C C ; "in_sub F7 D1D ; $ero_detect F7 C C ; num_$ero F7 D D ; end i" ; end i" ; end i" ; elsi"(rst_sub 7 D1D! then "in_sub F7 D D ; sub F7 C C ; num_$ero F7 D D ; $ero_detect F7 C C ; end i" ; end process ; process(a # b! 55 process to identi"y when a new number comes begin change F7 transport D1D a"ter 1 ns ; change F7 transport D D a"ter 4 ns ; end process ; end rtl ;

37
%tage.=0*
55 90></ .3,E/1 </./1>0+1. library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity stage_gen is port ( add_staged # add_clear : in std_logic ; st_stage : out std_logic_vector(1 downto end stage_gen ; architecture rtl o" stage_gen is begin process(add_staged # add_clear! variable s_count : std_logic_vector(1 downto ! ; begin i" (add_clear 7 D1D! then st_stage F7 C C ; s_count :7 C C ; elsi"(add_stagedDevent and add_staged7 D1D ! then st_stage F7 s_count J 1 ; s_count :7 s_count J 1 ; end i" ; end process ; end rtl ;

! ! ;

38
%0i&t2.=0*
55 9@2A0 3.20 library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; entity shi"t( is port ( sub_control : in std_logic_vector (% downto ! ; c_in : in std_logic_vector (3( downto ! ; shi"t_out : out std_logic_vector (31 downto ! ; clock # shi"t_en # rst_shi"t : in std_logic ; "inish_out : out std_logic ! ; end shi"t( ; architecture rtl o" shi"t( is begin process(clock! variable sub_temp : std_logic_vector(' downto ! ; variable temp( # temp4 : std_logic_vector(31 downto ! ; variable temp3 # t : std_logic ; begin i"(rst_shi"t7D D! then i"(shi"t_en 7 D1D! then i"(temp3 7 D1D! then i"(sub_control(%! 7 D1D! then sub_temp :7 sub_control (' downto ! ; temp( :7 D1D I c_in (31 downto 1! ; 55D1D "or implicit one temp3 :7 D D ; end i" ; end i" ; end i" ; end i" ; i"(rst_shi"t7D D! then i"(shi"t_en 7 D1D! then i"(t 7 D1D! then i" (sub_control(%! 7 D1D! then i" (conv_integer(sub_temp(' downto !! 7 shi"t_out F7 temp( ; "inish_out F7 D1D ; t :7 D D ; elsi" ( clock 7 D1D! then temp( :7 D D I temp( (31 downto 1! ; sub_temp :7 sub_temp 5 C 1C ; end i" ; end i" ; end i" ; end i" ; elsi"(rst_shi"t7D1D! then

! then

39
temp3 :7 D1D ; "inish_out F7 D D ; t :7 D1D ; end i" ; end process ; end rtl ;

40
roma**<gen.=0*
55 >::1/99 </./1>0+1 A+1 1+, library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity romadd_gen is port ( io_rom#c #c1#c(#c3 : in std_logic ; stage_rom : in std_logic_vector(1 downto ! ; butter"ly_rom : in std_logic_vector(3 downto ! ; romadd : out std_logic_vector(( downto ! ; romgen_en : in std_logic !; end romadd_gen ; architecture rtl o" romadd_gen is begin process(io_rom#c #c1#c(#c3#stage_rom#butter"ly_rom! begin i"(romgen_en 7 D1D! then i"(io_rom 7 D D! then case stage_rom is when C C 78 i"(c 7D1D or c(7D1D! then romadd F7 C C ; elsi"(c17D1D or c37D1D! then romadd F7 C 1C ; end i" ; when C 1C 78 i"(butter"ly_rom7 or butter"ly_rom71! then i"(c 7D1D or c(7D1D! then romadd F7 C C ; elsi"(c17D1D or c37D1D! then romadd F7 C 1C ; end i" ; elsi"(butter"ly_rom7( or butter"ly_rom73! then i"(c 7D1D or c(7D1D! then romadd F7 C1 C ; elsi"(c17D1D or c37D1D! then romadd F7 C1 1C ; end i" ; end i" ; when C1 C 78 i"(butter"ly_rom7 ! then i"(c 7D1D or c(7D1D! then romadd F7 C C ; elsi"(c17D1D or c37D1D! then

41
romadd F7 C 1C ; end i" ; elsi"(butter"ly_rom71! then i"(c 7D1D or c(7D1D! then romadd F7 C1 C ; elsi"(c17D1D or c37D1D! then romadd F7 C1 1C ; end i" ; elsi"(butter"ly_rom7(! then i"(c 7D1D or c(7D1D! then romadd F7 C 1 C ; elsi"(c17D1D or c37D1D! then romadd F7 C 11C ; end i" ; elsi" (butter"ly_rom73! then i"(c 7D1D or c(7D1D! then romadd F7 C11 C ; elsi"(c17D1D or c37D1D! then romadd F7 C111C ; end i" ; end i" ; when others 78 romadd F7 C C ; end case ; end i" ; end i" ; end process ; end rtl ;

42
rom.=0*
55 1+, 0+ 90+1/ 92./ >.: *+92./ K>;3/9 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity rom is port ( clock # en_rom : in std_logic ; romadd : in std_logic_vector(( downto ! ; rom_data : out std_logic_vector(31 downto ! ! ; end rom ; architecture rtl o" rom is begin process(clock#en_rom! begin i"(en_rom 7 D1D! then i"(clock 7 D1D! then case romadd is when C C 78 rom_data F7 C 1111111 when C 1C 78 rom_data F7 C when C 1 C 78 rom_data F7 C 111111 11 when C 11C 78 rom_data F7 C 111111 11 when C1 C 78 rom_data F7 C when C1 1C 78 rom_data F7 C 1111111 when C11 C 78 rom_data F7 C1 111111 11 when C111C 78 rom_data F7 C 111111 11 when others 78 rom_data F7 C 1 end case ; end i" ; end i" ; end process ; end rtl ;

C ; C ; 1 1 1 1 1 1 1 1 1C ; 1C ; C ; C ; 1 1 1 1 1 1 1 1 1C 1C ; C ; ;

43
r"#oc?.=0*
55 ./<>02K/ /:</ 012<</1/: A;2- A;+-9 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity r_block is port ( data : in std_logic_vector(31 downto ! ; trigger : in std_logic ; r_out : out std_logic_vector(31 downto ! ! ; end r_block ; architecture rtl o" r_block is begin process(data # trigger! begin i" (trigger7D D and triggerDevent! then r_out F7 data(31 downto ! ; end i" ; end process ; end rtl ;

44
ram<%0i&t.=0*
55 ->1>;;/ 2. ->1>;;/; +30 9@2A0/1 2. 0@/ >::1/99 </./1>02+. 3.20. 55 1/L321/: E/*>39/ AA0 29 *+,-30/: +. :>0> >.: B1200/. E>*M 2.0+ 0@/ 9>,/ 55 ;+*>02+. >A0/1 4 *?*;/9. 9+ 0@/ 1/>: >::1/99 29 9@2A0/: 0@1+3<@ 4 *?*;/9 55 >.: <2K/. >9 B120/ >::1/99. library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity ram_shi"t is port ( data_in : in std_logic_vector(3 downto ! ; clock_main : in std_logic ; data_out : out std_logic_vector(3 downto ! ! ; end ram_shi"t ; architecture rtl o" ram_shi"t is begin process(clock_main # data_in! begin i" (clock_mainDevent and clock_main 7 D D! then data_out F7 data_in(3 downto ! ; end i" ; end process ; end rtl ;

45
ram.=0*
55 Eehavioral description o" dual5port 91>, with : 55 >ctive @igh write enable (B/! 55 >ctive @igh read enable (1/! 55 1ising clock edge (*lock! library ieee; use ieee.std_logic_1164.all; use 2///.std_logic_arith.all; use 2///.std_logic_unsigned.all; use work.butter_lib.all ; entity reg_dpram is port ( data_""t # data_io : in std_logic_vector (31 downto ) : out std_logic_vector (31 downto !; clock # io_mode : in std_logic; we # re : in std_logic; waddress: in std_logic_vector (3 downto !; raddress: in std_logic_vector (3 downto !!; end reg_dpram; architecture behav o" reg_dpram is type ,/, is array ( to 14! o" std_logic_vector(31 downto signal ram0mp : ,/,; begin 55 Brite Aunctional 9ection process (clock#waddress#we! begin i" (clock7D D! then i" (we 7 D1D! then i" (io_mode 7 D D! then ram0mp (conv_integer (waddress!! F7 data_""t ; elsi" (io_mode 7 D1D! then ram0mp (conv_integer (waddress!! F7 data_io ; end i" ; end i" ; end i" ; end process ; 55 1ead Aunctional 9ection process (clock#raddress#re! begin i" (clock7D1D! then i" (re 7 D1D! then ) F7 ram0mp(conv_integer (raddress!! ; end i"; end i"; end process; end behav;

!;

!;

46
$rint.=0*
55 39/: 0+ -12.0 0@/ 1/93;09 2. > ./>0 A+1,>0. .+0 9?.0@/929>E;/. 55 39/: +.;? A+1 92,3;>02+. -31-+9/. library ieee ; use ieee.std_logic_1164.all ; use std.te&tio.all ; use work.butter_lib.all ; use ieee.std_logic_te&tio.all ; use ieee.std_logic_unsigned.all ; use 2///.math_real.all; use 2///.std_logic_arith.all; use work.t&t_util.all; entity print_result port (clock#op : in "in_res : +30 result : end print_result ; is std_logic ; std_logic_vector(31 downto !; in std_logic_vector(31 downto !!;

architecture rtl o" print_result is "ile vectorw_"ile : te&t open write_mode is C<:H=ilin&6(iHproGectsHproG_""t_22Hresult.t&tC ; begin process(op#clock! variable l # l( : line ; variable ) # p : integer :7 ; variable count : integer :7 1 ; begin i" (op 7 D1D! then i" (count F 1'! then i"(clock7D D and clockDevent! then ) :7 31 ; count :7 count J 1 ; "or p in 1 to 3( loop 55 data "rom 1>, 55write(l( # result(p!! ; ) :7 ) 5 1 ; end loop ; ) :7 31 ; 55writeline(vectorw_"ile # l(! ; end i" ; end i" ; end i" ; end process ; end rtl ;

47
o t<re% #t.=0*
55 +30-30 1/93;09. 9?.0@/929>E;/ library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity print_result is -+10( clock : 2. std_logic; op : 2. std_logic; "in_res : +30 std_logic_vector(31 downto !; result : 2. std_logic_vector(31 downto !!; end print_result ; architecture rtl o" print_result is begin process(op#clock! variable count : integer :7 1 ; begin i" (op 7 D1D! then i" (count F 1'! then i"(clock7D D and clockDevent! then "in_res F7 result ; count :7 count J 1 ; end i" ; end i" ; end i" ; end process ; end rtl ;

48
norma#i@e.=0*
library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; use ieee.std_logic_arith.all ; use std.te&tio.all ; use ieee.std_logic_te&tio.all ; use ieee.std_logic_unsigned.all ; entity normali$e is port ( a # b : in std_logic_vector (31 downto ! ; numb : in std_logic_vector (3( downto ! ; e&p : in std_logic_vector (' downto ! ; signbit # addsub # clock # en_norm # rst_norm : in std_logic ; $ero_detect : in std_logic_vector(1 downto ! ; e&it_n : out std_logic ; normal_sum : out std_logic_vector (31 downto ! ! ; end normali$e ; architecture rtl o" normali$e is begin process (clock! variable numb_temp : std_logic_vector (31 downto ! ; variable temp_e&p : std_logic_vector (' downto ! ; variable t # t( : std_logic :7 D1D ; begin i" (rst_norm 7 D D! then i" (en_norm 7 D1D! then i" (t 7 D1D! then numb_temp :7 numb(31 downto ! ; temp_e&p :7 e&p (' downto ! ; t :7 D D; end i" ; i" (t( 7 D1D! then i" ($ero_detect 7 ! then i" (addsub 7 D D! then i" (numb_temp 7 ! then normal_sum F7 numb_temp(31 downto ! ; e&it_n F7 D1D ; t( :7 D D ; elsi" (numb_temp(31! 7 D1D and clock 7 D1D! then normal_sum F7 signbit I temp_e&p(' downto ! I numb_temp(3 downto %! ;55checkNN e&it_n F7 D1D ; t( :7 D D ; elsi" (clock 7 D1D! then numb_temp :7 numb_temp(3 downto ! I D D ; temp_e&p :7 temp_e&p 5 C 1C ;

49
end i" ; elsi" (addsub 7 D1D and numb(3(! 7 D1D and clock 7 D1D! then temp_e&p :7 temp_e&p J C 1C ; normal_sum F7 signbit I temp_e&p(' downto ! I numb_temp(31 downto 6! ; e&it_n F7 D1D ; t( :7 D D ; elsi" (clock 7 D1D! then normal_sum F7 signbit I temp_e&p(' downto ! I numb_temp(3 downto %! ; e&it_n F7 D1D ; t( :7 D D ; end i"; elsi" ($ero_detect 7 1! then normal_sum F7 b; e&it_n F7 D1D ; t( :7 D D ; elsi" ($ero_detect 7 (! then normal_sum F7 a ; e&it_n F7 D1D ; t( :7 D D ; end i" ; end i" ; end i" ; elsi" (rst_norm 7 D1D! then e&it_n F7 D D ; t :7 D1D ; t( :7 D1D ; end i" ; end process ; end rtl ;

50
negate.=0*
55./<>02+. 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity negate is port ( neg_in : in std_logic_vector(31 downto ! ; neg_en # clock_main : in std_logic ; neg_out : out std_logic_vector(31 downto ! ! ; end negate ; architecture rtl o" negate is begin process(neg_in # neg_en # clock_main! variable neg_temp : std_logic_vector(31 downto begin neg_temp :7 neg_in(31 downto ! ; i" (clock_main 7 D1D! then i" (neg_en 7 D1D! then i"(neg_in(31! 7 D D! then neg_temp :7 D1D I neg_temp (3 downto ! ; else neg_temp :7 D D I neg_temp (3 downto ! ; end i" ; neg_out F7 neg_temp ; else neg_out F7 neg_in(31 downto ! ; end i" ; end i" ; end process ; end rtl ;

! ;

51
m '<" t.=0*
55 ,3;02-;/=/1 2. 0@/ E300/1A;? -1+*/992.< 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity mu& is port ( d # d1 : in std_logic_vector(31 downto ! ; mu&_out : out std_logic_vector(31 downto ! ; choose : in std_logic ! ; end mu& ; architecture rtl o" mu& is begin process(d # d1 # choose! begin i" (choose 7 D D! then mu&_out F7 d (31 downto ! ; elsi" (choose 7 D1D! then mu&_out F7 d1(31 downto ! ; end i" ; end process ; end rtl ;

52
m '<a**.=0*
55 multiple&er in the address generation unit library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity mu&_add is port ( a # b : in std_logic_vector(3 downto ! ; sel : in std_logic ; ) : out std_logic_vector(3 downto ! ! ; end mu&_add ; architecture rtl o" mu&_add is begin process (a # b # sel! begin i"(sel 7 D D! then ) F7 a(3 downto ! a"ter ( ns ; elsi"(sel 7 D1D! then ) F7 b(3 downto ! a"ter ( ns ; end i" ; end process ; end rtl ;

53
m #ti$#!.=0*
55 ,3;02-;? 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity multiply is port( num_mu& # num_rom : in std_logic_vector(31 downto clock : in std_logic ; mult_out : out std_logic_vector(31 downto ! ! ; end multiply ;

! ;

architecture rtl o" multiply is begin process(num_mu& # num_rom # clock! variable sign_mult # t : std_logic :7 D D ; variable temp1 # temp( : std_logic_vector((( downto ! ; variable e&p_mu& # e&p_rom : std_logic_vector(' downto ! ; variable mant_temp : std_logic_vector(44 downto ! ; variable e&p_mult # mu&_temp # rom_temp : std_logic_vector(% downto ! ; variable res_temp : std_logic_vector(31 downto ! ; begin temp1 :7 D1D I num_mu&((( downto 1! ; 55 D1D "or implicit D1D. temp( :7 D1D I num_rom((( downto 1! ; i" (num_mu&(31! 7 D1D and num_rom(31! 7 D1D and clock 7 D1D! then 55 sign o" results sign_mult :7 D D ; elsi" (num_mu&(31! 7 D D and num_rom(31! 7 D D and clock 7 D1D! then sign_mult :7 D D ; elsi"(clock 7 D1D! then sign_mult :7 D1D ; end i" ; i" (num_mu& 7 and clock 7 D1D! then 55 ie# the number is $ero. t :7 D1D ; elsi" (num_rom 7 and clock 7 D1D! then t :7 D1D ; elsi" (clock 7 D1D! then t :7 D D ; end i" ; i" (t 7 D D and clock 7 D1D! then 55 separation o" mantissa and e&ponent e&p_mu& :7 num_mu& (3 downto (3! ; e&p_rom :7 num_rom (3 downto (3! ;

54
mu&_temp rom_temp e&p_mult e&p_mult :7 :7 :7 :7 D D I e&p_mu&(' downto D D I e&p_rom(' downto mu&_temp J rom_temp ; e&p_mult 5 1(' ; ! ; ! ;

mant_temp :7 temp1 O temp( ; i"(mant_temp(44! 7 D1D! then 55 normalisation. e&p_mult :7 e&p_mult J 1 ; res_temp :7 sign_mult I e&p_mult(' downto ! I downto ((! ; mult_out F7 res_temp(31 downto ! ; elsi"(mant_temp(44! 7 D D! then res_temp :7 sign_mult I e&p_mult(' downto ! I downto (1! ; mult_out F7 res_temp(31 downto ! ; end i" ; elsi" (t 7 D1D and clock 7 D1D! then 55 number mult_out F7 C C t :7 D D ; end i" ; end process ; end rtl ;

mant_temp(44

mant_temp(43

$ero ;

55
m #t.=0*
55 ,3;02-;/=/1 0+ *@++9/ E/0B//. *;+*M >.: * library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity mult_clock is port ( clock_main # mult1_c # mult1_iomode # mult_clear : in std_logic ; mult1_addincr : out std_logic ! ; end mult_clock ; architecture rtl o" mult_clock is begin process(clock_main # mult1_c # mult1_iomode # mult_clear! variable temp1 : std_logic ; variable temp( : std_logic ; begin i"(mult1_iomode 7 D D! then 55 ie# ""t computation mode temp( :7 mult1_c ; elsi"(mult1_iomode 7 D1D! then 55 ie# io mode temp1 :7 clock_main ; end i" ; i" (mult1_iomode 7 D1D! then mult1_addincr F7 temp1 ; elsi"(mult1_iomode 7 D D! then mult1_addincr F7 temp( ; end i" ; end process ; end rtl ;

56
#"#oc?.=0*
55 -+9202K/ ;/K/; 012<</1/: A;2- A;+-9 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity l_block is port ( data_l : in std_logic_vector(31 downto trigger_l : in std_logic ; l_out : out std_logic_vector(31 downto end l_block ; architecture rtl o" l_block is begin process(data_l # trigger_l! begin i" (trigger_l7D1D! then l_out F7 data_l ; end i" ; end process ; end rtl ;

! ; ! ! ;

57
io*<%tage*.=0*
55 0@29 A2;/ +30-309 0@/ C2+ :+./C >.: C90></ :+./C >.: CAA0 :+./C 92<.>;9 >0 0@/ 55 *+11/*0 02,/. 20 >;9+ 1/*/2K/9 0@/ +30-30 +A 0@/ E300/1A;? </./1>0+1 55 >.: +30-309 20 3.*@>.</:. library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity iod_staged is port ( but_"ly : in std_logic_vector(3 downto ! ; stage_no : in std_logic_vector(1 downto ! ; add_incr # io_mode : in std_logic ; add_iod # add_staged # add_""td : out std_logic ; butter"ly_iod : out std_logic_vector(3 downto ! ! ; end iod_staged ; architecture rtl o" iod_staged is begin process(but_"ly#add_incr#io_mode! begin i"(but_"ly 7 14 and io_mode 7 D1D and add_incr7D D! then add_iod F7 D1D ; 55 io done signal butter"ly_iod F7 but_"ly ; elsi"(but_"ly 7 4 and io_mode 7 D D and add_incr7D1D! then butter"ly_iod F7 but_"ly ; add_iod F7 D D ; add_staged F7 D1D ; 55 stage done signal else butter"ly_iod F7 but_"ly ; add_staged F7 D D ; end i" ; end process ; process(stage_no! begin i" (stage_no73! then add_""td F7 D1D ; 55 ""t done signal end i" ; end process ; end rtl;

58
ioa**.=0*
55 2+ >::1/99 </./1>0+1 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity ioadd_gen is port ( io_butter"ly : in std_logic_vector(3 downto ! ; add_iomode # add_ip # add_op : in std_logic ; base_ioadd : out std_logic_vector(3 downto ! ! ; end ioadd_gen ; architecture rtl o" ioadd_gen is begin process(io_butter"ly # add_iomode # add_ip # add_op! variable out_data : std_logic_vector(3 downto ! ; begin i"(add_iomode 7 D1D! then i" (add_ip 7 D1D! then out_data :7 io_butter"ly(3 downto ! ; elsi"(add_op 7 D1D! then i"(io_butter"ly(3! 7 D D! then 55 ie# real part out_data :7 D D I io_butter"ly( ! I io_butter"ly(1! I io_butter"ly((! ; elsi"(io_butter"ly(3!7D1D! then 55 ie# comple& part out_data :7 D1D I io_butter"ly( ! I io_butter"ly(1! I io_butter"ly((! ; end i" ; end i" ; end i" ; base_ioadd F7 out_data(3 downto ! ; end process ; end rtl ;

59
*i=i*e.=0*
55 :2K2:/ E? 0B+ 3.20. 0@29 A2;/ @+B/K/1 ->99/: 0@/ :>0> 3.*@>.</: 55 E/*>39/ :2K292+. 29 1/L321/: +.;? 2A 9*>;2.< 29 39/: 0+ >K+2: +K/1A;+B. 55 .+ 9*>;2.< B>9 39/: 2. 0@29 -1+P/*0# 9+ 0@>0 1/93;09 +A ,>0;>E ,>0*@/: B20@ +319 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity divide is port ( data_in : in std_logic_vector(31 downto ! ; data_out : out std_logic_vector(31 downto ! ! ; end divide ; architecture rtl o" divide is begin process(data_in! variable divide_e&p : std_logic_vector(' downto ! ; variable divide_mant : std_logic_vector(31 downto ! ; begin i" (data_in 7 C C! then data_out F7 C C ; elsi" (data_in 7 C1 C! then data_out F7 C C ; else divide_e&p :7 data_in(3 downto (3! ; divide_mant :7 data_in (31 downto ! ; divide_e&p :7 divide_e&p 5 C 1C ; 55data_out F7 divide_mant(31! I divide_e&p(' downto ! I divide_mant((( downto ! ; data_out F7 data_in(31 downto ! ; 55 pass data unchanged end i" ; end process ; end rtl ;

60
*&&.=0*
55 -+9202K/ /:</ 012<</1/: A;2-A;+-9 -;>*/: E/A+1/ 0@/ :2K2:/ E? 0B+ 3.20 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity level_edge is port ( data_edge : in std_logic_vector(31 downto trigger_edge : in std_logic ; edge_out : out std_logic_vector(31 downto end level_edge ; architecture rtl o" level_edge is begin process(data_edge # trigger_edge! begin i" (trigger_edge7D1D and trigger_edgeDevent! then edge_out F7 data_edge(31 downto ! ; end i" ; end process ; end rtl ;

! ; ! ! ;

61
c!c#e%<" t.=0*
55B>K/A+1, </./1>0+1 55 0@/ 4 E209 +A C:>0>_+30C >1/ C* library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; *1 *( *3C

entity cycles is port ( clock_main # preset # c _en # cycles_clear : in std_logic ; waves : out std_logic_vector(3 downto ! ! ; end cycles ; architecture rtl o" cycles is 55type state_values is (st # st1 # st( # st3! ; 55signal pres_state1 # ne&t_state1 : state_values ; shared variable data_out : std_logic_vector(3 downto ! ; begin process (clock_main # preset # c _en#cycles_clear! variable t : std_logic ; begin i" (c _en 7 D1D! then i" (preset 7 D1D and t7D1D!then pres_state1 F7 st ; t :7 D D ; elsi" (clock_mainDevent and clock_main7 D D! then pres_state1 F7 ne&t_state1 ; end i" ; end i" ; i"(cycles_clear 7 D1D! then t :7 D1D ; end i" ; end process ; process(pres_state1 # c _en # clock_main! variable temp_clock : std_logic ; begin case pres_state1 is when st 78 data_out :7 C1 C ; ne&t_state1 F7 st1 ; when st1 78 data_out :7 C 1 C ; ne&t_state1 F7 st( ; when st( 78 data_out :7 C 1 C ; ne&t_state1 F7 st3 ; when st3 78

62
data_out :7 C 1C ; ne&t_state1 F7 st ; when others 78 ne&t_state1 F7 st end case ; waves F7 data_out ; end process ; end rtl ; ;

co nter.=0*
55 0@29 A2;/ *+3.09 0@/ .3,E/1 +A *?*;/9 >A0/1 AA0 *+,-30>02+. 29 /.>E;/:. 55 0@29 29 1/L321/: E/*>39/ B1202.< 2.0+ 0@/ 1>, E/<2.9 +.;? >A0/1 4 *?*;/9 (:312.< *1! library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity counter is port ( c : out std_logic_vector(( downto ! ; disable # clock_main # reset : in std_logic! ; end counter ; architecture rtl o" counter is begin process (reset # clock_main # disable! variable temp : std_logic_vector(( downto ! ; begin i" (disable F7 D D! then i"(reset 7 D1D! then c F7 C C ; temp :7 C C ; elsi"(clock_main 7 D1D and clock_mainDevent! then c F7 (temp J 1! ; temp :7 temp J 1 ; end i" ; end i" ; end process ; end rtl ;

63
contro##er.=0*
55 *+.01+; 3.20 +A 0@/ -1+*/99+1 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity cont_gen is port ( con_staged # con_iod # con_""td # con_init : in std_logic ; con_ip # con_op # con_iomode # con_""t : out std_logic ; con_enbw # con_enbor # c _enable # con_preset : out std_logic ; con_clear # disable : out std_logic ; c # clock_main : in std_logic ; en_rom # en_romgen # reset_counter : out std_logic ; con_clkcount : in std_logic_vector(( downto ! ! ; end cont_gen ; architecture rtl o" cont_gen is type state is (rst1#rst(#rst3#rst4#rst4#rst6#rst'! ; signal current_state # ne&t_state : state ; shared variable counter # temp( : std_logic_vector(1 downto C C ; begin process (current_state #con_staged # con_iod # con_""td # con_clkcount # c ! begin case current_state is when rst1 78 con_iomode F7 D1D ; 55 set mode to io. con_ip F7 D1D ; 55 input mode con_clear F7 D1D ; 55 clear all blocks con_enbw F7 D1D ; 55 enable write to 1>, con_enbor F7 D D ; 55 disable read c _enable F7 D D ; 55 disable cycles unit disable F7 D1D ; 55 disable counter ne&t_state F7 rst( ; when rst( 78 con_clear F7 D D ; 55 bring clear signal back to $ero ne&t_state F7rst3 ; when rst3 78 i"(con_iod 7 D1D! then con_preset F7 D1D ; 55 reset cycles reset_counter F7 D1D ; 55 reset counter c _enable F7 D1D ; 55 enable cycles con_iomode F7 D D ; 55 set io mode to D D

! :7

64
con_""t F7 D1D ; 55 ""t mode en_rom F7 D1D ; 55 enable 1+, en_romgen F7 D1D ; 55 enable 1+, address generator con_clear F7 D1D ; 55 clear all blocks con_enbw F7 D D ; 55 disable write to 1>, con_enbor F7 D1D ; 55 enable read "rom 1+, disable F7 D D ; 55 enable counter unit. ne&t_state F7 rst4 ; else ne&t_state F7 rst3 ; end i" ; when rst4 78 con_preset F7 D D ; 55 reset "or cycles reset_counter F7 D D ; 55 reset "or counter con_clear F7 D D ; 55 clear all signals i" (con_clkcount 7 4! then 55 check whether 4 or not con_enbw F7 D1D ; 55 enable write to 1+, disable F7 D1D ; 55 disable counter reset_counter F7 D1D ; 55 reset counter ne&t_state F7 rst4 ; else ne&t_state F7 rst4 ; end i" ; when rst4 78 i" (con_""td 7 D1D! then disable F7 D D ; 55 enable counter reset_counter F7 D D ; con_clear F7 D1D ; 55 clear butter"ly generator con_""t F7 D D ; 55 disable ""t address generator i" (con_clkcount 7 4! then disable F7 D1D; con_enbw F7 D D ; con_iomode F7 D1D ; con_op F7 D1D ; con_ip F7 D D ; ne&t_state F7 rst6 ; else ne&t_state F7 rst4 ; end i" ; else ne&t_state F7 rst4 ; end i" ; when rst6 78 con_clear F7 D D ; ne&t_state F7 rst' ; when rst' 78 i"(con_iod 7 D1D! then

65
con_clear F7 D1D ; con_preset F7 D1D ; con_enbor F7 D D; else ne&t_state F7 rst' ; end i" ; when others 78 ne&t_state F7 rst1 ; end case ; end process ; process(clock_main # con_init! begin i"(con_init 7 D1D! then current_state F7 rst1 ; elsi" (clock_mainDevent and clock_main 7 D D! then current_state F7 ne&t_state ; end i" ; end process ; end rtl ;

66
" tter<#i".=0*
55 0@29 A2;/ :/*;>1/9 0@/ 92<.>;9 39/: 2. 0@/ -1+*/99+1 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; package butter_lib is signal ram_data#d(#d3#d4#d4#d6#d'#d%#d6#d1 #d11#d1(#d13#d14#d14#d16#d1'# d1%#d16#out_data : std_logic_vector(31 downto ! :7 (others 78 D D! ; signal data_rom # rom_"" : std_logic_vector(31 downto ! ; signal clock_main # reset # enbl # clock : std_logic :7 D D ; signal c # c1 # c( # c3 # c _c1 # c(_c3 # c _c( # c1_c3 : std_logic ; signal c _and#c1_and#c(_and#c3_and#c _c1and#c(_c3and#c _c(and#c1_c3and : std_logic ; signal reset_count : std_logic ; type state is (reset1 # reset( # reset3 # reset4 # reset4 # reset6 # reset'! ; signal "inal_sum : std_logic_vector (31 downto ! :7 (others 78 D D! ; signal shi"t # "inish_sum # signbit # normalise # end_all # a_small # addsub #sum_out( # shi"t_done # done # num_rec # setbit # addpulse : std_logic :7 D D ; signal shi"t_outa # swap_num( : std_logic_vector ( 31 downto ! :7 (others 78 D D! ; signal swap_num1 # sum_out : std_logic_vector (3( downto ! :7 (others 78 D D! ; signal sub( : std_logic_vector (% downto ! :7 (others 78 D D! ; signal suba : std_logic_vector (% downto ! :7 (others 78 D D! ; signal e&p : std_logic_vector (' downto ! :7 (others 78 D D! ; signal rst # enswap # ensub # enshi"t # "insub # "inswap # "inshi"t # num$ero : std_logic :7 D D ; signal $erodetect : std_logic_vector(1 downto ! ; signal changea : std_logic ; signal "inal_sumb : std_logic_vector (31 downto ! :7 (others 78 D D! ; signal shi"tb # "inish_sumb # signbitb # normaliseb # end_allb # a_smallb # addsubb#sum_out(b # shi"t_doneb # doneb # num_recb # setbitb # addpulseb # clockb : std_logic :7 D D ; signal shi"t_outb # swap_num(b : std_logic_vector ( 31 downto ! :7 (others 78 D D! ; signal swap_num1b # sum_outb : std_logic_vector (3( downto ! :7 (others 78 D D! ; signal sub(b : std_logic_vector (% downto ! :7 (others 78 D D! ;

67
signal subb : std_logic_vector (% downto ! :7 (others 78 D D! ; signal e&pb: std_logic_vector (' downto ! :7 (others 78 D D! ; signal rstb # enswapb # ensubb # enshi"tb # "insubb # "inswapb # "inshi"tb # num$erob # clock_mainb # resetb # enblb : std_logic :7 D D ; signal $erodetectb : std_logic_vector(1 downto ! ; signal changeb : std_logic ; signal incr # clear # io_mode # staged # iod : std_logic ; signal butter"ly#""tadd_rd#shi"t1#shi"t3#shi"t4#shi"t4#shi"t6#ram_wr#ram _rd#io_add : std_logic_vector(3 downto ! :7 (others 78 D D! ; signal ""td # ""t_en # ip # op # init : std_logic ; signal stage : std_logic_vector(1 downto ! ; 55signal clock_main#c #c1#c(#c3#c _c1#c(_c3#c _c(#c1_c3 : std_logic ; signal preset#disable#c _en#rom_en#romgen_en : std_logic ; signal clk_count : std_logic_vector(( downto ! ; signal enbw # enbor : std_logic ; signal data_io : std_logic_vector(31 downto ! :7 (others 78 D D! ; signal rom_add : std_logic_vector(( downto ! ; type state_values is (st # st1 # st( # st3! ; signal pres_state1 # ne&t_state1 : state_values ; signal butter"ly_iod : std_logic_vector(3 downto ! ; signal cyc_clear : std_logic ; signal add_rd # add_wr : std_logic_vector(3 downto ! ; end butter_lib ;

68
" t.=0*
55 E300/1A;? </./1>0+1 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity but_gen is port ( add_incr # add_clear # stagedone : in std_logic ; but_butter"ly : out std_logic_vector(3 downto ! ! ; end but_gen ; architecture rtl o" but_gen is begin process(add_clear # add_incr # stagedone! variable cnt : integer ; variable count : std_logic_vector(3 downto ! ; begin i"(add_clear 7 D1D or stagedone 7 D1D! then count :7 C C ; but_butter"ly F7 C C ; elsi" (add_incrDevent and add_incr 7 D1D! then but_butter"ly F7 (count J 1! ; count :7 count J 1 ; end i" ; end process ; end rtl ;

69
"a%ein*e'.=0*
55E>9/ 2.:/= </./1>0+1 library ieee; use ieee.std_logic_1164.all; use work.butter_lib.all ; entity baseinde& is port( ind_butter"ly: in std_logic_vector(3 downto !; ind_stage: in std_logic_vector(1 downto !; add_""t: in std_logic; ""tadd_rd: out std_logic_vector(3 downto !; c #c1#c(#c3: in std_logic!; end baseinde&; architecture rtl o" baseinde& is begin process(ind_butter"ly#ind_stage#add_""t#c #c1#c(#c3! variable out_sig : std_logic_vector(3 downto !; begin i" (add_""t7D1D! then i"(c(7D1D! then 55 address "or D&D. 9ince this is the real part# case ind_stage is 55 ,.9.E is D D. when C C 78 out_sig :7 C C I ind_butter"ly(1 downto !; when C 1C 78 out_sig :7 D D I ind_butter"ly(1! I D D I ind_butter"ly( !; 55 when C1 C 78 out_sig :7 D D I D1D I D1D I ind_butter"ly(3!; when C1 C 78 out_sig :7 D D I ind_butter"ly(1 downto ! I D D; when others 78 out_sig :7 C C; end case; elsi"(c 7D1D! then 55 address "or DyD. case ind_stage is when C C 78 out_sig :7 C 1C I ind_butter"ly(1 downto !; when C 1C 78 out_sig :7 D D I ind_butter"ly(1! I D1D I ind_butter"ly( !; when C1 C 78 out_sig :7 D D I ind_butter"ly(1 downto ! I D1D; when others 78 out_sig :7 C C; end case; elsi"(c17D1D! then 55 addresss "or D?D case ind_stage is when C C 78 out_sig :7 C11C I ind_butter"ly(1 downto !; when C 1C 78 out_sig :7 D1D I ind_butter"ly(1! I D1D I ind_butter"ly( !; when C1 C 78 out_sig :7 D1D I ind_butter"ly(1 downto ! I D1D; when others 78 out_sig :7 C C; end case; elsi"(c37D1D! then 55 address "or D=D case ind_stage is

70
when C C 78 out_sig :7 C1 C I when C 1C 78 out_sig :7 D1D I ind_butter"ly( !; when C1 C 78 out_sig :7 D1D I when others 78 out_sig :7 C 55else 55out_sig :7 CQQQQC; end case; end i"; end i"; ""tadd_rd F7 out_sig (3 downto end process; end rtl; ind_butter"ly(1 downto !; ind_butter"ly(1! I D D I ind_butter"ly(1 downto C; ! I D D;

! ;

an*<gate%.=0*
550@29 A2;/ 1/*/2K/9 0@/ +30-30 +A 0@/ B>K/A+1, </./1>0+1 >.: 55+30-309 0@/ 1/L321/: *?*;/9 library ieee; use ieee.std_logic_1164.all; use 2///.std_logic_arith.all; use 2///.std_logic_unsigned.all; use work.butter_lib.all ; entity and_gates is port ( waves_and : in std_logic_vector(3 downto ! ; clock_main # c _en : in std_logic ; c #c1#c(#c3 : out std_logic ; c _c1#c(_c3#c _c(#c1_c3 : out std_logic ! ; end and_gates ; architecture rtl o" and_gates is begin process(clock_main#waves_and! begin i" (c _en 7 D1D and clock_main7D1D! then c F7 c1 F7 c( F7 c3 F7 c _c1 c _c( c(_c3 c1_c3 else c F7 c1 F7 waves_and(3! ; waves_and((! ; waves_and(1! ; waves_and( ! ; F7 waves_and(3! F7 waves_and(3! F7 waves_and(1! F7 waves_and( ! D D ; D D ;

or or or or

waves_and((! waves_and(1! waves_and( ! waves_and((!

; ; ; ;

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c( F7 D D ; c3 F7 D D ; c _c1 F7 D D ; c _c( F7 D D ; c(_c3 F7 D D ; c1_c3 F7 D D ; end i" ; end process ; end rtl ;