Professional Documents
Culture Documents
Microelectronic Manufacturing
Microelectronic Manufacturing
Manufacturing Processes
Rahul Panat
Manufacturing of Microelectronics
and MEMS Devices
BACKGROUND
Why study this topic?
Electronic devices have revolutionized our world!
Conceptual
Apple Watch
Intel-Fossil
Bracelet
Google Glass
Solder Resist
Co
(w
PTH
Filling
material
Intels 32nm Si **
(10s nm ~ 10um)
Processor**
(10s nm ~ 100um)
Cu
(Pa
Teardown.com
**Intel public information
BRIEF HISTORY
Transistor discovered in Bell labs enabling modern
computing revolution
Vacuum tubes used in computers limiting the number of
circuits in the computer; highly bulky
Solution: Jack Kilby patented first IC design and showed
first prototype; Bob Noyce (Intel founder) patented Al
metallization connect the ICs
Microelectronic manufacturing as a separate area emerged
from the miniaturization started by Kilby/Noyce
Bob Noyce
Jack Kilby
Jack Kilby, Texas Instruments, Miniaturized electronic circuits, U.S. Patent US3138743 A
Robert Noyce, Intel Corporation, Semiconductor device, U.S. Patent 2,981,877
IC MINIATURIZATION
Miniaturization of circuits continues per the prediction by Intels Moore
(Moores Law) With unit cost falling as the number of components per
circuit rises, by 1975 economics may dictate squeezing as many as 65 000
components on a single silicon chip..well.a chip with
3.1 billion components* was released in 2012 by Intel..
SILICON
Why Si
Cheap
SiO2, used for isolation and passivation and can be reliably and easily formed to
form the basis for metal oxide semiconductor (MOS) devices
SILICON WAFER
Making electronic grade silicon
SiO2 + C
Heat
95-98% pure
polycrystalline Si
Trichlorisilane
High T
H2 atm
ECG
Video Link
WAFER PROCESSING
CLEANING
CLEANING
Cross-contamination due to
close spacing between wafers
Large footprint
30 year old technology
PHOTOLITHOGRAPHY
Masking
Projection
system
Photoresist
Considerations
Feature size
Wavelength
HMDS: hexamethyldisilzane
OXIDATION
OXIDATION
Types of CVD
Atmospheric pressure CVD (APCVD)
Low pressure CVD (LPCVD)
Plasma enhanced CVD (PECVD)
Hybrid physical-chemical VD (HPCVD)
CVD
PVD
PVD: Sputtering
DEPOSITION
ETCHING
ETCHING PROCESSES
ETCHING PROCESSES
ETCHING ISSUES
PACKAGE TYPES
Leadframe
Flip Chip
FC-CSP
www.emeraldinsight.com
computing-dictionary.thefreedictionary.com
Si: ~3ppm/K
Package: ~17ppm/K
die
Die Bump
solder
substrate
Underfill (polymer)
die
Substrate (fiber reinforced polymer with metal traces connecting die to second level interconnect)
Motherboard (containing chipsets, power supply, Signal I/O connectivity and other peripherals)
substrate
Second Level
Interconnect
solder
PCB board
LAYERED COMPOSITE
Solder Resist
Bump(lead free)
Vias connecting Cu layers
Dielectric Film
Core Material
(woven glass
PTH Filling
material
composite)
Cu Layers
(Patterned)
Gold Wires
(~20um )
Molding Compound
Stacked Dies
Substrate
Application of flux
Substrate
LSCs
C4 bumps
Die Placement
Capacitor
Die
Substrate
Soldered
joint
FLI joint
formation
Die
Substrate
Capacitors
(land side)
SUBSTRATE
DIE
EPOXY DISPENSE
(or FILM)
Overmolding
DIE BONDING
GOLD
WIRE
DFM: Cu-MIGRATION
Per JEDEC standards, all packages must meet certain accelerated test
requirements such as high temperature and moisture under biased condition,
temperature cycling
After several
hours at high Temp
and moisture
Dendrite
Copper
line
Cu Migration Video
Intels Microprocessor
SUMMARY
Interconnect
6 Dielectric
Deposition Steps
12 Dielectric
Etch Steps
6 Ta/Cu PVD Steps
6 Cu Plating Steps
6 Cu CMP Steps
12 Wet Clean Steps
Ion Implantation
Courtesy of Intel
Silicon Wafer
Metal
Dielectric
Copper
Deposition
Copper
Dielectric
W-CMP
Deposition
Deposition
PVD
+ ECP
CMP
Etch
Deposition
PVD + WCVD
Transistor
Poly
Silicon
Gate
Oxide
Poly
Silicon
Shallow
Trench
Shallow
Trench
Deposition
Growth
16
Thermal
Steps
Gate
Etch
Isolation
CMP
Dielectric
Trench
Isolation
11Shallow
Implant
Steps
Deposition
Isolation
Etch
5 Etch
Steps
2 CMP Steps
38 Wet Clean Steps