Sequential Circuit Design:

Part 2

C2MOS Latch
Two-phase clock generators
Four-phase clocking
Pipelining and NORA-CMOS
TSPC logic

C2MOS Logic
Goal: Make circuit operation independent of phase
overlap
No need to worry about careful design of clock
phases, clock inversions, etc
Really ingenious design!

Flip-flop insensitive to clock overlap

VDD
M2

M6

M4

M8

X
CL1

M3

Modes of operation:
1) Evaluate ( = 1)
-section acts as inverter
-section is in high-impedance
(hold) mode
2) Roles reversed for = 0

VDD

Q
CL2

M7

M1

M5

-section
C2MOS master-slave negative edge-triggered D flip-flop

-section

Insensitive to clock overlap as long as clock rise and fall times are small
3

C2MOS avoids Race Conditions

Signal propagation requires pull-up followed by pull-down, or vice versa
VDD

VDD

M2

M6
0

D
1

M3
M1

Q
1

VDD

VDD

M2

M6

M4

M8

M7
M5

M1

M5

(1-1) overlap

(0-0) overlap

Only pull-down networks are enabled

Only pull-up networks are enabled

C2MOS avoids Race Conditions

Caution: If clock has low rise/fall times, then both pMOS and
nMOS may conduct

Typically need rise/fall time at most five times clock

propagation delay

Register

Register

Pipelining

Common in high-speed designs

Combinational logic (stages) separated by registers
Alternating clock phases typically used
Race may occur if clock phases overlap
6

Pipelined Logic using C2MOS

VDD

In

F
C1

VDD

VDD

G
C2

Out
C3

NORA CMOS (NO RAce CMOS)

What are the cons traints on F and G?
7

Example
VDD

VDD

VDD

Number o f

s tatic invers io ns s ho uld be eve n

NORA CMOS
Targets implementation of fast, pipelined
datapaths using dynamic logic
Combines C2MOS pipeline registers and npCMOS dynamic logic functional blocks
Combinational logic can be a mixture of static and dynamic logic
Latch and logic (feeding latch) are clocked in such a way that both
are simultaneously in either evaluation or hold (precharge)
Block in evaluation during =1 is a -module, inverse is a module
-modules and -modules alternate

NORA CMOS Modules

VDD

VDD

In1
In2
In3

VDD

PUN

PDN

Combinational logic
VDD

Out

VDD

-module

Latch
VDD

VDD

In 4

In 1
In 2
In 3

PDN

Out

-module

In4

10

NORA Logic Modules

Operation Modes

=0
=1

-block
Logic
Latch

-block
Logic
Latch

Precharge
Evaluate

Evaluate Evaluate
Precharge Hold

Hold
Evaluate

11

Doubled C2MOS Latches

Single clock (no inverse clock is needed)
Requires redesign of C2MOS latch

12

Doubled C2MOS Latches

VDD

VDD

VDD

Doubled n-C2MOS latch

VDD

Doubled p-C2 MOS latch

= 1, latch in transparent, evaluate mode

= 0, latch in hold mode, only pull-up
network active
Dual-stage approach: no races
13

Doubled C2MOS Latches:

Advantages
No even-inversion constraints between two
latches, or between latch and a dynamic block
Dynamic and static circuits can be mixed freely
Logic functions can be included in the n-C2MOS
or p-C2MOS latches, or placed between them
Disadvantage: More transistors per latch (six,
instead of four)

14

TSPC - True Single Phase Clock

Logic
VDD

VDD

VDD

VDD

PUN
In

Static

Logic

Out

PDN

Inserting logic between

Including logic into

latches

the latch

15

Simplified TSPC Latch (SplitOutput)

VDD

VDD

VDD

-latch

VDD

-latch

Reduced area
Voltage degradation at A

16

Master-Slave Flip-flops
VDD

VDD

(a) Positive edge-triggered D flip-flop

VD D

VDD

VDD

VDD

VDD

VDD

(b) Negative edge-triggered D flip-flop

VDD
D

(c) Positive edge-triggered D flip-flop

using split-output latches

17

Two-Phase Clock Generator

in

Considerations:

Drive: added buffers

Non-overlap: Two phases inverted with respect to each other
Minimum skew
Implement with NAND gates?
18

Registers with Load/Enable

Inputs
D

Ld

Ld

Multiplexed
input

19

Registers with Load/Enable

Inputs

C
C

Ld

Enable

Gated clock

Clock enable
circuit

Gnd

20

10

Comments on Transmission
Gates
(Common Misconceptions)
Enable

Clock enable
circuit

Enabled

Transmission gate used here as an AND gate

Gnd

21

Comments on Transmission
Gates
(Common Misconceptions)
b
a

F = ab

Transmission gate is not an AND gate

b
a

Transmission gate network does not

serve as an OR gate

C
b

F = a+b

22

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