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Scaling PDF
Scaling PDF
Figure1 to Figure 5 illustrates the technology scaling in terms of minimum feature size,
transistor count, prapogation delay, power dissipation and density and technology
generations.
10
10
10
10
-1
-2
10
1960
1970
1980
1990
2000
2010
Year
Propagation Delay
Figure-3:Technology Scaling (3)
rs
ea
0.1
0.01
80
MPU
DSP
85
90
Year
95
0.7
y
/3
4
x
1000
100
10
ears
x1.4 / 3 y
100
10
Scaling Factor
normalized by 4 m design rule
(b) Power density vs. scaling factor.
10
Technology Generations
Figure-5:Technology generation
4.
Table 1: ITRS
5.Scaling Models
Full Scaling (Constant Electrical Field)
Ideal model dimensions and voltage scale together by the same scale factor
Fixed Voltage Scaling
Most common model until recently only the dimensions scale, voltages remain constant
General Scaling
Most realistic for todays situation voltages and dimensions scale with different factors
6.Scaling Factors for Device Parameters
Device scaling modeled in terms of generic scaling factors:
1/ and 1/
1/: scaling factor for supply voltage VDD and gate oxide thickness D
Why is the scaling factor for gate oxide thickness different from other linear horizontal
and vertical dimensions? Consider the cross section of the device as in Figure 6,various
parameters derived are as follows.
Figure-6:Technology generation
Gate area Ag
Ag = L *W
Where L: Channel length and W: Channel width and both are scaled by 1/
Thus Ag is scaled up by 1/2
Cox = ox/D
Where ox is permittivity of gate oxide(thin-ox)= inso and D is the gate oxide thickness
scaled by 1/
1
=
Thus Cox is scaled up by
1
Gate capacitance Cg C g = Co * L *W
Thus Cg is scaled up by * 1/ 2 =/ 2
Parasitic capacitance Cx
Cx is proportional to Ax/d
where d is the depletion width around source or drain and scaled by 1/
Ax is the area of the depletion region around source or drain, scaled by (1/ 2 ).
Thus Cx is scaled up by {1/(1/)}* (1/ 2 ) =1/
Qon = Co * Vgs
where Qon is the average charge per unit area in the on state.
Co is scaled by and Vgs is scaled by 1/
Thus Qon is scaled by 1
L
1
*
W Qon *
Gate delay Td
Td is proportional to Ron*Cg
1
Td is scaled by
* =
fo =
W CoVDD
*
L
Cg
1 1
=
2
Co W
2
* * (Vgs Vt )
2
L
Current density J
I dss
Current density, J = A
where A is cross sectional area of the
Channel in the on state which is scaled by (1/ 2).
So, J is scaled by
1
1
E = 1 C V 2
g
g DD
2
So Eg is scaled by
1
1
* 2 = 2
2
Pg comprises of two components: static component Pgs and dynamic component Pgd:
Where, the static power component is given by:
2
V DD
Pgs =
R on
Pgd = E g f o
Since VDD scales by (1/) and Ron scales by 1, Pgs scales by (1/2).
Since Eg scales by (1/2 ) and fo by (2 /), Pgd also scales by (1/2). Therefore, Pg
scales by (1/2).
P g 2 2
Pa =
=
=
Ag 1 2
2
PT = Pg * Td =
1
1
= 2
2
2
Qon
Ron
General
(Combined V
Description
and
Dimension)
1/
Supply voltage
Channel length
1/
Channel width
1/
Gate oxide thickness 1/
2
Gate area
1/
Gate capacitance per
unit area
Gate capacitance
/2
Parsitic capacitance 1/
1
Carrier density
1
Channel resistance
Idss
Saturation current
Parameters
VDD
L
W
D
Ag
Co (or Cox)
Cg
Cx
1/
Constant E
Constant V
1/
1/
1/
1/
2
1/
1
1/
1/
1
2
1/
1
1/
1/
1/
1/
1
1
1
1
1/
10
Parameters
Ac
J
Vg
Eg
Pg
N
Pa
Td
fo
PT
Description
Conductor cross
section area
Current density
Logic 1 level
Switching energy
Power dissipation per
gate
Gates per unit area
Power dissipation per
unit area
Gate delay
Max. operating
frequency
Power speed product
General
Constant E
(Combined V
and
Dimension)
2
2
1/
1/
Constant V
2 /
1/
1/
2
1
1 / 2
1 / 3
1/
1/
1/
1/
1
2
2 / 2
2
1
2
2
/ 2
1/
2 /
1/
2
1 / 2
1 / 3
1/
7.Implications of Scaling
Improved Performance
Improved Cost
Interconnect Woes
Power Woes
Productivity Challenges
Physical Limits
11
7.1Cost Improvement
Moores Law is still going strong as illustrated in Figure 7.
Figure-7:Technology generation
7.2:Interconnect Woes
Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm, then get
worse because of wires
But
For short wires, such as those inside a logic gate, the wire RC delay is negligible.
However, the long wires present a considerable challenge.
Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm, then get
worse because of wires
But
For short wires, such as those inside a logic gate, the wire RC delay is negligible.
However, the long wires present a considerable challenge.
Figure 8 illustrates delay Vs. generation in nm for different materials.
Figure-8:Technology generation
12
We cant send a signal across a large fast chip in one cycle anymore
Figure-9:Technology generation
13
Figure-10:Technology generation
Moore(03)
Figure-11:Technology generation
14
7.6 Productivity
Transistor count is increasing faster than designer productivity (gates / week)
Dynamic power
Fabrication costs
Electro-migration
Interconnect delay
Effects, as a result of scaling down- which eventually become severe enough to prevent
further miniaturization.
o Substrate doping
o Depletion width
o Limits of miniaturization
15
2 si 0V
q NB 1
KT N B N D
o Vb built in potential and
VB =
ln
q ni ni
-against
Emax
Emax =
2V
d
ln
16
Where
si 0
q NB
d=
2 si Ecrit .d
q NB 2
( Ecrit )
Figure 12 , Figure 13 and Figure 14 shows the relation between substrate concentration
Vs depletion width , Electric field and transit time.
Figure 15 demonstrates the interconnect length Vs. propagation delay and Figure 16
oxide thickness Vs. thermal noise.
Figure-12:Technology generation
17
Figure-13:Technology generation
v drift = E
t=
L
Vdrift
smaximum
2d
E
18
Figure-14:Technology generation
19
Figure-15:Technology generation
As voltages are scaled down, ratio of Vgs-Vt to KT will reduce-so that threshold
current increases.
Emax = 2{Va + Vb }/ d
8.6 Limits on supply voltage due to noise
Decreased inter-feature spacing and greater switching speed result in noise problems
20
Figure-16:Technology generation
21
22