SELF-REPAIRABLE

RECONFIGURABLE CIRCUIT
USING EMBEDDED
AUTONOMOUSLY
RESTRUCTURING CORES
Field Programmable Gate Array

• Re-programmed system
• Re-configurable hardware
Hierarchical Model

S U U F
U U U U

S - SPARE
U - USED
F - FAULT
 • It Consists of Two Levels

Hierarchical Model

Lower Spare CLB Higher Spare CLB

FAULTY CLBs

CFG Bits

I/P and O/P

Decode
Function
Evolved
Architecture
Architecture

Fault
Identification
Module
Objectives are
•To provide a repair model for FPGA
if any fault is detected.

•To develop high speed reliable circuits.

•To identify the evolved FPGA

architecture

•To make use of spare resources to

repair a fault
METHODOLOGY
The inputs to re-structuring
circuits are

• The original configuration bits.

• The output of the Virtual
re-configuration circuit (VRC)
architecture decoder and
• The output of the fault
identification module.

The VRC architecture decoder identifies the

spare and the active CLBs.
VRC ARCHITECTURE DECODER
Configuration Bits

VRC Architecture
Decoder

Evolved VRC in
Hardware

PE’s Power Analyzer

Fault Decission Core

No-Fault Fault
Retain Configuration Autonomous Re-
Bits Structuring of VRC

Modified
Configuration Bus
SPARE SELECTION