Professional Documents
Culture Documents
2009
Chöông 1 Moâ hình heä thoáng duøng vi xöû lyù
Noäi dung :
1.1 Kieán truùc boä vi xöû lyù.
1.2 Heä thoáng vi xöû lyù.
1.3 Boä nhô.ù
1.4 Ngoaïi vi.
1.5 Heä thoáng ñôn chip vaø ña chip.
©2009, CE Department
dce
2009
Kieán truùc boä vi xöû lyù
CPU
Instruction Program
register (IR) counter (PC)
Registers
Instruction
decode and
control unit
Arithmetic
and logic
unit
©2009, CE Department 2
dce
2009
©2009, CE Department 3
dce
2009
Moät soá keát noái cô baûn vôùi vi xöû lyù
CPU
Memory I/O
MPU CPU
BUS
Control BUS
Data BUS Memory
Address BUS
I/O
CPU
Memory I/O
MPU
©2009, CE Department 4
dce
2009
Keát noái vi xöû lyù tieâu bieåu
BUS
©2009, CE Department 5
dce
2009
Interface circuitry
RAM ROM
Peripheral
devices
©2009, CE Department
©2009, CE Department 6
dce
2009
Caùc thuaät ngöõ cô baûn cuûa heä vi
xöû lyù
• CPU laø ñôn vò xöû lyù trung taâm bao goàm ALU, caùc thanh ghi
vaø maïch ñieàu khieån.
• BUS ñòa chæ duøng ñeå chæ vò trí oâ nhôù, coång nhaäp hay
coång xuaát maø CPU muoán chuyeån thoâng tin.
• BUS döõ lieäu laø ñöôøng truyeàn 2 chieàu ñeå chuyeån thoâng tin
giöõa CPU vaø caùc phaàn khaùc cuûa heä thoáng.
• BUS ñieàu khieån laø ñöôøng truyeàn tín hieäu cuûa CPU ñieàu
khieån caùc ñôn vò khaùc nhau trong heä thoáng.
• ROM laø boä nhôù chæ ñoïc. Noäi dung ñaõ ñöôïc ghi tröôùc.
• RAM laø boä nhôù cho pheùp ñoïc ghi ñöôïc.
• Maïch giao tieáp vaø thieát bò vaøo ra cung caáp vaø nhaän döõ
lieäu töø CPU vaø boä nhôù.
©2009, CE Department 7
dce
2009
Caùc heä thoáng maùy tính döïa treân vi xöû lyù
Buses
©2009, CE Department 8
dce
2009
Hoaït ñoäng cuûa BUS khi laáy
leänh
CPU
Address bus
N
Program
counter Data bus
Opcode
Instruction
register
Memory
Control N+2
bus N+1
Clock Opcode N
N-1
Read
©2009, CE Department 9
dce
2009
Chu kyø nhaän – giaûi maõ – thöïc thi cuûa CPU
Instruction
fetch
Instruction
decode
Execute
Result
store
Next
instruction
©2009, CE Department 10
dce
2009
Caùc tín hieäu vi xöû lyù cô baûn
Clock A0
D0
Interrupt
Data bus
Ready/Wait
D7
Control
BusReq Read
BusAck Write
©2009, CE Department 11
dce
2009 Caùc tín hieäu vi xöû lyù cô baûn
• Clock laø tín hieäu ñoàng hoà ñeå ñoàng boä caùc hoaït
ñoäng cuûa heä thoáng.
• Reset laø tín hieäu nhaäp duøng ñeå thieát laäp laïi heä
thoáng.
• A0 -> A15 laø tuyeán ñòa chæ.
• D0 -> D7 laø tuyeán döõ lieäu 2 chieàu.
• Interrupt laø tín hieäu nhaäp yeâu caàu ngaét heä thoáng.
• Ready/Wait laø tín hieäu nhaäp chôø boä nhôù.
• Read laø tín hieäu xuaát tích cöïc thaáp cho pheùp ñoïc.
• Write laø tín hieäu xuaát tích cöïc thaáp cho pheùp ghi.
• BusReq laø tín hieäu nhaäp yeâu caàu DMA heä thoáng.
• BusAck tín hieäu xuaát tích cöïc thaáp baùo CPU ñaùp
öùng DMA
©2009, CE Department 12
dce
2009
©2009, CE Department 13
dce
Daïng leänh maõ maùy cuûa boä vi
xöû lyù
2009
2009
Ba phöông aùn cô baûn trong vieäc maõ hoùa leänh:
Chieàu daøi coù theå thay ñoåi , chieàu daøi coá ñònh vaø chieàu daøi lai.
Address Address
Operation
specifier field
Address bus
µρ
Data bus
MWTC
MRDC
IOWC
IORC
Read-only Read/write
Memory Memory Keyboard Printer
ROM RAM
Vôùi MRDC (memory read control): Ñieàu khieån ñoïc boä nhôù
MWTC (memory write control): Ñieàu khieån ghi boä nhôù
IORC (I/O read control): Ñieàu khieån ñoïc I/O
IOWC (I/O write control): Ñieàu khieån ghi I/O
©2009, CE Department 17
dce
2009
So saùnh giöõa 2 moâ hình Harvard vaø Von Neumann
©2009, CE Department 18
dce
2009
Kieán truùc RISC ñoái nghòch vôùi
CISC
• CISC – Complex Instruction Set Computer
• RISC – Reduced Instruction Set Computer
• Ñaëc ñieåm cuûa RISC:
- Moät leänh thöïc hieän trong 1 chu kyø ñoàng hoà.
- Ñoä daøi leänh coá ñònh.
- Chæ duøng caùc leänh naïp, caát ñeå truy caäp boä nhôù.
- Caùc cheá ñoä ñònh vò ñôn giaûn.
- Soá taùc vuï ít hôn vaø ñôn giaûn hôn.
- Xöû lyù ñaëc bieät khi thöïc hieän leänh naïp vaø reõ
nhaùnh.
- Thöïc hieän laáy leänh tröôùc vaø suy ñoaùn.
©2009, CE Department 19
dce
2009
• RAM (random access memory) laø loaïi boä nhôù cho pheùp ñoïc ghi
ñöôïc.
• SRAM ( Static RAM) laø boä nhôù RAM maø thoâng tin ñöôïc ghi vaøo
caùc flipflop.
• DRAM (Dynamic RAM) laø boä nhôù RAM maøthoâng tin ñöôïc löu nhö
laø ñieän tích treân caùc tuï ñieän.
• ROM (read only memory) laø loaïi boä nhôù chæ ñoïc, noäi dung boä nhôù
ñaõ ñöôïc ghi tröôùc.
• PROM (programmable ROM) laø boä nhôù ROM cho pheùp ghi moät laàn.
• EPROM (erasable PROM) laø boä nhôù ROM coù theå xoùa ñöôïc baèng
tia cöïc tím vaø ghi nhieàu laàn.
• EEPROM (electrically erasable PROM) laø boä nhôù ROM coù theå xoùa
vaø naïp baèng ñieän.
©2009, CE Department 20
dce
2009
Toå chöùc maûng 4 x 4 cuûa boä nhôù 16 bit
bit line
©2009, CE Department 21
dce Maïch hoã trôï cho boä nhôù 16x1 vôùi maûng boä nhôù
2009
4x4
Memory
decoder
A0
2 to 4
Array
A1
A2
A3
4:1 mux/demux
OE
CS
WE
D0
©2009, CE Department 22
dce
2009
Giaûi maõ ñòa chæ
RD
74LS138 OE
A13 A CE A0 – A12
A14 B CE
A15 C data
CE
CE
G2A CE
A17 CE
A18 G2B
A19 CE
A16 G1 CE
2764
©2009, CE Department 24
dce
2009
I/O bus
Data
Processor Address
Control
©2009, CE Department 25
dce
2009
I/O tröïc tieáp (a) vaø I/O aùnh xaï boä nhôù (b)
Isolated I/O
Control
signal Control register
Address
bus
Control register
©2009, CE Department 26
dce
2009
Ba phöông phaùp ñieàu khieån I/O
Memory
Data bus
µΡ
a) Polling (hoûi
voøng) ?
I/O I/O
Memory
Data bus
b) I/O baèng ngaét µΡ
I/O I/O
INT
INT INT
c) I/O baèng µΡ
DMA
I/O I/O
©2009, CE Department 27
dce
2009
Heä thoáng VXL ñôn chip vaø ña chip
SINGLE IC
EPROM/ROM
I/O
CRYSTAL MICROPROCESSOR TO EXTERNAL
PORTS
DEVICES
CORE
RAM
MULTIPLE IC
EPROM/ROM
I/O TO EXTERNAL
CRYSTAL MICROPROCESSOR PORTS DEVICES
CORE
RAM
©2009, CE Department 28