VHDL example questions 1.

Write the entity section of a VHDL program to implement the following block: [4]

The left, right, up and down signals contain single bit values, and the out_x and out_y signals each contain 3 bits. 2. Suppose that the control block of question 1 drives a 8 by 8 grid of LEDs. Only one LED is lit (active) at one time, with the top-left LED initially active. The out_x and out_y singals are binary vectors that together drive a single LED, where the following decimal values of each signal activate each LED: Out_x: Out_y: 0 1 . 2 . . . 7 . . 0 1 2 3 4 7

The left, right, up and down signals change the position of the LED that is currently active. 2(a) 2(b) 2(c) How many states are required to represent the horizontal position of the active LED? How many states are required to represent the active LED position? [1] [1]

Write the architecture of the VHDL program that implements the above scheme. The program must use 1 bit to represent each state. (Hint: Use the conv_std_logic_vector(x,y) function to convert the integer x to a bit vector of size y). [12]

3(a)

Write a single VHDL statement to implement the logical function [1] Y = (A.B + C.D)* where + indicates logical OR, . indicates logical AND, and * indicates logical NOT. Write the structural architecture of the logical function in 3(a). All variables in the logical function are assumed to be signals. Assume that the architectures of the components are already implemented. [8] (From EAS410 semester test 2, 2004)

3(b)

4.

Extra references for VHDL: 1) Digital design, principles and practices, by John. F. Wakerly, 3rd edition, Prentice Hall (ERS210 textbook). 2) Digital systems design using VHDL, by CH Roth, PWS publishing. 3) EAS410 semester test 2 and exam paper for 2004 (available online).

Answers: 1. ENTITY control IS PORT( left, right, up, down : IN STD_LOGIC; out_x : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); out_y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END control; 8 states 8 states horizontal + 8 states vertical = 16 states total
ARCHITECTURE control_arch of control IS SIGNAL x_state : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001"; -- Initial states SIGNAL y_state : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001"; BEGIN PROCESS (left, right) BEGIN IF right = '1' THEN x_state <= x_state(6 DOWNTO 0) & x_state(7); ELSIF left = '1' THEN x_state <= x_state(0) & x_state(7 DOWNTO 1); ELSE null; END if; END PROCESS; PROCESS (up, down) BEGIN IF down = '1' THEN y_state <= y_state(6 DOWNTO 0) & y_state(7); ELSIF up = '1' THEN y_state <= y_state(0) & y_state(7 DOWNTO 1); ELSE null; END if; END PROCESS; PROCESS (x_state, y_state) VARIABLE out_x_temp : STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE out_y_temp : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN for i in 0 to 7 loop if x_state(i) = '1' THEN out_x_temp := CONV_STD_LOGIC_VECTOR(i,3); END if; if y_state(i) = '1' THEN out_y_temp := CONV_STD_LOGIC_VECTOR(i,3); END if; end loop; out_x <= out_x_temp; out_y <= out_y_temp; END PROCESS; END control_arch; -- Write to the output signals

2(a) 2(b) 2(c)

-- Left shift -- Right shift

-- Left shift -- Right shift

-- Convert to binary output vector format

-- Convert to binary output vector format

3(a) 3(b)

Y <= NOT((A and B) OR (C and D)); See page 7 of the VHDL guide (VHDL.pdf) on the web for a similar example.

ARCHITECTURE structural_arch of structural IS -- Structural description component AND2 port (I1, I2: in STD_LOGIC; O1: out STD_LOGIC); end component; component OR2 port (I1, I2: in STD_LOGIC; O1: out STD_LOGIC); end component; component NOT1 port (I: in STD_LOGIC; O1: out STD_LOGIC); end component; signal stage1_top, stage1_bottom, stage2 : STD_LOGIC;

-- Define components used in architecture

BEGIN PROCESS (A, B, C, D) BEGIN -- Behavioural description Y <= NOT((A AND B) OR (C AND D)); END PROCESS; U1: AND2 port map (A,B, stage1_top); U2: AND2 port map (C,D, stage1_bottom); U3: OR2 port map (stage1_top, stage1_bottom, stage2); U4: NOT1 port map (stage2, Y); END structural_arch; -- Map the components to the circuit