III SEM(E&E) ANALOG ELECTRONICS LAB

CLAMPING CIRCUIT
Expt No:2 Date:
AIM : To design a positive/negative clamping circuits for a given reference level
voltage.
APPARATUS :
THEORY :
A circuit that places either negative or positive peaks of a signal at the desired
D.C level is known as clamping circuit.
A clamping circuit essentially adds DC component to the signal. The input
signal is a sine wave having peak-to-peak value of 10. The clamper adds a D.C
component and pushes the signal upward so that the negative peaks fall on the !ero
level. As we can see the waveform now has peak values of 10 and 0.
"t may #e seen that the shape of the original signal has not changed$ there is
only a vertical shift in the signal. %uch a clamping is called positive clamping. The
negative clamper does the reverse& ie. it pushes the signal downward so that the
positive peak falls on the !ero level.
A clamping circuit should not change the peak-to-peak value of the signal. "t
should only change the DC level& for this a clamping circuit uses a capacitor with a
diode and a load resistance '
(
. The operation of the clamper is #ased on the principle
that the charging time of the capacitor is made small as compared to discharge time.
"n a positive clamper the input signal is assumed as s)uare wave with a time
period T. The clamped output is o#tained across '
(
. This circuit designs incorporate
two main features. *irstly the value of '
(
and C are so selected that constant T + '
(
.C
is very large. This means the voltage across the capacitor will not discharge
significantly during the interval the diode is in non-conducting state& secondly '
(
.C
time constant is deli#erately made much greater than the time period T of the
incoming signal.

DEPT. OF E& BLDEAS CET,
BIAPUR
S!. No. PARTICULARS RAN"E #UANTITY
1 Diode 1N 4007 1
2 'esistor ,00k- 1
3 Capacitor 1.* 1
4 DC /ower %upply 0-10 1
5 %ignal generator --- 1
6 C'1 --- 1
7 Connecting #oards 2 3ires --- ---
III SEM(E&E) ANALOG ELECTRONICS LAB
DESI"N : *re)uency of "nput s)uare wave is 1k4!
3.5.T Time period& T+1/* T+1ms.
'.C 66 T & '.C 66 1 ms 7say8
(et C + 1 .*
' 66 91 ms / 1.*:& ' 66 00 5-
' ,00 5-.
Let us Choose, R
L
=200 K & C = 1 F.
PROCEDURE :
1. ;efore wiring the circuit & check all the components using multimeter.
2. <ake the connections as shown in the circuit diagrams.
3. *or each of these circuit inputs& s)uare-wave is fed from A%=.
4. The fre)uency and amplitude of a symmetrical s)uare wave is suita#ly selected
7107p-p8&,004!8.
5. 'eference voltages are properly selected and ad>usted to the values shown in
figure.
6. The input output waveforms for all circuits are o#served on a C'1 and plotted on
graph sheet.
DEPT. OF E& BLDEAS CET,
BIAPUR
III SEM(E&E) ANALOG ELECTRONICS LAB
Positive c!"#i$% ci&cuit :
'esi%$ o( Positive c!"#i$% ci&cuit :
During negative half ccle!
3hen ?D@ is 1A 7short path with Diode drop8&
Capacitor ?C@ will get charged to peak with Diode drop.
*rom Circuit c+m-
. )3here m+ in/,&

=0.7 (o& *i+

During "#$itive half ccle!
?D@ is 1** 71pen path across Diode8&
Applying 5( - in B c C o + 0 or 7in C c B o+08
o + in C c

3hen& in + -m 7input at -ve peak 8 o + - m C m -

,o = -,

= -0.7
in + 0 o + 0 C c&
,o = ," - ,
.
in + Cm 7input at Cve peak 8 o + m C m -

,o = 2 ," - ,

III SEM(E&E) ANALOG ELECTRONICS LAB

"nput waveform 1utput waveform
i o
C0v ,m
,m 0 t 0 t
-0v
Positive c!"#i$% ci&cuit .ith /ve &e(e&e$ce :
'esi%$ o( Positive c!"#i$% ci&cuit :
During negative half cycle
?D@ is 1A& c+7m-

+ C '. 7m + in/,8
3hen Diode is '.; or open ckt
-in B c C o + 0 o + in C c

7,m-

8 7,m-

8
III SEM(E&E) ANALOG ELECTRONICS LAB
,o = ,i$ / ),"-,

+ / ,R.
3hen in + -m)0$#ut -ve #e!1 + &
o + m C 7m -
8 C '.
o + -m C m -
C '.
,o + ref -

)2ut#ut -ve #e!1 +

3hen in+0&
o + m C 7m -
8 C '.
,o = 0 / ," / ' - ,
.
3hen in + Cm)0$#ut /ve #e!1 + &
o + m C 7m -

8 C '
o + m C m C ' -

,o = 2 ," / ,R - ,
)2ut#ut /ve Pe!1 +
/ositive clamping circuit with /ositive reference voltage
,i ,o

2,"
C10v

2," 0 t 0 t
-10v
"nput 3aveform 1utput 3aveform
7'-
+
7,mC'-

8
III SEM(E&E) ANALOG ELECTRONICS LAB
Positive c!"#i$% ci&cuit .ith -ve &e(e&e$ce :
Positive C!"#i$% .ith 3 ve &e(e&e$ce vot!%e
,m
o
t
0
t
,m
,
o
0
7-
'
-

+
7,
m
-D
'
C

4 8
III SEM(E&E) ANALOG ELECTRONICS LAB
5e%!tive C!"#i$% Ci&cuit :
'esi%$ o( 5e%!tive C!"#i$% :
During %#$itive half Ccle!
3hen Diode ?D@ is 1A& ,c = ," - ,
.
During Negative half Ccle!
3hen Diode is 'everse ;iased or 1pen ckt
*rom circuit #y 5..( & -in C cC o + 0
,o = ,i$ - ,c
3hen in + Cm& o + in B c + m B 7m -

8
o + m B m C

.
,o = ,

3hen in + 0 o + 0 B c + 0 B 7m -

8
,o = ," -
.
3hen in + -m& o + in B c + -m B 7m -

8
,o = -2," / ,

.
III SEM(E&E) ANALOG ELECTRONICS LAB
Aegative Clamping 3aveformsE
,i ,o


C10v

2," 0 t 0 t
,,"
-10v

"nput 3aveform 1utput 3aveform
5e%!tive C!"#i$% .ith /ve Re(e&e$ce:
5e%!tive C!"#i$% .ith /ve Re(e&e$ce:
7-,mC

8
III SEM(E&E) ANALOG ELECTRONICS LAB
,i ,o


C10v

2," 0 t 0 t


-10v

"nput 3aveform 1utput 3aveform
5e%!tive C!"#i$% .ith -ve Re(e&e$ce:
'esi%$ o( 5e%!tive C!"#i$% .ith -ve Re(e&e$ce:
7-,mC7'C

+
7'C

8
2,"
III SEM(E&E) ANALOG ELECTRONICS LAB
During %#$itive half ccle!
?D@ is 1A& ,c=),"-,

+ / ,R. where 7m + in/,8

During %#$itive half ccle!
3hen Diode is '.; or open ckt& from circuit #y 5..(
-in C c C o + 0.
,o = ,i$ - ,c
3hen in + -m )0$#ut !t -ve #e!1 + &
o + in - c
o + -m B 7m-

C '8.
,o = -2," -,Re(./,

.)2ut#ut -ve #e!1 +

3hen in+0&
o + in - c
o + 0 -7m-

C 'ef.8
,o = -," - ,R /,
.
3hen in + Cm )0$#ut /ve #e!1 + &
o + in - c
o + m - 7m -

C ' 8
o + m - m - ' C

,o = ,R / ,
)2ut#ut /ve Pe!1 +
5e%!tive C!"#i$% .ith /ve Re(e&e$ce:
III SEM(E&E) ANALOG ELECTRONICS LAB
,i ,o


C10v

2," 0 t 0 t


-10v

"nput 3aveform 1utput 3aveform
7-,mC7'-

+
7-'C

8
2,"