AnsmAcr

Ferroelectrlcmate~showa~ntancouselectricalpolarlzatbnthatcan
be reversed in sense by an applied external electrlc Beld. It should,
ulcreforr.be tmslblt to bulld a krroelccMc " ~ r ydevlce that can store
~ormationindlgltalfom
E d y attempts to build such a memory have Failed forvarbus reams,
the major OM belag a &ck of a d deftncd and stable coerdve &U whtch
nsulted in the eventual bss of data due to half-select pulsea applied to
umekted ceb in the CrOBBpotnt array a
"
.
Fatlgue or wcarout
was also a problem in that the BmoIult of available signal depended upon
the number of polarkation"ab.
We havebeen able to mmm these problem by acombinationofdesign
innovationsandproceasandmatalalsbreakthmughs. Whavechosenm

Another obstacle to the cnatbn of a orroelectric " o r y in the 1950s

and 196Oswas the
of a depsition technique that could achieve high
quality submicron filma. EhIy ferroelectric memories I* employed bulk
material that resulted in switching thresholds of tens or hundreds of volts
and SwttcMngspeedsintheraageofabweumdsto mUUsecondsrenderlng
the techaobgy incompatlblewith inkgrated drcuit technobgy.
A further Umitation to practtcal memory applications was the Umited
enduraw (demmhg signal charge as a function of switching cycles) of
most fermelec&ma~ Eadurancevarieswidelyand can range h m a
lew cycles to >lOOcyclesdepending on the material chosen and subsequent

Prormslng.

-titanate)
a s t h e b a s l c ~ t r iM
c
dintegrakdit
into astandard CMOS pmccw. mhas awldc temperature range (+35ooc
Curie Tunpcrature)).bw uxrdvc voltage. hlgh specific polarkation charge
(10-20pC/a@)and good retention and axlurana.The lack ofa well d e M
coerdve &Id was o v e r c o ~with a DRAM like clrcuit architecture. which
providea for transistor switchca in aules with each caroelectrlc element
pmnntiagdlsturbpulses froma&&ngthelmaelectedcells.
As a demonstration vehicle. a fully decoded 256 Bit nonvolatile
ferroelectric Random Access Memory (FRAMB) was developed.
CharacMzatbnreaultswinbepresented. One ofthe unexpected Bndings
was theatmnelytast switching speed inhemt in the PzTmaterial which
was bund to be ofthe order of one mnoaecond. lhehlgh switchingspeed
and the high signal charge. which mdas the technob~hlghlyscalable.
oNers the potenthl to build nonvolatile scmtconductor memories with the
speed of static RAMS and the density and cost of dynamlc RAMS.

The ferroelei!trlc effect Is not a new discovery. As early as 1921 J.

Valaseklll discovered the phenomenon of spontaneous polarization on
Rochelle Salt (NaKCJi,0,4H,O)
and used the term "ferroelectric" to
emphasize the analogy between the non-linear hysteretic dielectric
properties of RocheIlc salt and the magnetic khavior of hmagnetic iron.
Spontaneous polarbation mans that electrical dipoh in the Malign
themsehrcs along electrical &Id Uneswhen an electric &Id is applied to a
spectmn and remab in the a@ed posltion cum if the &Id is subsequently
d.
Applying the oppoelte polarity cauwa the dipoles to switch and
allgnintheop~tedirectioIL
Bemuse knoelectrlc materhls athlbit at least two stable states that can
be switched back and l o a , it should be feasible to build a ferroelectric
memory device that can store informatbn in digltal form. A major attempt
was made in the 195osand 1960s by nsearchas in severallaboratoriesto
build such a lymMhttle " o r y . W At that time famelectrlc technobgy
was conssdend an attractive altematk to the main s t " magnetic core
technobgy. Hawevn. most of thesc attempts were abandoned for a varkty
of reasons.ont ofthcmwas the imperEct shape of the Q-vhysteresis bop
bscompared to the lk"ticw
1). whlchmade it diIBnrlt
t o i m p k m a t a t ~ e k a n e n t i n a " o r y q . lheonly
" o r y archit"
at that time was the crosspoint m a k
~ s h o a n i Qpre
n
2. Becausemaet fhroelccMc matalals M a d
deencd and stabk faalectrlc enltcMng threshold voltage (axmtve voltage)
(eee F@m 1). data in a "QY hp mcntdy lost due to the half-sekct
pulaesappued bunselected cells.

,++H

The attempts to build a ferroelectric memory had essentially been

abandoned in the eady 1970s and the industry has taken a diITerent route
toward satlsfylng the need for nonvolatile "les.Volatile semiconductor
"orles such as dynamlc RAMS or static RAMS have efkctively displaced
magnetic core memories. However, nonvolatility is quite often an important
q u i r e m a t which Is accomplished in many cases byabatteryback-up at
the board-or systems level. Howem. Tor many applications nonvolatility on
the component level is preferred. Numerous nonvolatile technologies (both
semiconductor-and magnetic) were developed such as ROM, EPROM,
EEPROM, M".
plated wire. bubble technology.etc. The hct that not one.
but many dmerent forms of nonvolaae memory components exist today,
illustrates clearly that no one single technology can satisfy all the
nquinmnts.
Them is no doubt that a

nonvolatile moly technobgy that could offer

low cost/bit. high speed, goad retention. and hlgh endurance and be
compatiblewith standard s c " d u c t o r technobgies such as CMOS, GaAa,
etc. would have tremendouspotenthl and an essentlalty unlimited market
I would like to show that the fenoeleetrlc technobgvbeing developed by
Ramtron has the potential to approach this "ideal memory technobgy."
First. the bask teclmobgywill be described and then the results will be
pmented that have beenachieved with discrrte "~rycapacltors as well
as on a 256 bit nomrolatlle Ferroelectric Random Access Memory 0
that was devebped as a darrmstrationvehlcle (EaJhr 8101).

,.-.

CH2704-5/89/ooaO/l020/$01.00
0 1989 IEEE

-=

lhen a~ baskaUy tm ways to build a digital" ~ r element

y
employing
a ferroelectric thin film dielectric. One approach Is to replace the gate

insulator ofa &Id e k t trau&tor with a famkchk layer. The threshold

voltagcofsuhadevicewin havc two distimtvaluesdependingonwhether
the dipoles in the tamelectric material are orknted up or down. The
advantagca of this implementation arc the inhermt ampWatIon built into
the device and the unlimited read cycles (the device is only ktigued if new
inbmution Isw~Ittenintoit). It ala0 ofkm the potential for amemorywith
avuy high pacblngdenslty, since only OIIC device pacell Is nquhd.
However, this device Is ray dWdt to build reltably. First in oder to

b. FaroelectrrIiy&mi~Loop
Figure 1. Comparison of Magnetic and Ferroelectric Hystmsb

t am

Figure 2. Cross Point Matrbr

o b t a i n b w v a l t a g e ~b w n e ~ d e c t r o d e s a r enquhd.Ihlsts
diffkdt to achieve. at lmst for the bottom electrode U m - a S l i c o n
hbxkm) arltbout -the
t"charactalatlca

1 - 20

Secondly, as shown by J. Schulz et al.161 due to the movement of slow

compensation charge through the ferroelectric layer the two distinct
threshold voltages correspondingto a logic 0and a logic 1approach each
other with time. Therefore. the information is lost after some Ume which
can be from several seconds to hours or days.
The second implementation.which is the one adopted by Ramtron. is a
ferroelectric capacitor as shown in Figure 3a. The device consists of a hyer
of ferroelectric materlal sandwiched between two metal electrodes. The
device is wrltten by applyinga voltage tV which is greater than the coercive
voltage of the structure. Under the influence of the electric field, the dipoles
are aligned in one direction (up in our example). The device is read by again
applying a voltage V across the device. If the dipoles are oriented in the
directionof the electric fleld a current pulse is generated that corresponds to
the charging current of the capacitor. ?his current is proportional to the
Unear dielectricconstant of the haterial.

c
Figure 3 a Ferroelectric Capacitor
lBw

SGNAL - A R E A MF ERENCE
,-ly?cfA:W

, ,

operation and a signal chage of at least 5pC/cm? The Curie temperature

should be sulllciently above the highest storage temperature and Inherent
switching speeds should be in the nanosecond range. The deposition
technique should be Compatible with standard semiconductorprocessing.
We have chosen PZT Pead &conate titanate) as the p r e f e d ferroelectric
material. PZT satisfies all of the above requirements.
PZT can be deposited in thin Blm form in various ways. Methods reported
in the literature include Sol-Gel processingY MOD (Metallo-organic
deposition)l*l. Chemical Vapor Depositionlgl. and SputterhgJM
We have chosen RF Magnetron Sputtering from a single ceramic target as
the preferred method of deposition mainly because it is compatible with
standard CMOS processing and offers excellent control of Blm thickness,
stoichiometryand adhesion to the electrodes.
Ferroelectric processing using PZT as the base material is a true add-on
technology to standard semiconductor processes. Figure 4 shows how it is
integrated into a standard CMOS process. The bottom electrode, the PZT
layer and the top electrode are placed on top of the underlying CMOS
circuitry before Source/Drain/Gate contacts are cut and before the
interconnect (e.g. Aluminum) technology is applied. From one to three
additional masking operations are required depending on how exactly the
ferroelectric technology is integrated with the standard process. Since the

12w

800

,:
aoo

Figure 4. Integrationinto CMOS

-1200

-1600

nw (mi

Figure 3b FerroelectricCapacitor
If however. the dipoles are oriented in the opposite direction. a larger current
pulse is generated that is the sum of the charging current of the capacitor
and the switching current caused by flipping the dipoles in the opposite
direction. A logic 0or 1can be detected dependingon whether or not the
switching current due to the change of dipole orientation is present. In
other words, the diflerencebetween switched or non-switched charge is the
signal charge which is sensed in a fashion similar to DRAMS. Therefore,
similar to the operation of a dynamic RAM. reading a ferroelectric capacitor
is always destructfve and the information has to be written back to the
device after every read cycle. In contrast to the ferroelectric Field Effect
Transistor, the ferroelectric capacitor is not sensitive to mobile charge
movement. The information is preserved even after the device is fully
compensated and the voltage across the device has decayed to zero. The
alignment of the dipoles is not altered and can be detected by pulsing the
device. Figure 3b illustrates the read/write operation of the device where
four voltage pulses are applied to the device and the current response is
plotted as a function of time. Thls data was obtained from a capacitor
employingPZT (lead zirconate titanate) as a ferroelectric materlal.
Several important features are evident from Figure 3b. First. the switching
time is very short. The current pulses have decayed to zero in less than
80ns. It will be shown later, that most of the time delay is caused by
parasitics and inadequate instrumentation. The Inherent switchingtime of
PZL is of the order of Ins. Secondly. the signal charge. which is the area
between N and D or P and U is large, of the order of 15pC/cmz.Thls renders
the technology highly scalable. As wlll be shown later, in a dynamic RAM
implementation,a Ixlp ferroelectric capacitor will develop a bit line voltage
differentialof about 2OOmv, which is well abve the detectionlimit.

=.

Of the many hundreds or even thousands of known ferroelectric mate-.

only few are suited for switching applications and can be integrated into a
semiconductor technology. To be commerciay. feasible the femelectric
material has to have good retention and endumce. adequate dielectric
breakdown for submimu layers. a coercive Beld compatible with h e volt

signal charge per unit area is very large. it is feasible to aggressively scale
the lateral dimensions and integrate the ferroelectric capacitor essentially
within the contact hole of an MOS transistor as shown in Figure 5a. Using
a one bsistor/one capacitor cell, as shown schematicallyin Figure 5b.
would allow a nonvolattle static RAM to be built with a density that is better
than that of a DRAM.

Figure 5a Advanced FRAM Cell

PUlSED COMMON P U T E
(UJRIZONTALOR VERTICAL)

Flgure 5b. Advanced FRAM Cell

N.

The basic ferroelectric memory element can be implemented into a

memory design in various way?. As mentioned before the early attempts all
tried to emulate the magnetic core memory by using a crosspoint array
matrix as shown in Figure 2. Although thls approach would yield a very
dense memory array it failed because of the lack of a well dehed and stable
coercive voltage.
The solution to the above problem is to add a switch to every memory
element and thus Isolate the nonselected bits from the addressing pulses.

1-21

The densest implementation uses one Transistor and one Capacitor per bit
(lT/lC), as shown in Figure 5b. The memory architecture chosen to
implement this cell is nearly identlcaltoa standard DRAM archltecturewith
the exception, that the bottom electrode of the capadtor is pulsed instead of
grounded or tied to.,V
A reference such as a dummy cell has to be
provided for the differential sensing. A mre conservattve approach that
relaxea the process control requi"ents is given in Figure 6 whlch uses a
cell with two Transiston and two Capadtors per bit (2T/2C).
MUlElRUE

W W E OQlPLEUENT

RITE
FERROELECTRIC CAPACTTOR

Figure 6. I\voTransistor/Two Capadtor Memory Cell

Data Is written to the cell by pladng truelcomplemnt data on the bit

h a , selectinga spec& cellby activating the word line pass transistorsand
by pulsing the plate enable to p o h the krmelectric capacitor. Data is
read from the " o r y by selecting the word line and latching the data on
the bit b.
This information Is then output on the Dm pin (see Figure 8).
Since this is a destructke read out, the information Is restored to the
memory cell by pulsing the plate enable prior to the end of the operation.

As a demonstration vehicle, we have designed and fabricated a 256 bit

FRAM,the FMx 8101. empbylng a two bansistor, two ferroelectric capacitor
memory cell structm as shown in Figure 6. A chip photograph and a block
diagram are @en in Ffguree7and 8. respe&wly. As win be shown later,
one of the present limltatlons is the 6nite number of read cycles permitted.
In some applications. the m m r y would fatigue before it has h e d its
useful life. To elimtnate this problem the FRAM can be operated in a
nonvolatile DRAMmode. In thismode the plate enable line (Figure 6)Is not
actlvated and the data is stored by charghg the kmlectrlc capadtor,
which acts as a hlgh dielectric constant standard capacitor. This charge
by reading the
must be "shed pe&ddly (e.& every f o w " d s )
cell to prevent data loss. Data is read by selecting the word h e and
transthe charge to the bit line data latch, At the end of the operation
the charge is restored tothe cell. &wbingitsdata. Slnce in this mode the
ferroelectric capadtor Is not pohlzed. n o d &/write does not impact
the ferroelectric cell endurance. However.prior to power down all rowsof the
memory are read in the nonvolatile FRAM mode to polarize the ferroelectric
elements and thus saving the m m r y contents in a nonvolatile fashion.
Because of the hlgh dielectric constant of m,which we measured to be
about 1OOO-1500. it seems feasible to build very high density nonvolatile
DRAMS (e.g. QMbit, 16Mbit and beyond) without having to resort to
complicated trench processing.

v.

Figures 9 and 10 present some expertmental results measured on 256 bit

FRAMs and corresponding test capadtors. One of the most intxlguing
results obtained Is probably the e&tmely East intrinsic switching speed of
the memory device. For all practical purposes the access tlme of the
memory devlce Is given by the bask parameters of the underlying CMOS
process. We have attempted to isolate the intrinsic switching ttme of the PZT
layer and belleve that it Is in thevidnityof Ins.
of PZT has m t l y been described
A theory of the switching
by Scott et al. 1111 who based their work on a model first described by
Ishibashi.1111 The model assums that the switching process is initiated by
local nucleation followed by forward and sideways domain growth. It Is also
assumed that the rate of nucleation is a constant throughout the switching
process. Fitting the experireental switching data to this model yields an
activationBeld of order 12OKV/cm at mom temperature and switching Umes
in the nanosecond range.

Flgure 7. FMx 8101

20

nn

I5
U
10

5
0

5
M-A+

-10
-1 5

-20
_.

10

50

I-=(

"i"

Flgure 9. Switched and Non-Swltched Charge vs. Time Curves

of a 100 x lOOp Ferroelectric Test Capacitor

Figure 8. FMx 8101 Block Diagram

1 - 22

56

40

16
8

1E7

1E8

1E9

NUMBER Of CYCLES

Figure 10. Polarization Charge as a Function of ' Fatigue Cycles

VI. !a!su!m
The ferroelectrictechnology based on
as the ferroelectric material and
combined with a standard semiconductor technology offers the potential to
become the "ideal" nonvolatile memory technology. It has been
demonstrated that the technology is highly scalable and offers extremely fast
intrinsic switching speeds. Nonvolatile semiconductor memories with the
speed of Static RAMSand the density and cost of DRAMS should be feasible
in the near future.

Refenncee
[ID. Valasek, Phys. Rw. U.475 (1921).
12M.R Anderson,Trans.Amer. Inst. Elect. Engrs.. part 1.395 (1952).
131D.S. Campbell,J. Brit. [.RE..
E,395 (1957).
I4lW.J. Men and J.R Anderson. Bell Lab Records, 335 (Sept. 1955).
151RA. Dork. N.W. Schubringand J.P. Noh. J. Appl. Physics, p,1984
(1964).
161J. Schulz. St. Koch, P. Wurfel. W. Ruppel. to be published in J. of
Ferroelectrics.
I7lKD. Budd, S.K. Dey and D.A. Payne. Brit Cer. Proc.
107 (1985).
I8lFbbertW. Vest and Jiejie Xu. to be published.
19jl'aichi Nakagawa. Jim Yamaguchi. Masanoji Okuyama and Nishihiro
Harnakawa Jap. J. of Appl. Phys.. Vol. 2.No. 10. 655 (1982).
[lO]S.B.Krupanidhi. N. Maffel. M. Sayer and K El-Assal. J. Appl. Phys.,
Vol. 54, No. 11, 6601 (1983).
[111J.F.Scott. L. Kammerdher,M. Parrls. S.Traynor. V. Ottenbacher.A.
Shawabkeh. and W. F. Oher, J. Appl. Phys., (2). 787 (1988).
1121 Y. Ishibashiand Y. Takagi, J. Phys. Soc.Jpn. 3,506 (1971);Y.
Ishibashi, Jpn. J. Appl. Phys., 24, 126 (1986).

a.

s,

1 - 23