Flexible Hybrid Electronics:

System Design & Reliability

Next Generation Flexible Hybrid Health Monitoring Devices
SEMICON West
13 July 2016

Proprietary Information
1
 FHE Health Monitoring Programs

FCB Print Design & Layout FleX-IC Design & Fabrication

FHE Integration FHE Integration

Power

Amplified Signal
Signal
Ground
FHE Circuit Design FHE Circuit Design
FCB Layout FCB Print Design & Layout
Sensor
10101101
FHE Integration
FleX- FleX-
OpAmp MCU
ADC

2016 American Semiconductor, Inc. All rights reserved. 2

 Solving FHE
Design Flow Challenges
Flexible Circuit Boards (FCBs) are similar in function to PCBs
The current FCB layout to fabrication data flow presents known challenges
Even with the issues identified and in mind, the data flow is difficult
Additional design considerations include printed devices, e.g. passives & TFT devices

PCB Data Flow Printing Data Flow

PCB Gerber PCB Graphics Graphics Printing

Layout SW Data File Fabrication Layout SW Data File

Current FCB Data Flow

Drawn
PCB Gerber Graphics Graphics FCB
Printed
Layout SW Data File Data File Layout SW Fabrication
(21% delta)
Desired FCB Data Flow

PCB Gerber FCB

Layout SW Data File Fabrication
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 FCB Fabrications
Multiple Suppliers & Materials
Vendor A: 4 mil (100um) lines on PET
13 web backside substrate scratches due to rollers, cosmetic only
Printed trace width: 175um
Trace resistance: 40 MCU pad to ZIF

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 FCB Fabrications
Multiple Suppliers & Materials
Vendor B: 4 mil (100um) lines on PET
18 x 32 sheets
Printed trace width: 160um
Trace resistance: 23 MCU pad to ZIF

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 FCB Fabrications
Multiple Suppliers & Materials
Vendor B: 4 mil (100um) lines on Ultem
18 x 32 sheets (no scratches on backside of substrate)
Printed trace width: 160um
Trace resistance: 22 MCU pad to ZIF

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 FCB Fabrications
Multiple Suppliers & Materials
Vendor B: 4 mil (100um) lines on Etched PET
18 x 32 sheets (no scratches on backside of substrate)
Printed trace width: 100um
Trace resistance: 23 MCU pad to ZIF

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 Thin Devices

Flexible Electronics present a new opportunity for semiconductor industry

Challenges
Availability FHE low volume and IDMs are unlikely to support
Grind Edge Damage
Die thinness targets are still in flux With edge trim Without edge trim
Conventional die challenges
Wafer/die handling
Die cracking/chipping
Singulation methods
Blade, Laser, Stealth, DBG Images Courtesy of Disco Hi-Tec America

Reliability / mechanical robustness

New unknowns due to flexibility Dicing Edge Damage
Small Grit (#4800) Typical Grip (#2000)
Emerging Technology Solutions
FleX Silicon-on-Polymer Ultra Thin Die
Thin device integration methods
Thin device / FHE reliability test procedures

Images Courtesy of Disco Hi-Tec America

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 Key Technology
Enabling FHE Products
Thin device singulation has been identified as a serious challenge
Thin (ex: 50um) conventional die have been reported to chip or fracture when diced
Laser singulation has been evaluated as an alternative, but slag issues persist
Dice before grind has been suggested to resolve conventional thin device singulation

FleX Silicon-on-Polymer device singulation has been resolved

Tape mount, saw, and vacuum pick have been demonstrated with good results
Chipping and fracturing at wafer saw is NOT a problem for FleX Silicon-on-Polymer technology
Development of Tape and Reel or equivalent packaging for assembly is in progress

No edge chip or
fracture on SoP
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 FleX Commercial
Silicon-on-Polymer Process
Silicon-on-Polymer (SoP) is a Thin Device technology to
convert single crystalline foundry wafers into flexible thin devices.
FleX SoP-SOI FleX SoP-Bulk
Technology: TowerJazz CS18/13 PD-SOI CMOS to be announced
Devices: FleX-ADC, FleX-MCU, FleX-OpAmp, to be announced
Interconnect: 4-level Aluminum to be announced
Flexibility: <5mm Radius of Curvature to be announced FleX: 200mm CMOS 180nm Wafer

Polymer & Bond Pads Polymer & Bond Pads

Polymer & Bond Pads Circuitry Circuitry
Circuitry Polymer & Bond Pads
Circuitry
SOI Substrate
Polymer
SOI Substrate Polymer

Standard CMOS Wafer Handle Silicon Removed Polymer Substrate Applied SoP Wafer

Polymer & Bond Pads Polymer & Bond Pads

Circuitry Circuitry
Bulk Substrate Bulk Substrate Polymer & Bond Pads
Polymer & Bond Pads
Circuitry Circuitry
Bulk Substrate
Bulk Substrate
Polymer
Bulk Substrate Polymer

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 IC Materials Delayering Analysis
Per ASI Procedure TEST007

Scanning Electron Microscope (SEM) inspection based upon MIL-STD-883K, Method 2018.16
Layer by layer deconstruction analysis of all passivation and all 4 metal layers
The purpose of this analysis is to look for cracking, delamination, or other visual defects
Six thin, flexible FleX-ADC die, AS_ADC1003.fxd, used for analysis
RESULT: PASS. No defects attributed to the FleX SoP process.
Expected result, consistent with functional testing of FleX-ICs before and after FleX conversion

Industry first: FleX-IC SEM reliability testing

Layout View
Layout view as designed and sent for manufacturing
Metal 4 (top metal) in purple dominates the image

SEM Image Top Polymer

Exposed surface shows particles and cosmetic surface
scratches from sample prep
No delamination, cracking, or unexpected visual defects

Layout View - Passivation SEM Image

2016 American Semiconductor, Inc. All rights reserved. 11

Layout View
2016 American Semiconductor, Inc. All rights reserved.
IC Materials Delayering Analysis
ASI Procedure TEST007 Results
Layout View M4
Metal 4 waffle dummy fill are only features in this image
SEM Image Top Polymer
No delamination, cracking, or visible defects
Waffles appear denser than layout view due to thickness
of conformal polymer coating
Exposed surface shows particles accumulated on the
wafer surface normal for material handled in open
environment
SEM Image
Layout View M3 & M4
Metal 4 (purple) is deposited on planar interlayer
dielectric over Metal 3 (orange)
SEM Image - Oxide-Nitride Passivation
Passivation layer is a thin conformal coat over Metal 4
No delamination, cracking, or visible defects
Waffles appear denser than layout view due to thickness
of passivation layer
Metal 3 can be seen below the transparent interlayer
dielectric
12
 IC Materials Delayering Analysis
ASI Procedure TEST007 Results

Layout View M3 & M4

Metal 4 (purple) is deposited on planar interlayer dielectric
over Metal 3 (orange)
SEM Image Metal 4 (Top Metal 2.8um thick)
No delamination, cracking, or visible defects
Metal 3 is faintly visible through the interlayer dielectric

Layout View SEM Image

Layout View M2 & M3
Metal 3 (orange) is deposited on interlayer dielectric over
Metal2 (gray)
SEM Image - Metal 3 (0.52um thick)
No delamination, cracking, or visible defects
Metal 2 is barely visible through the interlayer dielectric

2016 American Semiconductor, Inc. All rights reserved. 13

 IC Materials Delayering Analysis
ASI Procedure TEST007 Results

Layout View M2 & Via2

Via2 (dark gray) and Metal 2 (light gray) are the features
visible in this image
SEM Image Metal 2 (0.52um thick)
No delamination, cracking, or visible defects
A few metal 1 fills are visible at the top center of the image
through dielectric

Layout View SEM Image

Layout View M1 & Via1
Via1 (gray) and Metal 1 (blue) are the features visible in
this image
SEM Image - (bottom metal - 0.52um thick)
No delamination, cracking, or visible defects

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 IC Materials Delayering Analysis
ASI Procedure TEST007 Results

Examples of defects unrelated to the FleX Silicon-on-Polymer wafer processing

Narrow metal 2 line was damaged by

plasma-induced charging during the Irregular shaped defect in passivation
SEM analysis consistent with in-fab induced particles

SEM Image Metal 2 SEM Image Passivation

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 FHE Reliability Testing
FleXform-ADC Development Kit
Radius of Curvature Testing
Robotics system used to dynamically flex the FHE
system around a 15mm radius mandrel
Continuous electrical testing
Sample 1 10K cycles convex followed by 13.6K
cycles concave without failure
Sample 2 11K cycles concave followed by 15.8K
cycles convex before first failure
Failure due to crack in the silver flake conductive
adhesive used for interconnect on the VDD line
Sample would still function if stress applied to
bridge the crack

Torsion Testing
Robotics used to rotate the sample 60 or 90
degrees
Continuous electrical testing
Sample 3 10K cycles of 60 degrees followed by
92K cycles of 90 degrees before failure
Failure mode indicates a crack in the silver flake
conductive adhesive
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 ESD Testing
Per ASI Procedure TEST010

FHE test procedure adapted from ANSI-ESDA-JEDEC_JS-001 and JS-002

TEST 1 Rigid, Full Thickness Die
Six AS_ADC1004.pkg packaged ADCs using full thickness die wire bonded to the lead frame
Pre- and post-stress functional testing
Pin leakage testing
RESULT: Passed both 2kV and 4KV human body model (HBM) testing

TEST 2 Thinned, Flexible Silicon-on-Polymer Die

Three AS_ADC1004.fxd FleX-ADC die mounted to PET substrates, inserted into packages and connected to
the lead frame using conductive epoxy
FHE system mount designed to accommodate industry standard ESD test equipment and methodologies
Pre-stress functional testing completed
FHE parts in process for 4kV HBM testing

Industry first: FHE ESD reliability testing

2016 American Semiconductor, Inc. All rights reserved. 17
 Flexible ICs Today

SoP FleX-ICs
FleX-OPA1 Dual General Purpose Opamps (AS_OPA1) NOW!
FleX-OPA2 Quad General Purpose Opamps (AS_OPA2) Q3 2016
FleX-OPA3 Quad High Performance Opamps (AS_OPA3) Q4 2016
FleX-OPA4 Quad Output Transconductance Amps (AS_OPA4) Q4 2016
FleX-ADC1 8-channels, 8-bits (AS_ADC1) NOW!
FleX-ADC2 ADC with 3 Configurable Opamps (AS_ADC2) Q4 2016
FleX-MCU1 8-bit PIC Microcontroller (AS_MCU1) Q2 2016
Bend it, shape it, FleX-MCU2 Microcontroller with ADC (AS_MCU2) Q4 2016
anyway you want it, FleX-SoC System-on-Chip Q4 2016
a FleX chip makes for FleX NVM High performance flexible memory In Development
limitless possibilities FleX Display Driver In Development
in FHE.
Thin / Ultra-Thin Conventional ICs
Thin wafers from just a few microns to full thickness
Customer Supplied Wafers NOW!
Standard Products In Development

2016 American Semiconductor, Inc. All rights reserved.

 Thank You
Thank You
American Semiconductor Boise HQ
FleX-IC & FHE Manufacturing Facility

American Semiconductor, Inc.

6987 W Targee St
Boise, ID 83709
Tel: 208.336.2773
2016 American Semiconductor, Inc. All rights reserved. American Semiconductor is a registered trademark of American Semiconductor,
Fax: 208.336.2752
Inc. FleXform, FleXform-ADC, FleX, Silicon-on-Polymer, FleX-ADC, FleX-MCU and FleX-IC are trademarks of American Semiconductor, Inc. www.americansemi.com