Checks in Netlist:

1) Number of Output Pins connect to Power/Ground

2) Number of Inst with input pins tied together
3) Number of TiHi/Lo terms nets not connected to instances PG terms
4) Number of Input/InOut floating pins
5) *Number of Output floating pins
6) *Number of Output floating nets
7) Number of nets with tri-state drivers
8) Number of nets with Parallel drivers
9) Numbers of nets with multiple drivers
10) Number of High Fanout nets
11) Number of nets with no drivers
12) *Number of cells of input netlist marked don’t use.
13) *Verify netlist is Unique.
14) *Check the assign statement.
Check in Physical Library
1) Cell with PG PIN missing
2) Cells with missing dimension
3) Cells pin with missing direction
4) Cells pin with missing geometry
5) Cells PG pin with missing geometry
6) Cells with missing LEF
Check in timing Library
1) Checks whether the cells used in the design have been defined in the timing library.

2) If multiple delay corners are being analyzed then each cell needs to be characterized
for each corner
Check timing constraint file (SDC)

1) Clock reaching all clock pins of flops.

2) Ports missing i/p and o/p delays.
3) Ports missing slew/load constraints.
4) Multiple clocks driving same register.
What is the error if one cell missing LEF and present in netlist
EX: MX2X1
Warning : MX2X1 has no physical library or has wrong dimension values
Related Instance has no physical library or has wrong dimension value.
What is the error if one cell missing (.lib) and present in netlist
Ex MX2X1
ERROR: cell ‘MX2X1’ is not defined in all timing analysis view.
The cell should be defined in all analysis views.
ERROR: some cells are missing from each of the timing analysis views. Please check the library finding of
instances in active views using the command “check_instance_library_in_views” and set the missing in
corresponding views
“”””””LibraryMisMatchError””””””””””””””””””””
What is the error if “create_clock is not defined” in SDC?
No constrained timing path found.
Design may not be constrained or library is missing timing information.
** I was found this error in report _timing
What is the error if footprint is not defined in .lib?
no warning or no error is displayed.
What is the error if a PIN miss in LEF?
Combinational cell: no pin placement (** but pin is at orientation)
Sequential cell: pin is getting placed but no connectivity is being established.
*******observed in routing stage
*Why we don’t have assign statements in netlist
In hierarchy if we want to connect from one output of the cell to input of another cell we need a assign
statement
In flat design we directly connect from on cell to another cell

What will happen when the assign statement in the netlist?

Tool will do temporary buffers to remove assign statements
** Done with setDoAssign with 22 assigns removed.
** at stage place in Floorplan mode.
What is the error if tech.lef not loaded first.
ERROR: No technology information defined in the first lef file