University of Bahrain

College of Information Technology

Department of Computer Engineering

ITCE362: Computer Architecture

Experiment No. 2
Register File Design

Name: Halima Mohamed Ismail Alturabi

ID: 20133684
Sec NO:1
Date of submission: \ \
 Objective:
In this lab you will design a small register file in VHDL and verify it by functional simulation.

Introduction:
Computer architecture is defined as the science and art of selecting and interconnecting hardware
components to create computers that meet functional, performance and cost goals. Data path
which’s the part of the CPU where data signal flow is one of the factors affecting computers
performance. Register files are part of the data path for any CPU which needs to be designed
accurately. Register files are generally fast RAMS with multiple read and write ports. In Memory
Builder, to build a register file you need to specify two parameters for the size of the register file,
word (the number of the words) and bpw(bits per word).

Equipments Required:

 Xilinx ISE 6.1 i

 ModelSim XE II

Procedure and results:

1. Write the VHDL code for the above circuit supposing that the
entity of the register file module is:

entity regfile is
port (clk, wr_en : in std_logic;
A_add, B_add, WB_add : in integer range 0 to 3;
WB : in std_logic_vector(7 downto 0);
A, B : out std_logic_vector(7 downto 0));
end regfile

Hint: The registers in the register file can be declared using an array. Then you can declare a
signal using that 'type', for example:
type reg_array is array(3 downto 0) of std_logic_vector(7 downto 0);
signal myreg : reg_array;
2. Write two processes in VHDL where one of them is responsible for reading from the register file
while the other control the writing operation.
3. Synthesize your code and make sure it has no syntax errors.
4. Show the RTL schematic for your circuit (up to 2 Levels).

5. Do functional simulations for your code by writing to all registers different data and then read
them all to verify that the writing operation done successfully. Follow the table below:

Clock cycle 1 2 3 4 5 6

Write to Write to Write to Write to Read Read

Operation register R0 register R1 register R2 register R3 registers registers
“0” “1” “2” “3” R0 and R1 R2 and R3
Discussion:

1. Design a new circuit in which you will connect the ALU circuit from Experiment(1) to the
register file you designed in this experiment. The values for the two input operands in the ALU
(A and B ) will be read from the register file while the output of the ALU circuit (R) will be
stored in the register file as well. The new circuit will receive as an input the addresses of
operands A and B on which the ALU will operate as well as the address of R in which the result
will be stored. Additionally, the circuit will receive a fourth input (op) to indicate the operation
type, while the fifth and sixth inputs will be wr_en and Clk. As an output the value of R will be
read from the register file. Simulate your circuit using the following data:

A_ad 0 2 0 2
B_ad 1 3 1 3
WB_ad 2 3 1 0
oper 0 1 2 3
wr_en 1 1 1 1

The entity, architecture, and signals necessary to run your code are:
entity ALU_REG is
Port ( A_ad : in integer range 0 to 3;
B_ad : in integer range 0 to 3;
WB_ad : in integer range 0 to 3;
oper : in std_logic_vector (2 downto 0);
Clk : in std_logic;
wr_en : in std_logic;
Rout : out std_logic_vector(7 downto 0));
end ALU_REG;
 architecture Behavioral of ALU_REG is
type reg is array(3 downto 0) of std_logic_vector(7 downto 0);
signal my_reg: reg:=("11111111", "00000000", "11110000", "00001111");
…………..
begin
read: process (A_ad, B_ad, Clk)
begin
……………
end process;
write: process (WB_ad, Clk, WB_val, wr_en)
begin
………….
end process;

alu: process (Clk, oper, A_val, B_val)

begin
………….
end process;
………………
end Behavioral;

Please note that you may need to define more signals.

Conclusion :
At the end un this experiment we design a small register file in VHDL and verify it by functional
simulation. Register files are part of the data path for any CPU which needs to be designed
accurately. Register files are generally fast RAMS with multiple read and write ports . then we
design new circuit which connect the ALU circuit from Experiment(1) to the register file.
There was no difficulties in this experiment .