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Design of Gilbert Cell in CMOS Technology: Pulse Wideband Multiplier

Conference Paper · December 2008

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 9th International conference on Sciences and Techniques
of Automatic control & computer engineering

Design of Gilbert Cell in CMOS Technology: Pulse

Wideband Multiplier
Mohamed DHIEB1, Mongi LAHIANI1 & Hamadi GHARIANI1

1Laboratory of electronics and information technologies (LETI) ENIS, BP W, 3038 SFAX,

TUNISIA.
E-mail: dhieb_mohamed@yahoo.fr

Abstract. In ultra-wide band (UWB), the receiver includes a correlator, which

is the basic component for UWB signal detection and demodulation. The corre-
lator constituted of two components: the multiplier (allowing the signal to its
Square) and the integrator. Thus, the signal of demodulation in UWB is result
of multiplying received signal to reference (UWB impulse) or to itself (UWB
MB-OOK ‘MBOOK: Multi Band On Off Keying’), then we Integrate the re-
sulting product in the correlation. In this paper we propose a multiplier pulse
circuit based on the Gilbert cell and designed by 0.35μm AMS technology.
Thereafter we present the simulation results of this circuit, to show the theory
of UWB signal receiver.

Keywords: correlator, ultra wide band (UWB), multiplier, integrator

1. Introduction

One of the fundamental blocks in analog circuit design is the analog multiplier. Mul-
tipliers are particularly important in communication and signal processing circuits.
Some of advancements in biomedical devices are low power multipliers for portable
battery, power applications are also becoming increasing important [1]. Most multi-
plier architectures were originally developed in bipolar technology, where signal
distortion can be kept low across a wide range of frequencies [2, 3]. As digital design,
analog and digital circuits can be designed with a single technology. To meet mixed
signal and low power needs, development of CMOS multiplier architectures was
evolved [1]. In Ultra-Wideband (UWB) communication technology, the detection of
received signal is obtained by correlation [4, 5, 6]. A correlator consists of followed
function: multiplication, square and integration of signal. But for UWB, the correla-
tion must have very large bandwidth [7, 8, 9].
In this paper we present our devise based on a multiplier circuit with large bandwidth
typical of Gilbert cell in four simulations. This structure provides the function of pure
multiplication. It doesn’t use nonlinear function to generate the increase, as happens
in most mixers. Each of the two voltages at the input of the structure can have posi-
tive or negative polarity. We’ll now propose a new structure based on CMOS transis-
tors technology 0.35μm AMS and the results of this design.

STA'2008-IRM-476, pages 1-9

Academic Publication Center of Tunis, Tunisia
2. The Gilbert cell MOS technology

For our study, we worked on an extension of the original Gilbert cell. It consists of
MOS transistors provided by the AMS 0.35μm technology in place of bipolar transis-
tors. CMOS technology is better suited for digital circuits than bipolar technology due
to its low processing cost and low power consumption. However, reaching the level
of nonlinear error that bipolar multipliers can achieve is difficult in CMOS technol-
ogy.
Its electrical diagram is shown in Figure 2. We propose first to study the characteris-
tics of a differential pair of MOS transistors with common source presented in Fig-
ure1:

Figure 1: Differential pair transistors to n-channel MOS

We assume that both transistors and resistors drain are identical, so we have:
Vin1 − Vgs1 + Vgs 2 − Vin 2 = 0 (1)

The drain current Id is linked to the voltage Vgs by the following equation:

⎛ Vgs ⎞
2 (2 )
I d = I DSS ⎜1 − ⎟⎟
⎜ V
⎝ p ⎠

Vgs ⎛ Id ⎞ (3 )
= ⎜1 − ⎟⎟
Vp ⎝⎜ I DSS ⎠
With Vp is the clamping voltage of the transistor and IDSS is the during saturation
drain. From équations (1) and (3), we get:

Vin1 − Vin 2 I Id 2 (4 )
= − d1 +
VP I DSS I DSS

The Iee current is given by the addition of node current in the reveals source:
I d 1 + I d 2 = I ee (5 )

By combining equations (4) and (5), we get:

 ⎡ (6 )
⎞ ⎛ I DSS ⎞ ⎥⎤
2 2
⎛I ⎞ ⎛ Vin
= ee ⎢1 + in
I V
I d1 2 ⎜ DSS ⎟ − ⎜⎜ ⎟⎟ ⎜ ⎟ ⎥
2 ⎢ Vp ⎝ I ee ⎠ ⎝ Vp ⎠ ⎝ I ee ⎠ ⎦⎥
⎣⎢

⎡ (7 )
⎞ ⎛ I DSS ⎞ ⎥⎤
2 2
I ee ⎢ Vin ⎛I ⎞ ⎛ Vin
Id 2 = 1− 2 ⎜ DSS ⎟ − ⎜⎜ ⎟⎟ ⎜ ⎟ ⎥
2 ⎢ Vp ⎝ I ee ⎠ ⎝ Vp ⎠ ⎝ I ee ⎠ ⎥⎦
⎢⎣

With Vin = Vin1 − Vin 2

The output differential pair voltage VS is written as follows:
VS = VS 1 − VS 2 = − ( I d 1 RD − I d 2 RD ) (8 )

By replacing (6) and (7) in (8), we get:

2 2 (9)
I R ⎛I ⎞ ⎛ Vin ⎞ ⎛I ⎞
VS = − ee D Vin 2 ⎜ DSS ⎟ − ⎜⎜ ⎟⎟ ⎜ DSS ⎟
Vp ⎝ I ee ⎠ ⎝ Vp ⎠ ⎝ I ee ⎠
In saturation, the current expression of Id becomes:

I d = k (Vgs − Vt ) (10)
2

μn Cox W (11)
k=
2 L
With: Vt is the threshold voltage, µn is the mobility of electrons, Cox is the capacity of
the grid per area unit, W is the width of the transistor, L is the length of the transistor
and k is the setting transconductance gm:

I d1 − I d 2 I W (12)
gm = = out = 2 μ n Cox I D = 4kI D
Vin1 − Vin 2 Vin L

When the two transistors, T1 and T2, are identical, is the transconductance gm = gm1 =
gm2 which gives the following equations:
gm (13)
I d1 = Vin
2

gm (14)
I d 2 = − I d1 = − Vin
2
Using (13), (14), (6) the (7) can be rewrite as follows:
 2 (15)
k⎛ I V2 V ⎞
I d1 = ⎜ ee − in + in ⎟
2 ⎜⎝ k 2 2 ⎟⎠

2 (16)
k⎛ I V2 V ⎞
Id 2 = ⎜ ee − in − in ⎟
2 ⎜⎝ k 2 2 ⎟⎠

The expression of Iout is given by:

2 I ee (17)
I out = I d 1 − I d 2 = kVin − Vin2
k
The equations (15), (16) and (17) are valid if the input voltage is:

I ee I ee (18)
− ≤ Vin ≤
k k
Dynamics of input is limited by the nonlinearity of input pair of all differential pairs,
Figure 2 illustrate the electrical diagram of the Gilbert cell MOS version:

Figure 2: Diagram of the Gilbert cell version of MOS.

We assume that the MOS transistors operate in saturation mode. We get to the output:
I out = I d 7 − I d 8 = ( I d 3 + I d 5 ) − ( I d 4 + I d 6 ) = ( I d 3 − I d 4 ) − ( I d 6 − I d 6 ) (19)

Using the result in (15), (16) and (17), then Iout can be written as follows:
⎡ 2 2 ⎤ (20)
⎛ I VY2 VY ⎞ ⎛ I VY2 VY ⎞
I out = kVX ⎢⎢ ⎜ SS
− + ⎟ − VX − ⎜
2 SS
− − 2 ⎥
⎟ − VX
⎥
⎜ k 2 2 ⎟⎠ ⎜ k 2 2 ⎟⎠
⎢⎣ ⎝ ⎝ ⎥⎦

With VX and VY is input voltages applied to the two differential pairs.

By limiting the level of input voltages, the equation (20) becomes:
 ⎡ 2 2 ⎤ (21)
⎛ I VY2 VY ⎞ ⎛ I VY2 VY ⎞ ⎥
I out = kVX ⎢⎢ ⎜ SS
− + ⎟ − ⎜ SS
− − ⎟
⎜ k 2 2 ⎟ ⎜ k 2 2 ⎟ ⎥
⎢⎣ ⎝ ⎠ ⎝ ⎠ ⎥⎦

I out = 2kVX VY (22)

Thus we get the operation of multiplication.

3. Design and simulation of the multiplier using MOS technology

After the theoretical analysis of the original Gilbert cell and its extension MOS tech-
nology, we present the results of design and simulation of this multiplier circuit based
on the Gilbert cell MOS technology. The basic scheme of circuit design is presented
in Figure 3.

TRANSIENT

Tran V_DC
Tran1 R R Vcc
StopTime=3 nsec Rc RC
MaxTimeStep=10 psec

ams - C35 Vs1 Vs2

Set
Model
Path

ModelPathInclude
ModelPathInclude

Ve1
VtPulseDT
V1
nmos4 nmos4 nmos4
DT T3 T4 T5 nmos4
T6

Ve2

nmos4 nmos4
VtPulseDT T1 T2
V2
DT
I_DC
Iss

Figure 3: Basic multiplier design.

We use a current mirror as a source of ISS current designed in Figure 3. At the input,
we apply the UWB signals previously modeled on the ADS software. As the multi-
plier is used to receiver block, then it is the UWB signal reception modeled as the
second derivative of Gaussian pulse. The output is taken between Vs collectors T3
and T6 via a differential pair of transistors connected to collectors T3 and T4. Rc is
the load impedance, for this circuit Rc = 1000Ω. VDC is the voltage bias, for our cir-
cuit Vcc = 2.5 V. Icc is the source of power for this circuit Icc = 2.4 mA. The design
of the circuit use 0.35μm AMS components.
The multiplier circuit was designed simulated in the time domain under the ADS
software. The results of simulations are presented below in Figure 4 and 5:
 First input signal First input signal

m1 m1
time=2.107nsec 200 time=2.016nsec
600
Ve1=515.1mV m1 Ve1=-567.7mV
500
0
400

Ve1, mV
Ve1, mV

300
-200
200

100 -400
0 m1
-100 -600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

time, nsec time, nsec

Second input signal Second input signal

m2 m2
500 time=2.108nsec m2 200 time=2.016nsec
Ve2=471.5mV Ve2=-550.1mV
400
0
300
Ve2, mV
Ve2, mV

200 -200

100
-400
-0 m2
-100 -600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

time, nsec time, nsec

Output signal Output signal

m3 m3
time=2.108nsec time=2.108nsec
Vs2-Vs1=0.671 m3 Vs2-Vs1=0.671 m3
0.8 0.8

0.6 0.6
Vs2-Vs1
Vs2-Vs1

0.4 0.4

0.2 0.2

0.0 0.0

-0.2 -0.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

time, nsec time, nsec

Figure 4: Multiplication of two signals of the same polarity.

 First input signal First input signal

m1 m1
200 time=2.016nsec time=2.107nsec
Ve1=-567.7mV
600
Ve1=515.1mV m1
500
0
400
Ve1, mV

Ve1, mV
300
-200
200

-400 100
m1 0
-600 -100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
time, nsec time, nsec

Second input signal Second input signal

m2 m2
500 time=2.108nsec m2 200 time=2.016nsec
Ve2=471.5mV Ve2=-550.1mV
400
0
300
Ve2, mV
Ve2, mV

200 -200

100
-400
-0 m2
-100 -600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

time, nsec time, nsec

Output signal Output signal

m3
0.2 time=2.107nsec m3
Vs2-Vs1=-0.669 time=2.108nsec
0.2
0.0 Vs2-Vs1=-0.671
0.0
Vs2-Vs1

-0.2
Vs2-Vs1

-0.2
-0.4

-0.6
m3 -0.4

-0.6
m3
-0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0
-0.8
time, nsec 0.0 0.5 1.0 1.5 2.0 2.5 3.0

time, nsec

Figure 5: Multiplication of two signals with different polarity.

The above figures represent the results of simulation obtained by multiplying two
signals receiving UWB pulse in two cases: the same polarity and different polarity.
The multiplication is obtained by using the multiplier circuit designed based on the
Gilbert cell. In each figure, the first two curves represent both two input signals; the
third curve represents the resulted signal at the output of the conceived multiplier.
Figure 4 represents the multiplication of two signals having same polarity (positive or
negative). These signals are synchronized between them. At the output multiplier
designed, we get a positive peak and a positive product, as multiplication of two sig-
nals of the same polarity. But in the sixth curve, the output signal is the multiplication
of two signals with different polarity. We get to just after the negative peak multiplier
(which is a negative result). Then we can deduce that the circuit designed plays the
role of a multiplier of input voltages.
Based on the results of simulations presented above, we find that the multiplier get a
multiplication pulses applied to its two inputs, and if associated with a component
integrator ideal, it can correlate UWB signals. It can be tested for three types of
modulation: PPM (Pulse Position Modulation), BPM (Bi-Phase Modulation) (BPSK
"Bi-Phase Shift Keying modulation") and OOK (On Off Keying).

4. Conclusion

In this paper, we present this design of a multiplier circuit pulse in the time domain. A
multiplier is essential component of a UWB receiver, which is based on correlation,
demodulation or detection of coherent energy. Therefore, we studied and designed a
multiplier circuit based on 0.35μm AMS technology from the Gilbert cell. Thereafter,
we simulated this circuit separately to confirm its role as a multiplier. In both cases
simulation (and polarity and different polarity), the multiplier function of this design
was confirmed by the simulation results. It was showed and this circuit is working
correctly for the tow cases.

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