VLSI Design Verification and Testing Overview

Motivation

Logic Modeling
Logic and Fault Modeling  Model types

 Models at different levels of abstractions

 Models and definitions

Fault Modeling
 Why model faults?

Mohammad Tehranipoor  Some real defects in VLSI and PCB

Electrical and Computer Engineering Department  Common fault models

 Stuck-at faults
University of Connecticut

Single stuck-at faults

Multiple stuck-at faults
 Transistor faults
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Motivation Logic Modeling – Model types

 Models are often easier to work with

Behavior
 Models are portable
 System at I/O level
 Models can be used for simulation, thus
 Timing info provided
avoiding expensive hardware/actual circuit
 Internal details missing
implementation
 Nearly all engineering systems are studied
Functional
 DC behavior – no timing
using models
 All the above apply for logic as well as for fault
Structural
 Gate level description
modeling

• Models are often described using a hierarchy

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Hierarchical Model: A Full-Adder Modeling Levels

Modeling Circuit Signal Timing Application
HA; level description values
c inputs: a, b;
a Architectural
outputs: c, f; Function, Programming 0, 1 Clock and functional
e boundary
AND: A1, (a, b), (c); behavior, RTL language-like HDL verification
d f AND: A2, (d, e), (f);
Zero-delay
Logic Connectivity of 0, 1, X Logic
b OR: O1, (a, b), (d); unit-delay, verification
HA NOT: N1, (c), (e);
Boolean gates, and Z multiple-
flip-flops and and test
transistors delay

Switch Transistor size 0, 1 Zero-delay Logic

and connectivity, and X verification
node capacitances
FA;
A D inputs: A, B, C;
Carry Timing Transistor technology Analog Fine-grain Timing
B
HA1 E F outputs: Carry, Sum; data, connectivity, voltage timing verification
node capacitances
C
HA2 Sum HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum); Circuit Continuous Digital timing
Tech. Data, active/ Analog
time and analog
OR: O2, (D, F), (Carry); passive component voltage,
circuit
connectivity current
verification

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1
 Logic Models and Definitions Logic Models and Definitions

Structural model
 External representation in the form of netlist

Program model of a circuit
 Express circuit (gate level) as a program consisting
 Examples of this are uw format, iscas format,
of interconnected logic operations EDIF, …
 Execute the program to determine circuit output  Some keyword used in such representation
for varying inputs
Primary inputs and Primary outputs

RTL model
Gates: AND, OR, NOT, …
 Higher level model of the circuit
Storage: latch, flip-flop

HDL model
Connections: lines, nets
 Examples at this level are verilog HDL and VHDL
Fanin: number of inputs to a gate

Fanout: number of lines a signal feeds

Fanout-free circuit: every line or gate has a fanout of
one

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netlist Format: Two Examples Logic Models and definitions

ISCAS Benchmarks: http://www.fm.vslib.cz/~kes/asic/iscas/

uw format iscas format (comb.)
Additional useful terms

# gate connected to
 Graph representation
# gate #outputs # inputs 4 not 1 1
1 PI 4, 5;  Reconvergent fanouts
input gate # 9
2 PO 3, 6;  Stems and branches
1 input 2 0 5 and 1 2
3 not 5;
8 fanoutfrom 1  Logic levels in a circuit
3 8
4 not 6;  “levelization” of a circuit
9 fanoutfrom 1 6 and 1 2
5 and 7;
2 input 2 0 4 10
6 and 7;
10 fanoutfrom 2 7 or 1 2
7 or;
11 fanoutfrom 2 5 6
7 PO
3 not 1 1 7 output
11

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Why Model Faults?

I/O function tests inadequate for
manufacturing (functionality versus
component and interconnect testing)

Real defects (often mechanical) too

Fault Modeling numerous and often not analyzable

A fault model identifies targets for testing

A fault model makes analysis possible

Effectiveness measurable by experiments

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2
 Some Real Defects in Chips FMA
 Processing defects  Defects occur either during manufacture or
 Missing contact windows
 Parasitic transistors during the use of device.
 Oxide breakdown
 ...
 Material defects  Repeated occurrence of the same defects
 Bulk defects (cracks, crystal imperfections) indicates the need for improvements in the
 Surface impurities (ion migration) manufacturing process or design of the
 ... device.
 Time-dependent failures (Age defects)
 Dielectric breakdown
 Electromigration  Procedures for diagnosing defects and finding
 ...
 Packaging failures
their causes are known as failure mode
 Contact degradation analysis (FMA).
 Seal leaks
 ...
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -
Semiconductor Devices and Circuits, Wiley, 1981.

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Defect, Fault, and Error Observed PCB Defects

 Defect (imperfection in hardware): Defect classes Occurrence frequency (%)
 A defect in an electronic system is the unintended
difference between the implemented hardware and its
intended design. Shorts 51
Opens 1
 Error: Missing components 6
 A wrong output signal produced by a defective system Wrong components 13
is called an error. An error is an “effect” whose cause
is some “defect”. Reversed components 6
Bent leads 8
 Fault (imperfection in function): Analog specifications 5
 A representation of a “defect” at the abstracted Digital logic 5
function level is called a fault.
Performance (timing) 5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

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Common Fault Models Stuck-at Faults

Single stuck-at faults
Single stuck-at faults

Transistor open and short faults
What does it achieve in practice?

Memory faults
Fault equivalence

PLA faults (stuck-at, cross-point, bridging)
Fault dominance and checkpoint theorem

Functional faults (processors)
Classes of stuck-at faults and multiple faults

Delay faults (transition, path)

Analog faults

For more examples, see Section 4.4 (p. 60-
70) of the book.

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3
 Single Stuck-at Fault Single Stuck-at Faults (contd.)

Three properties define a single stuck-at fault

Only one line is faulty

How effective is this model?

The faulty line is permanently set to 0 or 1  Empirical evidence supports the use of

The fault can be at an input or output of a gate this model

Example: XOR circuit has 12 fault sites ( ) and 24  Has been found to be effective to detect
single stuck-at faults Faulty circuit value
other types of faults
Good circuit value  Relates to yield modeling
c j  Simple to use
s-a-0 0(1)
a d 1(0)
1 g h
z
0 1 i
b e 1

f k
Test vector for h s-a-0 fault

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Why Not Multiple Stuck-at Faults Fault Equivalence

In general, several stuck-at faults can be
Number of fault sites in a Boolean gate circuit
simultaneously present in the circuit. = #PI + #gates + # (fanout branches).

A circuit with n lines can have 3n-1 possible
stuck line combinations.
Fault equivalence:
 There are three states: s-a-1, s-a-0, and fault-free  Two faults f1 and f2 are equivalent if all tests that

Even a moderate value n will give an detect f1 also detect f2.
enormously large number of multiple stuck-at  If faults f1 and f2 are equivalent then the
faults. corresponding faulty functions are identical.

It’s a common practice to model only single
Fault collapsing:
stuck-at faults.  All single faults of a logic circuit can be divided into
 A n-line circuit can have at most 2n single stuck-at disjoint equivalence subsets, where all faults in a
faults. subset are mutually equivalent. A collapsed fault set
 This number is further reduced by techniques contains one fault from each equivalence subset.
known as Fault Collapsing.

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Equivalence Rules Equivalence Example

sa0 sa0
sa0 sa1
sa1 sa1 Faults in brown
sa0 sa1 removed by
sa0 sa1 sa0 sa1 WIRE sa0 sa1 equivalence
sa0 sa1 sa0 sa1
AND OR collapsing
sa0 sa1 sa0 sa1
sa0 sa1 sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1 sa0 sa1
NOT
sa1 sa0 sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1 sa0
NAND NOR sa0 sa1
sa1 sa0 sa1
sa0
sa0 sa1 sa0 sa1 sa0 sa1
sa1
sa0 20
sa1 Collapse ratio = ----- = 0.625
FANOUT 32

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4
 Equivalence Example Fault Dominance

sa1
If all tests of some fault f1 detect another fault f2,

sa0 then f2 is said to dominate f1.
sa1

Dominance fault collapsing:
sa0 sa1 sa1  If fault f2 dominates f1, then f2 is removed from the fault
sa0 list.
sa1
sa0 sa1  When dominance fault collapsing is used, it is sufficient to
sa0 sa1
sa1
consider only the input faults of Boolean gates.
 See the next example.
sa0 sa1 sa0
sa1
In a tree circuit (without fanouts) PI faults form a
sa1 dominance collapsed fault set.
sa0
sa1

If two faults dominate each other then they are
equivalent.

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Dominance Example Dominance Example

sa0 sa1
All tests of f2: T(f2)
f1 sa0 sa1
s-a-1 001
f2 sa0 sa1
s-a-1 110 010 sa0 sa1
000 sa0 sa1
101 011
100 sa0 sa1

Only test of f1: T(f1) sa0 sa1 sa0 sa1

s-a-1
s-a-1 sa0 sa1

s-a-1 sa0 sa1

s-a-0 17
Collapse ratio = ----- = 0.53
A dominance collapsed fault set 32

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Checkpoints Classes of Stuck-at Faults

Primary inputs and fanout branches of a
combinational circuit are called checkpoints.

Checkpoint theorem: A test set that detects all
single (multiple) stuck-at faults on all checkpoints of
a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit.
Total fault sites = 16
Checkpoints ( ) = 10

Following classes of single stuck-at faults are
identified by fault simulators:

Potentially-detectable fault -- Test produces an unknown
(X) state at primary output (PO); detection is
probabilistic, usually with 50% probability.

Initialization fault -- Fault prevents initialization of the
faulty circuit; can be detected as a potentially-detectable
fault.

Hyperactive fault -- Fault induces much internal signal
activity without reaching PO.

Redundant fault -- No test exists for the fault.

Untestable fault -- Test generator is unable to find a test.

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5
 Multiple Stuck-at Faults

A multiple stuck-at fault means that any set of
lines is stuck-at some combination of (0,1) values.

The total number of single and multiple stuck-at
faults in a circuit with n single fault sites is 3n-1.
Transistor (Switch) Faults

MOS transistor is considered an ideal switch and
two types of faults are modeled:

Stuck-open -- a single transistor is permanently stuck in
the open state.

Stuck-short -- a single transistor is permanently shorted
irrespective of its gate voltage.

A single fault test can fail to detect the target fault
if another fault is also present, however, such
masking of one fault by another is rare.

Statistically, single fault tests cover a very large
number of multiple faults.

Detection of a stuck-open fault requires two
vectors (V1 and V2).

Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ).

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Stuck-Open Example Stuck-Short Example

Vector 1: test for A s-a-0
Test vector for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1) pMOS
pMOS VDD
VDD Two-vector s-op test FETs IDDQ path in
FETs faulty circuit
can be constructed by A
A ordering two s-at tests 1 Stuck-
1 0 short
Stuck-
open
0
B Good circuit state
0 0
B
C
C 0 1(Z)
0 (X)

Good circuit states nMOS

nMOS FETs Faulty circuit state
FETs Faulty circuit states

NOR Gate
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