Assignment: #1

Due Date: Aug. 22, 2019, 10PM

PROBLEM 1. Phase and frequency variables

Consider a voltage gain block with gain G as shown below.

vin(t) vout(t)
G

Signals vin (t), vout (t) are given by

vin (t) = ain cos(ω0 t)

vout (t) = aout cos((ω0 + ∆ω)t)

(a) Find frequency (ω) and phase variables (φ) for vin (t) and vout (t).

(b) Find frequency and phase errors between ωout and ωin and φout and φin , respectively.

(c) Comment on the relationship between vin (t) and φout (t).
R
(d) If vout (t) = aout cos(ω0 t + Kout vin dt), find Φout (s)/Vin (s).

EE6324: Phase-locked loops 1 Aug.-Nov.

Aug. 2018
- Nov. 2019
PROBLEM 2. Frequency and phase in the presence of noise
Consider the signal waveforms for an ideal clock and real clock as shown below. The real clock
experiences an additional phase shift ∆ti with its every rising edge. Random noise ∆ti is i.i.d
and normally distributed with mean zero and variance σ 2 .

t=0 t=T t=2T t=kT

Ideal Clock

Real Clock

∆t0 Σ(∆ti) Σ(∆ti) Σ(∆ti)

0≤i≤1 0≤i≤2 0≤i≤k

(a) What is the average time period for real clock after N clock periods?

(b) What is the variance of time period for real clock after N clock periods?

(c) Sampling time error between ideal and real clock is given by
!
X
∆T (k + 1) = kT − kT + ∆ti
0≤i≤k

. What is the variance of sampling time error?

PROBLEM 3. Phase error
Consider voltage inputs to a multiplier or phase error detector as shown below. In sub-figures
(a) and (b), find and plot average phase error detector output ver vs. φer (0) for φer (0) ∈ [0, 2π].

vin(t) vout(t)=sin(ωoutt+Φer(0))

1 1
(a) vin(t) vout(t)
t t

-1 -1 T 2T
T 2T
ver(t)

vin(t) vout(t)=sin(ωoutt+Φer(0))

1 1
(b) vin(t) vout(t)
t t

-1 -1 T 2T
T 2T
ver(t)
PROBLEM 4. Phase and frequency acquisition in Type-I PLL.
Consider a Type-I PLL as shown below. vfree is external bias voltage.

PD Loop Filter VCO

vin ve v vo
F(s) c

fo VCO

vin(t) = sin(ωint) F(s) 1.5GHz

vo(t) = sin(ωot-Φe(0)) 1
ve(t) = vin(t) x vo(t) =
1+s/ωp 0.5GHz
vc+vfree
-5V 5V

(a) Find and plot ve vs. Φe (0) for the phase detector (PD) in open loop when ωin = ωo .

(b) At time t=0, input frequency fin = 1 GHz, free running frequency of the voltage controlled
oscillator (VCO) ffree = 0.975 GHz, Φe (0) = 0, ve (0) = vc (0) = 0, ωp → ∞, and the loop
is closed. Find the steady state values for phase error (Φe ), ve , and vc .

(c) Model the above PLL at behavioral level and simulate with initial conditions as stated in
1(b). Plot Φe , ve , and vc w.r.t time. Verify the simulation results with steady state values
evaluated previously.

(d) Simulate the above PLL with ωp = 2π × 250 Mrad/s and initial conditions as stated in
1(b). Plot Φe , ve , and vc w.r.t time. Verify the simulation results with steady state values
evaluated previously.

(e) With fin = 1 GHz and ωp = 2π × 250 Mrad/s, find the range of free running frequency of
the VCO that can be brought in lock by the PLL.

(f) If ffree = 1.475 GHz, find the range of input frequencies (fin) that can be tracked at the
PLL output.

(g) If ffree = 0.5 GHz and fin = 1.0 GHz, suggest a modification in the PLL loop to bring the
VCO in lock with the input frequency. What is the hold-in range of the new PLL?