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Features Description: LTC6811-1/LTC6811-2 Multicell Battery Monitors
Features Description: LTC6811-1/LTC6811-2 Multicell Battery Monitors
TYPICAL APPLICATION
LTC6811
ISO26262
DIAGNOSTICS 2.0
REAL WORLD CELL
SWITCH 1.5 MEASUREMENT BUDGET
ON/OFF
MEASUREMENT ERROR (mV)
1.0
16 0.5
DATA ADC MUX CELL = 3.3V
I/O 0.0 MEASUREMENT
ERROR, 25°C
+ –0.5
–
ADDITIONAL PCB ASSEMBLY SHIFT
–1.0
VOLTAGE ADDITIONAL
REFERENCE –1.5 CHANGE
–40°C TO 125°C
–2.0
68111 TA01b
68111 TA01a
SENSORS
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PIN CONFIGURATION
LTC6811-1 LTC6811-2
TOP VIEW TOP VIEW
V+ 1 48 IPB V+ 1 48 A3
C12 2 47 IMB C12 2 47 A2
S12 3 46 ICMP S12 3 46 A1
C11 4 45 IBIAS C11 4 45 A0
S11 5 44 SDO (NC)* S11 5 44 SDO (IBIAS)*
C10 6 43 SDI (NC)* C10 6 43 SDI (ICMP)*
S10 7 42 SCK (IPA)* S10 7 42 SCK (IPA)*
C9 8 41 CSB (IMA)* C9 8 41 CSB (IMA)*
S9 9 40 ISOMD S9 9 40 ISOMD
C8 10 39 WDT C8 10 39 WDT
S8 11 38 DRIVE S8 11 38 DRIVE
C7 12 37 VREG C7 12 37 VREG
S7 13 36 DTEN S7 13 36 DTEN
C6 14 35 VREF1 C6 14 35 VREF1
S6 15 34 VREF2 S6 15 34 VREF2
C5 16 33 GPIO5 C5 16 33 GPIO5
S5 17 32 GPIO4 S5 17 32 GPIO4
C4 18 31 V– C4 18 31 V–
S4 19 30 V–** S4 19 30 V–**
C3 20 29 GPIO3 C3 20 29 GPIO3
S3 21 28 GPIO2 S3 21 28 GPIO2
C2 22 27 GPIO1 C2 22 27 GPIO1
S2 23 26 C0 S2 23 26 C0
C1 24 25 S1 C1 24 25 S1
G PACKAGE G PACKAGE
48-LEAD PLASTIC SSOP 48-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 55°C/W TJMAX = 150°C, θJA = 55°C/W
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD *THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, NC, NC ISOMD TIED TO VREG: IMA, IPA, NC, NC
**THIS PIN MUST BE CONNECTED TO V– **THIS PIN MUST BE CONNECTED TO V–
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SPECIFIED
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6811IG-1#PBF LTC6811IG-1#TRPBF LTC6811G-1 48-Lead Plastic SSOP –40°C to 85°C
LTC6811HG-1#PBF LTC6811HG-1#TRPBF LTC6811G-1 48-Lead Plastic SSOP –40°C to 125°C
LTC6811IG-2#PBF LTC6811IG-2#TRPBF LTC6811G-2 48-Lead Plastic SSOP –40°C to 85°C
LTC6811HG-2#PBF LTC6811HG-2#TRPBF LTC6811G-2 48-Lead Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ADC DC Specifications
Measurement Resolution l 0.1 mV/bit
ADC Offset Voltage (Note 2) l 0.1 mV
ADC Gain Error (Note 2) 0.01 %
l 0.02 %
Total Measurement Error (TME) in Normal C(n) to C(n – 1), GPIO(n) to V– = 0 ±0.2 mV
Mode C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 2.0 l ±1.4 mV
C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV
C(n) to C(n – 1), GPIO(n) to V– = 3.3 l ±2.2 mV
C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV
C(n) to C(n – 1), GPIO(n) to V– = 4.2 l ±2.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 5.0 ±1 mV
Sum of Cells l ±0.05 ±0.25 %
Internal Temperature, T = Maximum Specified ±5 °C
Temperature
VREG Pin l ±0.1 ±0.25 %
VREF2 Pin l ±0.02 ±0.1 %
Digital Supply Voltage VREGD l ±0.1 ±1 %
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Note 1: Stresses beyond those listed under the Absolute Maximum Note 4: These timing specifications are dependent on the delay through
Ratings may cause permanent damage to the device. Exposure to any the cable, and include allowances for 50ns of delay each direction. 50ns
Absolute Maximum Rating condition for extended periods may affect corresponds to 10m of CAT5 cable (which has a velocity of propagation of
device reliability and lifetime. 66% the speed of light). Use of longer cables would require derating these
Note 2: The ADC specifications are guaranteed by the Total Measurement specs by the amount of additional delay.
Error specification. Note 5: These specifications do not include rise or fall time of SDO. While
Note 3: The ACTIVE state current is calculated from DC measurements. fall time (typically 5ns due to the internal pull-down transistor) is not a
The ACTIVE state current is the additional average supply current into concern, rising-edge transition time tRISE is dependent on the pull-up
VREG when there is continuous 1MHz communications on the isoSPI ports resistance and load capacitance on the SDO pin. The time constant must
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply be chosen such that SDO meets the setup time requirements of the MCU.
current. See Applications Information section for additional details.
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NUMBER OF PARTS
–3
0.5
4
0 –10
3
–0.5
–18
2
–1.0
1 –25
–1.5
–2.0 0 –32
–50 –25 0 25 50 75 100 125 –100 –60 –20 20 60 100 140 0 500 1000 1500 2000 2500
TEMPERATURE (°C) CHANGE IN GAIN ERROR (ppm) TIME (HOURS)
68111 G01 68111 G02 68111 G03
Measurement Error vs Input, Measurement Error vs Input, Measurement Error vs Input, Fast
Normal Mode Filtered Mode Mode
2.0 2.0 10
10 ADC MEASUREMENTS 10 ADC MEASUREMENTS 8 10 ADC MEASUREMENTS
1.5 1.5
AVERAGED AT EACH INPUT AVERAGED AT EACH INPUT AVERAGED AT EACH INPUT
6
MEASUREMENT ERROR (mV)
–0.5 –0.5 –2
–4
–1.0 –1.0
–6
–1.5 –1.5 –8
–2.0 –2.0 –10
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
INPUT (V) INPUT (V) INPUT (V)
68111 G04 68111 G05 68111 G06
0.6 0.6 6
0.5 0.5 5
0.4 0.4 4
0.3 0.3 3
0.2 0.2 2
0.1 0.1 1
0 0 0
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
INPUT (V) INPUT (V) INPUT (V)
68111 G07 68111 G08 68111 G09
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NUMBER OF PARTS
30
30
25 –30
20 –40
20
15
–50
10 10
–60
5
0 0 –70
–40 –20 0 20 40 60 80 100 –75 –50 –25 0 25 50 75 10 100 1k 10k 100k 1M
CHANGE IN GAIN ERROR (ppm) CHANGE IN GAIN ERROR (ppm) INPUT FREQUENCY (Hz)
68111 G10 68111 G11
26Hz 422Hz 1kHz
2kHz 3kHz 7kHz
14kHz 27kHz 68111 G12
0 0 0
VREG(AC) = 0.5Vp–p
1BIT CHANGE < –70dB –20 1BIT CHANGE < –90dB
1.0 –20 VREG GENERATED FROM
–30 DRIVE PIN, FIGURE 28
0.5 –30 –40
PSRR (dB)
PSRR (dB)
0 –40 –50
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Measurement Error CMRR vs Cell Measurement Error vs Input GPIO Measurement Error vs Input
Frequency RC Values RC Values
0 2 20
–10 VCM(IN) = 5VP-P 1 16 TIME BETWEEN MEASUREMENTS > 3RC
NORMAL MODE CONVERSIONS
–40 –3 4
–50 –4 0
–60 –5 –4
–6
–70 –8
–7 C=0
–80 100nF –12
–8 C = 100nF
–90 10nF –16 C = 1µF
–9 1µF C = 10µF
–100 –10 –20
100 1k 10k 100k 1M 10M 100 1k 10k 1 10 100 1k 10k 100k
FREQUENCY (Hz) INPUT RESISTANCE, R (Ω) INPUT RESISTANCE, R (Ω)
68111 G19 68111 G20 68111 G21
Measurement Time vs
Temperature Sleep Supply Current vs V+ Standby Supply Current vs V+
2.40 7 80
12 CELL NORMAL MODE CONVERSIONS SLEEP SUPPLY CURRENT = STANDBY SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT 75 V+ CURRENT + VREG CURRENT
2.35
70 85°C
2.30 25°C
65 –40°C
5
2.25 60
4 55
2.20
125°C 50
VREG = 4.5V 3
2.15 85°C
VREG = 5V 25°C 45
VREG = 5.5V –40°C
2.10 2 40
–50 –25 0 25 50 75 100 125 5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75
TEMPERATURE (°C) V+ (V) V+ (V)
68111 G22 68111 G23 68111 G24
85°C 3.165
25°C
950 –40°C 12.0
3.160
VREF1 (V)
3.150
900 11.0
125°C 3.145
875 10.5 85°C
25°C 3.140
–40°C
850 10.0 3.135
5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75 –50 –25 0 25 50 75 100 125
V+ (V) V+ (V) TEMPERATURE (°C)
68111 G25 68111 G26 68111 G27
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3.000 0
2.999 –60 –20
2.998 125°C –40
85°C 125°C
2.997 –130 25°C –60
85°C
2.996 –40°C –80 25°C
–40°C
2.995 –200 –100
–50 –25 0 25 50 75 100 125 4.5 4.75 5 5.25 5.5 5 15 25 35 45 55 65 75
TEMPERATURE (°C) VREG (V) V+ (V)
68111 G28 68111 G29 68111 G30
40
NUMBER OF PARTS
–200 20
20
–400 0 15
–20
–600 10
–40
125°C
85°C –60
–800 5
25°C
–80
–40°C
–1000 –100 0
0.01 0.1 1 10 0 500 1000 1500 2000 2500 –50 –25 0 25 50 75 100 125
IOUT (mA) TIME (HOURS) CHANGE IN VREF2 (ppm)
68111 G31 68111 G32 68111 G33
NUMBER OF PARTS
5.6
3
VDRIVE (V)
40
5.5
30
2
5.4
20
1
10 5.3
0 0 5.2
–75 –50 –25 0 25 50 75 100 –175 –125 –75 –25 25 75 125 –50 –25 0 25 50 75 100 125
CHANGE IN VREF2 (ppm) CHANGE IN VREF2 (ppm) TEMPERATURE (°C)
68111 G34 68111 G35 68111 G36
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0 –70 125°C 15
85°C
–80 25°C 10
–5 –40°C
–90 5
–10 –100 0
5 15 25 35 45 55 65 75 0.01 0.1 1 1 1.4 1.7 2.1 2.4 2.8 3.1 3.5 3.8 4.2 4.5
V+ (V) IOUT (mA) CELL VOLTAGE (V)
68111 G37 68111 G38 68111 G39
VREF1: CL = 1µF
45 8 VREF2: CL = 1µF, RL = 5kΩ
INCREASE IN DIE TEMPERATURE (°C)
ISOSPI CURRENT
VREG 5
2V/DIV CS 4.5
CS 4
5V/DIV LTC6811–1, READ
4.0
50.0µs/DIV
68111 G43
LTC6811–2, ISOMD=VREG LTC6811–1, WRITE
3
LTC6811–1, ISOMD=VREG LTC6811–2, READ
LTC6811–1, ISOMD=V– LTC6811–2, WRITE
3.5 2
–50 –25 0 25 50 75 100 125 0 200 400 600 800 1000
TEMPERATURE (°C) isoSPI CLOCK FREQUENCY (kHz)
68111 G44 68111 G45
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21
2.00 2.000
20
1.99 1.995
19 VA = 1.6V
VA = 1.0V
VA = 0.5V
1.98 1.990 18
–50 –25 0 25 50 75 100 125 0 200 400 600 800 1000 0 200 400 600 800 1000
TEMPERATURE (°C) IBIAS CURRENT, IB (µA) IBIAS CURRENT, IB (µA)
68111 G46 68111 G47 68111 G48
4.5 0.52
21
4.0 0.50
20
3.5 0.48
19
3.0 0.46
IB = 100µA IB = 100µA VICMP = 0.2V
IB = 1mA IB = 1mA VICMP = 1V
18 2.5 0.44
–50 –25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
TEMPERATURE (°C) PULSE AMPLITUDE, VA (V) RECEIVER COMMON MODE, VCM (V)
68111 G49 68111 G50 68111 G51
isoSPI Comparator Threshold Gain isoSPI Comparator Threshold Gain Typical Wake-Up Pulse Amplitude
(Port A/Port B) vs ICMP Voltage (Port A/Port B) vs Temperature (Port A) vs Dwell Time
0.56 0.56 300
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
3 PARTS
WAKE–UP PULSE AMPLITUDE, VWAKE (mV)
0.46 0.46 50
VICMP = 0.2V
VICMP = 1V
0.44 0.44 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 –50 –25 0 25 50 75 100 125 0 100 200 300 400 500 600
ICMP VOLTAGE (V) TEMPERATURE (°C) WAKE–UP DWELL TIME, TDWELL (ns)
68111 G52 68111 G53 68111 G54
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V+ IPB
1 48
C12 IMB
2 47
S12 VREGD POR VREG ICMP
3 46
C12
C11 IBIAS
C11
4 C10
P + 45
6-CELL
S11 C9 ADC2 SERIAL I/O SDO/(NC)
MUX
C8 16 PORT B
5
C7
M – 44
C10 LOGIC SDI/(NC)
DIGITAL
6 AND 43
FILTERS
MEMORY
S10 C6 SCK/(IPA)
7 C5 P + SERIAL I/O 42
C4 7-CELL PORT A
C9 ADC1 CSB/(IMA)
C3 MUX
16
8 C2 M – 41
S9 C1 ISOMD
9 C0 40
C8 WDT
10 39
S8 DRIVE
11 12 BALANCE FETs 38
C7 S(n) VREG
12 VREGD 37
SC
S7 C(n – 1) VREG DTEN
13 DISCHARGE 36
P TIMER
C6 VREF1
AUX
14 MUX 35
S6 M VREF2
15 34
REGULATORS
C5 GPIO5
16 V+ 33
LDO2
S5 GPIO4
DRIVE
17 32
V+ DIE
C4 TEMPERATURE V–
LDO1 VREGD
18 31
POR
S4 2ND V–*
REFERENCE
19 30
C3 GPIO3
20 29
1ST
S3 REFERENCE GPIO2
21 28
C2 GPIO1
22 27
S2 C0
23 26
C1 S1
24 25
68111 BD1
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V+ A3
1 48
C12 A2
2 47
S12 VREGD POR VREG A1
3 46
C12
C11 A0
C11
4 C10
P + 45
6-CELL
S11 C9 ADC2 SERIAL I/O SDO/(IBIAS)
MUX
C8 16 ADDRESS
5
C7
M – 44
C10 LOGIC SDI/(ICMP)
DIGITAL
6 AND 43
FILTERS
MEMORY
S10 C6 SCK/(IPA)
7 C5 P + SERIAL I/O 42
C4 7-CELL PORT A
C9 ADC1 CSB/(IMA)
C3 MUX
16
8 C2 M – 41
S9 C1 ISOMD
9 C0 40
C8 WDT
10 39
S8 DRIVE
11 12 BALANCE FETs 38
C7 S(n) VREG
12 VREGD 37
SC
S7 C(n – 1) VREG DTEN
13 DISCHARGE 36
P TIMER
C6 VREF1
AUX
14 MUX 35
S6 M VREF2
15 34
REGULATORS
C5 GPIO5
16 V+ 33
LDO2
S5 GPIO4
DRIVE
17 32
V+ DIE
C4 TEMPERATURE V–
LDO1 VREGD
18 31
POR
S4 2ND V–*
REFERENCE
19 30
C3 GPIO3
20 29
1ST
S3 REFERENCE GPIO2
21 28
C2 GPIO1
22 27
S2 C0
23 26
C1 S1
24 25
68111 BD2
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The reference and ADCs are powered down. The watchdog When a valid ADC command is received, the IC goes to
timer (see Watchdog and Discharge Timer) has timed the MEASURE state to begin the conversion. Otherwise,
out. The discharge timer is either disabled or timed out. the LTC6811 will return to the STANDBY state when the
The supply currents are reduced to minimum levels. The REFON bit is set to 0, either manually (using WRCFGA
isoSPI ports will be in the IDLE state. The Drive pin is 0V. command) or automatically when the watchdog timer
expires (the LTC6811 will then move straight into the
If a WAKEUP signal is received (see Waking Up the Serial SLEEP state if both timers are expired).
Interface), the LTC6811 will enter the STANDBY state.
MEASURE State
STANDBY State
The LTC6811 performs ADC conversions in this state. The
The reference and the ADCs are off. The watchdog timer reference and ADCs are powered up.
and/or the discharge timer is running. The DRIVE pin
powers the VREG pin to 5V through an external transistor. After ADC conversions are complete, the LTC6811 will
(Alternatively, VREG can be powered by an external supply). transition to either the REFUP or STANDBY state, depend-
ing on the REFON bit. Additional ADC conversions can
When a valid ADC command is received or the REFON bit is be initiated more quickly by setting REFON = 1 to take
set to 1 in the Configuration Register Group, the IC pauses advantage of the REFUP state.
for tREFUP to allow for the reference to power up and then
enters either the REFUP or MEASURE state. Otherwise, if Note: Non-ADC commands do not cause a Core state tran-
no valid commands are received for tSLEEP (when both the sition. Only an ADC conversion or diagnostic commands
watchdog and discharge timer have expired), the LTC6811 will place the Core in the MEASURE state.
SLEEP IDLE
STANDBY READY
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tCYCLE
tREFUP
tSKEW2
Table 5. Conversion Times for ADCV Command Measuring All 12 Cells in Different Modes
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C
27kHz 0 57 103 243 290 432 568 975 1,113
14kHz 0 86 162 389 465 606 742 1,149 1,288
7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335
3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033
2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430
1kHz 0 959 1,907 4,753 5,701 5,961 6,213 6,970 7,222
422Hz 0 1,890 3,769 9,407 11,287 11,547 11,799 12,555 12,807
26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317
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tREFUP
MEASURE CALIBRATE
ADC2
C10 TO C9 C10 TO C9
MEASURE CALIBRATE
ADC1
C4 TO C3 C4 TO C3
t0 t1M t1C
68111 F04
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tCYCLE
tREFUP
tSKEW
SERIAL ADAX + PEC
INTERFACE
ADC2
Figure 5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
Table 7. Conversion Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C
27kHz 0 57 103 243 290 432 568 975 1,113
14kHz 0 86 162 389 465 606 742 1,149 1,288
7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335
3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033
2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430
1kHz 0 959 1,907 4,753 5,701 5,961 6,213 6,970 7,222
422Hz 0 1,890 3,769 9,407 11,287 11,547 11,799 12,555 12,807
26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317
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tCYCLE
tREFUP
tSKEW1
tSKEW1
SERIAL ADCVAX + PEC
INTERFACE
Table 8. Conversion and Synchronization Times for ADCVAX Command in Different Modes
SYNCHRONIZATION
CONVERSION TIMES (in µs) TIME (in µs)
MODE t0 t1M t2M t3M t4M t5M t6M t7M t8M t8C tSKEW1
27kHz 0 57 104 150 204 251 305 352 398 1,503 194
14kHz 0 86 161 237 320 396 479 555 630 1,736 310
7kHz 0 144 278 412 553 687 828 962 1,096 3,133 543
3kHz 0 260 511 761 1,018 1,269 1,526 1,777 2,027 4,064 1009
2kHz 0 493 976 1,459 1,949 2,432 2,923 3,406 3,888 5,925 1939
1kHz 0 959 1,907 2,856 3,812 4,760 5,716 6,664 7,613 9,648 3801
422Hz 0 1,890 3,769 5,648 7,535 9,415 11,301 13,181 15,060 17,096 7,525
26Hz 0 29,817 59,623 89,430 119,244 149,051 178,864 208,671 238,478 268,442 119,234
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tCYCLE
tREFUP
tSKEW
ADC2
Table 9. Conversion Times for ADSTAT Command Measuring SC, ITMP, VA, VD
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t3M t4M t1C t2C t3C t4C
27kHz 0 57 103 150 197 338 474 610 748
14kHz 0 86 162 237 313 455 591 726 865
7kHz 0 144 278 412 546 804 1,056 1,308 1,563
3kHz 0 260 511 761 1,011 1,269 1,522 1,774 2,028
2kHz 0 493 976 1,459 1,942 2,200 2,452 2,705 2,959
1kHz 0 959 1,907 2,856 3,804 4,062 4,313 4,563 4,813
422Hz 0 1,890 3,769 5,648 7,528 7,786 8,036 8,287 8,537
26Hz 0 29,817 59,623 89,430 119,237 122,986 126,729 130,472 134,218
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tCYCLE
tREFUP
tSKEW
SERIAL ADCVSC + PEC
INTERFACE
Table 10. Conversion and Synchronization Times for ADCVSC Command in Different Modes
SYNCHRONIZATION
CONVERSION TIMES (in µs) TIME (in µs)
MODE t0 t1M t2M t3M t4M t5M t6M t7M t7C tSKEW
27kHz 0 57 106 155 216 265 326 375 1,322 159
14kHz 0 86 161 237 320 396 479 555 1,526 234
7kHz 0 144 278 412 553 695 829 962 2,748 409
3kHz 0 260 511 761 1,018 1,269 1,526 1,777 3,562 758
2kHz 0 493 976 1,459 1,949 2,432 2,923 3,406 5,192 1,456
1kHz 0 959 1,907 2,856 3,812 4,767 5,716 6,664 8,450 2,853
422Hz 0 1,890 3,769 5,648 7,535 9,422 11,301 13,181 14,966 5,645
26Hz 0 29,817 59,623 89,430 119,244 149,058 178,864 208,672 234,893 89,427
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tREFUP
MEASURE CALIBRATE
ADC2
C7 TO C6 C7 TO C6
MEASURE CALIBRATE
ADC1
C7 TO C6 C7 TO C6
t0 t1M t1C
68111 F09
Figure 9. Timing for ADOL Command Measuring Cell 7 with both ADC1 and ADC2
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PULSE DENSITY
MODULATED
BIT STREAM
ANALOG 1-BIT
MUX
INPUT MODULATOR 1 DIGITAL RESULTS
FILTER 16 REGISTER
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RST1
(RESETS DCTO, DCC) WDTRST && ~DCTEN
WDT
RST2
(RESETS REFUP, GPIO, VUV, VOV)
WDTPD
WATCHDOG
WDTRST
TIMER
OSC 16Hz CLK
RST
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Table 20 describes the valid write codes for ICOMn[3:0] three bytes of data to the slave, send STCOMM command
and FCOMn[3:0] and their behavior when using the part and its PEC followed by 72 clock cycles. Pull CSB high
as a SPI master. at the end of the 72 clock cycles of STCOMM command.
Note that only the codes listed in Tables 19 and 20 are During I2C or SPI communication, the data received from
valid for ICOMn[3:0] and FCOMn[3:0]. Writing any other the slave device is updated in the COMM register.
code that is not listed in Tables 19 and 20 to ICOMn[3:0] RDCOMM Command: The data received from the slave
and FCOMn[3:0] may result in unexpected behavior on device can be read back from the COMM register using
the I2C or SPI port. the RDCOMM command. The command reads back six
COMM Commands bytes of data followed by the PEC. See the section Bus
Protocols for more details on a read command format.
Three commands help accomplish I2C or SPI commu-
nication to the slave device: WRCOMM, STCOMM and Table 21 describes the possible read back codes for
RDCOMM. ICOMn[3:0] and FCOMn[3:0] when using the part as an
I2C master. Dn[7:0] contains the data byte transmitted by
WRCOMM Command: This command is used to write data the I2C slave.
to the COMM register. This command writes 6 bytes of
data to the COMM register. The PEC needs to be written at Table 21. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master
the end of the data. If the PEC does not match, all data in CONTROL BITS CODE DESCRIPTION
the COMM register is cleared to 1s when CSB goes high. ICOMn[3:0] 0110 Master generated a START signal
See the section Bus Protocols for more details on a write 0001 Master generated a STOP signal
command format. 0000 Blank, SDA was held low between bytes
0111 Blank, SDA was held high between bytes
STCOMM Command: This command initiates I2C/SPI com-
FCOMn[3:0] 0000 Master generated an ACK signal
munication on the GPIO ports. The COMM register contains
0111 Slave generated an ACK signal
3 bytes of data to be transmitted to the slave. During this
1111 Slave generated a NACK signal
command, the data bytes stored in the COMM register are
transmitted to the slave I2C or SPI device and the data 0001 Slave generated an ACK signal, master
generated a STOP signal
received from the I2C or SPI device is stored in the COMM 1001 Slave generated a NACK signal, master
register. This command uses GPIO4 (SDA) and GPIO5 generated a STOP signal
(SCL) for I2C communication or GPIO3 (CSBM), GPIO4
(SDIOM) and GPIO5 (SCKM) for SPI communication. In case of the SPI master, the read back codes for
The STCOMM command is to be followed by 24 clock ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111
cycles for each byte of data to be transmitted to the slave respectively. Dn[7:0] contains the data byte transmitted
device while holding CSB low. For example, to transmit by the SPI slave.
68111fb
SDA (GPIO4)
BLANK NACK
SCL (GPIO5)
SDA (GPIO4)
START ACK
SCL (GPIO5)
SDA (GPIO4)
STOP
SCL (GPIO5)
SDA (GPIO4)
NO TRANSMIT
SCL (GPIO5)
(SCK)
SCKM (GPIO5)
SDIOM (GPIO4)
SCKM (GPIO5)
SDIOM (GPIO4)
SCKM (GPIO5)
Timing Specifications of I2C and SPI Master Table 23. SPI Master Timing
The timing of the LTC6811 I2C or SPI master will be TIMING RELATIONSHIP TIMING
SPI MASTER TO PRIMARY SPI SPECIFICATIONS
controlled by the timing of the communication at the PARAMETER INTERFACE AT tCLK = 1µs
LTC6811’s primary SPI interface. Table 22 shows the SDIOM Valid to SCKM Rising t3 Min 200ns
I2C master timing relationship to the primary SPI clock. Setup
Table 23 shows the SPI master timing specifications. SDIOM Valid from SCKM tCLK + t4* Min 1.03µs
Rising Hold
Table 22. I2C Master Timing SCKM Low tCLK Min 1µs
TIMING RELATIONSHIP TIMING SCKM High tCLK Min 1µs
I2C MASTER TO PRIMARY SPI SPECIFICATIONS SCKM Period (SCKM_Low + 2 • tCLK Min 2µs
PARAMETER INTERFACE AT tCLK = 1µs SCKM_High)
SCL Clock Frequency 1/(2 • tCLK) Max 500kHz CSBM Pulse Width 3 • tCLK Min 3µs
tHD;STA t3 Min 200ns SCKM Rising to CSBM 5 • tCLK + t4* Min 5.03µs
tLOW tCLK Min 1µs Rising
tHIGH tCLK Min 1µs CSBM Falling to SCKM t3 Min 200ns
Falling
tSU;STA tCLK + t4* Min 1.03µs
CSBM Falling to SCKM tCLK + t3 Min 1.2µs
tHD;DAT t4* Min 30ns Rising
tSU;DAT t3 Min 200ns SCKM Falling to SDIOM Valid Master requires < tCLK
tSU;STO tCLK + t4* Min 1.03µs
* Note: When using isoSPI, t4 is generated internally and is a minimum of
tBUF 3 • tCLK Min 3µs 30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high
* Note: When using isoSPI, t4 is generated internally and is a minimum of times of the SCK input, each with a specified minimum of 200ns.
30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high
times of the SCK input, each with a specified minimum of 200ns.
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Table 24
NIBBLE VALUE S PIN BEHAVIOR
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
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V+ IPB V+ A3
LTC6811-1 DAISY-CHAIN SUPPORT LTC6811-2 ADDRESS PINS
C12 IMB C12 A2
S12 ICMP 5k S12 A1 5k
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SCK
SDI D3 D2 D1 D0 D7…D4 D3
t5
CSB
t8
SDO D4 D3 D2 D1 D0 D7…D4 D3
68111 F16
PREVIOUS COMMAND CURRENT COMMAND
2-WIRE ISOLATED INTERFACE (isoSPI) PHYSICAL level of the receiver are set by two external resistors. The
LAYER values of the resistors allow the user to trade off power
The 2-wire interface provides a means to interconnect dissipation for noise immunity.
LTC6811 devices using simple twisted pair cabling. The Figure 17 illustrates how the isoSPI circuit operates. A 2V
interface is designed for low packet error rates when the reference drives the IBIAS pin. External resistors RB1 and
cabling is subjected to high RF fields. Isolation is achieved RB2 create the reference current IB. This current sets the
through an external transformer. drive strength of the transmitter. RB1 and RB2 also form
a voltage divider to supply a fraction of the 2V reference
Standard SPI signals are encoded into differential pulses.
for the ICMP pin, which sets the threshold voltage of the
The strength of the transmission pulse and the threshold
receiver circuit.
LTC6811
WAKEUP
CIRCUIT
(ON PORT A)
Tx • 20 • IB IP
Tx = +1
SDO Tx = 0 •
LOGIC RM
IM •
AND Tx = –1
MEMORY SDI
PULSE
SCK ENCODER/
DECODER Rx = +1
+
CSB Rx = 0
Rx = –1 IB IBIAS
–
+ 2V
1V • RB2
– RB1
COMPARATOR THRESHOLD = ICMP
RB1 + RB2
0.5X
RB2
68111 F17
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•
•
•
•
•
•
•
•
44
V+ IPB V+ IPB V+ IPB V+ IPB
LTC6811-1 LTC6811-1 LTC6811-1 LTC6811-1
C12 IMB C12 IMB C12 IMB C12 IMB
S12 ICMP S12 ICMP S12 ICMP S12 ICMP
C11 IBIAS C11 IBIAS C11 IBIAS C11 IBIAS
S11 SDO (NC) S11 SDO (NC) S11 SDO (NC) S11 SDO (NC)
C10 SDI (NC) C10 SDI (NC) C10 SDI (NC) C10 SDI (NC)
S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA)
C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) MISO VDD
OPERATION
C4 V– C4 V– C4 V– C4 V– MISO ICMP
S4 V– S4 V– S4 V– S4 V– SCK GND
S2 C0 S2 C0 S2 C0 S2 C0
C1 S1 C1 S1 C1 S1 C1 S1
68111 F18
•
•
•
•
•
•
•
•
ADDRESS = 0x3 ADDRESS = 0x2 ADDRESS = 0x1 ADDRESS = 0x0
V+ A3 V+ A3 V+ A3 V+ A3
LTC6811-2 LTC6811-2 LTC6811-2 LTC6811-2
C12 A2 C12 A2 C12 A2 C12 A2
S12 A1 S12 A1 S12 A1 S12 A1
C11 A0 C11 A0 C11 A0 C11 A0
C4 V– C4 V– C4 V– C4 V– MISO ICMP
S4 V– S4 V– S4 V– S4 V– SCK GND
S2 C0 S2 C0 S2 C0 S2 C0
C1 S1 C1 S1 C1 S1 C1 S1
68111 F19
68111fb
LTC6811-1/LTC6811-2
OPERATION
TERMINATED UNUSED PORT
•
LTC6811-1 100Ω
V+ IPB VDD
•
C12 IMB MISO
S12 ICMP MOSI
C11 IBIAS CLK
S11 SDO(NC) CS MPU
C10 SDI(NC)
S10 SCK(IPA)
C9 CSB(IMA) LTC6820
S9 ISOMD
C8 VDDS VDD
WDT
S8 EN POL
DRIVE
C7 PHA
VREG
S7 MSTR
DTEN
C6 ICMP
VREF1
S6 MISO IBIAS
VREF2
C5 GPIO5 MOSI GND
S5 GPIO4 SCK SLOW
C4 V– CS
IP •
S4 V–
IM
C3 GPIO3 •
S3 GPIO2
C2 GPIO1
S2 C0
C1 S1
68111 F20
C12 A2 MISO
S12 A1 MOSI
C11 A0 CLK
S11 SDO(IBIAS) CS MPU
C10 SDI(ICMP)
S10 SCK(IPA)
C9 CSB(IMA) LTC6820
S9 ISOMD
C8 VDDS VDD
WDT
S8 EN POL
DRIVE
C7 PHA
VREG
S7 MSTR
DTEN
C6 ICMP
VREF1
S6 MISO IBIAS
VREF2
C5 GPIO5 MOSI GND
S5 GPIO4 SCK SLOW
C4 V– CS
IP •
S4 V–
IM
C3 GPIO3 •
S3 GPIO2
C2 GPIO1
S2 C0
C1 S1
68111 F21
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Figure 22. Single Device LTC6811-1 Using 4-Wire Port A Figure 23. Single Device LTC6811-2 Using 4-Wire Port A
RM. A negative voltage is developed by IP sinking and IM Short +1 +VA (50ns) –VA (50ns) 0V
sourcing. When both outputs are off, the load resistance Short –1 –VA (50ns) +VA (50ns) 0V
forces the differential output to 0V.
To eliminate the DC signal component and enhance reli- A host microcontroller does not have to generate isoSPI
ability, the isoSPI uses two different pulse lengths. This pulses to use this 2-wire interface. The first LTC6811 in
allows four types of pulses to be transmitted, as shown in the system can communicate to the microcontroller using
Table 25. A +1 pulse will be transmitted as a positive pulse the 4-wire SPI interface on its Port A, then daisy-chain to
followed by a negative pulse. A –1 pulse will be transmit- other LTC6811s using the 2-wire isoSPI interface on its
ted as a negative pulse followed by a positive pulse. The Port B. Alternatively, the LTC6820 can be used to translate
duration of each pulse is defined as t½PW, since each is the SPI signals into isoSPI pulses.
half of the required symmetric pair (the total isoSPI pulse
duration is 2·t½PW).
68111fb
MARGIN
+VTCMP tFILT MARGIN
–1 PULSE
MARGIN
tWNDW
68111 F24
LTC6811-1 Operation with Port A Configured for SPI each transmitted pulse and reconstructs the SPI signals
internally, as shown in Table 27. In addition, during a READ
When the LTC6811-1 is operating with Port A as a SPI
command this port may transmit return data pulses.
(ISOMD = V–), the SPI detects one of four communication
events: CSB falling, CSB rising, SCK rising with SDI = 0 Table 27. Port A (Slave) isoSPI Port Function
and SCK rising with SDI = 1. Each event is converted into RECEIVED PULSE INTERNAL SPI RETURN PULSE
one of the four pulse types for transmission through the (Port A isoSPI) PORT ACTION
daisy chain. Long pulses are used to transmit CSB changes Long +1 Drive CSB High None
and short pulses are used to transmit data, as explained Long –1 Drive CSB Low
in Table 26. Short +1 1. Set SDI = 1 Short –1 pulse if reading a 0 bit
2. Pulse SCK
Table 26. Port B (Master) isoSPI Port Function Short –1 1. Set SDI = 0 (No return pulse if not in READ
COMMUNICATION EVENT TRANSMITTED PULSE 2. Pulse SCK mode or if reading a 1 bit)
(Port A SPI) (Port B isoSPI)
CSB Rising Long +1
CSB Falling Long –1
The lower isoSPI port (Port A) never transmits long
SCK Rising Edge, SDI = 1 Short +1
(CSB) pulses. Furthermore, a slave isoSPI port will only
SCK Rising Edge, SDI = 0 Short –1
transmit short –1 pulses, never a +1 pulse. The master
port recognizes a null response as a logic 1. This allows
for multiple slave devices on a single cable without risk
On the other side of the isolation barrier (i.e. at the other
of collisions (Multi-drop).
end of the cable), the 2nd LTC6811 will have ISOMD = VREG.
Its Port A operates as a slave isoSPI interface. It receives
68111fb
CSB t7 t6 t5
t1
SDI t2
tCLK
SCK t4 t3
t8
t11
tRISE
SDO Xn Xn-1 Z0
t10 t9 t10
Wn W0 Yn Yn-1
ISO B1
Wn W0 Yn Yn-1
ISO A2
tRTN
tDSY(CS) tDSY(CS)
tDSY(D)
Wn W0 Zn Zn-1
ISO B2
Wn W0 Zn Zn-1
ISO A3
68111 F25
0 1000 2000 3000 4000 5000 6000
CSB OR IMA
SCK OR IPA
VWAKE = 200mV
|SCK(IPA) - CSB(IMA)|
tDWELL= 240ns
WAKE-UP
RETRIGGERABLE
CSB OR IMA tDWELL = 240ns tIDLE = 5.5ms WAKE-UP
SCK OR IPA DELAY ONE-SHOT 68111 F26
Figure 26 illustrates the timing and the functionally will remain IDLE. This situation can occur when attempt-
equivalent circuit. Common mode signals will not wake ing to wake up the daisy chain after only tIDLE of idle time
up the serial interface. The interface is designed to wake (some devices may be IDLE, some may not).
up after receiving a large signal single-ended pulse, or a
low-amplitude symmetric pulse. The differential signal | Waking a Daisy Chain—Method 2
SCK(IPA) – CSB(IMA)|, must be at least VWAKE = 200mV A more robust wake-up method does not rely on the built-
for a minimum duration of tDWELL = 240ns to qualify as a in wake-up pulse, but manually sends isoSPI traffic for
wake-up signal that powers up the serial interface. enough time to wake the entire daisy chain. At minimum,
a pair of long isoSPI pulses (–1 and +1) is needed for each
Waking a Daisy Chain—Method 1
device, separated by more than tREADY or tWAKE (if the Core
The LTC6811-1 sends a long +1 pulse on Port B after it is state is STANDBY or SLEEP, respectively), but less than
ready to communicate. In a daisy-chained configuration, tIDLE. This allows each device to wake up and propagate
this pulse wakes up the next device in the stack which will, the next pulse to the following device. This method works
in turn, wake up the next device. If there are ‘N’ devices in even if some devices in the chain are not in the IDLE state.
the stack, all the devices are powered up within the time In practice, implementing method 2 requires toggling
N • tWAKE or N • tREADY, depending on the Core state. For the CSB pin (of the LTC6820, or bottom LTC6811-1 with
large stacks, the time N • tWAKE may be equal to or larger ISOMD = 0) to generate the long isoSPI pulses. Alternatively,
than tIDLE. In this case, after waiting longer than the time dummy commands (such as RDCFGA) can be executed
of N • tWAKE, the host may send another dummy byte and to generate the long isoSPI pulses.
wait for the time N • tREADY, in order to ensure that all
devices are in the READY state. DATA LINK LAYER
Method 1 can be used when all devices on the daisy chain All data transfers on LTC6811 occur in byte groups. Every
are in the IDLE state. This guarantees that they propagate byte consists of 8 bits. Bytes are transferred with the most
the wake-up signal up the daisy chain. However, this significant bit (MSB) first. CSB must remain low for the
method will fail to wake up all devices when a device in entire duration of a command sequence, including be-
the middle of the chain is in the READY state instead of tween a command byte and subsequent data. On a write
IDLE. When this happens, the device in READY state will command, data is latched in on the rising edge of CSB.
not propagate the wake-up pulse, so the devices above it
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I/P
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
68111 F27
68111fb
68111fb
LTC6811 calculates PEC for any command or data received Broadcast Commands (LTC6811-1 or LTC6811-2)
and compares it with the PEC following the command or
A broadcast command is one to which all devices on the
data. The command or data is regarded as valid only if
bus will respond, regardless of device address. This com-
the PEC matches. LTC6811 also attaches the calculated mand format can be used with LTC6811-1 and LTC6811-2
PEC at the end of the data it shifts out. Table 29 shows the parts. See Bus Protocols for Broadcast command format.
format of PEC while writing to or reading from LTC6811. With broadcast commands all devices can be sent com-
While writing any command to LTC6811, the command mands simultaneously.
bytes CMD0 and CMD1 (see Table 36 and Table 37) and In parallel (LTC6811-2) configurations, broadcast com-
the PEC bytes PEC0 and PEC1 are sent on Port A in the mands are useful for initiating ADC conversions or for
following order: sending write commands when all parts are being written
CMD0, CMD1, PEC0, PEC1 with the same data. The polling function (automatic at the
end of ADC commands, or manual using the PLADC com-
After a broadcast write command to daisy-chained
mand) can also be used with broadcast commands, but
LTC6811-1 devices, data is sent to each device followed
not with parallel isoSPI devices. Likewise, broadcast read
by the PEC. For example, when writing the Configuration
commands should not be used in the parallel configuration
Register Group to two daisy-chained devices (primary
(either SPI or isoSPI).
device P, stacked device S), the data will be sent to the
primary device on Port A in the following order: Daisy-chained (LTC6811-1) configurations support broad-
cast commands only, because they have no addressing.
CFGR0(S), … , CFGR5(S), PEC0(S), PEC1(S), CFGR0(P),
All devices in the chain receive the command bytes simul-
…, CFGR5(P), PEC0(P), PEC1(P)
taneously. For example, to initiate ADC conversions in a
After a read command for daisy-chained devices, each stack of devices, a single ADCV command is sent, and all
device shifts out its data and the PEC that it computed for devices will start conversions at the same time. For read
its data on Port A followed by the data received on Port and write commands, a single command is sent, and then
B. For example, when reading Status Register Group B the stacked devices effectively turn into a cascaded shift
from two daisy-chained devices (primary device P, stacked register, in which data is shifted through each device to
device S), the primary device sends out data on port A in the next higher (on a write) or the next lower (on a read)
the following order: device in the stack. See the Serial Interface section.
STBR0(P), …, STBR5(P), PEC0(P), PEC1(P), STBR0(S),
Polling Methods
… , STBR5(S), PEC0(S), PEC1(S)
The simplest method to determine ADC completion is
Address Commands (LTC6811-2 Only) for the controller to start an ADC conversion and wait for
An address command is one in which only the addressed the specified conversion time to pass before reading the
device on the bus responds. Address commands are used results. Both LTC6811-1 and LTC6811-2 also allow polling
only with LTC6811-2 parts. All commands are compatible to determine ADC completion.
with addressing. See Bus Protocols for Address command In parallel configurations that communicate in SPI mode
format. (ISOMD pin tied low), there are two methods of polling.
68111fb
tCYCLE
CSB
SCK
SDO
68111 F28
CSB
SCK
SDO
68111fb
SCK 1 2 N
SDO
68111 F30
CSB
SCK 1 2 N
SDO
68111 F31
CONVERSION DONE
68111fb
68111fb
68111fb
68111fb
68111fb
68111fb
68111fb
68111fb
68111fb
to support any additional load, a transistor with an even LT3990 33µH VREG
OFF ON EN/UVLO SW 5V
higher Beta may be required. PG BD 40mA
2.2µF 22pF 1M
The NPN collector can be powered from any voltage source RT FB 22µF
that is a minimum 6V above V–. This includes the cells that 374k
GND
316k
are being monitored, or an unregulated power supply. A
f = 400kHz
100Ω/100nF RC decoupling network is recommended for
68111 F33
68111fb
V+ DRIVE NSV1C201MZ4
100Ω LTC6811 RBM-0512S
6 1
C12 VREG +VOUT +VIN +5V
10nF 1µF 5 2 1µF
MOST CELL CONNECTIONS –VOUT –VIN
OMITTED FOR CLARITY 1µF
4
100Ω NC
C0 V–
4.7Ω 10nF
600Z
68111 F34
100nF 39µH
100Ω 7V TO 12V +5V
49.9k 4.7µF
180pF LT3999 RBIAS
V+ DRIVE NSV1C201MZ4 1M 453k
BAT54S BAT54S
LTC6811 VIN
100Ω
C12 VREG SWA UVLO
10nF 39Ω OVLO/DC
MOST CELL CONNECTIONS 1M 261k
OMITTED FOR CLARITY 1µF SWB RDC
100Ω PH9185.011NL
RT
C0 V– 10µF
1:1CT 4.7µF
ILIM/SS SYNC 12.1k
4.7Ω 10nF
600Z GND
17.4k
68111 F35
100nF
BAT54
100Ω
• 100Ω
V+
40µH 640µH
BAT54 100nF LTC6811 100nF
• 1k
VIN VIN SW C12
10µF LT8301 R 3.6V
10µF C11
ENABLE EN/UVLO RFB
3.6V
GND C10 DRIVE NSV1C201MZ4
3.6V
C9 VREG
3.6V 1µF
SOME CELL CONNECTIONS
OMITTED FOR CLARITY
C4
3.6V
C3
3.6V
C2
3.6V
C1
3.6V C0
V–
68111 F36
will only be drawn from the batteries during shutdown. It C11 12V 12V 96V
4
is critical to add a diode between the top monitored cell 1k
12V
S11 IPB
and V+ so that supply current will not conduct through 5 24V 48
8 12V
IBIAS
45
Internal Protection Features 9
S9 1k
12V
SDO (NC)
12V 12V 44
The LTC6811 incorporates various ESD safeguards to 10
C8
12V
ensure robust performance. An equivalent circuit showing S8 1k SDI (NC)
43
11 24V
the specific protection structures is shown in Figure 37. C7 12V 12V
12V
SCK (IPA)
While pins 43 to 48 have different functionality for the 12 42
12V
–1 and –2 variants, the protection structure is the same. 13
S7 1k CSB (IMA)
41
Zener-like suppressors are shown with their nominal clamp C6 12V 12V 12V
14 ISOMD
voltage, while the unmarked diodes exhibit standard PN 1k
40
S6
junction behavior. 15
12V
WDT
12V 12V 39
C5
16 12V
Filtering of Cell and GPIO Inputs S5 1k
DRIVE
38
17 24V 12V
The LTC6811 uses a delta-sigma ADC, which includes a C4 12V 12V VREG
37
delta-sigma modulator followed by a SINC3 finite impulse 18
12V
S4 1k DTEN
response (FIR) digital filter. This greatly relaxes input 19 36
demand the highest level of battery voltage ripple rejec- NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 35
tion, grounded capacitor filtering is recommended. This
Figure 37. Internal ESD Protection Structures of the LTC6811
configuration has a series resistance and capacitors that
decouple HF noise to V–. In systems where noise is less
68111fb
100Ω 100Ω
CELL2 C2 CELL2 C2
BSS308PE 3.3k BSS308PE 3.3k
S2 S2
33Ω 33Ω
10nF LTC6811 C * LTC6811
100Ω 100Ω
CELL1 C1 CELL1 C1
BSS308PE 3.3k BSS308PE 3.3k
S1 S1
33Ω 33Ω C
10nF *
100Ω 100Ω
C0 C0
10nF C
*
BATTERY V– V– BATTERY V– V–
68111 F38
*6.8V ZENERS RECOMMENDED IF C ≥ 100nF
2 2
1 1
CELL MEASUREMENT ERROR (mV)
CELL MEASUREMENT ERROR (mV)
0 0
–1 –1
–2 –2
–3 –3
–4 –4
–5 –5
–6 –6
–7 –7
–8 100nF –8 100nF
10nF 10nF
–9 1µF –9 1µF
–10 –10
100 1k 10k 100 1k 10k
INPUT RESISTANCE, R (Ω) INPUT RESISTANCE, R (Ω)
68111 F39a 68111 F39b
(a) Cell Measurement Error Range (b) Cell Measurement Error vs Input RC Values
vs Input RC Values (Extra Conversion and Delay Before Measurement)
(b) ADCV (C1/C7) Delay 6τ ADCV (all cells) CNV Time RDCVA-D
(c) ADCV (all cells) CNV Time RDCVA-D ADCV (C1/C7) Delay 6τ
68111 F40
to reduce TME levels to near data sheet specifications by the internal switches due to excessive die heating. When
implementing an extra single channel conversion before discharging cells with the internal discharge switches, the
issuing a standard all channel ADCV command. Figure 40a die temperature should be monitored. See the Thermal
shows the standard ADCV command sequence. Figure 40b Shutdown section.
and Figure 40c show recommended command sequence Note that the anti-aliasing filter resistor is part of the dis-
and timing that will allow the MUX to settle. The purpose charge path, so it should be removed or reduced. Use of
of the modified procedure is to allow the MUX to settle at an RC for added cell voltage measurement filtering is OK
C1/C7 before the start of the measurement cycle. The delay but the filter resistor must remain small, typically around
between the C1/C7 ADCV command and the All Channel 10Ω, to reduce the effect on the balance current.
ADCV command is dependent on the time constant of the
RC being used, the general guidance is to wait 6τ between
RFILTER LTC6811
the C1/C7 ADCV command and the All Channel ADCV com- C(n)
mand. Figure 39b shows the expected TME when using
the recommended command sequence.
+ RDISCHARGE 1k
S(n)
CFILTER
CELL BALANCING
RFILTER
C(n – 1)
Cell Balancing with Internal MOSFETs
With passive balancing, if one cell in a series stack becomes a) Internal Discharge Circuit
overcharged, an S output can slowly discharge this cell
C(n) LTC6811
by connecting it to a resistor. Each S output is connected BSS308PE
to an internal N-channel MOSFET with a maximum on + 3.3k
resistance of 25Ω. An external resistor should be con- S(n)
nected in series with these MOSFETs to allow most of the
heat to be dissipated outside of the LTC6811 package, as RDISCHARGE
C(n – 1)
illustrated in Figure 41a.
68111 F41
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RB1
RB2
RB1
RB2
RB1
V+
LTC6811
C12
RB2
S12
C11
RB1
S11
RB2 C10
S10
C9
RB1
S9
RB2 C8
S8
RB1 C7
S7
RB2 C6
S6
RB1 C5
S5
RB2
C4
S4
RB1 C3
S3
RB2
C2 V–
S2 C0
RB1
C1 S1
RB2
RB1
RB2
RB1
RB2
RB1
RB2
68111 F44
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isoSPI IBIAS and ICMP Setup in the READY and ACTIVE states, while a high IB increases
the amplitude of the differential signal voltage VA across
The LTC6811 allows the isoSPI links of each application
the matching termination resistor, RM. The IB current is
to be optimized for power consumption or for noise
programmed by the sum of the RB1 and RB2 resistors
immunity. The power and noise immunity of an isoSPI
connected between the 2V IBIAS pin and GND as shown in
system is determined by the programmed IB current, which
controls the isoSPI signaling currents. Bias current IB can Figure 45. The receiver input threshold is set by the ICMP
range from 100μA to 1mA. Internal circuitry scales up this voltage that is programmed with the resistor divider created
bias current to create the isoSPI signal currents equal to by the RB1 and RB2 resistors. The receiver threshold will
be half of the voltage present on the ICMP pin.
20 • IB. A low IB reduces the isoSPI power consumption
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The following guidelines should be used when setting the cables over 50m and a transformer with a 1:1 turns ratio
bias current (100µA to 1mA) IB and the receiver compara- and RM = 100Ω, RB1 would be 1.5k and RB2 would be 499Ω.
tor threshold voltage VICMP/2: The maximum clock rate of an isoSPI link is determined
RM = Transmission Line Characteristic Impedance Z0 by the length of the isoSPI cable. For cables 10 meters
Signal Amplitude VA = (20 • IB) • (RM/2) or less, the maximum 1MHz SPI clock frequency is pos-
sible. As the length of the cable increases, the maximum
VTCMP (Receiver Comparator Threshold) = K • VA possible SPI clock rate decreases. This dependence is a
VICMP (voltage on ICMP pin) = 2 • VTCMP result of the increased propagation delays that can cre-
ate possible timing violations. Figure 46 shows how the
RB2 = VICMP/IB maximum data rate reduces as the cable length increases
RB1 = (2/IB) – RB2 when using a CAT5 twisted pair.
Select IB and K (Signal Amplitude VA to Receiver Compara- Cable delay affects three timing specifications: tCLK, t6
tor Threshold ratio) according to the application: and t7. In the Electrical Characteristics table, each of these
specifications is de-rated by 100ns to allow for 50ns of
For lower power links: IB = 0.5mA and K = 0.5
cable delay. For longer cables, the minimum timing pa-
For full power links: IB = 1mA and K = 0.5 rameters may be calculated as shown below:
For long links (>50m): IB = 1mA and K = 0.25 tCLK, t6 and t7 > 0.9μs + 2 • tCABLE(0.2m per ns)
For addressable multi-drop: IB = 1mA and K = 0.4
1.2
CAT5 ASSUMED
For applications with little system noise, setting IB to 0.5mA
is a good compromise between power consumption and 1.0
0.8
and RM = 100Ω, RB1 should be set to 3.01k and RB2 set
to 1k. With typical CAT5 twisted pair, these settings will 0.6
•
LTC6811-1 isoSPI LINK
cal for each device in the network due to the daisy-chain
•
10nF 62Ω 300Ω
point-to-point architecture. The simple design as shown in IM 10nF
Figure 45 is functional, but inadequate for most designs. The V–
termination resistor RM should be split and bypassed with
a)
a capacitor as shown in Figure 47. This change provides
both a differential and a common mode termination, and IP
CT XFMR
as such, increases the system noise immunity. 51Ω 100µH CMC
• •
•
LTC6811-1 isoSPI LINK
The use of cables between battery modules, particularly
•
10nF 51Ω
in automotive applications, can lead to increased noise IM 10nF
susceptibility in the communication lines. For high levels V– 68111 F47
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IPB
49.9Ω
LTC6811-1
10nF
49.9Ω
GNDD
IMB
1k 1k
IBIAS
ICMP GNDD
IPA
49.9Ω
10nF
49.9Ω GNDD
GNDD 10nF*
V– IMA
•
GNDD
•
10nF*
GNDC
IPB
49.9Ω
LTC6811-1
10nF
49.9Ω
GNDC
IMB
1k 1k
IBIAS
ICMP GNDC
IPA
49.9Ω
10nF
49.9Ω GNDC
GNDC 10nF*
V– IMA
•
GNDC
•
10nF*
GNDB
IPB
49.9Ω
LTC6811-1
10nF
49.9Ω
GNDB
IMB
1k 1k
IBIAS
ICMP GNDB LTC6820
IPA • • IP
49.9Ω 10nF* 10nF* 49.9Ω 1k 1k
IBIAS
10nF 10nF ICMP
49.9Ω GNDB GNDA 49.9Ω GNDA
GNDB GNDA
V– IMA IM V–
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100Ω 3.3V
GNDB 590Ω
IMB
1.5k 499Ω
IBIAS
ICMP GNDB
VREG
IPA
100Ω 3.3V 10nF CMC
•
•
V– 100Ω 3.3V
GNDB
IMA
GNDB 1nF 1nF
VREG 590Ω
IPB
LTC6811-1 100Ω 3.3V 10nF
100Ω 3.3V
GNDA 590Ω
IMB
1.5k 499Ω
IBIAS
ICMP GNDA
VREG
IPA
100Ω 3.3V 10nF CMC
•
•
V– 100Ω 3.3V
GNDA
IMA
GNDA 1nF 1nF
68111 F49
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IPB
• •
LTC6811-1 49.9Ω 10nF*
10nF
49.9Ω GNDB
GNDB
IMB
1k 1k
IBIAS
ICMP
IPA IP
• •
LTC6820
49.9Ω 10nF* 49.9Ω
1k 1k
IBIAS
10nF 10nF ICMP
10nF* GNDA
49.9Ω GNDB 49.9Ω
GNDB GNDA GNDA
V– IMA IM V–
GNDB GNDA 68111 F50
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP
Figure 50. Interfacing an LTC6811-1 with a µC Using an LTC6820 for Isolated SPI Control
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LTC6811-2 VREGB
IPA ISOMD
• •
IBIAS
1.21k
ICMP
IMA 806Ω
V–
100nF
5V LTC6820 1.21k 806Ω GNDB
VDDS GNDB
EN IBIAS
5k MOSI ICMP
µC
SDO MISO GND
SDI SCK SLOW
LTC6811-2 VREGA
SCK CS MSTR 5V
CS IP IPA ISOMD
• • • •
POL IM
IBIAS
5V PHA VDD 5V
100Ω 1.21k
100nF ICMP
IMA 806Ω
V–
GNDA
GNDA 68111 F51
IPA
100µH CMC HV XFMR 22Ω
100µH CMC isoSPI
402Ω • • BUS
•
LTC6811-2
22Ω
•
15pF
IMA 10nF
V–
a)
IPA
CT HV XFMR 22Ω
100µH CMC isoSPI
402Ω • • BUS
•
LTC6811-2
22Ω
•
15pF
IMA 10nF
V–
68111 F52
b)
Transformer Selection Guide substantially, reducing noise margin. Some droop is ac-
ceptable as long as it is a relatively small percentage of
As shown in Figure 45, a transformer or pair of transform-
the total pulse amplitude. The leakage inductance primarily
ers isolates the isoSPI signals between two isoSPI ports.
affects the rise and fall times of the pulses. Slower rise
The isoSPI signals have programmable pulse amplitudes
and fall times will effectively reduce the pulse width. Pulse
up to 1.6VP-P and pulse widths of 50ns and 150ns. To be
able to transmit these pulses with the necessary fidelity width is determined by the receiver as the time the signal
the system requires that the transformers have primary is above the threshold set at the ICMP pin. Slow rise and
inductances above 60µH and a 1:1 turns ratio. It is also fall times cut into the timing margins. Generally it is best
necessary to use a transformer with less than 2.5µH of to keep pulse edges as fast as possible. When evaluating
leakage inductance. In terms of pulse shape the primary transformers, it is also worth noting the parallel winding
inductance will mostly affect the pulse droop of the 50ns capacitance. While transformers have very good CMRR at
and 150ns pulses. If the primary inductance is too low, low frequency, this rejection will degrade at higher frequen-
cies, largely due to the winding to winding capacitance.
the pulse amplitude will begin to droop and decay over
When choosing a transformer, it is best to pick one with
the pulse period. When the pulse droop is severe enough,
less parallel winding capacitance when possible.
the effective pulse width seen by the receiver will drop
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10Ω
LTC6811
100Ω V+
C12
B12 100Ω
C11
B11 B11 100Ω
C10
B10 B10 B10 100Ω
C9
B9 B9 B9 B9 100Ω
C8
B8 B8 B8 B8 B8 100Ω DRIVE
C7 VREG
B7 B7 B7 B7 B7 B7 100Ω
C6
B6 B6 B6 B6 B6 B6 B6 100Ω
C5
B5 B5 B5 B5 B5 B5 B5 B5 100Ω
C4 V–
B4 B4 B4 B4 B4 B4 B4 B4 100Ω
C3
B3 B3 B3 B3 B3 B3 B3 B3 100Ω
C2
B2 B2 B2 B2 B2 B2 B2 B2 100Ω C0
C1
B1 B1 B1 B1 B1 B1 B1 B1 100Ω
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100Ω
LTC6811 100nF
100Ω
V+
100nF C12
C11
BAT54 BAT54 C10
1k
C9 DRIVE NSV1C201MZ4
CMDZ5248B • 3.6V C8
10µF
40µH 40µH C7 VREG
CMHD448 • 3.6V C6 1µF
C5
VIN
2.7V TO 36V VIN SW R C4
10µF LT8301 3.6V C3
EN/UVLO RFB C2
ENABLE
C1
GND
3.6V C0
V–
68111 F54
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3.6V
3.6V
3.6V
3.6V 100Ω
IN+ OUT GPIO1
SENSE 10nF
100µΩ LTC6811
REF VREF2
IN– 1µF
VREG
LTC6915 V+ VREG
SHDN 1µF
10k 10k 10k
CS GPIO3
DIN GPIO4
1µF
CLK GPIO5
V– SERIAL DGND
V–
C+ C–
+5V –5V 68111 F54
VIN VOUT
1µF EN
LTC3261
10µF
MODE
RT GND
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100
90
VREF2 80
70
VTEMPx (% VREF2)
10k
60
VTEMP 50
NTC 40
10k AT 25°C
30
V–
20
10
0
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
68111 F55
1 16
ANALOG1 S0 VCC
2 15
ANALOG2 S1 SCL LTC6811
3 14 4.7k 4.7k 1µF 37
ANALOG3 S2 SDA VREG
4 13 33
ANALOG4 S3 A0 GPIO5(SCL)
5 LTC1380 12 32
ANALOG5 S4 A1 GPIO4(SDA)
6 11
ANALOG6 S5 GND 31 –
7 10 V
ANALOG7 S6 VEE
8 9 3 5
ANALOG8 S7 DO +
1 100Ω 27
LTC6255 GPIO1
1 16 4
ANALOG9
2
S0 VCC
15
– 2
ANALOG10 S1 SCL 10nF
3 14
ANALOG11 S2 SDA
4 13
ANALOG12 S3 A0
5 LTC1380 12
ANALOG13 S4 A1 68111 F57
6 11
ANALOG14 S5 GND
7 10
ANALOG15 S6 VEE
8 9
ANALOG16 S7 DO
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G Package
48-Lead G Plastic
Package SSOP (5.3mm)
48-Lead Plastic
(Reference SSOP
LTC DWG (5.3mm)Rev A)
# 05-08-1887
(Reference LTC DWG # 05-08-1887 Rev A)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
0.50
0.25 ±0.05
BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PARTING 0° – 8°
LINE
SEATING
0.50 PLANE
0.10 – 0.25 0.55 – 0.95**
(.01968)
(.004 – .010) (.022 – .037)
BSC 0.05
1.25 0.20 – 0.315† (.002)
(.0492) (.008 – .0124) MIN G48 (SSOP) 0814 REV A
REF TYP
NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
2. CONTROLLING DIMENSION: MILLIMETERS BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
MILLIMETERS
3. DIMENSIONS ARE IN **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
(INCHES)
†THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
4. DRAWING NOT TO SCALE
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
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100nF
100nF
100Ω
V+ IPB
100Ω LTC6811-1
C12 IMB TG110-AE050N5*
3.3k
CELL12 + S12 ICMP 1 16 isoSPIB+ 1
33Ω BSS308PE 1k
3.6V C11 IBIAS 2
• • 15
100Ω 10nF 100Ω isoSPIB– 2
S11 SDO (NC) 1k 3 14 isoSPI PORT B
C10 SDI (NC)
CELL11 + 6 11 +
isoSPIA 1
S10 SCK (IPA)
3.6V
7 • • 10
C9 CSB (IMA) 100Ω isoSPIA– 2
8 9 isoSPI PORT A
S9 ISOMD
C8 WDT 10nF 10nF
S8 DRIVE NSV1C201MZ4
*THE PART SHOWN IS A DUAL
C7 VREG TRANSFORMER WITH BUILT-IN
COMMON MODE CHOKES
S7 DTEN
CELL3 TO CELL11 CIRCUITS
C6 VREF1
S6 VREF2
1µF
C5 GPIO5
1µF
S5 GPIO4
1µF
C4 V–
S4 V–
CELL3 + C3 GPIO3 68111 TA02
3.6V
S3 GPIO2
100Ω
C2 GPIO1
3.3k
CELL2 + BSS308PE
S2 C0
33Ω
3.6V C1 S1
100Ω 10nF
3.3k
CELL1 + BSS308PE
33Ω
3.6V
10nF
RELATED PARTS
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88
LT 0817 REV B • PRINTED IN USA
www.linear.com/LTC6811-1
For more information www.linear.com/LTC6811-1 LINEAR TECHNOLOGY CORPORATION 2016