Digital Logic Design Laboratory Hand Book

Government College University, Faisalabad

Department of Electrical Engineering

Digital logic Design

Lab Manual
By
Engr.Irfan Riaz Shohab Sandhu

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Digital Logic Design Laboratory Hand Book

Prepared & Edited by:

Engr. Irfan Riaz Shohab Sandhu

irfanriazshohab@gcuf.edu.pk
shohabsons@hotmail.com

Verified by:

Dr. Engr. Arsalan Dawood Butt

Approved by:

Engr. Dr. Abdul Rauf Bhatti

Chairman, Associate Professor
Department of Electrical Engineering

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Digital Logic Design Laboratory Hand Book

PREFACE

The laboratory of each and every subject taught in the degree of Bachelors in Electrical

Engineering is of very much importance in every University. Fully equipped laboratory meeting

the industrial demands under the supervision of qualified, talented and practically motivated lab

assistants and lab engineers is also a basic criterion of the Pakistan Engineering Council. This

Manual has been formulated considering all these above mentioned points.

This manual is according to the equipment supplied by the RIMS, USA and meets the requirements

of all the course of Digital Logic Design as per the curriculum of GC University Faisalabad.

Special thanks to the staff and students for assisting me in the preparation of this manual.

With Regards
Engr. Irfan Riaz Shohab

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General Lab Instructions

 Each student group consists of a maximum of 2-4 students. Each group member is
responsible in submitting lab report upon completion of each experiment on their practical
Note book.
 Students are to wear proper attire i.e shoe or sandal instead of slipper. Jewelries are not
advisable as they might cause electrical shock.
 A permanent record in ink of observations as well as results should be maintained by each
student and enclosed with the report.
 The recorded data and observations from the lab manual need to be approved and signed
by the lab instructor upon completion of each experiment.
 Before beginning connecting up, it is essential to check that all sources of supply at the
bench are switched off.
 Start connecting up the experiment circuit by wiring up the main circuit path, then adds the
parallel branches as indicated in the circuit diagram.
 After the circuit has been connected correctly, remove all unused leads from the experiment
area, set the voltage supplies at the minimum value, and check the meters are set for the
intended mode of operation.
 The students may ask the lab instructor to check the correctness of their circuit before
switching on.
 When the experiment has been satisfactory completed and the results approved by the
instructor, the students may disconnect the circuit and return the components and
instruments to the locker tidily. Chairs are to be slid in properly.

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Experiment No. 1
VERIFICATION OF TRUTH TABLES OF ALL LOGIC
GATES
(Assemble the circuit related to each logic gate, manipulate
the circuit and then display their result.)
OBJECTIVE
 Familiarization with the RIMS ePAL Trainer (digital logic design prospective) and ICs
of all logic gates
 Familiarization with the proteus software tool (digital logic design prospective)
 Verification of truth tables of all logic gates

EQUIPMENT
 ePAL Trainer Board
 2 resisters 1K ohm
 Connecting wires

COMPONENTs
 IC Type 7400 Quadruple 2-input  IC Type 7408 Quadruple 2-input
NAND gates AND gates
 IC Type 7402 Quadruple 2-input  IC Type 7432 Quadruple 2-input OR
NOR gates gates
 IC Type 7404 Inverters  IC Type 7486 Quadruple 2-input
XOR gate
THEORY
An integrated circuit (IC) is a small electronic device made out of a semiconductor material. A
semiconductor material is a one which is neither a good conductor of electricity nor a good
insulator. Semiconductors make it possible to miniaturize electronic components, such as
transistors. Not only does miniaturization mean that the components take up less space, it also
means that they are faster and require less energy.
Active Components:
Those devices or components which required external source to their operation is called Active
Components.
For Example:
Diode, Transistors, SCR etc…
Explanation and Example:

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As we know that Diode is an Active Components. So it is required an External Source to its

operation. Because, If we connect a Diode in a Circuit and then connect this circuit to the Supply
voltage., then Diode will not conduct the current Until the supply voltage reach to 0.3(In case of

Germanium) or 0.7V(In case of Silicon). I think you got it

Passive Components:
Those devices or components which do not required external source to their operation is called
Passive Components.
For Example: Resistor, Capacitor, Inductor etc…
Explanation and Example:
Passive Components do not require external source to their operation. Like a Diode, Resistor does
not require 0.3 0r 0.7 V. I.e., when we connect a resistor to the supply voltage, it starts work
automatically without using a specific voltage. If you understood the above statement about active
Components

KEY BLOCK OF EPAL

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ICs Families

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Guide to Assembling your Circuits.

In this section we describe the use of the breadboard and give basic hints about the wiring process
needed to power up and interconnect your circuits. Assembling circuits on your breadboard is a
fast and easy process once you get used to it. To assemble your circuit first select the chips that
you need, insert them in the breadboard, wire up the power and ground connections as described
in the next section and next wire the logic elements according to the circuit connections that you
obtained from the design process. Before you insert a chip into the breadboard, make sure it is
properly oriented (see Fig.), and that when you press it down the pins of the chip actually enter the
holes and do not bend underneath the chip package. When wiring, be careful to hit the right hole
needed in the connection, because this is one of the most common mistakes found to cause an error
in your projects.
Breadboard Description.

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Logic gates are the digital circuits with one output and one or more inputs. They are the basic
building blocks of any logic circuit. Different logic gates are: AND, OR, NOT, NAND, NOR,
EX-OR. There logic is briefly explained below.
AND: Logic eqn. Y = A.B
The output of AND gate is true when the inputs A and B are True.
OR: Logic eqn. Y = A+B.
The output of OR gate is true when one of the inputs A and B or both the inputs are true.
NOT: Logic eqn. Y = Ā.
The output of NOT gate is complement of the input.
NAND: Logic eqn. Y = A.B
The output of NAND gate is true when one of the inputs or both the inputs are low level.
NOR: Logical eqn. Y = A+B.
The output of NOR gate is true when both the inputs are low.
EX-OR: Logic eqn. Y=AB+AB.
The output of EX-OR gate is true when both the inputs are low.

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Fig. 1.1 Symbol for digital logic gates

In a circuit, logic variables (values 0 and 1) can be represented as levels of voltage. The most
obvious way of representing two logic values as voltage levels is to define a threshold voltage;
any voltage below the threshold represents one logic value and voltages above the threshold
Correspond to the other logic value.
To implement the threshold – voltage concept, a range of low and high voltage levels is defined,
as shown in Fig. 1.2. This figure indicates that voltages in the range Gnd to Vo, max represent
logic value 0. Similarly, the range from V1, min to Vcc corresponds to logic value 1. Logic
signals do not normally assume voltages in undefined range except in transition from one logic
value to the other.

Fig. 1.2 Representation of logic values by voltage levels

CONNECTION DIAGRAM

Figure 1.3 IC 74LS00 (NAND Gate)

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Figure 1.4 IC 74LS02 (NOR Gate)

Figure 1.5 IC 74LS04 (NOT Gate)

Figure 1.6 IC 74LS08 (AND Gate)

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Figure 1.7 IC 74LS32 (OR Gate)

Figure 1.8 IC 74LS86 (XOR Gate)

PROCEDURE
1. First get above mentioned apparatus and component from the lab staff.
2. Turn ON the RIMS (ePAL trainer) and the required functions i.e. input, output terminals,
Vcc and GND etc.
3. Take IC 74LS00 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.1. And compare your result with truth table.
4. Take IC 74LS02 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.2. And compare your result with truth table.
5. Take IC 74LS04 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.3. And compare your result with truth table.
6. Take IC 74LS08 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.4. And compare your result with truth table.

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7. Take IC 74LS32 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.5. And compare your result with truth table.
8. Take IC 74LS86 and place it on bread board. Apply Vcc and GND to the specified pins
as shown in the pin configuration below. Apply four combination of input to each gate
of the IC and fill the following table 1.6. And compare your result with truth table.
RESULTS & CALCULATIONS
Table 1.1
IN OUT
A B Gate 1 (V) Gate 1 (H/L) Gate 2 (V) Gate 2 (H/L) Gate 3 (V) Gate 3 (H/L) Gate 4 (V) Gate 4 (H/L)
L L
L H
H L
H H

Table 1.2

IN OUT
A B Gate 1 (V) Gate 1 (H/L) Gate 2 (V) Gate 2 (H/L) Gate 3 (V) Gate 3 (H/L) Gate 4 (V) Gate 4 (H/L)
L L
L H
H L
H H
Table 1.3

IN OUT
A B Gate 1 (V) Gate 1 (H/L) Gate 2 (V) Gate 2 (H/L) Gate 3 (V) Gate 3 (H/L) Gate 4 (V) Gate 4 (H/L)
L L
L H
H L
H H

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Table 1.4
IN OUT
A B Gate Gate 1 Gate Gate 2 Gate Gate 3 Gate Gate 4 Gate Gate 5 Gate Gate 6
1 (V) (H/L) 2 (V) (H/L) 3 (V) (H/L) 4 (V) (H/L) 5 (V) (H/L) 6 (V) (H/L)
L L
L H
H L
H H

. Table 1.5
IN OUT
A B Gate 1 (V) Gate 1 (H/L) Gate 2 (V) Gate 2 (H/L) Gate 3 (V) Gate 3 (H/L) Gate 4 (V) Gate 4 (H/L)
L L
L H
H L
H H

Table 1.6
IN OUT
A B Gate 1 (V) Gate 1 (H/L) Gate 2 (V) Gate 2 (H/L) Gate 3 (V) Gate 3 (H/L) Gate 4 (V) Gate 4 (H/L)
L L
L H
H L
H H

CONCLUSION

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