Transistor Design

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 Est. read time: 41 minutes |  Last updated: August 21, 2019 by  John Gentile
Bipolar Junction Transistor (BJT) Design
Contents

re / ‘T’ Model
BJT Output Impedance: Early Effect
Emitter Impedance re
Input Impedance
Voltage Gain & Output Impedance
Common Emitter
Common Collector
Current Gain
Common Emitter
Common Collector
BJT Biasing for AC Circuits
Standard Voltage-Divider Bias Circuit
Common Emitter Amplifier Design
Improving Voltage Gain
Isolating Output Load
Frequency Response & Capacitor Selection
Common Collector Amplifier Design
Common Base Amplifier Design
BJT High-Frequency Response
Gain-Bandwidth Product
Miller Effect
Cascaded CE Amplifiers
BJT Noise Model
BJT Circuit Noise Analysis
Noise Matching
Cascaded Noise
Direct-Coupled BJT Circuits
CE-CC Amplifier
Cascode (CE-CB) Amplifier
Cascode Bias Design
Differential Amplifier (Long-Tailed Pair)
Background
LTP Small Signal Analysis: Single-Ended Input
LTP Small Signal Analysis: Differential Mode
Input
LTP Small Signal Analysis: Common Mode
Input
LTP Increases Bandwidth
Current Mirrors
Current Mirror: High Output Impedance
CMRR Improvement in LTP
Common Collector Distortion Improvement
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11/2/2019 Transistor Design | John-Gentile.com
DC Level Shifting
Output Stages & Classes
Class A
Class B
Contents
re / ‘T’ Model
The T orre model is a simple model for a BJT which is great for quickly characterizing a BJT
circuit’s behavior for low to mid frequencies. It is modeled as a three-terminal device, with a
dynamic resistancere and a simple, linear current-dependent current-source with gainβ
(given from the BJT’s datasheet) on base currentib ; by KCL, this simply means the total
emitter current isie = (β + 1)ib ≈ βib . NOTE: the simpli cation ofic ≡ ie is valid for
most analog analysis since the gainβis large- between 100 and 300- such that removing
the one extra base currentib term is< 1%error. The NPN model is explained here but the
PNP is the same with only a difference in polarity.
The collector terminal in the model is an ideal current source since a BJT operating in it’s
active region has nearly similar characteristics; the collector currentic is nearly independent
of the collector voltagevce (assumingvce is high enough that BJT is not in saturation).
Contents
This also follows the ideal current source characteristic of having nearly in nite output
impedance:
v Δvce → ∞
= r → ≈ ro = ∞Ω
i Δic → 0
BJT Output Impedance: Early Effect

As shown above though, a real transistor does not exhibit perfectly constant (zero slope)
output impedance in the curve above. Instead, there is a property called the Early Effect
which describes the increase of depletion regions within the transistor with a correlation to
increased bias voltage across the collector-emitter junction:
This Early Voltage is denoted by the device parameterVA which is an imaginary intercept
along the negative voltage axis which is shown to follow the slopes of resulting active
region plots. The Early voltage of a device is usually around 100V, with higher values
indicating higher output impedance numbers. The Early Effect and subsequent changes in
depletion regions can more accurately model the collector current and output impedances
knowing the Early Voltage of the device and the collector-emitter bias voltage:
VCE
IC = IB β(1 + )
VA
VA + VCE
ro =
IC
Output impedance of a BJT can also be speci ed by the BJT’s datasheet as output
admittancehoe in℧(Mhos), the inverse of which gives the output impedance of the BJT asro
.
Emitter Impedancere
Contents
The base emitter junction has a dynamic impedancere that is given from the relationship of
Bipolar Junction
v Transistor (BJT) Design
. Given the BJT can be seen as a forward biased diode from base to emitter, the
be
i e
Shockley diode equation can show the relationship betweenvbe andie .
v
be
V
ie = Is (e T
− 1)
WhereVT =
nKT
q
andnis device parameter (~1),K is Boltzmann constant,T is absolute
−12
temp andqis electron charge; at 25°C,VT ≈ 26mV .Is is saturation current (≈ 10 ). So
v
since i is not linear, and a xedre is ideal for our simple model, we can pick a value ofie on
be
the curve that is nominal for the application at hand and make linear by taking the derivative
of the Shockley diode equation w.r.t.vbe :
v v
∂
be
Is
be
ie
V V
[Is (e T
− 1)] ⇒ e T
≈
∂vbe VT VT
ie 1 VT
= ∴ re =
VT re ie
With this equation, quick estimates of emitter impedance can be made; for instance, at
room temperature and with a design speci cation ofie = 1mA, the emitter resistance is
26mV
= 26Ω .
1mA
Input Impedance
To get the input impedance of the BJT model looking into the base terminal, we can
Contents v v
express asZin = i = i . The base-emitter voltagevbe can be expressed as the voltage
in
in
be
created
Bipolar Junction by the emitter
Transistor (BJT)current
Designie through the previously calculated emitter impedancere
(using a speci ed collector current), and simpli ed to be a function of base currentib :
vb = ie re ⇒ (ib + ic )re ⇒ (ib + βib )re ⇒ ib (β + 1)re
vb ib (β + 1)re
∴ Zin = = ⇒ Zin = (β + 1)re
BJ T
ib ib
Plugging the value ofβin for the same speci ed collector current- usually given in a
datasheet- gives the resultant input impedance; this also means the variations inβ(over
process, temperature and collector current) have a direct impact on input impedance as
well.
This same calculation follows for input impedance when resistance is added to the emitter
(e.g. emitter resistorRE ) in a common emitter design such that the base voltage is still
dependent on the current ow through the total resistance at the emitter. Thus, this can
also be expressed as:
Zin = (β + 1)(re + RE )
Furthermore, the bias resistorsR1andR2in an ampli er stage (explained more below) can
be factored into the input impedance as being in parallel with this adjusted BJT impedance:
Contents
Zin = R1 ∥ R2 ∥ Zin
amp BJ T
Again, input impedance of the BJT is directly related toβbut overall input impedance, due to
the parallel nature of the bias resistors, is dominated by the least resistance, commonly the
R2bottom leg resistor.
Voltage Gain & Output Impedance
Common Emitter
For a simple common emitter con guration where the output voltage comes from the
collector node- note, the DC bias circuit is not present but for instructional sake, ignore for
now- the voltage gain can be found using similar parameters above (given speci edic ,βand
re ) using small-signal analysis (note also setting DC voltage sources likeVCC → 0V ):
Contents
Voltage gain is given by:

vout vc
Av = =
vin vb
Collector voltage is negative due to grounding theVCC and current owing towards the
emitter such that:
vc = −ic Rc = −βib Rc
Base voltage is produced by the emitter currentie through the equivalent series resistance
ofre + Re but is simpli ed in terms ofib (given relationship with current gainβ) such that we
can simplify the voltage gain equation:
vb = ie (re + Re ) ⇒ ib (β + 1)(re + RE )
vc −βib Rc
∴ Av = ⇒
vb ib (β + 1)(re + RE )
Since we already approximatedβ ≈ β + 1 , the voltage gain can be further simpli ed with
little error to:
−βib Rc −βib Rc Rc
≈ ⇒ Av = −
ib (β + 1)(re + RE ) βib (re + RE ) re + Re
Furthermore, since usually the emitter resistor componentRe ≫ re (e.g. given a nominal
re = 26Ωat room temp andic = 1mAandRe > 1kΩ),re can often be ignored with
reasonable error such that:
Rc
Av ≈ − , when(Re ≫ re )
Re
What’s also powerful about this simpli cation is that the ideal voltage gain is independent
of device characteristics likeβ.
When looking at the output impedance of there model of a common emitter con guration,
the external resistorRc is in parallel with the series combination of the current source
impedanceZc ,re and external resistorRe :
Zout = Rc ∥ (Zc + re + Re )
However, since in this model we are using an ideal current source, the impedanceZc = ∞.
Thus, the added resistancesre andRe are insigni cant and the series impedance is∞, and
since this looks like an open circuit in parallel withRc , the output resistance is simplyRc :
Zout = Rc ∥ ∞ ⇒ Zout = Rc
However, the current source in our model may not always be able to be treated as having
in nite output impedance due to the contribution ofro depending on collector current (or
more accurately the Early Effect ):
Contents
This value is highly dependent on base current (see varyingIC vsVCE slopes discussed
previously ) but is sometimes large enough to be a factor in computing output
impedance such that:
Zout ≈ ro ∥ RC
When the series combination ofre + RE is negligible compared toro , which is often the
case.
This inclusion ofro can affect voltage gain as well if it’s in the same order of magnitude as
RC ; both are in parallel with each other so a more precise output voltage at the collector
would be the potential across both. Thus CE voltage gain can be given as:
RC ∥ ro
Av = −
re + RE
Common Collector
For a common collector con guration, the output voltage comes from the emitter node.
Contents
Thusvout is produced from the current through external resistorRe such that:
vout = ie Re
The base voltage at the input is the emitter current through the series resistance ofre and
Re :
vin = vb = ie (re + Re )
vout ie Re Re Re
Av = = = ≈ , when(Re ≫ re )
vin ie (re + Re ) (re + Re ) Re
∴ Av ≈ 1
The common collector’s near unity gain is why this con guration is also called a Voltage
Follower as the output voltage closely follows the input voltage.
The output impedance for a common collector is a little less apparent though; since it’s
known that the ideal current source has∞impedance, the whole collector node looks like
an open circuit and thus one would reason thatZout = Re ∥ (re + Rb )(note an added
base resistance to illustrate the point). However, this is not true as the current throughre
andRb are not the same! To solve this, we know that the emitter currentie = ib (β + 1)
thus we treat the current as a ratio ofib : ib (β + 1)throughRb andre respectively. This
means the current throughRb isβ + 1times less than through the emitter so we can treat
′ Rb
the base resistance as effectively equallingRb = .
β+1
Contents
Rb
′
∴ Zout = Re ∥ (re + R ) ⇒ Zout = Re ∥ (re + )
b
β + 1
This effective scaling of the base-emitter impedances through the BJT is known as the
base-emitter re ection rule and means that impedances at the emitter appearβ + 1times
larger when looking in through the base and, inversely, base impedances appearβ + 1
times smaller when looking through the emitter.
Current Gain
Current gain,Ai , is simply output current divided by input current, so simplifying further, we
can see current gain is the voltage gain multiplied by the ratio of input impedance to output
impedance:
io vo /Zo vo Zi
Ai = = = ∗
ii vi /Zi vi Zo
Zin
∴ Ai = Av
Zout
The current gain of a particular BJT can also be used to determine how many “stages” of
BJT ampli ers are required to meet a system level gain speci cation. For example, if a
system speci cation called for a current gain of 10,000 it would be hard for a single BJT
circuit to meet that, given the typical device current gain is100 < β < 300. Since current
gain is usually multiplicative with each BJT stage, we can take the n-th root of the system
current gain speci cation (where n would be the number of BJT stages) until the value is
below a typical deviceβ. For instance, if we take the square root of the speci cation of
10,000 we get√10, 000 = 100which is the typical current gain for a BJT, so two stages
would likely satisfy the requirement.
Common Emitter
With common CE circuits, this current gain is similar to theβof the BJT used. So if a system
needs a current gain that is≫ β, than one knows multiple stages will be required to meet
that spec.
Common Collector
Zin
Since the voltage gain for a CC stage is about unity, the current gain isAi ≈ . From
Zout
previous, we know the output impedance is (when DC bias resistors are used and
Rb = R1 ∥ R2 ):
R1 ∥ R2
Zout = Re ∥ (re + )
β + 1
Contents
And we know the input impedance to be:
Zin = R1 ∥ R2 ∥ (β + 1)(re + RE )
R1 ∥ R2 ∥ (β + 1)(re + RE )
∴ Ai =
R1 ∥R2
Re ∥ (re + )
β+1
This current gain is nominallyAi ≈ β

2
which makes the CC ampli er a great buffer.
BJT Biasing for AC Circuits

Since the AC performance or application of BJT circuits is highly dependent on collector
currentIC and other DC operating points- as well as fundamentally keeping a BJT in its
active region, for instance- the need for proper biasing circuitry around a BJT circuit is
critical to the overall design. A DC bias circuit may also contend with circuit/environment
variables such as:
Ambient temperature changes

Part/process variation (resulting in changes toβfor instance)
Resistor tolerances
Power dissipation (self-heating affecting tempco similarly to ambient temperature
changes)
For example, DC bias of an NPN BJT should generally achieve the following to operate
adequately:
VCE high enough that the BJT is operating in its Active region (out of saturation)
Base-emitter voltageVBE > 0V
Base-collector voltageVBC < 0V
Standard Voltage-Divider Bias Circuit
Contents
To specify a standard voltage-divider bias network for an NPN BJT, there are some general
steps one can take:
Vcc −Vee
1. SetVC =
2
: this allows the most voltage swing at the collector, equally in both
directions. If the rail voltages are fairly low, the drop acrossRE can be accounted for
by setting:
Vcc − VE
VC =
2
Since for NPN transistors to function,VCE must be positive, so any drop acrossRE is
not available as voltage swing at the collector.
2. Set Collector CurrentIC large enough for required output current: make sure the
intended collector current isn’t too high that the BJT is dissipating too much power
but also high enough that the current gainβis high enough for good high frequency
performance; this is commonly in the range of 0.1mA to 10 mA.
3. Set Emitter VoltageVE slightly aboveVee : since we want the largest output voltage
swing range at the collector, we relatively want the emitter voltage to be close to the
negative rail. However, we also want to account for changes in emitter voltage due
to temperature; given a constantVB , the dropVbe has a tempco of around -2mV/°C,
so for every +1°C increase in temperature, the emitter voltageVE increases by +2mV,
thereby increasingIE . So for instance, ifVee = GN D(0V ), setVE = 1V so
changes inVbe do not affect emitter current too greatly, while also not wasting too
much power acrossRE . If temperature stability is desired though- at the cost of
decreased output range- one can increaseVE so that the change inVbe is even less
noticeable.
4. Set Emitter ResistorRE : with a targetVE , and the assumption thatIE ≈ IC for large
β, we can set the emitter resistor knowing the potential across it and the current
through it:
VE − Vee
RE =
IC
5. Set Collector ResistorRC : given the intended DC operating point ofIC andVC , the
resistor can simply be calculated by:
Vcc − VC
RC =
IC
6. SpecifyVB : with an intended emitter potential of 1V and

= VEintended + Vbe
, the base voltage should be set to 1.7V. This will be achieved by the
Vbe ≈ 0.7V
voltage divider ofVcc withR1&R2. The simple resistive voltage divider does not
Contents provide tightly controlled line regulation (e.g. doesn’t compensate for changes inVcc )
nor load regulation (e.g. doesn’t compensate for changes in load current) but is
Bipolar Junction Transistor
adequate (BJT)
for mostDesign
designs. However, the selection of these resistors cannot be
arbitrary as they also control the base currentIB .
7. TargetIB given expected BJT current gain: use the typical current gainβof the BJT
used to calculate the target base current given the collector current speci ed. Noteβ
is also dependent on collector currentIC and temperature:
IC
IB =
βtyp
8. Set Voltage Divider Resistors: A rule of thumb in this design is to have the current
through the voltage divider be about 10x that which ows into the base of the BJT;
this is a compromise between a low impedance circuit with high base current (which
provides more stable bias but also causes a lot of current to divert from the
transistor leading to more static power consumption) and a higher impedance
circuit with low base current (which is more susceptible to uctuations in collector
voltage due to changes inβ). Thus, the bottom leg of the divider can be found by:
VB − Vee
R2 =
10 ∗ IB
Similarly the top leg is found by accounting for the extra base current pulled through
the same resistor (current entering base node is equal to current owing out to BJT
+ current owing through bottom resistor leg):
Vcc − VB
R1 =
11 ∗ IB
The capacitorsCI N andCC are used to isolate the bias circuit from external DC disturbance
or loading while allowing AC voltages to pass.Ce is chosen to bypass the emitter resistor at
operating frequencies to allow full AC gain.
Deviations from these design parameters due to process (min/max deviceβ) or

temperature (change inβandVbe ) can be calculated by:
1. Computing new values of base current (due to changes inβfor a targetIC ) and base
voltage given the thevenin equivalent circuit of the resistor divider network:
R2 IC
VB = Vcc ( ) − ( )R1 ∥ R2
R1 + R2 β
2. Calculating any changes in circuit due to system changes (e.g.Vbe changes with
temperature).
3. Using any changes to potentialVE overRE to calculate changes in emitter current,
which we can equate to changes in collector current sinceIE ≈ IC .
4. If there’s a large change in calculatedIC than what was assumed in Step 1,
recalculate steps 1-3 until the change is minimal (the values considered converged).
5. Calculate output voltage at the collector knowing the positive rail voltage and current
throughRC :
VC = Vcc − IC RC
In general this bias design uses a fair amount of components but can maintain≈ 10% of
output across a range of temperature andβ uctuations.
Common Emitter Ampli er Design
Improving Voltage Gain

Contents
As noted earlier in standard bias circuit design , the existence of the emitter
capacitor (BJT) Design
CE is used to help bypass the emitter resistorRE at operating frequencies. This is
because we don’t want to mess with the DC bias resistors we setup for stability but we
usually want improved voltage gain over the standard CE voltage gain given by
RC ∥ro
Av = − ; for instance withRC ,
= 1.4kΩ RE + re = 100Ω andro ≫ RC , the gain
re +RE
is only 14.
Full Bypass
With a capacitorCE directly in parallel withRE , the external emitter resistance is completely
shorted at high frequencies (or large enough for a given range of frequency operation)
which leads to maximum gain due to being only limited by the BJT’s internal emitter
resistance:
RC ∥ ro RE =0 RC ∥ ro RC
Av = − → Av = − ≈ − , (ro ≫ RC )
re + RE re re
Partial Bypass
However, in most systems we want to control the actual amount of gain in a given CE
ampli er which means we only want to short some of the emitter resistance, but not all.
This leads to a common con guration where the DC emitter resistance found from
standard bias calculations is split into two resistors, with the bottom leg being shorted at
high-frequencies (there is another con guration where the second resistor follows the
capacitor but involves heavier math- parallel resistance withRE - with little bene t):
Contents
Where the top resistorR^E that is always present is simply the calculated DC Bias emitter
resistorRE subtracted by the series resistorRes which is shorted at high frequencies:
^
RE = RE − Res
So at high frequencies, the voltage gain is given by:
RC ∥ ro RC
Av = − ≈ − , (ro ≫ RC )
^ ^
re + RE re + RE
And, given an already calculatedRC from the bias circuit, and a calculatedre , one can nd
^
RE andRes from:
RC ∥ ro
^
RE = − re
Av
target
^
Res = RE − RE
DCBias
This addition of the emitter capacitor means that the BJT input impedance we
calculated earlier needs to be adjusted for:
Zin = (β + 1)(re + Zemitter )
BJ T
With noR^E , thus maximum gain, the input impedance is very low which can lead to voltage
divider errors at the input (ideally we want as high input impedance as possible for voltage
ampli ers). The more voltage gain, the lower the input impedance.
Contents As mentioned before, current gainAi is mainly dependent on deviceβ, and it is largely
independent of the emitter capacitance added to bypass the emitter resistor. As the voltage
Bipolar Junction
gainATransistor (BJT) Design
v is nearly inversely related to input impedanceZin , whenAv rises with added bypass
in the emitter circuit,Zin drops at a similar rate.
Isolating Output Load

Since we don’t want the DC bias circuit to be affected by a load connected at the output, it’s
common to add a series, DC-blocking, output capacitorCout to isolate the CE circuit from
the load.
However, this has consequences on the AC circuit response as the load is in parallel with
there small signal BJT model (shown w/o emitter capacitor):
Contents
This leads to the collector voltage beingvc = −ic (ro ∥ RC ∥ Zload ). Therefore, the
voltage gain equation, with an emitter capacitor from above, can be expanded with a load
attached as:
RC
w/load (ro ∥ RC ∥ Zload )
Av = − → Av = −
^ ^
re + RE re + RE
This means that to preserve a target voltage gain, ideally the load impedance
ZL ≫ (ro ∥ RC )(and sincero is usually much greater thanRC , we can usually simplify
that we want load impedance to be much more greater thanRC ). Thus, with light loads
relative to the collector resistance, the voltage gain drops below speci cation.
Frequency Response & Capacitor Selection

Nominally, a BJT CE ampli er circuit will not operate from DC to Daylight but instead in a
certain band of frequencies. The 3dB bandwidth has many factors. The low frequency
cutoff is mainly a function of the input & output DC coupling capacitors and the emitter
capacitor (if used for higher gain). The high frequency cutoff is dependent upon the BJT’s
speci cations- a BJT only has a certain bandwidth itself- and the capacitance of the
connected load. To acheive a certain low & high frequency cutoff, we must choose the
emitter, input and output capacitors.
Emitter Capacitor Selection- Full Bypass
In a full-bypass emitter con guration for a CE ampli er, the capacitor is in parallel withRE
RC
and we already know the gain is given byAv = − . To expand this, the emitter
re +ZE
RE
impedance isZE = R E ∥ XC
E
= . Thus the full derivation of gain is:
1+jωRE CE
RC
Av = −
RE
re +
1+jωRE CE
As before, when the input frequency is well above the lower cutoff frequencyωc , the gain
can be simpli ed to:
Contents RC
Av ∣ω≫ω ≈ −
c
re
So if we desire to nd the lower frequency cutoff point, the gain will be 3dB lower than the
1
midband gain leading orAv × . So setting the two gain equations equal to each other
√2
can solve for the desired emitter capacitor using the magnitude of the reactive impedance:
RC RC
− = −
RE
√2re re +
1+jωc RE CE
2 2
√1 + (ωc RE CE )
1 ∣ 1 + jωc RE CE ∣ 1
= ∣ ∣ → =
√2re ∣ re (1 + jωc RE CE ) + RE ∣ √2re √(re + RE )
2 2
+ (ωc RE CE )
2
1 1 + (ωc RE CE )
=
2 2 2
2re (re + RE ) + (ωc RE CE )
2 2
(RE + re ) − 2re
2
C =
E 2 2 2
r e ωc R
E
When BJT internal emitter resistancere is≪ RE - which is often the case- the numerator of
the equation above can reduce yeilding a much simpler, and logical, representation of
required capacitance as essentially a time constantτ related tore :
2
R 1
2 E
RE ≫ re ⟹ C = → CE =
E 2 2 2
r e ωc R r e ωc
E
Emitter Capacitor Selection- Partial Bypass
A similar derivation as above can be performed (equating mid-band gain equation at -3dB
with the full voltage gain equation with emitter capacitor reactance to solve for emitter
capacitance at a certain frequency) and is very lengthy and leads to:
2
√R ^ 2 ^
es − (re + RE ) + 2(re + RE )Res
CE =
^
ωc (re + RE )Res
But this is not intuitive and can be approximated into a time constant like equation above
^
based on the nearly equivalent resistance ofRes ∥ (re + RE ) :
1
CE ≈
^
[Res ∥ (re + RE )]ωc
Input Capacitor Selection
Given we know the total input impedance of a CE circuit to be
R1 ∥ R2 ∥ Zin , we can assume that any emitter capacitor has impedanceXC
BJ T E
= 0
such that the input capacitor is chosen for a given low frequency cutoffωc as:
1
Cin =
ωc (R1 ∥ R2 ∥ Zin )
BJ T
Output Capacitor Selection

Contents Similarly to the input capacitor selection, the output capacitor forms a time constantτ with
the output impedance- which we know previously to be Zout = ro ∥ RC - and the
load impedance (which could be a nominal/speci ed load or the input impedance of the
following ampli er stage):
1
Cout =
ωc [(ro ∥ RC ) + ZLoad ]
In general, the computed capacitor values can be rounded up to the next largest standard
value to ensure the lower frequency cutoff speci cation is met or exceeded given the other
system variables and component tolerances.
Common Collector Ampli er Design

Common Collector (CC) ampli ers are useful circuit building blocks in that they provide
high input impedance (which presents less of a load to a previous stage/input) and low
output impedance (less voltage divider error to following stage, assuming it has high input
impedance) while having a voltage gainAv ≈ 1; this unity gain is useful in seperating
stages and using a CC ampli er as a buffer (or impedance transformer) as well as the fact
that they have very large current gain usually withAi ≈ β 2 .
Contents
The biasing design is similar to a CE stage however:

The Collector is tied directly toVcc (no collector resistor needed).
Output is taken from the emitter node so set the DC bias halfway between the rail
Vcc −Vee
voltagesVE =
2
to maximize output voltage swing.
Common Base Ampli er Design
In a common base (CB) BJT ampli er, the output is taken at the collector and the input is
applied to the emitter through an AC coupling capacitorCin to protect the DC bias. The DC
bias is similar to the CE circuit, however the emitter resistor can be replaced with a generic
current source andVE is highly application dependent.
The input impedance (ignoring the source impedance connected in the diagram) looking
into the emitter is simply the parallel combination ofre andZE , whereZE can be either a
standard emitter resistorRE or the impedance of a current source (e.g.ro ):
Contents Zin = re ∥ ZE
Output
Bipolar Junction impedance
Transistor looking
(BJT) into the collector is similarly the parallel resistance of the
Design
collector resistor and the inverse of the BJT admittancehOE :
1
Zout = RC ∥ ro → Zout ≈ RC , when ≫ RC
hOE
The voltage gain can be given by nding the ratio of collector voltage to emitter voltage:
vout = −ic (ro ∥ RC ) = −ib β(ro ∥ RC )
vin = −ib (β + 1)(Rs + re )
vi −ib β(ro ∥ RC ) ro ∥ RC
Av ≜ = ≈
vo −ib (β + 1)(Rs + re ) Rs + re
Zin
The current gain de ned asAi ≜ Av can be found as:
Zout
ro ∥ RC re ∥ Z E re ∥ Z E
Ai = ( )( ) →
Rs + re RC ∥ ro RS + re
This can be further reduced ifZE ≫ re and no source connected soRS = 0 :

re
Ai ≈ → Ai ≈ 1
re
This makes sense that current gain is about unity sinceIC ≈ IE . Thus the CB ampli er can
be used as a current gain buffer.
BJT High-Frequency Response
Gain-Bandwidth Product
The main gure of merit for high-frequency response of a BJT is it’s current gain-
bandwidth product (GBW) which is usually given in datasheets asfT or it’s
transition frequency.
Contents
This transition frequency is the extrapolated product of the low frequency current gain and
the high cutoff frequency (-3dB point) as it is representative of the frequency at which the
current gain would drop to unity (gain of 1, or 0dB). This also means that there is a direct
tradeoff between gain and bandwith; the higher the magnitude of the gain|Av |, the lower
the high-frequency 3dB cutoff pointfB occurs:
fT
fB =
|Av |
fTalso increases with collector currentIC so running a BJT hotter can increase its effective
BW (up to a certain point).
Miller Effect
Another primary factor in the high-frequency BW limit of BJTs in large, inverting gain
con gurations (e.g. CE ampli ers) is due to the Miller effect which effectively
multiplies the stray input capacitance of the BJT by the voltage gain. The miller capacitance
can be shown with an ideal inverting voltage ampli er with gainAv (∴ Vo = −Av Vi ) and
reactive impedanceZ = XCm :
Contents
Given an ideal ampli er, the ampli er input draws no current (∞input impedance) so all the
current (BJT)
goes through Design
Z leading to an input impedance inversely related to gain:
Vi − Vo Vi (1 + Av ) Vi Z
Ii = = → Zin = =
Z Z Ii 1 + Av
1
WithZ = XC = , we can see where the multiplicative effect of gain on input
jωCin
capacitanceCin comes from and the effective miller capacitanceCm is derived by(1) :
1
Zin = → ∴ Cm = (1 + Av )Cin (1)
jωCin (1 + Av )
For a BJT there exists two main stray capacitances: input capacitance (between base and
emitter) and output capacitance (between collector and base). The miller capacitanceCm
(which is a product of voltage gainAv andCcb ) is added to the input stray capacitance
Thus, given an input impedance of the BJT circuit and the source impedance of an input
voltage source, there exists a pole from the time constantτ = RC formed which gives the
dominant high-frequency cutoff pointfH ,1 (2) :
1
fH ,1 = (2)
2π(Zsource ∥ Zin )(Cbe + (1 − Av )Ccb )
There also exists another HF polefH ,2 given from the output capacitance & output
Contents impedance, however it’s usually much higher frequency than the input capacitance
(assuming no external load capacitance):
1
fH ,2 =
2πZout Cout
Av +1
Note,Cout ≈ Ccb .
Av
Cascaded CE Ampli ers

Since we know that there’s a tradeoff between gain and bandwidth in a BJT ampli er, what
if we wanted the best of both worlds? That’s where cascading one or more CE ampli ers to
the output of a CE stage may help. For instance, if we need to hit system gainA, but need
higher BW, we could use two CE stages, each with a gain of√Ato achieve more BW in each
stage (due to constant gain-bandwidth product). For voltage stages, we ideally want high
input impedance and low output impedance to minimize voltage divider losses to each
stage.
There are two main methods to calculate system gain of a cascaded CE that produce
similar results:
1. Compute unloaded gainG,Zin andZout for each stage and cascade the transfer
functions. Then correct for voltage divider loss between stages.
2. Compute the loaded gain of each stage by including the load resistance in the gain
calculation. Then cascade transfer functions.
For example, with the following cascaded CE circuit, method #1 can be used to nd the
system gain:
Stage 1 Properties
R12
Base voltage:VB = Vcc (
R11 +R12
) ≈ 1.7V
Emitter voltage:VE = VB − vbe ≈ 1.0V
VE
Device Current:IE =
Re1
= 1.0mA →≈ IC
VT
BJT internal resistance:re = = 26Ω
IE
Deviceβ@IC = 1.0mA → β = 120

Inverse output admittance @IC = 1mA → ro = 120kΩ
Input Impedance:Zin1 = R11 ∥ R12 ∥ (β + 1)re = 2.7kΩ
Rc1
Voltage Gain:Av = −
re
= −230
Output Impedance:Zout1 = ro ∥ Rc1 ≈ 6kΩ
Contents Stage 2 Properties

R22
Base
Bipolar Junction Transistor voltage:
(BJT) VB = Vcc (
Design R +R
) ≈ 1.8V
21 22
Emitter voltage:VE = VB − vbe ≈ 1.1V

VE
Device Current:IE =
Re2
≈ 5.0mA →≈ IC
VT
BJT internal resistance:re = ≈ 5Ω
IE
Deviceβ@IC = 5.0mA → β = 150

Inverse output admittance @IC = 5mA → ro = 42kΩ
Input Impedance:Zin2 = R21 ∥ R22 ∥ (β + 1)re = 680Ω
Rc2
Voltage Gain:Av = −
re
= −230
Output Impedance:Zout2 = ro ∥ Rc2 ≈ 1kΩ
Given these properties of each stage, we can build a representative circuit of voltage
dependent voltage sources (voltage gain of each stage) to compute the effects of the input
voltage dividers and output load on the effective system gain:
2.7kΩ
vin1 = vi = 0.98vi
50Ω + 2.7kΩ
680Ω
vin2 = −230 ∗ vin1 = −23vi
680Ω + 6kΩ
1kΩ
vout = −230 ∗ vin2 = 2645vi
1kΩ + 1kΩ
Av = 2645(68.4dB)
total
BJT Noise Model

BJTs inherent noise can be modeled by both current and voltage noise sources coinciding
as separate sources.
Contents
From both noise sources, there exists a resistive noise parameterRN that is developed from
device theory (not a lumped component) equivalent to the square root ofβand internal
emitter resistance:
vn
RN = = √β ∗ re
in
The use ofRN in noise analysis results in a conservative, or pessimistic, evaluation of noise
levels of a given circuit (roughly 4-5 times greater than theoretical low-noise BJT levels) that
are good enough for initial analysis. The noise voltage and current sources- in RMS since
random, uncorrelated sources- can be de ned as:
vn = √4kT RN B
(RM S)
4kT B
in = √
(RM S)
RN
SinceRN = √ β ∗ re , we can control noise levels with choice of circuit emitter/collector

VT
current sincere = (e.g. higher emitter current leads to lower noise).
IE
Noise is often referred to the input of a device as Referenced To Input, or RTI. Noise
Referenced To Output, or RTO, can be found by multiplying the RTI noise by the voltage gain
Av .
BJT Circuit Noise Analysis

The total noise of a BJT circuit can be found by analyzing the individual noise sources and
combining them into a total noise contribution. Importantly, the analysis should be done for
a given operational bandwidth (either theoretical or dictated by band-limiting ltering or
other system effects) and a given operational temperature (assume room temp if not
speci ed) as both directly contribute to the magnitude of noise seen (e.g. higher system
bandwidth, higher noise voltage).
Contents
1. First, the transistor noise resistanceRN = √β ∗ re should be found.

2. The transistor voltage noise (vn,Q ) and current noise (in,Q ) can be found by:
vn,Q = √4kT RN B
4kT B
in,Q = √
RN
3. Find the Johnson noise of the resistorsR1&R2as they form parallel current
noise sources with the BJT current noise sourcein,Q , where the current noise can be
found with a resistanceRxas:
4kT B
in,Rx = √
Rx
4. The total parallel current noise can then be found by combining the RMS current
noise sources as:
2 2 2
in,Qtotal = √i + i + i
n,R1 n,R2 n,Q
5. The equivalent input resistance can be used to express the combined current noise
as a voltage noise across the equivalent resistance at the base, and in the above
circuit, the BJT input resistanceRin,Q is equivalent to(β + 1)re since the emitter is
fully bypassed by the emitter capacitorCE at operating frequency:
Req = Rs ∥ R1 ∥ R2 ∥ Rin,Q
∴ vn,Qtotal = in,total ∗ Req
6. The source voltage noisevn,s can be found by the Johnson equation:
vn,R = √4kT Rs B
s
7. The Johnson noise contribution from the collector resistorRC is applied to the
output (assuming CE ampli er) so, as mentioned above, we can have noise referred
to the input by dividing by voltage gainAv . In a CE con guration like above with a
Contents fully bypassed emitter,Av ≈ −
RC
re
whenro ≫ RC .
Bipolar Junction Transistor (BJT) Design vn,R
C (RT O)
vn,R (RT I )
=
C
|Av |
8. Similarly, the Johnson noise from the emitter resistanceRE has to change from RTO
to RTI noise (if even a contributing source at all and not fully bypassed like above!).
However, the voltage gain at the emitter is about unity so dividing by 1
means the RTI noise voltage can be considered equivalent to the RTO Johnson
noise:
vn,R (RT I )
≈ vn,R (RT O)
E E
9. Finally the total noise voltage seen at the input can be found by the RMS
combination of all RTI noise sources:
2 2 2 2 2
vn,total = √v + (in,Qtotal ∗ Req ) + v + v + v
n,Q n,RE n,RC n,Rs
Note, a calculation simpli cation for systems at room temperature is

−10
√4kT = 1.3 × 10 so this can be pulled out of the sqaure root in voltage and current
noise equations.
As well, an interesting outcome in some CE designs is that the input noise voltage is
dominated by the source impedance, so the lower that can become, the lower the input
noise voltage!
Noise Matching
One way to minimize total system noise is to set BJT noise equal to source noise. To do
VT
this, setRN = √ β ∗ re = Rs such that- givenre =
IE
- you try to nd the best value of
emitter current to match:
Rs VT Rs VT √β
re = → = → = IE
IE Rs
√β √β
Since deviceβis highly dependent on collector current (andIC ≈ IE ), you may have to
make a couple interations (using a typicalβvalue, then seeing whatIE results, and then
checking what value ofβcorresponds to that emitter current) until the values converge.
After convergence, follow standard bias design to match the calculatedIE .
Cascaded Noise
For multi-stage noise analysis, each stage’s noise is computed seperately and then
combined in an RMS fashion to nd total system noise:
However, like we saw above, the output noise RTO is related back to the input (RTI) by
Contents dividing by the voltage gainAv , thus in this two stage ampli er above, the total system
noiseTransistor
Bipolar Junction would be: (BJT) Design
vn2
2 2
vn,total = √v + ( )
n1
Av1
This same effect can be applied across multiple stages where:
vn4
2 2
vn3,stage = √v + ( )
n3
Av3
vn3 2
2
vn2,stage = √v + ( )
n2
Av2
vn2 2
2
vn1,total = √v + ( )
n1
Av1
This divide-by-gain effect means that for low noise design, one really need only care about
creating a high-gain & low-noise rst stage; each stage after has less and less contribution
to overall noise in the system compared to the rst input stage.
To help quanitify a system and the contribution of each of it’s stages to overall noise, there
is the gure-of-merit speci cations of Noise Figure (N F ) and Noise Factor (F ); NF is the
logarithmic noise power (dB) that is added to a system with respect to source impedance.
ThusN F = 0dBmeans a completely noiseless system or stage. Noise FactorF is the
linear equivalent ofN F and is thus the ratio of added noise to source noise. Noise Factor
can then be used to describe cascaded noise within a system given each stage’s Noise
FactorFi and each stage’s gainGi such that:
F2 − 1 F3 − 1 FN − 1
Fsystem = F1 + + + ⋯ +
G1 G1 G2 n−1
∏ Gi
i=1
Noise FigureN F can be found from the system by:
2 2
vn,source + v
n,total
N F = 10 ∗ log ( )
10 2
vn,source
BJT datasheet NF can also be used to verify calculations or use in system analysis.
Direct-Coupled BJT Circuits

Contents In previous sections, the use of inter-stage AC coupling capacitors are used to isolate each
stage/circuit from DC pertrubutions. However, the cons of using them for each stage are:
Large capacitors take up board real estate as well as added to system cost as they
are needed at least once per stage.
Obviously, the very intention of blocking DC interaction between stages means BJT
circuits with interstage capacitors will not work at DC.
Thus, circuits which can share components between stages in a “direct coupled” fashion
are ideal in many practical systems.
CE-CC Ampli er
The rst stage is a standard CE ampli er con guration & bias design. However, the second
stage CC/voltage-follower eliminates the need ofR1andR2by sharing the rst stage’s
collector resistorRC (as well as removing the interstage capacitor). This also has the
advantage of maintaining the voltage gain of the rst CE stage while also having the current
gain of the second CC stage. The buffering action of the second CC stage also acts in
providing enough current drive capacity to- in most systems- prevent negatively loading the
CE stage, which would otherwise cause a reduction in overall voltage gain (since the
RC ∥RL
voltage gain of an otherwise vanilla CE ampli er isAv ≈ −
re
).
To design a CE-CC ampli er:
1. Since directly coupled, notice that the collector voltage/output of the CE input stage,
VC1 , directly sets the base voltage of the second CC stage. If following standard
bias, the output of the rst stage is set toVC1 ≈ Vcc /2which, since the output
voltage of the second stage is only a diode drop, means the output of the second
Contents stage should be roughly halfway between the supply rails as well. Thus the emitter
resistor of the second CC stage is found by dividing the voltage seen at the emitter
(a BJT base-emitter voltage drop from the collector voltage of stage 1),VE2 , by the
desired emitter current for the design:
VC1 − Vbe2
RE2 =
IE2specif ied
2. Next, we want to set the collector current of the rst stage,IC1 , large enough in
comparison to the second stage input base current that the second stage does not
negatively affect the bias design of the rst stage. A good rule of thumb is to have
IC1 ≥ 10 ∗ IB2 . Also, since the base current required for the second stage is
determined by the current gain ofQ2and the desired bias current, we calculate this
minimum required current forIC1 using the minimum speci edβforQ2(given the
desired bias currentIC2 ≈ IE2 ) such that we guarantee that even with the worst
case device, the speci ed current will be enough:
IC2
IC1min ≥ 10 ∗
β2min
Note that setting the collector current ofQ1also plays a role in its input impedance
sinceZin ≈ (β1 + 1)re1 , so setting the rst stage bias current arbitrarily high may
have a negative impact to input impedance.
3. From here, one should have enough information to create the standard bias
circuit for the input CE stage.
Input impedance is calculated similar to a typical CE stage and output
impedance is similar to a standard CC stage output impedance calculation
where the base-emitter re ection reduces the impedance (looking in through the output of
the second stage) of the output impedance of the rst CE stage which is then
RC1 ∥ro1
Zout1 ≈ .
β2
The voltage gain is the loaded gain (the load being the second CC stage on the input CE
stage) of the CE input stage given by the following for a fully emitter bypassed CE design:
RC1 ∥ ro1 ∥ RQ2

Av1 ≈ −
re1
WhereRQ2 = (β2 + 1)(re2 + RE2 ). The voltage gain of a CC is≈ 1so the total
voltage gain is equal to the rst stage loaded voltage gain.
Cascode (CE-CB) Ampli er
Contents
Since CE ampli ers suffer from bandwidth limitations due to the Miller Effect , the
cascode ampli er increases the bandwidth of a stage by inserting a CB circuit into the
collector of a CE circuit. The main reason this happens is the CB ampli er has a very
low input impedance of ≈ re which reduces the gain seen at the collector of the CE
stage (since the gain is directly related what would be the collector resistorRC but is now
the CBZin ), thereby negating the Miller Effect (which increases input capacitance linearly
with inverting voltage gain). Like a standard CB circuit, the base of the upper stage is
grounded at frequency via a coupling capacitorCb .
Even though this may seem like this negatively affects overall voltage gain, the small signal
model of the Cascode con guration can show how the system voltage gain, though, is
preserved since the current through the CB stage is about equal through the lower CE
stage, thus producing a similar output voltage through the collector resistor in the CB stage.
So given equivalent transistors (βroughly equivalent in both) and similar base currents, we
can see:
Contents
vout vc2
Av = =
vin vb1
vc2 = −ic2 RC = −β2 ib2 RC
vb1 = ie1 re1 = ib1 (β1 + 1)re1
β2 ib2 RC RC
∴ Av = − ≈ −
ib1 (β1 + 1)re1 re1
Input and Output Impedance of the Cascode design is similar to CE calculations since the
base of the upper transistor is grounded.
Cascode Bias Design
Contents
1. Decide on the overall bias currentIC = IE as this will set the bias current of both
transistors.
2. Set the emitter voltage of the CE stageVE1 = 1V similar to standard bias design,
and set the emitter resistance in typical fashion as:
VE
RE =
IE
3. Given we want to have equal base currents for each transistor, the base currents can
be found with typicalβ(given the bias current) as:
IC
IB1 = IB2 =
βtyp
4. The base voltage of the bottom stageVB1 is set similarly to standard bias design,
nominally 1.7V as a standard diode drop above the emitter voltage:
VB1 = VE1 + vbe
5. Next to set the emitter voltage of the second stage, which is the same node as the
collector voltage of the rst/bottom stage, we want to ensure with our bias design
that we keep the transistorQ1out of saturation and in a constant, active mode. To
do this, you must reference the BJT datasheet for theVCE cutoff voltage, below
which the BJT operates in a non-linear saturation mode. Leave some voltage margin
for device & system variations; for instance, if the minimum collector-emitter voltage
across a BJT is 0.4V to be in an active mode, round up to 1V. Thus, the second stage
emitter voltage- and thereby the second stage base voltage by adding a standard
diode drop to that potential- is set by:
VE2 = VE1 + VCEminQ1
VB2 = VE2 + vbe
6. Since we know the required base currents for each transistor, and that they are
treated as equivalentIB , we can nd the three bias resistor values by maintaining at
least 10x base current through the bias resistors as well as creating the current
division such that a single base current is peeled off at each stage:
Contents
VB1 VB2 − VB1 Vcc − VB2
R3 = , R2 = , R1 =
10 ∗ IB 11 ∗ IB 12 ∗ IB

7. Similarly to the above step of setting the second stage emitter voltage to keepQ1
out of saturation, we must biasQ2for the same reason by settingVC2 appropriately.
The minimum and maximum collector voltages are dictated by the added collector-
emitter potential to the second stage emitter voltage, and the supply rail,
respectively:
VC2min = VE2 + VCEminQ2
VC2max = Vcc
To have a symmetric output voltage swing, we nd the midway point of these two
extremes and add the minimum DC voltage bias to keepQ2active to nd the
collector bias as:
VC2max − VC2min
VC2 = + VC2min
2
8. From the above collector voltage calculation, we can nd the collector resistor by
nding the voltage across it and dividing by our ampli er bias current:
Vcc − VC2
RC =
IC
Differential Ampli er (Long-Tailed Pair)
Background
For most of the previous BJT circuits and con gurations, an emitter capacitorCE was used
to bypass the emitter degeneration resistorRE to:
1. Acheive high voltage gain at AC/operating frequencies asCE shortsRE

2. Maintain stable DC bias asCE acts as an open circuit in parallel withRE at DC
However, the cons of this approach is that:
1. The circuit- by design of using this emitter capacitor- cannot operate at DC

2. CE is usually a very large capacitor component in order to hit the low frequency
operation for applications like audio ampli ers.
An alternative con guration is the Long Tailed Pair (LTP) which acheives the same
objectives of the emitter capacitor by replacing it with a PN junction. This also removes the
negative side affects of the emitter capacitor- the PN junction can work at DC and takes up
much less space/cost as a large capacitor- while necessating the use of a negative power
supply rail,Vee , in place of what would usually be ground:
Contents
The PN junction- represented by diodeD1in the diagram- is forward biased by the negative
VT
supply railVee and has the familiar dynamic impedance ofrd1 = . Assuming the PN
ID
junction properties of this diode andQ1are similar, and that the current through both is
approximately the same, then we can sayreQ1 ≈ rd1 and the voltage gain will then be:
vout vc ic RC RC
Av = = = − = −
vin vb ie (reQ1 + RE ∥ rd1 ) reQ1 + RE ∥ rd1
And if the dynamic PN junction resistances of the transistor and the diode are much
smaller than the external emitter resistorRE (which is often the case), and both are similar
in value to each other, voltage gain of the LTP can be simpli ed to:
RC RC
Av = − = −
reQ1 + rd1 2re
So the voltage gain is about half that of a CE con guration using a capacitor.
Again, a fundamental assumption here is that the PN junction represented by a diode is

matched to the PN junction in the transistor. However, an external discrete diode may not
work as good as an actual similar BJT; remember that an NPN BJT is basically composed
of two back-to-back diodes or PN junctions. Therefore, we can convert another BJT into an
equivalent diode to match the properties of the rst transistor by shorting the collector to
the base, creating a diode-connected transistor:
Note this only works well when shorting the BE junction, rather than the BC junction, as the
BC junction is usually manufactured in a way that doesn’t behave in the way we intend here-
basically as a diode.
The use of this second BJT is the motivation behind the nal topology of the LTP
Differential ampli er:
Contents
The output can be taken from either collector, or the difference of both, and the inputs can
be single-ended or differential. This is a fundamental building block for linear integrated
circuits like opamps. Most all voltage feedback designs use an LTP topology at the input
stage.
NOTE: for designs which take output voltage at only one output, one need not have a
collector resistor on the other leg; small signal current is still present but an output voltage
across a collector resistor does not need to be developed.
LTP Small Signal Analysis: Single-Ended Input
Contents
For explanation, we’ll rst consider the single-ended (SE) con guration when the rst input
has applied signal voltage and the second input is grounded. Whenvin is positive, the
current ows through the emitter of the input transistor and into the emitter of the
secondary transistor, through its base to ground.
vr = −vr
e1 e2
ir = −ir
e1 e2
vin = vr + vr
e1 e2
Almost no current ows through the tail resistor as usuallyRT ≫ re thus current is shunted
between transistors. This also shows that the transistors have equal and opposite AC small
signal currents (ic1 andic2 are equal in magnitude, opposite current ow direction), while
maintaining equal DC bias currents (IC1 andIC2 are equal in both magnitude and direction
of current ow). As such, there of each transistor is the same (given matched transistors)
thus the voltage across each is equal in magnitude; this leads to each transistor seeing half
of the total input voltage applied.
Whenvin is negative, the same effects can be seen:
Contents
Similar to the proof above , the voltage gain seen at the output (collector) on the same
side of the input voltage is:
vc1 −ib1 β1 RC1 RC1

Av1 = = ≈ −
vb1 ib1 (β1 + 1)(re1 + re2 ) 2re
Due to the small signal current through each transistor being equal and opposite, this
results in the total collector currents in each to slightly increase or decrease, depending on
input voltage polarity; this causes the small signal voltages across the collector resistors,
and thus the output voltages, to move in equal opposition such that they are also in equal
magnitude but opposite polarity (note, this is for the small signal voltages, the DC bias
voltages of each should keep the total collector voltage positive enough to keep the
transistors active and out of saturation). Thus, the voltage gain at the output of the
opposite side of the input voltage is:
RC2
Av2 = −Av1 = +
2re
This equal and opposite output voltage at each leg means the differential voltage gain is
twice the voltage gain of each leg since:
RC
Av = Av1 ± Av2 ≈ ±
dif f
re
Note the polarity of the output voltage/gain depends on how the differential output is
de ned.
LTP Small Signal Analysis: Differential Mode Input
Contents
When the inverting/negative terminal of the input voltage is connected directly to the
opposite transistor (opposed to the transistor directly connected to the non-
inverted/positive terminal of the input voltage), the con guration is de ned as a Differential
Mode (DM) Input. The voltage gain can be seen to be similar to the SE; if the input voltage
has a peak-to-peak amplitude of1Vpk−pk , then one transistor would, for instance, see an
input rise1/2V while the opposite transistor would see a fall of an equal1/2V . Thus the
voltage gain at the output of the non-inverting side can be seen as:
RC RC RC
vc1 = vi ∗ Av1 + vi ∗ Av1 = (+1/2)(− ) + (−1/2)(− ) = −
Q1 Q2
2re 2re 2re
And the ouput of the inverting side can be seen similarly as:
RC RC RC
vc2 = vi ∗ Av2 + vi ∗ Av2 = (−1/2)(− ) + (+1/2)(− ) = +
Q2 Q1
2re 2re 2re
Thus the differential output gain can be seen as (again depending on polarity de ned):
RC
Av = ±
dif f
re
The input impedance can be seen as:

vi vb
Zin = =
ii ib
vb = ie (re1 + re2 ∥ RT ) ≈ ib (β + 1)(re1 + re2 )
∴ Zin ≈ (β + 1)(2re )
LTP Small Signal Analysis: Common Mode Input
Contents
Common Mode (CM) is de ned as when both inputs (e.g. positive & negative, or inverting
and non-inverting terminals) see the same signal/voltage simultaneously. In the case of an
LTP con guration, this means that the input base voltages to the transistors
increase/decrease by the same amount. Therefore, in a matched/ideal design, the emitter
voltages of both transistors are always at equal potential, thus no small signal current ows
between them like in previous con gurations. This means, for analysis purposes, each side
can be treated separately, but with1/2the bias current (or equally twice the tail resistance
seen) for each leg in a Half-Pair Model:
Thus, similar to a standard CE con guration, the voltage gain of each leg can be seen as:
RC
Av = −
CM
re + 2RT
Since most designs do not want to have large CM gain (usually CM voltages are seen as
coupled noise or other unintended voltage sources) but rather reject common mode
voltages, it’s desired for CM gain to be as low as possible relative to differential mode gain.
This gure of merit if called Common Mode Rejection Ratio (CMRR) and is the ratio of DM
to CM gain in dB:
Av
DM
CM RR = 20 ∗ log10 ( )
Av
CM
CMRR in LTP designs can often be improved by replacing the discrete tail resistorRT with a
current source.
The input impedance of each leg can be seen similarly to a CE con guration as:
Zin1 ≈ (β + 1)(re + 2RT )
Contents
And since the same input voltage is seen simultaneously to each leg, the total input
impedance
Bipolar Junction is the(BJT)
Transistor parallel impedance of each leg:
Design
Zin = Zin1 ∥ Zin2
LTP Increases Bandwidth

A single-ended mode LTP is an effective means of cancelling out the Miller Effect as it
negates the two necessary contributors to the effect:
Inverting Gain: we saw above we can achieve a non-inverting gain by taking the
output voltage on the opposite side of the input voltage.
Large Voltage Gain: Since we only need to have a collector resistor (or current
mirror) on the opposite collector side to develop an output voltage, the collector of
the input transistor can be tied directly to the positive supply rail, effectively creating
a voltage gain of 0 at that collector, further negating the Miller Effect.
Current Mirrors
In linear circuit design, a common circuit used is the Current Mirror and as the name
implies the output current is a “mirror” of the input current. It can be used to make an exact
copy of sensed current or a scaled version at the output. Current mirrors can also be used
to replace collector load resistors, or other resistors, in transistor circuit designs, and in
integrated circuit design, transistors can be more advantageous than discrete resistors as
they take up less real estate and can be more accurate.
The basic design is to take two matched transistors (nearly identicalVbe ) and make the rst
transistor as a “diode-connected transistor” and the reference current can be set with a
programming resistorRprog :
Contents
Vcc − Vbe1
Iref =
Rprog
Q2 must be matched (matched-pair design on same piece of silicon where the base-emitter
voltages track over temperature and have the same characteristics) so it sensesVbe1 and
generates an equal current inQ2 since the device characteristics are near identical. If
devices are not matched, the difference in base-emitter voltagesΔVbe can cause large base
currents inQ2 which can lead to even larger collector currents inQ2 . Compliance of a
current source is the min/max range of voltages over which it will operate.
For example, to replace the tail resistor in a LTP con guration, a current mirror can be
placed in the emitter:
Contents
Current mirrors can also be used to replace the collector resistors in CE & LTP
con gurations, which allows for large gain without the need for emitter bypass capacitors:
Contents
For instance, total gain can be seen as:
RC ro2 ∥ ro6
Av = − = −
2re 2re
Current Mirror: High Output Impedance

The choice of which transistor to short base-to-emitter (e.g. to create a diode-connected
transistor) depends on which output voltage one wants to take (which also depends on
wanting inverting or non-inverting polarity output). When the output voltage is taken at the
same side as the diode-connected transistor tying- for instance the output of a LTP using a
Current Mirror in place of Collector Resistors atQ5 above- the impedance is looking into the
base terminal of both transistors in parallel:
(β + 1)re
Zout = Z5base ∥ Z6base = (β5 + 1)re5 ∥ (β6 + 1)re6 ≈
2
This usually means a much higher input impedance than desired so most designs take the
output voltage on the opposite leg of the diode-connected transistor:
Contents
Even higher output impedance (e.g.> 100M Ω) can be found using matched transistors
such as the MAT-14 (which also provide much more accurate operation) in a
con guration such as:
Again, as shown above, the replacement of collector resistors with a super high output
impedance current mirros can lead to much larger voltage gain in a LTP design.
CMRR Improvement in LTP

Given CMRR is the ratio of differential to common-mode gain, we can make a rough
approximation that CMRR is directly related toRT :
RC
−
Av 2re RT
DM
= ≈
Av RC re
CM
re +2RT
Thus the implication is that to increase CMRR, a designer has two options:
1. Decreasere
2. IncreaseRT
It’s often di cult to decreasere as it requires an increase in bias current- which directly
relates to increased power consumption- and there is often an upper limit to how low this
resistance can go. Thus the second option is often more effective as the tail resistance can
be increased much more by replacing the discrete tail resistor with a current mirror source;
in the gure above, the output impedance of the transistorQ3,ro3 ≫ RT for the same bias
current setup. For example, for a bias setup ofIbias = 1mA, a tail resistor is calculated as:
(Vb1 − Vbe1 ) − Vee

RT = ≈ 7.2kΩ
2 ∗ Ibias
Contents
Compare that value to the equivalent output resistance ofQ3 (e.g. a 2N3904 BJT) when
programming the current mirror to 2 mA (1 mA bias current for each leg):
1
Zmirror = ro3 = ≈ 83kΩ
hOE@2mA
Compared to the tail resistor, this results in around a 21 dB increase in CMRR.
Common Collector Distortion Improvement

The Common Collector can be improved by replacing the emitter degredation resistor
with a current mirror. Since the goal of a CC ampli er stage is to provide unity gain and
isolate a stage from a load (or other lower input impedance stage), we ideally want a CC’s
input impedance to be as high as possible. For example, for a 1 mA bias with a 6V emitter
voltage,RE = 6kΩ. SinceZin = (β + 1)(re + RE ),Zin ≈ 720kΩfor a typical Beta of
around 120. Compare to the input impedance when replacingRE with a CM:
Contents
The output impedance of the current mirror is≈ 120kΩfor 1 mA bias, so multiplied by
β = 120, the input impedance has increased 20x to≈ 14M Ω!
The other great improvement of using a CM instead of a discrete resistor in the emitter of a
RE
CC is a much improved distortion performance; since CC voltage gain isAv ≜ , and
re +RE
VT
re ≜ , it can be seen that changes in collector current- caused by changes in
IC
emitter/output voltage in large signal operation over the constant emitter resistor- can
change the values ofre which can distort the output voltages in a non-linear fashion. For
instance, over a 1V to 10V large signal output voltage range, the output voltage gain can
vary by ~2%:
VE IE re Av
1V 0.17 mA 156 Ω 0.975

6V 1 mA 26 Ω 0.996
10V 1.7 mA 16 Ω 0.997
Compare this to the constant current source a current mirror provides; irregardless of
emitter/output voltage, the emitter current doesn’t change, leading to a constantre .
Furthermore, the output impedance of the current mirror is much larger than the discrete
resistor so, even ifre did vary, it contributes much less to the voltage gain equation. Thus
output distortion for a CC is much improved.
DC Level Shifting
Since the basic principle of base voltage being a diode drop away from the emitter (
Vbe ≈ 0.7V ), this property can be exploited to do a variety of things, for instance chaining
diode-connected transistors together to create a larger voltage drop from some input
voltage:
Contents
Vout = Vin − [(n + 1)Vbe ]
Output Stages & Classes

The Output Stage is designated as the nal stage in an ampli er circuit or chain. Whereas
previous stages handled input coupling and ampli cation, the main function of an output
stage is to drive an load (e.g. speaker, antenna, other device, etc.). One of the main gures
of merit for ampli er designs is it’s e ciency, where a more e cient ampli er, which
wastes less power, is usually more desirable. E ciencyηis simply the ratio of output power
(for AC circuits, the RMS power delivered to a load) to input power (the DC power required
to operate the ampli er design):
Pout
η =
Pin
Class A
The basic con guration that has mainly been shown is classi ed as Class A; in these
circuits, the transistor is always biased to be on (in its active region, conducting and
dissipating DC power) which means power is being dissipated whether an input signal is
present or not. Because of this, Class A is the least power e cient. For instance, for a basic
design below, the input power can be seen to be dominated by the magnitude of supply
voltage:
Contents
Vcc − VC
Pin = Vcc IC = Vcc
RC
AssumingVC = VCC /2 :
2
Vcc
Pin =
2RC
In an ideal case in this con guration, an output transistor can swing from the positive
supply rail all the way to ground, meaning the peak-to-peak voltage out is approximately
Vcc
Vcc /2 . Converting to RMS by dividing by the square root of 2,Vout RM S
= . Thus the
2√2
output power can be de ned as:

2
Vcc Vcc Vcc
Pout = Vout Iout = =
RM S RM S
2√2 2√2RL 8RL
Thus the ideal e ciency can be seen as:

2
Pout Vcc 2RC RC
ηideal = = =
2
Pin 8RL Vcc 4RL
Since the load current is less than the DC supply current, we can assumeRC < RL ,
meaning in general for class A,ηideal ≤ 25%
Class B
Maintained by John Gentile • Found a problem on this site? File an Issue

This work is licensed under a Creative Commons Attribution 4.0
International License .
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Bipolar Junction Transistor (BJT) Design

BJT Output Impedance: Early Effect

Shockley diode equation can show the relationship betweenvbe andie .

(using a speci ed collector current), and simpli ed to be a function of base currentib :

vb = ie re ⇒ (ib + ic )re ⇒ (ib + βib )re ⇒ ib (β + 1)re

Voltage Gain & Output Impedance

Voltage gain is given by:

reasonable error such that:

This current gain is nominallyAi ≈ β

BJT Biasing for AC Circuits

Ambient temperature changes

Standard Voltage-Divider Bias Circuit

6. SpecifyVB : with an intended emitter potential of 1V and

Deviations from these design parameters due to process (min/max deviceβ) or

Common Emitter Ampli er Design

Improving Voltage Gain

So at high frequencies, the voltage gain is given by:

in the emitter circuit,Zin drops at a similar rate.

Isolating Output Load

Frequency Response & Capacitor Selection

Emitter Capacitor Selection- Full Bypass

Emitter Capacitor Selection- Partial Bypass

Input Capacitor Selection

Output Capacitor Selection

Common Collector Ampli er Design

The biasing design is similar to a CE stage however:

Common Base Ampli er Design

vout = −ic (ro ∥ RC ) = −ib β(ro ∥ RC )

vin = −ib (β + 1)(Rs + re )

This can be further reduced ifZE ≫ re and no source connected soRS = 0 :

BJT High-Frequency Response

Cascaded CE Ampli ers

Emitter voltage:VE = VB − vbe ≈ 1.0V

Deviceβ@IC = 1.0mA → β = 120

Output Impedance:Zout1 = ro ∥ Rc1 ≈ 6kΩ

Contents Stage 2 Properties

Emitter voltage:VE = VB − vbe ≈ 1.1V

Deviceβ@IC = 5.0mA → β = 150

Output Impedance:Zout2 = ro ∥ Rc2 ≈ 1kΩ

BJT Noise Model

SinceRN = √ β ∗ re , we can control noise levels with choice of circuit emitter/collector

BJT Circuit Noise Analysis

1. First, the transistor noise resistanceRN = √β ∗ re should be found.

6. The source voltage noisevn,s can be found by the Johnson equation:

Note, a calculation simpli cation for systems at room temperature is

This same effect can be applied across multiple stages where:

Noise FigureN F can be found from the system by:

Direct-Coupled BJT Circuits

To design a CE-CC ampli er:

RC1 ∥ ro1 ∥ RQ2

Cascode (CE-CB) Ampli er

vc2 = −ic2 RC = −β2 ib2 RC

vb1 = ie1 re1 = ib1 (β1 + 1)re1

Cascode Bias Design

VB1 = VE1 + vbe

VB2 = VE2 + vbe

Bipolar Junction Transistor (BJT) Design

VC2min = VE2 + VCEminQ2

Differential Ampli er (Long-Tailed Pair)

1. Acheive high voltage gain at AC/operating frequencies asCE shortsRE

However, the cons of this approach is that:

1. The circuit- by design of using this emitter capacitor- cannot operate at DC