Design and implementation of 2bit Vedic multiplier at 16nm using PTL logic

Kshitij Sharma, Anubhav Garg, Deepak Agrawal, Anu Mehra, Smita Singhal
Department of ECE, ASET
Amity University, Uttar Pradesh

Abstract––As the demand for high speed

computations have increased, Vedic multipliers
have been implemented in circuits. In this paper, a
2bit Vedic multiplier has been implemented using
Pass Transistor Logic. The implementation of 2
bit Vedic Multiplier using PTL results in 59.63%
power reduction and 42.07% reduction in delay as
compared to CMOS design at typical value of
0.9V. The tool for implementation is ngspice. The
implementation technology of the circuit is 16 nm.
Keywords: Vedic multiplier, CMOS(Complementary
Metal Oxide Semiconductor), PTL(Pass Transistor
Logic).
I. INTRODUCTION
Multipliers act as the basic blocks for almost all
combinational circuits. They are complex circuits
which deploy algorithms among themselves and
hence pose two major concerns in VLSI design; High
power dissipation and high computational
delay.These two problems need to be addressed
simultaneously to make better circuits. Multipliers in
particular need to be fast as they form Adders are one
of the necessary hardware in the designing of digital
systems. Digital signal processors, microprocessors
use multipliers .The most significant quantitative
measure of any digital circuit is its power dissipation
and computational delay.Reducing the on-chip area is
another very important aspect that designers have to
keep in mind while proposing a design.
Vedic mathematics is easier for the human brain to
understand. Vedic logic is preferred in circuit design
because of its high speed and low on-chip area
consumption. Vedic multiplication is the universal
method[1& 2] of multiplication and the most
commonly used sutra of the 16 sutras is the UT or the
‘Urdhva Tiryagbhyam’ sutra
Pre-processing
The product terms for 2-bit Vedic multiplier are
given by the following expressions[3]:
S0=A0B0
S1=(A0B1) XOR (A1B0)
S2=(A0A1B0B1) XOR (A1B1)
S3=A0A1B0B1
Multiplication processing
To implement 2-bit Vedic multipliers, there are three
simple steps that need to be followed. The first step
th
includes multiplication of the 0 bit of both the
inputs. The second step involves cross multiplication
th st
of bits of the two inputs (0 and 1 ) of both the
inputs and their addition. The third step requires the
st
multiplication of the 1 bit of both the inputs.
For the two inputs A and B, the arrangement for the
multiplier is demonstrated:
Figure 1: Representation of UT multiplier steps
Implementation
In this step, the different logics are implemented and
their simulations are carried out at 16nm channel
length.
The implementation can be better understood by the
following example:

Technology used
This paper uses the concept of reducing the channel
length and subsequently reducing the on-chip
area.[3]To make area and power efficient circuits,
directly reducing channel lengths can prove to be
very instrumental. Figure 2: Implementation example

978-1-5386-5257-2/18/$31.00 ©2018 IEEE

 II. PROPOSED LOGIC
CMOS logic is used to implement most logics by
designers due to its ability to have a large output
swing. However, CMOS logic is slower than PTL[4]
logic which require fewer transistors to implement
the same logic.
This, however, makes the circuit robust, increases
number of transistors and slows down the function
implemented.Therefore, CMOS logic is not preferred
while design fast applications such as multipliers.

Shorter channel length transistors (Lmin=16nm)

ensure that the circuit occupies less area on the chip
and this overcomes another challenge faced by VLSI
designers.

CIRCUIT DIAGRAM
Even though the algorithm specifically decides every
term in the output of the product term, a general
schematic can be made with the help of standard
logical gates for the sake of understanding. The
following schematic is the implemented circuit which
actually processes these equations[5-8]

Figure 4(a)-First product term (A0B0)

Figure 3- Proposed Circuit Diagram

Various Logic implementations

The Vedic Multiplier was implemented using CMOS
and PTL logic. PTL logic is fast whereas CMOS is
useful when larger output swings are required. A
brief about these logics have been given for better
understanding.
Figure 4(b)- Second product term (A1B0 XOR
CMOS
A0B1)
CMOS(Complementary MOS) is a highly noise
immune logic which has low static power dissipation.
It is used most often to implement circuits because of
its output swing.

The circuit consists of two networks- Pull up network

and Pull down network which provide
complementary outputs at the same input therefore at
a time only one network is on. This accounts for low
static power dissipation.

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)
 PTL
PTL (Pass Transistor Logic) employs the concept of
switches to operate and implement a particular
function. Suppose there are ‘n’ input signals, so ‘n-1’
control signals are taken which operate. The
remaining signal is provided as the input at the first
stage and the outputs keep on passing and acting as
inputs to the next stages.

Usage of PTL not only reduces the transistor count of

the circuits, but also helps in making the circuits
much faster. There is a general lower power
dissipation as compared to CMOS as fewer
transistors are used.

PTL logic can be further improved by reducing the

redundant transistors. For example a logical ‘0’ input
is to be given, in that case, instead of using both p-
mos and n-mos transistors, only n-mos transistor is
used as it conducts a good ‘0’. All this more than
Figure 4(c)- Third product term (A1B1 XOR makes up for the compromised output swing in larger
A0A1B0B1) circuits. Therefore, PTL is highly useful when fast
circuits are to be considered.

Figure 5(a)- First product term (A0B0)

Figure 4(d)- Fourth product term

(A0A1B0B1)

Figure 5(b)-Second product term (A1B0 XOR

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)
 A0B1)
Table 2- Power Comparison of multiplier Logics
Vdd in V Power dissipated(µW)
CMOS PTL
0.6 6.349 3.162
0.7 10.91 5.561
0.8 20.40 9.312
0.9 38.37 15.48
1 68.54 25.39
1.1 118 41.71

Figure 5(c)- Third product term (A1B1 1.2 195 70.45

XOR A0A1B0B1)
Table 3- Delay Comparison of multiplier Logics

Vdd in V Delay(ns)

CMOS PTL
0.6 13.32 6.94

0.7 12.69 5.41

0.8 12.37 4.73

0.9 12.19 3.99

1 12.11 3.21
1.1 12.08 2.63
Figure 5(d)- Fourth product term 1.2 12.07 2.40
(A0A1B0B1)

RESULTS
Table 4- PDP Comparison of multiplier Logics
2-bit multiplier was implemented using CMOS and
PTL logic and it was found that PTL was better in Vdd in V PDP(fJ)
terms of i.) power dissipation, ii.) computational
delay and iii.) on-chip area occupancy. CMOS PTL

Table 1- Comparison of different multiplier logics 0.6 84.59 21.94

Multiplier Logic No. of Transistors 0.7 138.4 30.07
CMOS 50 0.8 252.4 44.03
PTL 35
0.9 467.8 61.77

1 830.1 81.46

1.1 1422 109.7

1.2 2352 169.4

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)
 improvements in PTL logic when compared to
Power Comparison CMOS can be observed from tables 2 & 3. Reduction
in channel length also has its effect on on-chip area.
2.50E-04
2.00E-04 REFERENCES
wer
in W

1.50E-04
1.00E-04 CMOS [1] Jagadguru Swami Sri Bharati Krisna Tirthaji
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PTL
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0.6 0.7 0.8 0.9 1 1.1 1.2
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“Comparative study of subthreshold leakage in
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Figure 6- Power Comparison of different logics
International Conference on Microelectronics,
Computing and Communications (MicroCom) 2016

[3] Sushma R. Huddar, Sudhir Rao Rupanagudi,

Delay Comparison Kalpana M and Surabhi Mohan,“Novel High Speed
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[4]Gaurav Bajaj, Kabir Grover, Anu Mehra, Sachin

2.00E-08 PTL
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0.00E+00 and CMOS Logic” Springer-ICICCD 2017
0.6 0.7 0.8 0.9 1 1.1 1.2
Vdd in V [5] G.Ganesh Kumar, V.Charishma, “Design of High
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PDP Comparison
[6]M.E. Praramasivam, Dr. R.S. Sabeenian, “An
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1.50E-11
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1.00E-11
CMOS [7] K V Gowreesrinivas,
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5.00E-12 P.Samundiswary“Comparative Study on Performance

PTL
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0.6 0.7 0.8 0.9 1 1.1 1.2 ICCICCT 2016
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[8] Sushma S. Mahakalkar, Sanjay L. Haridas,
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2014

CONCLUSIONS

The 2-bit Vedic multiplier implemented by the PTL

logic has significantly fewer transistors and hence has
lower on-chip area occupancy. Power and delay

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)