•'C.

41 Single-Ended and Differential Operation 101

An important advantage of differential operation over single-ended signaling is higher

immunity to "environmental" noise. Consider the example depicted in Fig. 4.2, where two
adjacent lines in a circuit can-y a small, sensitive signal and a large clock waveform. Due to
capacitive coupling between the lines, transitions on line L2 corrupt the signal on line L 1.
Now suppose, as shown in Fig. 4.2(b), the sensitive signal is distributed as two equal and
opposite ph~ses . If the clock line is placed midway between the two, the transitions disturb
the differential phases by equal amounts, leaving the difference intact. Since the common-
mode level of the two phases is disturbed but the differential output is not corrupted, we
say this arrangement "rejects" common-mode noise.

CK

Capacitance
(a)

t----.-,--;-~

CK~H+nn
~------..r
-. (b)

Figure 4.2 (a) Corruption of a signal due to coupling,

(b) reduction of coupling by differential operation.

Another example of common-mode rejection occurs with noisy supply voltages. In

Fig. 4.3(a), if Vnn varies by b. V, then V01u changes by approximately the same amount,
i.e., the output is quite susceptible to noise on VDD· Now consider the circuit in Fig. 4.3(b).
Here, if the circuit is symmetric, noise on VDD affects Vx and Vy but not Vx- Vy = Vout·
Thus, the circuit of Fig. 4.3(b) is much more robust to supply noise.
 v

102 Chap. 4 Differential Amplifier:.

-.. -.
(a) (b)

Figure 4.3 Effect of supply noise on (a) a single-ended circuit, (b) a differential circuit.

Thus far, we have seen the importance of employing differential paths for sensitive
signals. It is also beneficial to employ differential distribution for noisy lines. For example,
suppose the clock signal of Fig. 4.2 is distributed in differential form on two lines (Fig. 4.4).
Then, with perfect symmetry, the components coupled from CK and CK to the signal line
cancel each other.

Figure 4.4 Reduction of coupled noise by differential

operation.

Another useful property of differential signaling is the increase in maximum achievable

voltage swings. In the circuit of Fig. 4.3, for example, the maximum output swing at X or
Y is equal to Vvv ..:... (Vas- VrH), whereas for Vx - Vy, the peak-to-peak swing is equal
to 2[Vvv- (Vas- VrH)].
Other advantages of differential circuits over single-ended counterparts include simpler
biasing and higher linearity (Chapter 13).
While it may seem that differential circuits occupy twice as much area as single-ended
alternatives, in practice this is a minor drawback. Also, the suppression of nonideal effects
by differential operation often results in a smaller area than that of a brute-force single-ended
design. Furthermore, the numerous advantages of differential operation by far outweigh the J
possible increase in the area. J
••r:. 4.2 Bas1c Differential Pair 103

•1.2 Basic Differential Pair

How do we amplify a differential signal? As suggested by the observations in the previous
section, we may incorporate two identical single-ended signal paths to process the two
phases [Fig. 4.5(a)]. Such a circuit indeed offers some of the advantages of differential

~------------~Voo

(a)

·---~~f!f/X)
,,"ln2 ···.. ~-~~ '·•··
1

Vln CM
' \
~ ~
..
~~-~ ··•·

t t

t t
(b)

Figure 4.5 (a) Simple differential circuit, (b) illustration of sensi-

tivity to the input common-mode level.

signaling: high rejection of supply noise, higher output swings, etc. But what happens if
V;n 1 and V;n 2 experience a large common-mode disturbance or simply do not have a well-
defined common-mode de level? As the input CM level, V;n ,CM· changes, so do the bias
currents of M1 and M 2 , thus varying both the transconductance of the devices and the output
CM level. The variation of the transconductance in turn leads to a change in the small-signal
gain while the departure of the output CM level from its ideal value lowers the maximum
allowable output swings. For example, as shown in Fig. 4.5(b), if the input CM level is
excessively low, the minimum values of V;n 1 and Vin2 may in fact turn off Mt and M2,
leading to severe clipping at the output. Thus, it is important that the bias currents of the
devices have minimal dependence on the input CM level.
A simple modification can resolve the above issue. Shown in Fig. 4.6, the "differential
pair" 1 employs a current source Iss to make /Dl + /D2 independent of V;n,C M· Thus, if
Vin1 = V;n2 , the bias current of each transistor equals lss/2 and the output common-mode

1
Also called a source-coupled pair or (in the British literature) a long-tailed pair.
104 Chap.4 Differential Amplifiers

~---....,...Voo

-. Figure 4.6 Basic differential pair.

level is V00 - Rvlss/2. It is instructive to study the large-signal behavior of the circuit for
both differential and common-mode input variations.

4.2.1 Qualitative Analysis

Let us assume that in Fig. 4.6, Vinl - Vin2 varies from -oo to +oo. If Vinl is much
more negative than V;n2· Mt is off, M2 is on, and lm = Iss· Thus, Your! = Yoo and
Vout2 = Yoo - Rvlss· As Yin! is brought closer to \-'in2• Mt gradually turns on, drawing
a fraction of Iss from R01 and hence lowering Vourl· Since Im + Im = Iss, the drain
current of M2 decreases and Youtz rises. As shown in Fig. 4.7(a), for Yin! = Vin2• we have
Youtl = Vout2 = Yoo - Rvlss/2. As Ytni becomes more positive than Yin2• Mt carries a
greater current than does M2 and Vouti drops below Vout2· For sufficiently large Vinl- \-'in2.
M1 "hogs" all of Iss, turning M2 off. As a result, Your! = Yoo- Rvlss and Youtz= Vvv.
Fig. 4.7 also plots Voutl - Yout2 versus Vinl - Y;n2·

Vout1- Vout2
+ Ro Iss

(a) (b)

Figure 4. 7 Input-output characteristics of a differential pair.

The foregoing analysis reveals two important attributes of the differential pair. First, _.
the maximum and minimum levels at the output are well-defined (Y00 and Yoo- Rvlss.
respectively) and independent of the input CM level. Second, the small-signal gain
(the slope of Your! - Your2 versus V;ni - V; 11 2) is maximum for V;n! = V;"2' gradu-
ally falling to zero as IV; 111 - Vin 2 increases. In other words, the circuit becomes more
1

nonlinear as the input voltage swing increases. For V; 111 = Yin2• we say the circuit is in _,
equilibrium. '
.....

•l 4.2 Basic Differential Pair 105

Now let us consider the common-mode behavior of the circuit. As mentioned earlier,
the role of the tail current source is to suppress the effect of input CM level variations on
the operation of M1 and M2 and the output level. Does this mean that V;n ,CM can assume
arbitrarily low or high values? To answer this question, we set V;n 1 = V;n2 = V;n,CM and
vary V;n,CM from 0 to Vvv. Fig. 4.8(a) shows the circuit with Iss implemented by an NFET.
Note that the symmetry of the pair requires that Vautl = Vaut2·

------P"'Voo ..,...----~ Voo

\lin,CM

-.
(a) (b)

Vp

Iss
Voo--Ro
--- 2

\lin,CM \lin,CM \lin,CM

(c)

Figure 4.8 (a) Differential pair sensing an input common-mode change, (b) equivalent circuit if M3 operates in deep
It lode region, (c) common-mode input-output characteristics.

What happens if V;n,CM = 0? Since the gate potential of M 1 and M2 is not more
positive than their source potential, both devices are off, yielding I 03 = 0. This indicates
that M3 is in deep triode region because Vb is high enough to create an inversion layer in
the transistor. With I Dl = I 02 = 0, the circuit is incapable of signal amplification, and
Vauti = Vaut2 = VDD·
Now suppose V;n,CM becomes more positive. Modeling M3 by a resistor as in Fig. 4.8(b),
we note that M1 and M2 turn bn if V; 11 ,cM ::: Vr H. Beyond this point, IDI and I D2 continue to
increase and Vp also rises [Fig. 4.8(c)]. In a sense, M1 and M2 constitute a source follower,
forcing Vp to track V;n,CM· For a sufficiently high V;n,CM. the drain-source voltage of
M3 exceeds V0 s3 - VrHJ, allowing the device to operate in saturation. The total current
through M 1 and M2 then remains constant. We conclude that for proper operation, V;n ,c M ::=:::
VGS! + (VGS3 - Vr HJ).
What happens if V;n,CM rises further? Since Vaut! and V0111 2 are relatively constant, we
expect that M1 andM2 enter the triode region if V;n ,CM > Vautl +VrH = Voo- Rviss/2+
Vr H. This sets an upper limit on the input CM level. In summary, the allowable value of
106 Chap.4 Differential Amplifiers

V;n ,CM is bounded as follows:

Voo J. (4. 1)

Example 4 . 1 - - - - - - - - - - - - - - - - - - - - - -
Sketch the small-signal differential gain of a differential pair as a function of the input CM level.
Solution
As shown in Fig. 4.9, the gain begins to increase as V;n,CM exceeds Vr H . After the tail current source""'

Figure 4.9

enters saturation {V;n,CM = Vl), the gain remains relatively constant. Finally, if V;n ,CM is so high
that the input transistors enter the triode region (V;n,CM = V2), the gain begins to fall. -

With our understanding of differential and common-mode behavior of the differential

pair, we can now answer another important question: How large can the output voltage
swings of a differential pair be? As illustrated in Fig. 4.10, for M 1 and M2 to be saturated,
each output can go as high as Vvv but as low as approximately V; n,CM - VrH· In othe1

-·~--

J
Figure 4.10 Maximum allowable out-
-. put swings in a differential pair.

words, the higher the input CM level, the smaller the allowable output swings. For this
reason, it is desirable to choose a relatively low V;n,CM. but the preceding stage may not
provide such a level easily.
An interesting trade-off exists in the circuit of Fig. 4. 10 between the maximum value
of V;n,CM and the differential gain. Similar to a simple common-source stage (Chapter 3)._..
 ' . 4.2 Baste Differential Pair 107

the gain of a differential pair is a function of the de drop across the load resistors. Thus, if
Rolss/2 is large, V;n,CM must remain close to ground potential.

4.2.2 Quantitative Analysis

We now quantify the behavior of aMOS differential pair as a function of the input differential
voltage. We begin with large-signal analysis to arrive at an expression for the plots shown
in Fig. 4.7.

..,..---...... Voo

-. Figure 4.11 Differential pair.

For the differential pair in Fig. 4.11, we have Vout 1 = VDD - RD1/D 1 and Vout2 = VDD -
R02ID2, i.e., Voutl- Vout2 = R02Io2- Rmlm = Rv(/D2- lm) if Rm = RD2 = Rv.
Thus, we simply calculate Im and !02 in terms of V; 111 and Vin2· assuming the circuit is
symmetric, M1 and M2 are saturated, and).. = 0. Since the voltage at node P is equal to
V;nJ - VGsJ and Vin2 - VGs2,

(4.2)

For a square-law device, we have:

2 lv
(VGs-VrH) = l W' (4.3)
-11
21""11
c -L
OX

and, therefore,

2lv (4.4)
VGs = ---:::w:-::- + VrH ·
!lnCoxL

It follows from (4.2) and (4.4) that

2ID2
(4.5)
w·
JLnCoxL

r
108 Chap. 4 Differential Amplifiers

Our objective is to calculate the differential output current, IDI - !02. Squaring the two
sides of (4.5) and recognizing that /Dl + /02 =Iss, we obtain

2 2
(Vinl- Vinz) = ---::-:w=-=-Uss- 2jJDIID2). (4.6)
J-1-nCoxL
.
I'

That is,

(4.7)

Squaring the two sides again and noting that 4/Dl/02 = UDI + /02)2 - Um - /D2) 2 =
Ils - (/D1 - I D2) 2 , we arrive at

(4.8)

Thus,

(4.9)

As expected, /Dl - lvz is an odd function of V;nt - V;nz, falling to zero for V;nt = V;n2· As
IVint - V;n2l increases from zero, I/DI - /D21 also increases because the factor preceding
the square root rises more rapidly than the argument in the square root drops. 2
Before examining (4.9) further, it is instructive to calculate the slope of the characteristic,
i.e., the equivalent Gm of Mt and M2. Denoting lv 1 - ID2 and Vinl - Vin2 by ~lv and
D. Vin, respectively, the reader can show that

(4.10) •

For ~ V;n = 0, Gm = J J-LnCox(W / L)lss. Moreover. since Voutl - Vout2 = Rv~l

RvGmD. Vin. we can write the small-signal differential voltage gain of the circuit in the ~
equilibrium condition as

IAvl = (4.11) ""'

2
It is interesting to note that, even though I Dl and I 02 are even functions of their respective gate-source _,
voltages, IDI - ID2 is an odd function of V;nl - V;n2· This effect is studied in Chapter 13.
4.2 Basic Differential Pair 109

Equation (4.10) also suggests that Gm falls to zero for ~ V; 11 = J 21ss I(JJ-n Cox WI L).
As we will see below, this value of 11 V; 11 plays an important role in the operation of the
circuit.
Let us now examine Eq. (4.9) more closely. It appears that the argument in the square
root drops to zero for .6. V;n = J4Iss/(JL 11 Cox WIL), implying that ~lv crosses zero at
two differer,t values of~ V; 11 • This was not predicted in our qualitative analysis in Fig. 4.7.
This conclusion, however, is incorrect. To understand why, recall that (4.9) was derived
with the assumption that both M1 and M2 are on. In reality, as ~ V;n exceeds a limit,
one transistor carries the entire Iss, turning off the other. 3 Denoting this value by ~ V;nJ,
we have IDJ = Iss and ~ V;nt = Vas 1 - VTH because M2 is nearly off. It follows
that

(4.12)

For~ V; 11 > .6. V; 111 , M2 is off and (4.9) does not hold. As mentioned above, Gm falls to zero
for~ V; 11 = ~ Vinl· Figure 4.12 plots the behavior.

+b. V1n1 uAVIn +b. Vln1 A""In

u

(a) (b)

Figure 4.12 Variation of drain currents and overall transconductance of a differen-

tial pair versus input voltage.

Example4.2 - - - - - - - - - - - - - - - - - - - - - -
Plot the input-output characteristic of a differential pair as the device width and the tail current vary.
Solution
Consider the characteristic shown in Fig. 4.13(a). As WIL increases, 11 V; 11 t decreases, narrowing the
input range across which both devices are on [Fig. 4.13(b)]. As Iss increases, both the input range
and the output current swing increase [Fig. 4.13(c)]. Intuitively, we expect the circuit to become more
linear as Iss increases or WIL decreases.

The value of 11 V; 111 given by (4.12) in essence represents the maximum differential
input that the circuit can "handle." It is possible to relate ~ V; 111 to the overdrive voltage

3 We neglect subthreshold conduction here.

110 Chap. 4 Differential Amplif ers '-~

- 1ss ........ .

(a) (b)

(c)

Figure 4.13

of M1 and M2 in equilibrium. For a zero differential input, IDJ lssl2, and

hence

Iss
(Vas- Vr H )J,2 = (4.13)

Thus, the equilibrium overdrive is equal to 6. V; 111 1..fi. The point is that increasing t:. V;n 1 to
make the circuit more linear inevitably increases the overdrive voltage of M 1 and M2. For
a given Iss. this is accomplished only by reducing WILand hence the transconductance of
the transistors.
We now study the small-signal behavior of differential pairs. As depicted in Fig. 4.14,
we apply small signals V;n 1 and V;n2 and assume M1 and M2 are saturated. What is the dif-
ferential voltage gain, V0 urf(V; 111 - V; 11 2)? Recall fromEq. (4.11) that this quantity equals
JtL,CoxfssWfL Rn . Since in the vicinity of equilibrium, each transistor carries approxi- 'Y
mately lssl2, this expression reduces to g111 R0 , where g111 denotes the transconductance of J
M 1 and M2 • To arrive at the same result by small-signal analysis, we employ two different """
methods, each providing insight into the circuit's operation. We assume R01 = RD2 = R0 . \i.;oj
I 42 Basic Differential Pair 111

..,...- -- -.,... Voo

Vout2

-. .
...
Figure 4.14 Differential pair with
-. small~signal
inputs.

.......--- -Voo

Vln1f
. -
-.
(a)
..,..____...,... Voo

T
-. -.
(b) (c)

Figure 4.15 (a) Differential pair sensing one input signal, (b) circuit of
(a) viewed as a CS stage degenerated by M2, (c) equivalent circuit of (b).

Method I The circuit of Fig. 4.14 is driven by two independent signals. Thus, the output
can be computed by superposition.
Let us set Vinz to zero and find the effect of Vtn! at X andY [Fig. 4.15(a)]. To obtain Vx,
we note that M 1 forms a common~source stage with a degeneration resistance equal to the
impedance seen looking into the source of M2 [Fig. 4.15(b)]. Neglecting channel-length
112 Chap.4 Differential Amplifiers -v.

--·------------·---·-------: v
DD

v,.,f-. .
-.
.................................. .......... J
-.
(a) (b)

Figure 4.16 Replacing Mt by a Thevenin equivalent.

modulation and body effect, we have Rs =118m2 [Fig. 4.15(c)] and

Vx -Ro
(4.14)
Ylnl 1 1
-+-
8ml 8m2

To calculate Vr, we note that M1 drives M2 as a source follower and replace Yln! and M1
by a Thevenin equivalent (Fig. 4.16): the Thevenin voltage Vr = V;n 1 and the resistance
Rr = 1/8ml · Here, M2 operates as a common-gate stage, exhibiting a gain equal to

Vr Ro
- = --:------:--
1 1 . (4.15)
-+-
8m2 8ml

It follows from (4.14) and (4.15) that the overall voltage gain for V;n1 is

-2Ro
(Vx - Yr)lnueto Vinl = l (4.16)
1 Vinl•
-+-
8ml 8m2
which, for 8ml =8m2= 8m reduces to

(Vx- Vy )loue to Vinl = -8mRD Vinl· (4.17)

By virtue of symmetry, the effect of V;n2 at X and Y is identical to that of Vinl except ...
for a change in the polarities:

(Vx - Vy )lnue to Vin2 = 8mRD Vin2· (4.18)

.....
Adding the two sides of (4.17) and (4.18) to perfonn superposition, we have

(Vx- Vr )rot
- - - - = - gmRo . (4.19) .....
Vinl - Vin2
. t1.2 Basic Differential Pair 113

Comparison of (4.17), (4.18), and (4.19) indicates that the magnitude of the differential
gain is equal to gmRD reg~rdless of how the inputs are applied: in Figs. 4.15 and 4.16, the
input is applied to only one side whereas in Fig. 4.14 the input is the difference between
two sources. It is also important to recognize that if the output is single-ended, i.e., it is
sensed between X or Y and ground, the gain is halved.

Example 4~3 - - - - - - - - - - - - - - - - - - - - - - -
In the circuit of Fig. 4.17, Mz is twice as wide as M!· Calculate the small-signal gain if the bias values
of V;n! and V;n2 are equal.

....,----....,... Voo

Vout1

Figure4.17

Solution
If the gates of M1 and Mz are atthe samedc potential, then Vas I = Vasz and /D2 =21m = 2/ss/ 3.
Thus, 8m! = J2J..LnC0 x(WJL)Iss/3 and 8m2= J2J..LnCox(2WjL)2Iss/3 = 2gml· Following the
same procedure as above, the reader can show that

2RD
IAul = (4.20)
1 1
- + -
8m1 2gmJ

(4.21)

Note that, for a given Iss, this value is lower than the gain of a symmetric differential pair (with
2W j L for each device) [Eq. (4.19)] because gm! is smaller.

How does the gain of a differential pair compare with that of a common-source stage?
For a given total bias current, the value of gm in (4.19) is 1/ .../2 times that of a single
transistor biased at Iss with the same dimensions. Thus, the total gain is proportionally less.
Equivalently, for given device dimensions and load impedance, a differential pair achieves
the same gain as a CS stage at the cost of twice the bias current.
Method II If a fully-symmetric differential pair senses differential inputs (i.e., the two
inputs change by equal and opposite amounts from the equilibrium condition), then the
concept of "half circuit" can be applied. We first prove a lemma.
114 Chap. 4 Differential Amplifiers

Lemma. Consider the symmetric circuit shown in Fig. 4.18(a), where D 1 and D2 represent

/2

b.Vin b.V1
Vln2 Vo Va
.1Vin .1V2

':
t t
(a) (b) (c)

Figure 4.18 Illustration of why node P is a virtual ground.

any three-tenninal active device. Suppose Vin 1changes from V0 to Vo +D. Vin and V;n2 from
Vo to Vo - D. V;n [Fig. 4.18(b)]. Then, if the circuit remains linear, Vp does not change.
Assume A= 0.

Proof. Let us assume that V1 and V2 have an equilibrium value of Va and change by D. V1
and D. V2, respectively [Fig. 4.18(c)]. The output currents therefore change by g111 !:!:. V1 and
gml:!:. V2. Since /1 + h = /r, we have gml:!:. V1 + gml:!:. V2 = 0, i.e., D. VI = - D. V2. We also
know V;nt- V1 = V;n2- V2, and hence Vo+l:!:. V;n - (Va+ D. VI)= Vo -D. V;n - (Va+D. V2).
Consequently, 21:!:. Yin = D. Vt - D. V2 = 21:!:. V1. In other words, if Yin1 and V;n2 change by
+D. Vin and -D. V/n,respectively, then VI and V2change by the same values, i.e., a differential
change in the inputs is simply "absorbed" by V1 and V2. In fact, since Vp = V;nl -VI> and
since V1 exhibits the same change as V;n 1, Vp does not change. 0

The proof of the foregoing lemma can also be invoked from symmetry. As long as the
operation remains linear so that the difference between the bias currents of D1 and D2 is
negligible, the circuit is symmetric. Thus, Vp cannot "favor" the change at one input and
"ignore" the other.
From yet another point of view, the effect of D1 and D2 at node P can be represented
by Thevenin equivalents (Fig. 4.19). If Vn and VT2 change by equal and opposite amounts
and Rn and Rr2 are equal, then Vp remains constant. We emphasize that this is valid if
the changes are small such that we can assume Rn = RT2 .4 ·
The above lemma greatly simplifies the small-signal analysis of differential amplifiers.
As shown in Fig. 4.20, since Vp experiences no change, node P can be considered "ac
ground" and the circuit can be decomposed into two separate halves, hence the term
"half-circuit concept" [1]. We can write Vx / Vinl = -g111 RD and Vyj(- Vinl) = -g111 Rv,
where V;ni and- Yin I denote the voltage change on each side. Thus, (Vx- Vr )/(2V;n 1) =
-gm Rv .

4
It is also possible to derive an expression for the large-signal behavior of Vp and prove that for small
V;nl - V;n2• Vp remains constant. We defer this calculation to Chapter 14.
I 'l~, 4.2 Basic Differential Pair 115

Figure 4.19 Replacing each half of

p
-. a differential pair by a Thevenin
equivalent.

....,..-----.- Voo ..,....---~ Voo

Vout2 Vout1 Vout2

1-Vtn1
-.
.v,,,f- •
-. -. 1-Vtn1
-.
-.
(a) (b)

Figure 4.20 Application of the half-circuit concept.

Example 4 . 4 - - - - - - - - - - - - - - - - - - - - - -
Calculate the differential gain of the circuit of Fig. 4.20(a) if A. # 0.
Solution
Applying the half-circuit concept as illustrated in Fig. 4.21, we have Vx/Vini = -gm(RDIIroi)
and Vy / (-Vini) = -gm(RDIIr02), thus arriving at (Vx- Vy)j(2V;ni) = -gm(RDIIro), where
ro = ro1 = r02. Note that Method I would require lengthy calculations here.

Vout1 <>----+--, X

.v,,,f-•.
-. Flgure4.21

The half-circuit concept provides a powerful technique for analyzing symmetric differ-
ential pairs with fully differential inputs. But what happens if the two inputs are not fully
- ,..

116 Chap. 4 Differential Amplifier~.

vin1 + vin2
+- +-
2 2
Vin1 + vin2
+- +-
-. +-
2
vln2 +
+-
2
Vln1
2 2
Vln2 + Vln1
2 2
-.
(a) (b)

Vln1- Vln2 + V1n2- V1n1

2 2
+
V1n1+ Vin2 V1n1+ V1n2
-.
2
-. -. 2

(c) (d)
~
Figure 4.22 Conversion of arbitrary inputs to differential and common-mode components.

differential [Fig. 4.22(a)]? As depicted in Figs. 4.22(b) and (c), the two inputs V;n 1 and V; 11 2
can be viewed as

=
Vinl- Vin2 V;nl + V;n2 (4.22\
V;nt 2 + 2 J

Vin2 - V;nt V;nt + Vin2

Vin2 = 2 + 2
(4.23)"'

""
Since the second term is common to both inputs, we obtal.n the equivalent circuit i:.._
Fig. 4.22(d), recognizing that the circuit senses a combination of a differential input and
a common-mode variation. Therefore, as illustrated in Fig. 4.23, the effect of each typ
of input can be computed by superposition, with the half-circuit concept applied to th"
differential-mode operation.

Example 4 . 5 - - - - - - - - - - - - - - - - - - - - - - -
In the circuit of Fig. 4.20(a), calculate Vx and Vr if V; 11 1 # - V; 11 2 and .A # 0.
-
l 't:. 4.2 Basic Differential Pair 117

-
I' -.
--
(a) (b)

Figure 4.23 Superposition for differential and corrunon-mode signals.

Solution
For differential-mode operation, we have from Fig. 4.24(a)

Vx = -gm(RD IIro!) Vinl-2 Vin2 (4.24)

Vy = -gm(RDIIr02) Vin2-2 Vin! . (4.25)

That is,
(4.26)

which is to be expected.

- . - - - - - -... Voo

-r------,-. Voo

-.
v vin1 + vin2 +
in,CM=
2
-.
(a) (b)

Figure 4.24

For corrunon-mode operation, the circuit reduces to that in Fig. 4.24(b). How much do Vx and
Vy change as Vin.C M changes? If the circuit is fully symmetric and Iss an ideal current source, the
118 Chap. 4 Differential Amplifiers J

current drawn by M1 and Mz from Rv1 and Rvz is exactly equal to Iss/2and independent of V;,z ,CM ·
Thus, Vx and Vy experience no change as V;n,CM varies. Interestingly, the circuit simply amplifie~
the difference between V;11 J and V; 11 2 while eliminating the effect of V;n,CM·

4.3 Common-Mode Response

An important attribute of differential amplifiers is their ability to suppress the effect of
common-mode perturbations. Example 4.5 portrays an idealized case of common-mode
response. In reality, neither is the circuit fully symmetric nor does the current source exhibit
an infinite output impedance. As a result, a fraction of the input CM variation appears at
the output.
We first assume the circuit is symmetric but the current source has a finite output
impedance, Rss [Fig. 4.25(a)]. As V;n,CM changes, so does Vp , thereby increasing the
drain currents of M1 and Mz and lowering both Vx and Vy. Owing to symmetry, Vx re-
mains equal to Vy and, as depicted in Fig. 4.25(b), the two nodes can be shorted together.
Since M1 and M2 are now "in parallel," i.e., they share all of their respective terminals, the

Voo
Ro
Vout1 Vout2

l'in,CM
p

Rss

-
(a)

Voo

~n.cMo4

Rss

-.
(b) (c)

Figure 4.25 (a) Differential pair sensing CM input, (b) simplified

version of (a), (c) equivalent circuit of (b).
'•!~C. 4.3 Common-Mode Response 119

circuit can be reduced to that in Fig. 4.25(c). Note that the compound device, M 1 + M2 ,
has twice the width and the bias current of each of M 1 and M2 and, therefore, twice their
transconductance. The CM gain of the circuit is thus equal to

A - · Vout (4.27)
v,CM- V:
in,CM
Rv/2
(4.28)
1/(2gm) + Rss'

where 8m denotes the transconductance of each of M1 and M2 and)..= y = 0.

What is the significance of this calculation? In a symmetric circuit, input CM variations
disturb the bias points, altering the small-signal gain and possibly limiting the output voltage
swings. This can be illustrated by an example.

Example4.6 - - - - - - - - - - - - - - - - - - - - - -
The circuit of Fig. 4.26 uses a resistor rather than a current source to define a tail current of 1 rnA.

...,..----,... Voo

1 mA ~ Rss

-: Figure 4.26
Assume (W /Lh,2 = 25/0.5, J.LnCox =50 J,LNV2, VrH = 0.6 V, A.= y = 0, and Vvv = 3 V.
(a) What is the required input CM _for which Rss sustains 0.5 V?
(b) Calculate Rv for a differential gain of 5.
(c) What happens at the output if the input CM level is 50 mV higher than the value calculated in
(a)?

Solution
(a) Since /Dl = /D2 = 0.5 rnA, we have
2/Dl
Vcs1 = Vcs2 = W +VrH (4.29)
J.LnCoxL
= 1.23 v. (4.30)

Thus, Vin,CM = Vest+ 0.5 V= 1.73 V. Note that Rss = 500 Q.

(b) The transconductance of each device is 8m = ../2J.LnCox(WI L)/Dl = 1/(632 Q), requiring
Rv = 3.16 kQ for a gain of 5.
Note that the output bias level is equal to Vvv- IDlRD = 1.42 V. Since Vin,CM = 1.73 V and
Vr H = 0.6 V, the transistors are 290 rnV away from the triode region.
120 Chap. 4 Differential Amplifiers v

(c) If Vin,CM increases by 50 mY, the equivalent circuit of Fig. 4.25(c) suggests that Vx and V1
drop by

l bVX,Y 1- b~· RD / 2 (4.31)

- m,CM Rss + l /(2gm)
=50 mY x 1.94 (4.32)
= 96.8 mY . (4.33)

Now, M1 and M2 are only 143 mY away from the triode region because the input CM level has
increased by 50 mY and the output CM level has decreased by 96.8 mY.

The foregoing discussion indicates that the finite output impedance of the tail current
source results in some common-mode gain in a symmetric differential pair. Nonetheless,
this is usually a minor concern. More troublesome is the variation of the differential output
as a result of a change in Vin.c M, an effect that occurs because in reality the circuit is not
fully symmetric, i.e., the two sides suffer from slight mismatches during manufacturing.
For example, in Fig. 4.25(a), RDI may not be exactly equal to Rm.
We now study the effect of input common-mode variation if the circuit is asymmetric
and the tail current source suffers from a finite output impedance. Suppose, as shown in
Fig. 4.27, RDI = RD and Rm = RD + b.RD , where b.RD denotes a small mismatch and

...,.-----,.. Voo

Rss
Figure 4.27 Common-mode response
-. in the presence of resistor mismatch.

the circuit is otherwise symmetric. What happens to Vx and Vr as Vin,CM increases? Since.....,
M1 and M2 are identical, /Dl and I m increase by [gm/(1 + 2gm Rss)]b. Vin,cM, but Vx and
Vy change- by different amounts: ..

8m '-'
D. Vx = -D. Vin CM RD (4.34)
' 1 + 2gm Rss
8m
D. Vr = -D. Vin,CM (RD + D.RD). (4.35) -
1 + 2gmRss

Thus, a common-mode change at the input introduces a differential component at the output. \w
We say the circuit exhibits common-mode to differential conversion. This is a critical
problem because if the input of a differential pair includes both a differential signal and
·~ec. 4.3 Common-Mode Response 121

common-mode noise, the circuit corrupts the amplified differential signal by the input CM
change. The effect is illustrated in Fig. 4.28 .

.....------ Vvo

-. -.
Figure 4.28 Effect of CM noise in the presence of resistor mismatch .

...,..----.,- Vvo

Vout2

Figure 4.29 CM response with finite

tail capacitance.

In summary, the common-mode response of differential pairs depends on the output

impedance of the tail current source and asymmetries in the circuit, manifesting itself
through two effects: variation of the output CM level (in the absence of mismatches) and
conversion of input common-mode variations to differential components at the output. In
analog circuits, the latter effect is much more severe than the former. For this reason, the
common-mode response should usually be studied with mismatches taken into account.
How significant is common-mode to differential conversion? We make two observations.
First, as the frequency of the CM disturbance increases, the total capacitance shunting the tail
current source introduces larger tail current variations. Thus, even if the output resistance of
the current source is high, common-mode to differential conversion becomes significant at
high frequencies. Shown in Fig. 4.29, this capacitance arises from the parasitics of the current
source itself as well as the source-bulk junctions of M 1 and M 2 • Second, the asymmetry in
the circuit stems from both the load resistors and the input transistors, the latter contributing
a typically much greater mismatch.
Let us now study the asymmetry resulting from mismatches between M, and M2 in
Fig. 4.30(a). Owing to dimension and threshold voltage mismatches, the two transistors
122 Chap. 4 Differential Amplifier~

-,-----,... Voo ...,..----.,... Voo

p
Rss Rss

-. -.
(a) (b)

Figure 4.30 (a) Differential pair sensing CM input, (b) equivalent circuit of (a).

carry slightly different currents and exhibit unequal transconductances. To calculate the
gain from V;n,CM to X and Y, we use the equivalent circuit in Fig. 4.30(b), writing /Dl =
gmJ (V;n ,CM - Vp) and /D2 = gm2(\-'in ,CM - Vp ). That is,

(gmJ + gm2)(V;n,CM - Vp)Rss = Vp, (4.36)

and

Vp = (gm! + gmz)Rss V;n CM· (4.37)

(gmJ + gm2)Rss + 1 '

We now obtain the output voltages as

Vx = -gmt(V;n,CM- Vp)Ro (4.38)

-gm!
- - - - - - - R o V;n CM (4.39)
(gmt + gmz) Rss + 1 ·

and

Vy = -gm2(Vin,CM- Vp)Ro (4.40)

- gm2
- - - - -- Ro \-'in CM · (4.41)
(gm 1 +gmz)Rss + 1 '

The differential component at the output is therefore given by

_ gm1 - gm2 R V:
VX - VY -- D in CM · (4.42)
(gm! + gmz)Rss + 1 '

In other words, the circuit converts input CM variations to a differential error by a factor
•IJC. 4.3 Common-Mode Response 123

equal to

(4.43)

where AcM- DM denotes common-mode to differential-mode conversion and l::..gm =

I

gmi - gm2· ·

Example4.7 - - - - - - - - - - - - - - - - - - - - - -
Two differential pairs are cascaded as shown in Fig. 4.31. Transistors M3 and M4 suffer from a 8m

~-~~--~----~------~~0

Figure 4.31

mismatch of !:lgm, the total parasitic capacitance at node P is represented by Cp, and the circuit is
otherwise symmetric. What fraction of the supply noise appears as a differential component at the
output? Assume A. = y = 0.
Solution
Neglecting the capacitance at nodes A and· B, we note that the supply noise appears at these nodes
with no attenuation. Substituting 1/(Cps) for Rss in (4.43) and taking the magnitude, we have

!:lgmRD
lAc M -DM I = r==========:: (4.44)

1 +(gm, +gm•PI c:.,i'

The key point is that the effect becomes more noticeable as the supply noise frequency, w, increases.

For meaningful comparison of differential circuits, the undesirable differential com-

ponent produced by CM variations must be nonnalized to the wanted differential output
resulting from amplification. We define the "common-mode rejection ratio" (CMRR) as

CMRR =I AvM
AcM- DM
. (4.45)
124 Chap. 4 Differential Amplifier v

If only gm mismatch is considered, the reader can show from the analysis of Fig. 4.1 5 thai

_ RD gm l + gm2 + 4gmlgm2Rss (4.4(J)

lA DM-
I '
2 1 + (gml + gm2)Rss
where it is assumed V;n1 = - V; 112, and hence

CMRR = gm l + gm2 +4gmlgm2 Rss (4.47)

2 ~gm

~ ~(1 + 2gmRss), (4.48)

~gm

where gm denotes the mean value, i.e., gm = (gm1 + gm 2 )j2. In practice, all mismatches
must be taken into account.

4.4 Differential Pair with MOS Loads

The load of a differential pair need not be implemented by linear resistors. As with the
common-source stages studied in Chapter 3, differential pairs can employ diode-connected
or current-source loads (Fig. 4.32). The small-signal differential gain can be derived using

-.
(a) (b)

Figure 4.32 Differential pair with (a) diode-connected and (b) current-
source loads.
the half-circuit concept. For Fig. 4.32(a),

Av = -gmN (g;;;~ !IroN ll rop ) (4.49)

gmN
~-- (4.50)
'

where subscripts N and P denote NMOS and PMOS, respectively. Expressing gmN an().oo
gmP in terms of device dimensions, we have

Av ~ _ JJ-n(W / L)N (4.511'

JJ- p(Wj L)p
-
I 4.4 Differential Pair with MOS Loads 125

For Fig. 4.32(b), we have

(4.52)

In the circuit of Fig. 4.32(a), the diode-connected loads consume voltage headroom, thus
creating a tr~de-off between the output voltage swings, the voltage gain, and the input CM
range. Recall from Eq. (3.35) that, for given bias current and input device dimensions, the
circuit's gain and the PMOS overdrive voltage scale together. To achieve a higher gain,
(W/L)p must decrease, thereby increasing IVasP- VrHP I and lowering the CM level at
nodes X and Y. ·
In order to alleviate the above difficulty, part of the bias currents of the input transistors
can be provided by PMOS current sources. Illustrated in Fig. 4.33, the idea is to lower the
gm of the load devices by reducing their current rather than their aspect ratio. For example,

Figure 4.33 Addition of current

-. sources to increase the voltage gain.

if M5 and M6 carry 80% of the drain current of M1 and M2 , the current through M3 and M4
is reduced by a factor of five. For a given IVasP - Vr Hp 1. this translates to a factor of five
reduction in the transconductance of M3 and M4 because the aspect ratio of the devices can
be lowered by the same factor. Thus, the differential gain is now approximately five times
that of the case with no PMOS current sources.
The small-signal gain of the differential pair with current-source loads is relatively low-
in the range of 10 to 20 in submicron technologies. How do we increase the voltage gain?
Borrowing ideas from the amplifiers in Chapter 3, we increase the output impedance of both
PMOS and NMOS devices by cascading, in essence creating a differential version of the
cascade stage introduced in Chapter 3. The result is depicted in Fig. 4.34(a). To calculate
the gain, we construct the half circuit of Fig. 4.34(b)', which is similar to the cascade stage
of Fig. 3.60. Thus,

(4.53)

Cascading therefore increases the differential gain substantially but at the cost of consuming
more voltage headroom.
As a fi nal note, we should mention that high-gain fully differential amplifiers require a
means of defining the output common-mode level. For example, in Fig. 4.32(b), the output
126 Chap. 4 Differential Amplifier!.

vb2 vb2----f
Vout
vb1 vb1.-f
Vin o---f

-.
-.
(a) (b)

Figure 4.34 (a) Cascode differential pair, (b) half circuit of (a).

common-mode level is not well-defined whereas in Fig. 4.32(a), diode-connected transistors

define the output CM level as V00 - VasP· We return to this issue in Chapter 9.

4.5 Gilbert Cell

Our study of differential pairs reveals two important aspects of their operation: (1) the
small-signal gain of the circuit is a function of the tail current and (2) the two transistors in a
differential pair provide a simple means of steering the tail current to one of two destinations.
By combining these two properties, we can develop a versatile building block.
Suppose we wish to construct a differential pair whose gain is varied by a control voltage.
This can be accomplished as depicted in Fig. 4.35(a), where the control voltage defines the

...,.----!""' Voo "'T"""---I""'VDD -----.,...Voo

+ +
..,_--o Vout1 Vout2 o---...

-.
(a)
-.
(b)
-.
Figure 4.35 (a) Simple VGA, (b) two stages providing variable gain.
Gilbert Cell 127

tail current and hence the gain. In this topology, Av = Vout I Vin varies from zero (if I D3 = 0)
to a maximum value given by voltage headroom limitations and device dimensions. This
circuit is a simple example of a "variable-gain amplifier" (VGA). VGAs find application
in systems where the signal amplitude may experience large variations and hence requires
inverse changes in the gain.
Now suppose we seek an amplifier whose gain can be continuously varied from a negative
value to a positive value. Consider two differential pairs that amplify the input by opposite
gains [Fig. 4.35(b)]. We now have Voun / V;n = -gmRv and Vour2/ V;n = +gmRv, where
8m denotes the transconductance of each transistor in equilibrium. If / 1 and /z vary in
opposite directions, so do IVouti! V;n I and 1Vout2! V;n 1.
But how should Voutl and Vout2 be combined into a single output? As illustrated in Fig.
4.36(a), the two voltages can be summed, producing Vout = Voutl +Vout1 == A1 V;n +A1V;n ,

Vcont1
..,----~ Voo

Vout1

Vln
Vout
Vln
<>-4

Vout2
Vcont1

-. -.
Vcont2
(a) (b)

Voo
Voo
+
Vout

(c)
-.
(d)

Figure 4.36 (a) Summation of the output voltages of two amplifiers, (b) summation in the current
domain, (c) use of M5-M6 to control the gain, (d) Gilbert cell.
128 Chap. 4 Differential Amplifier::, v

where A 1 and A2 are controlled by Vconr1 and Vcont2• respectively. The actual implementation
is in fact quite simple: since Vour1 = Ro!Dl - Ro/02 and Vortr2 = Rolo4- RolDJ , we
have Voutl + Vo,112 = RoUDJ + lo4)- RoUD2 + /03). Thus, rather than add Voutl and Vout2•
we simply short the corresponding drain terminals to sum the currents and subsequently
generate the output voltage [Fig. 4.36(b)]. Note that if h = 0, then Vout = +gmRD Yin and
if h = 0, then V0111 = -gmRo Vin· For I, =h. the gain drops to zero.
In the circuit of Fig. 4.36(b), Vconr 1 and Vconr 2 must vary hand h in opposite directions
such that the gain of the amplifier changes monotonically. What circuit can vary two currents
in opposite directions? A differential pair provides such a characteristic, leading to the
topology of Fig. 4.36(c). Note that for a large IVcont1 - Vcont21, all of the tail current is
steered to one of the top differential pairs and the gain from Yin to Vout is at its most positive
or most negative value. For Vcontl = Vcont2• the gain is zero. For simplicity, we redraw the
circuit as shown in Fig. 4.36(d). Called the "Gilbert cell" [2], this circuit is widely used in
many analog and communication systems. In a typical design, M1-M4 are identical and so
are M5 and M6.

Example4.8 - - - - - - - - - - - - - - - - - - - - - -
Explain why the Gilbert cell can operate as an analog voltage multiplier.
Solution
Since the gain of the circuit is a function of Vcont = Vcont 1 - Vcont2. we have Vout = V;n · f (Vcont ).
Expanding f(Vcont) in a Taylor series and retaining only the first-order term, a Vcont• we have Vout =
a V;n Vcont. Thus, the circuit can multiply voltages. This property accompanies any voltage-controlled
variable-gain amplifier.

As with a cascode structure, the Gilbert cell consumes a greater voltage headroom than
a simple differential pair does. This is because the two differential pairs M1-M2 and M3-M4
are "stacked" on top of the control differential pair. To understand this point, suppose the
differential input, Vin. in Fig. 4.36(d) has a common-mode level VcM,in· Then, VA = V8 =
VcM,in- Vas I, where M1-M4 are assumed identical. For M 5 and M6 to operate in saturation,
the CM level of Vcont• VcM,cont• must be such that VcM,cont ~ VcM,in - Vas!+ VrH5,6·
Since Vast - Vr H5 ,6 is roughly equal to one overdrive voltage, we conclude that the control
CM level must be lower than the input CM level by at least this value.
In arriving at the Gilbert cell topology, we opted to vary the gain of each differential
pair through its tail current, thereby applying the control voltage to the bottom pair and the
input signal to the top pairs. Interestingly, the order can be exchanged while still obtaining
a VGA. Illustrated in Fig. 4.37(a), the idea is to convert the input voltage to current by
means of Ms and M6 and route the current through M1-M4 to the output nodes. If, as
shown in Fig. 4.37(b), Vcont is very positive, then only M 1 and M 2 are on and V0111 =
gms,6Ro Yin· Similarly, if Vc0111 is very negative [Fig. 4.37(c)], then only M3 and M4 are on ......
and Vout = -gms,6 Ro Vin· If the differential control voltage is zero, then V0111 = 0. The
input differential pair may incorporate degeneration to provide a linear voltage-to-current '-"
conversion.
·l dt:rns 129

(a)
-.
(b)
-.
(c)

Figure 4.37 (a) Gilbert cell sensing the input voltage by the bottom differential pair, (b) signal path for very
positive Vcont• (c) signal path for very negative Vcont·

Problems
Unless otherwise stated, in the following problems, use the device data shown in Table 2.1and assume
Vvv = 3 V where necessary. All device dimensions are effective values and in microns.

4.1. Suppose the total capacitance between adjacent lines in Fig. 4.2 is 10 fF and the capacitance
from the drains of Mt and M2 to ground is 100 fF.
(a) What is the amplitude of the glitches in the analog output in Fig. 4.2(a) for a clock swing
of3 V?
(b) If in Fig. 4.2(b ), the capacitance between L 1 and L2 is 10% less than that between L 1 and
L3, what is the amplitude of the glitches in the differential analog output for a clock swing
of3 V?
4.2. Sketch the small-signal differential voltage gain of the circuit shown in Fig. 4.8(a) if Vvv varies
from 0 to 3 v. Assume (WI Lh-3 = 5010.5, V;n ,CM = 1.3 V, and vb = 1 v.
4.3. Construct the plots of Fig. 4.8(c) for a differential pair using PMOS transistors.
4.4. In the circuit of Fig. 4.10, (WI Lh.2 = 5010.5 and Iss= 0.5 rnA.
(a) What is the maximum allowable output voltage swing if V;n,C M = 1.2 V?
(b) What is the voltage gain under this condition?
·4.5. A differential pair uses input NMOS devices with WI L ~ 5010.5 and a tail current of 1 rnA.
(a) What is the equilibrium overdrive voltage of each transistor?
(b) How is the tail current shared between the two sides if Vin!- Vin2 =50 rnA?
(c) What is the equivalent Gm under this condition?
(d) For what value of Vinl - Vin2 does the Gm drop by 10%? By 90%?
4.6. Repeat Problem 4.5 with WI L = 2510.5 and compare the results.
4.7. Repeat Problem 4.5 with a tail current of 2 rnA and compare the results.
4.8. Sketch I D! and ID2 in Fig. 4.17 versus VinJ - Vin2· For what value of V;11 1 - Vin2 are the two
currents equal?
 ~-------T------~Voo

-. (b)
(a)
..,.....----- Voo

-.
(c)

Figure4.39

-. Figure 4.40

132
 -. Figure 4.41

-. Figure 4.42

~in1o-f

Figure 4.43

133
134 Chap. 4 Differential Amplifier!. wJ

...,..------,- Voo

-. Figure4.44

Figure 4.45

References
1. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., New
York: Wiley, 1993.
2. B. Gilbert, "A Precise Four-Quadrant Multiplier with Subnanosecond Response," IEEE J. Solid·
State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.