BITS Pilani

Pilani Campus

MEL G 621: VLSI Design

Performance Metrics
& Inverter Circuit
Outlines

Historical Perspectives

Progresses in Semiconductor Industry

Digital Design Metrics

Inverter Circuit

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Major Challenges in Digital Designs

α DSM α 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.

Everything Looks a Little Different …and There’s a Lot of Them!

?
Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design in Deep Submicron
Design in the deep submicron (DSM) era creates new
challenges
Devices become somewhat different
Global clocking becomes more challenging
Interconnect effects play a more significant role
Power dissipation may be the limiting factor
We must understand and be able to design digital ICs in
advanced technologies (at or below 180 nm)

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Metrics
How to evaluate performance of a digital circuit (gate, block,


…)?

Cost (Yield)

Reliability (Noise Immunity)

Scalability (Fan-In, Fan-out)

Speed (delay, operating frequency)

Power dissipation

Energy to perform a function

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor

Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Reliability

Noise in Digital Integrated Circuits

i(t) v(t) V DD

Inductive coupling Capacitive coupling Power and ground

noise

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Voltage Transfer Characteristics
V(y)
VOH = f(VOL)
VOL = f(VOH)
V f
OH VM = f(VM)
V(y)=V(x)

VM Switching Threshold

V OL DC Operations
V OL V
OH
V(x)

Nominal Voltage Levels

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Mapping between Analog and Digital
V
out
V
“1” OH Slope = -1
V
V OH
IH

Undefined
Region

V
IL
Slope = -1

V
“0” V
OL
OL
V V V
IL IH in

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Definition of Noise Margins

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Mapping between Analog and Digital
V
out
V
“1” OH Slope = -1
V
V OH
IH

Undefined
Region

V
IL
Slope = -1

V
“0” V
OL
OL
V V V
IL IH in

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Key Reliability Properties
1. Absolute noise margin values are deceptive

A floating node is more easily disturbed than a node
driven by a low impedance (in terms of voltages)
2. Noise Immunity is the more important metric

The capability to suppress noise sources (Regenerative
property)

Key metric:
Noise transfer functions,
Output impedance of the driver, and Input impedance of
the receiver.
Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Regenerative Property

v0 v1 v2 v3 v4 v5 v6

A chain of inverters

Ability to recover a corrupted signal

to a well-defined digital signal

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Regenerative Property I
Vout Vout

v3
f(v) finv(v)

v1 v1

finv(v) v3
f(v)

v2 v0 Vin v0 v2 Vin
Regenerative Non-Regenerative
Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Fan-in and Fan-out
Indirectly define scalability

M
N

Fan-out N Fan-in M

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Delay Definitions
Vin tpHL : High-to-Low
propagation delay

tpLH : Low-to-High
50%
propagation delay
t
tpHL tpL
Vout H
90%

50% tr : Rise Time

tf : Fall Time
10% t
tf tr

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Power Dissipation
Instantaneous power: Vsupply
p(t) = v(t) i(t) = Vsupply i(t) i(t)

Peak power:
Ppeak = Vsupply ipeak
GND

Average power:
1 V supply
Pave = ∫ p ( t ) dt= ∫ i supply ( t ) dt
T T

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Energy and Energy-Delay Product
Power-Delay Product (PDP) =

E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) =

Quality metric of gate = E × tp

Energy is limited in certain situations such as in

Cell Mobile phone, PC Notebooks, etc.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Inverter

Ideal Voltage Transfer Characteristics (VTC)

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

VTC DESIGN ISSUES

STATIC POWER CONSUMPTION

FULL LOGIC LEVELS

SHARP TRANSITION

SWITCHING THRESHOLD→ NOISE MARGINS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Practical VTC

Voltage Transfer Characteristics (VTC)

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Five Critical Voltages on VTC
 VOH: Maximum output voltage when the output level is logic “1”

 VOL : Minimum output voltage when the output level is logic “0”

 VIL : Maximum input voltage which can be interpreted as logic “0”

 VIH : Minimum input voltage which can be interpreted as logic “1”

 VTH : Switching threshold

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
Noise Margin

NMH = VOH- VIH

NML = VIL-VOL

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Resistive Load Inverter
 Enhancement nMOS transistor is the driver device

 Load is a resistor RL

 Drain current ID = Load current IR

 Taking VSB = 0

 Threshold voltage of the driver

transistor is VTO

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Operating regions of driver Transistor

Input voltage range Operating Mode

Vin < VTO cut-off

VTO<= Vin < Vout + VTO saturation

Vin >= Vout + VTO linear

BITS Pilani, Pilani Campus

VOH

Vout = VDD – IR. RL

when input voltage is low, i.e., less than the threshold
voltage of the MOST, driver transistor will be in cutoff.

ID = IR = 0

VOH = VDD
BITS Pilani, Pilani Campus
VOL
To calculate VOL , assume that the input voltage is VOH. i.e., Vin =
VOH = VDD

Since VIN – VTO > Vout, driver transistor operates in linear region

IR = ( VDD – Vout)/ RL ( IR = ID)

(VDD – Vout)/ RL = kn/2 [ 2(VDD- V TO) VOL – VOL2]

Solving for VOL: VOL = VDD- VTO +1/knRL – ((VDD-VTO +

I/knRL)2 –2VDD/knRL))1/2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
VIL
VIL is the smaller of the two input voltage values at which the slope of
the VTC becomes equal to ( -1)

By inspection when input is VIL , output is only slightly smaller than

VOH.
Vout > Vin – VTO driver transistor operates in saturation

( VDD – Vout)/ RL = kn/2 [ (Vin- V TO)2]

Differentiating both the sides with respect to Vin:

(-1/RL) dVout/dVin = kn ( Vin – VTO) , substituting dVout/dVin =
-1
VIL = VTO + 1/kn RL
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
VIH
VIH is the larger of the two points on the VTC in which slope is
equal to ( -1).

By inspection when Vin = VIH, Vout is only slightly larger than

VOL.
Hence, VOUT < VIN – VTO , driver transistor operates in linear
region.
( VDD – Vout)/ RL = kn/2 [ 2(Vin- V TO) Vout – Vout2]

Differentiating Vout with respect to Vin

substituting dVout/dVin = -1 and also Vin = VIH

VIH = VTO + 2VOUT - 1/knRL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Operating regions of driver Transistor
Using the two equations with two unknowns Vout and VIH
Solving gives

Vout ( Vin = VIH) = ( 2.VDD/3.kn.RL)1/3.

and

VIH = VTO + (8.VDD/3.kn.RL)1/3 - 1/knRL.

The four critical points

VIH, VIL, VOH, VOL help calculate noise margin.

Vth can be found by solving Vin = Vout = Vth.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Power Consumption
The average power consumption of a resistive load inverter circuit is
found by considering

Vin= VOL(low) and Vin = VOH ( high)

When Vin = VOL driver transistor cut-off ( ID = IR = 0) and the DC

power dissipation is zero.

When Vin = VOH driver and load conduct a non zero current.
Vout = VOL
ID = IR = (VDD - VOL)/RL

PDC(average) = (VDD/2) .( VDD- VOL) RL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design for Vol
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 VDD Saturated enhancement load.

Single power supply

VOH = VDD- VTload

IL Vout

ID
Vin

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 VGG
VDD Linear- enhancement load.

Two power supplies

VOH = VDD
IL Vout

ID
Vin

Both consumes static DC Power.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Depletion Load nMOS inverter
Driver transistor enhancement
nMOS with V TO, driver > 0
VDD
VGG
Load is depletion type nMOS with
V TO, load < 0

V GS,
Load device always conducting as
IL Vout
load= 0 V GS, load > V T, load
ID
Load device subjected to substrate
Vin
bias.

Operation of load transistor

depends on the output voltage

Vout when small, the load is in

saturation.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
The shape of VTC , noise margin are determined by the threshold
voltages of the driver and load devices and by the ratio kdriver/ kload

Determined by the W/L ratio of the transistors.

Inverter requires relatively small driver-to-load ratios.

Total area occupied by the depletion load inverter with acceptable

circuit performance is expected to be much smaller than the area
occupied by a comparable resistive-load or enhancement load inverter.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Depletion Load nMOS inverter

- Fabrication slightly complicated

- Sharp VTC Transition

- Better noise Margin

- Smaller overall layout area.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Questions ?

Thanks

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus