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While studying circuits with one or more MOS transistors though we have to deal with very
complicated circuits involving the equivalent circuits of such transistors. So, we have to deal
with circuits featuring a pretty large number of components, which we cannot easily deal with
by hand.
This is where knowing the impedances seen with respect to the reference potential comes in
handy, since it simplifies a lot the computations.
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we apply a test source to the gate of the transistor:
ZD
ZiG (D)
(G)
iT
(S)
vT
ZS
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If we substitute the equivalent small-signal circuit of the MOS transistor we get:
iT (G) io (D)
vT gm vGS ro vo ZD vD
vGS
(S)
ZS vS
1
We can see how the gate of the MOS transistor is an open circuit, so:
iG = 0
So, from the gate of the MOS transistor we see an open circuit.
This means that the gate input impedance is infinite:
ZiG = +∞
ZS
(S)
(G)
(D)
ZG ZiD
iT vT
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If we substitute the equivalent small-signal circuit of the MOS transistor we get:
iG (G) io (D)
vG ZG vGS gm vGS ro vo iT vT
iT
(S)
ZS vS
iD = 0
2
vG = −ZG iD = −ZG 0 = 0
So:
vG = 0
We can write a KVL at the left side to get:
vG = vGS + vS
0 = vGS + vS
vGS = −vS
We can substitute using Ohm’s law to get:
vGS = −ZS iT
We can then find the current io with a KCL at the drain node:
io = iT − gm vGS
We can substitute the relationship for vGS into the last KCL to get:
io = iT + gm ZS iT
We can then find the voltage across the test source by writing a KVL at the right side:
vT = vS + vo
vT = ZS iT + ro io
We can then substitute the expression for io into this last equation to get:
vT = ZS iT + ro (iT + gm ZS iT )
vT = ZS iT + ro iT + gm ro ZS iT
vT = [ZS + ro (1 + gm ZS )] iT
| {z }
vT
ZiD =
iT
Therefore, the input impedance seen by the drain of the MOS transistor is:
ZiD = ZS + ro (1 + gm ZS )
3
0.1.3 source input impedance
In order to compute the source impedance, we consider the most general case, which consists
in a gate and a drain impedance connected to the other two terminals of the MOS transistor
and we apply a test source to the source of the transistor:
ZD
(D)
(G)
(S)
ZG ZiS
iT
vT
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If we substitute the equivalent small-signal circuit of the BJT we get:
iG (G) io (D) iD
vG ZG vGS gm vGS ro vo ZD vD
iD
(S)
iT
vT
We start by deriving an expression for the controlling voltage vGS by writing a KCL at the
input side:
vG = vGS + vT
We can then substitute Ohm’s law into it to get:
−ZG iG = vGS + vT
Because of the open circuit at the gate terminal of the MOS transistor we have:
iG = 0
4
So, the last equation becomes:
0 = vGS + vT
Therefore, the gate-source voltage is:
vGS = −vT
We can now derive the current io by writing a KCL at the drain terminal:
io = iD − gm vGS
io = iD + gm vT
We can write a KVL at the right side in order to determine the drain current iD :
vT + vo = vD
vT + ro io = −ZD iD
vT + ro (iD + gm vT ) = −ZD iD
vT + ro iD + ro gm vT = −ZD iD
vT + ro gm vT = −ZD iD − ro iD
(1 + ro gm )vT = (−ZD − ro )iD
We can now get a relation between the drain current iD and the current iT flowing from the
test source to the circuit by writing a KCL at the lower (source) node:
iD = −iT
ZD + ro
ZiS =
1 + ro gm
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0.1.4 approximate gate input impedance
We can now derive the gate input impedance when the channel length modulation effect is
negligible, so when:
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ro → +∞
In this case, the equivalent circuit becomes:
iT (G) (D) iD
vT vGS gm vGS ZD vD
(S)
ZS vS
Because of the open circuit at the input, the test current is:
iT = 0
We can then check the result by taking the limit of the previously derived general expression
for the gate input resistance when the output resistance ro is tending to infinity:
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0.1.5 approximate drain input impedance
We can now derive the drain input impedance when the channel length modulation effect is
negligible, so when:
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ro → +∞
In this case, the equivalent circuit becomes:
(G) (D)
iG iT
vG ZG vGS gm vGS vT
iT
(S)
ZS vS
We need to use a test voltage source since we cannot have a node with just current sources
connected to it.
We can use Ohm’s law to derive the source voltage vS :
vS = ZS i T
We can substitute the constraint on iT given by the controlled source (iT = gm vGS ) to get:
vS = ZS gm vGS
We can now derive the same source voltage by writing a KVL at the left side:
vS + vGS = vG
iG = 0
vS + vGS = 0
vS = −vGS
We can equate the two boxed expressions for vS to get:
ZS gm vGS = −vGS
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Since, in general:
ZS gm 6= −1
The only way in which this equation is consistent is when the gate-source voltage is zero:
vGS = 0
Therefore, the current through the controlled source is:
gm vGS = 0
Therefore, the current flowing through the test source is zero:
iT = gm vGS
iT = 0
Therefore,the drain terminal behaves as an open circuit.
This is equivalent to the approximate drain input impedance being infinite:
ZiD = +∞ (ro → +∞)
We can then check the result by taking the limit of the previously derived general expression
for the drain input impedance when the output resistance ro is tending to infinity:
= ZS + k1 lim [ro ]
ro →+∞
= ZS + k1 (+∞)
= +∞
Which is exactly the result we obtained from the circuit.
So, the two results are compatible.
34 ro → +∞
In this case, the equivalent circuit becomes:
iG (G) (D) iD
vG ZG vGS gm vGS ZD vD
iD
(S)
iT
vT
8
We can start by deriving the gate-source (controlling) voltage by writing a KVL at the left side:
vG = vGS + vT
−ZG iG = vGS + vT
Because of the open circuit at the input we have that the gate current is zero:
iG = 0
0 = vGS + vT
vGS = −vT
The drain current is then imposed by the controlled source and is:
iD = gm vGS
iD = −gm vT
We can then relate the current flowing through the test source and the drain current through
a KCL at the bottom (source) node:
iD = −iT
Substituting into the boxed equation for the drain current we get:
−iT = −gm vT
iT = gm vT
1
vT = iT
gm
|{z}
vT
ZiS =
iT
Therefore, the source approximate input impedance is:
1
ZiS = (ro → +∞)
gm
We can then check the result by taking the limit of the previously derived general expression
for the source input resistance when the output resistance ro is tending to infinity:
ZD + ro
lim ZiS = lim
ro →+∞ ro →+∞ 1 + ro gm
1
=
gm
Which is exactly the result we obtained from the circuit.
So, the two results are compatible.
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0.1.7
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Input impedances
(G) (G)
nMOS pMOS
EXACT
ZiG = +∞
ZiD = ZS + ro (1 + gm ZS )
ZD + ro
ZiS =
1 + ro gm
ZiD = +∞
1
ZiS =
gm
BJT MOS
B G
C D
E S
rπ +∞ (open circuit)
gm vπ or βiB gm vGS
Therefore, we can perform the following substitutions into the expressions for the input impedances
of the BJT to find the input impedances of the MOS transistor.
Since the input resistance rπ becomes infinite, we have to introduce a limit to perform such
substitution.
Since β depends on rπ remember that β should be substituted with gm rπ before evaluating the
limit for rπ → +∞.
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