Malaviya National Institute Of Technology, Jaipur

SYSTEM DESIGN LAB-II

Session 2019-20

Submitted by: Submitted to:

AMISHA JAIN DR. MENKA YADAV
2016UEC1006 Assistant Professor
 EXPERIMENT – 1
AIM: To design and simulate NOT gate using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: CMOS Circuit design of NOT gate.

TRUTH TABLE:

INPUT OUTPUT
1 0
0 1

LAYOUT:

Fig 2: CMOS implementation of NOT gate

OUTPUT:

Fig 3: Input and Output representation of NOT gate

RESULT: I have successfully designed and simulated NOT gate using virtuoso.
 EXPERIMENT – 2(a)
AIM: To design and simulate 2-input NAND gate using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: CMOS Circuit design of 2-input NAND gate

TRUTH TABLE:
INPUT INPUT
OUTPUT
(A) (B)

0 0 1
0 1 1
1 0 1
1 1 0

LAYOUT:

Fig 2: CMOS implementation of 2-input NAND gate

OUTPUT:

Fig 3: Input and Output Implementation of 2-input NAND gate

RESULT: I have successfully designed and simulated 2-input NAND gate using
virtuoso.
 EXPERIMENT – 2(b)
AIM: To design and simulate 2-input NOR gate using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: CMOS Circuit design of 2-input NOR gate

TRUTH TABLE:
INPUT INPUT
OUTPUT
(A) (B)
0 0 1
0 1 0
1 0 0
1 1 0
LAYOUT:

Fig 2: CMOS implementation of 2-input NOR gate

OUTPUT:

Fig 3: Input and Output Implementation of 2-input NOR gate

RESULT: I have successfully designed and simulated 2-input NOR gate using virtuoso.
 EXPERIMENT – 3(a)
AIM: To design and simulate half adder using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: Circuit design of half adder

TRUTH TABLE:

INPUT INPUT
(A) (B) SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
LAYOUT:

Fig 3: CMOS implementation of half adder

OUTPUT:

Fig 2: Input and Output Implementation of half adder

RESULT: I have successfully designed and simulated half adder using virtuoso.
 EXPERIMENT – 3(b)
AIM: To design and simulate full adder using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: Circuit design of full adder

TRUTH TABLE:

INPUT INPUT INPUT CARRY

SUM
(A) (B) (Cin) OUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LAYOUT:

Fig 3: CMOS implementation of full adder

OUTPUT:

Fig 2: Input and Output Implementation of full adder

RESULT: I have successfully designed and simulated full adder using virtuoso.