“Education is what remains after one has

forgotten what one has learned in school.”

…Albert Einstein

3
CHAPTER

MOSFET

Level-1 (A) g mnew = 3g m (B) g mnew = √3 g m

1 1
(C) g mnew = gm (D) g mnew = g m
1. A FET is a __________ driven device √3 3
(A) current
(B) voltage 6. The transconductance of a JFET is 3 mS and its
(C) both current and voltage amplification factor is 120 then the dynamic
(D) None of these resistance of JFET is __________ kΩ

2. The gate of P-channel E-MOSFET is _________ 7. For the circuit shown below, the transistor
biased. parameters are Vp = −3 V, IDSS = 6 mA and
(A) reverse biased λ = 0. The value of drain voltage VD is
(B) forward biased __________ volts.
(C) can be operate in both (A) and (B) +15V
(D) None of these
4kΩ
3. When drain voltage equals the pinch-off
VD
voltage then drain current __________ with the
increase in drain voltage.
(A) decrease 4MΩ
(B) increase
(C) remains constant 2V
(D) first increases than decreases

4. In the following circuit the region of operation

8. Consider the circuit shown below the
of transistor is (Vth = 0.5 Volt]
transistor parameters are as follows
+1V
k = 0.2 mA/V 2
VTH = +2 V
the value of VDS in volt is __________
2V +5V

0.5V VDS
(A) linear (B) saturation −
(C) cut-off (D) cannot say
5kΩ

5. Transconductance of N-channel MOSFET

operating in saturation region is g m . If the
9. The pinch-off voltage of N-channel JFET is
parameter W/L is trippled with current
(A) the value of VDS at which, further
remaining constant, the new trans
increase in VDs will cause no further
conductance g mnew will be
increase in ID .

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 MOSFET
(B) the value of VGS at which, further (A) linear region
decreases in VGS will cause no further (B) saturation region
increase in ID . (C) cut-off
(C) the value of VDG at which, further (D) None of these
increase in VDG will cause no further
increase in ID . 15. The parameters for the transistor in the given
(D) The value of VDS at which, further circuit are VTH = 2 V and k n = 0.4 mA/V 2 . The
increase in VGs will cause no further power dissipated in the transistor is
increase in ID . __________mW
+10V
10. P: As compare to BJT input impedance of
MOSFET is very high
Q: As compare to MOSFET, the voltage gain of
BJT is low
Out of the above two statements
(A) only P is right
10kΩ
(B) only Q is right
(C) both P and Q is right
(D) both P and Q is wrong

11. In the common source configuration of FET,
the voltage gain and input impedance is
(A) very high and very high
(B) low and very high
(C) high and very low
(D) very low and very low
16. In a small signal model of an FET, what does
g m VGS stand for
(A) a pure resistor
(B) voltage controlled current source
(C) voltage controlled voltage source
(D) current controlled current source

12. N-channel D-MOSFET with positive VGS is 17. A FET source follower circuit has g m of 0.2 mS
operating in and rd of 50 kΩ, the output resistance of the
(A) the depletion mode amplifier is
(B) the enhancement mode (A) 4550 Ω (B) 555 Ω
(C) cut-off (C) ≈ 0.5 kΩ (D) ≈ 50 kΩ
(D) saturation
18. A depletion MOSFET can operates in
13. A FET has IDSS = 4ID and g mo = 10 m then (A) enhancement mode only
g m = __________ (B) depletion mode only
(A) 10 ms (B) 20 ms (C) enhancement and depletion mode
(C) 5 ms (D) 14 ms (D) JFET mode

14. In the given circuit of figure if VTH = −0.4 V, 19. JFET can operates in
the transistor M1 is operating in (A) depletion mode
1V (B) enhancement mode
(C) both mode
(D) never operates in depletion or
enhancement mode
M1
20. Enhancement type N-MOS will be in linear
region if
+
0.3V (A) VGS > VGS th and VDS > VGS − VGS th
−
(B) VGS > VGS th and VDS < VGS − VGS th
(C) VGS < VGS th and VDS < VGS − VGS th
(D) VGS < VGS th and VDS = VGS

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 MOSFET

Level-2 +12V

1. In the given circuit of figure, the transistor 2.5mA 2kΩ

parameters are given as
VTH = 0.4 V, μn Cox = 200 μA/V 2 Vx
If the transistor operates at the edge of
saturation, then parameter W/L is __________
3.6 Volt

1kΩ

W
5. For the given figure shown, the μn Cox ( )
L
1V + = 800 μ Amp/V 2 and VTH = 1 V. The value of
−
VDS in volt is __________. If MOSFET operates in
saturation.
+18V
2. Common drain amplifier
(a) is also known as source follower
(b) is a current buffer 33k 3k
(c) introduced 0° phase shift in the output
(d) having voltage gain nearly equal to 1 +
In the given options, which one is/are wrong? VDS
(A) (a) (B) (b) and (d) −
(C) Only (b) (D) (a), (b) and (c)
11k 1k
3. In the below circuit shown all the MOSFET’s
are in saturation region. The value of Vx is 5 V
and R D is 2.5 kΩ. The value of Iref in mA is
__________ 6. For the given figure shown. k n = 0.5 mA/V 2
+10V and Vth = 1 Volt. The value of VS in volt is
__________. If MOSFET operates in linear region.
Iref +16V
R D = 2.5kΩ
Vx

5M 6k

VS
5M
2k

4. In the below figure shown all the MOSFET

operates in saturation and are matched. The
value of Vx in volt is __________
7. For the given figure shown, both MOSFET
having VTh = 1 V and k n = 0.4 mA/V 2 . The
value of Vo in volt is __________. If reverse
voltage or zener voltage across zener is 3 V,
otherewise 0 volt. Assume MOSFET M1 is in
saturation

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 MOSFET
+10V 11. In the circuit shown below the transistor
parameters are VTH = 1.7 V and
W
μn Cox ( ) = 0.8 mA/V 2
5V M1 L
If ID = 0.8 mA and VD = 1 V then the value of
Vo resistor R S and R D are respectively
+5V
0.8V M2
1k
RD
VD

8. In a common-source MOSFET amplifier, the

output voltage is
(A) 180o out of phase with input RS
(B) 0o phase with input 50k
(C) taken at source
(D) 45o out of phase with input −5V

9. The given figure shown, a composite (A) 4 kΩ, 5.8 kΩ (B) 2.35 kΩ, 5 kΩ
transistor consists of a MOSFET and a bipolar (C) 5.8 kΩ, 4 kΩ (D) 5 kΩ, 4 kΩ
transistor in cascade. The MOSFET has a
transconductance of 1.5 mA/V and the bipolar 12. Consider the common-source circuit with
transistor has β = 199. The overall source bypass capacitor. The signal frequency
transconductance of the composite transistor is sufficiently large. The transistor parameters
is __________ mA/V are VTN = 0.8 V, k n = 1 mA/V 2 and λ = 0.
−Vcc The voltage gain is
+5V
7kΩ
Vo

Vs + 20kΩ
~
−
C­large 0.5mA
−5V
(A) −15.6 (B) −9.9
(C) −6.8 (D) −3.2
10. The transistors in the circuit of figure have
parameters VTh = 0.8 V, μn . Cox = 40 μA /V 2 . 13. Consider the following network
W
The ( ) ratio of M2 is 2. If Vo = 3 Volts VGS = 0.4 V and ID = 6 mA
L 2
W 18V
when Vin = 2 V, then ( ) for M1 is __________
L 1
+5V
1.8kΩ
121MΩ
Vo
M1
IDSS = 6.8 mA
Vi VP = −3.5 V
Vo

M2 11MΩ 100Ω
Vin

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 MOSFET
The value of transconductance (g m ) is VDD = 8V
(A) 1 S (B) 0 S
(C) 8 S (D) 4.33 mS
RD 1kΩ
14. Consider the MOSFET amplifier circuit shown 3MΩ
in figure.
VDD

8kΩ 5MΩ RS 1kΩ

Vo
ii io

Vs ~ 50kΩ
100Ω 4kΩ 17. An n-channel E-MOSFET is biased at VGS > Vth
and VDS < (VGS − Vth ), where VGS is gate-to-
source voltage. VDS is the drain-to-source
250Ω
voltage and Vth is the threshold voltage.
Considering channel length modulation effect
to be significant, the MOSFET behaves as a
Transistors parameters are (A) voltage variable capacitor
IDSS = 2 mA, VP = −2, λ = 0 (B) voltage variable resistor
Transconductance is (C) current source with finite output
(A) 1.57 mA/V (B) 0.785 mA/V impedance
(C) 11.28 mA/V (D) 13.81 mA/V (D) current source with infinite output
impedance
15. In the circuit shown in the figure, the MOSFET
is operating in the saturation zone. The 18. For the transistor circuit shown below, the
characteristics of MOSFET is given by parameters are VP = −3.5 Volts, IDSS = 18 mA
ID =
1
(VGS − 1)2 mA. where VGS is in Volt. If and λ = 0. The value of VDS in volts is _________.
2
+15V
VS = +5 V, then the value of R S in kΩ is
__________
0.8kΩ
22.5V

RD
8MΩ IQ = 8mA

−15V

VS 19. For the circuit shown, the value of drain to

7MΩ
RS source voltage, VDS in volts is __________.
+18V

16. For the circuit shown, assume that the NMOS 620Ω
transistor is in saturation. Its threshold
voltage VTh = 1 V. and its transconductance
W VGS off = −8V
parameters μn Cox ( ) = 1 mA/V 2 . Neglect
L
channel length modulation and body bias IDSS = 12 mA
10MΩ
effect. Under these conditions, the drain
current ID in mA is __________.

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 MOSFET
20. The voltage gain of a common gate amplifier +5V +5V
shown below with
rdg = 100 kΩ, g m = 3000 µΩ, R L = 10 kΩ
R S = 600 Ω, will be (Neglecting CS & CC ) 40kΩ 40kΩ
V1 V2
CS
CC M1 M2

+
RS
+ RL
~V i
VDD
Vo V3
− 200μA
−

Vo Vo The voltages V1 , V2 and V3 are respectively

(A) = 28.4 (B) = 26.2 (A) 1 V, 1 V, −1.1 V
Vi Vi
(B) 1 V, 2 V, 1 V
Vo Vo
(C) = 25.5 (D) = +27.37 (C) 2 V, 1 V, 1.32 V
Vi Vi
(D) 1 V, 1 V, −1.32 V

Level-3 3. The parameter of the transistor shown below

are VTN = 1.2 V, k n = 0.5 mA/V 2 and λ = 0
1. In the circuit shown below, the transistor The voltage VDS is __________ Volt
parameters are VTN = 1 V and k ′n = 36 μA/V 2 . +5V
+10V

50μA

M1
V1

M2
V2
W
M3 4. An Amplifier shown MOSFET has μn Cox =
L
V0
2 mA/V , VT = 1 V, λ = 0 the ratio of
2
is
Vi
12V
If ID = 0.5 mA, V1 = 5 V and V2 = 2 V then the
width to length ratio required in each
transistor are 10MΩ 2kΩ
W W W Vo
( ) ( ) ( )
L 1 L 2 L 3
(A) 1.75 6.94 27.8 12kΩ
(B) 4.93 10.56 50.43 20MΩ
(C) 35.5 22.4 5.53
~V i
2kΩ
(D) 56.4 38.21 12.56

2. In the following circuit, transistors Q1 and Q 2

has following parameters (A) 13.04 (B) 20
W W (C) 50 (D) −5.58
( ) = ( ) = 20
L 1 L 2
(VTH )1 = (VTH )2 = 1 V
(k ′n )1 = (k ′n )2 = 100 μA/V 2

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 MOSFET
5. MOSFET circuit is shown below, It has 8. Following two stages amplifier is shown in
W Vo
following parameter, μP Cox = 4 mA/V , 2
figure, determine its overall gain ( ).
L Vin
VT = −1.5 V, λ = 0, the magnitude of small Assume all transistors are in saturation and
signal voltage gain is also include the effect of channel length
10V modulation.
VDD
2kΩ

VG2 M2 (g m2 , rd2 ) M4 (g m4 , rd4 )

Vo
~V i
500kΩ Vo
2.2kΩ

Vin M1 (g m1 , rd1 ) M3 (g m3 , rd3 )

−10V VG3
(A) −11.7 (B) 50
(C) 11.7 (D) None

Common Data for Q. No. 6 & 7 Vo

(A) = −g m1 g m4 (rd1 ∥ rd2 )(rd3 ∥ rd4 )
Shown below is the JEFT amplifier in self-bias Vin
arrangement. Vo rd1 rd2
(B) = −g m1 g m4
+VDD Vin rd1 + rd2
Vo rd3 rd4
(C) = −g m1 g m4
id Vin rd3 + rd4
R2 D
(D) None of above
~
ii
CC G 9. Consider the given circuit. The parameters of
N-MOS are Vth = 1 V, k n = 0.4 mA/V 2 .
+ S
+ VDD = 16 Volts. Applied input voltage
Vi R3
R1 Rs Vo Vi = 2 sin(2t) + 1 sin(2 × 108 t). Then the
− − output voltage |Vo | is __________
Given rd = 50 kΩ.
(Assume that MOSFET is operating in
Zin Zo saturation region)
Given details +VDD
R 3 = 1 MΩ
R1 = 15 kΩ R s = 1 kΩ 3k
Cb = Cs = 500nF 2M
R 2 = 90 kΩ rd = 25 kΩ
μ = 135 Vo
NMOS
+ CC
Cb
6. The voltage gain AV = Vo /Vi is
(A) 0.839 (B) 0.769 Vi 2M 1k CS
(C) 0.525 (D) 0.422 _

7. The output impedance Zo for the amplifier is

(A) 0 Ω (B) 184 Ω
(C) ∞ (D) 16 Ω 10. A Enhancement NMOS transistor circuit is
shown in figure below

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 MOSFET
+ 5V Circuit ②
4V 4V 4V
Vout2
Vout2
+ C
2.6V −
Vo

VS + (A) 3.6 V, 3.2 V (B) 3.2 V, 3.6 V

−~ 200kΩ
1.2kΩ 2kΩ
(C) 4.0 V, 2.6 V (D) 2.6 V, 4 V

13. In the given circuit shown, all MOSFETs are

− 5V N-channel MOSFET. MOSFET M1 and M2 are
Transistor parameter are given as VTH = 1 V, matched and identical. Transistor M3 operates
k′n = 5 mA/V 2 . Then transconductance g m is in saturation and parameters are
(A) 5 mA/V (B) 3.33 mA/V
2
k n = 0.5 mA/V , Vth = 1 V. For MOSFET
(C) 11.25 mA/V (D) 6.81 mA/V M4 , k n = 0.5 mA/V 2 and Vth = 1.1 V. The
voltage across R L in volts is __________.
11. Consider the circuit shown below. The [Voltage across Zener is 3 V]
transistors have following parameters: +8V
μn Cox = 2.5, μp Cox = 20 μA/V 2
VTN = 1 V
VTP = −1V, λ = 0 M3
W 2mA 3.5kΩ Vo
=3 Vx
L +
The value of voltage V is __________Volts. M1 M2 M4 Vz
+3V R L = 5kΩ = 3V
−

14. In the amplifier circuit shown below, the

voltage applied at the input is Vi . The
V magnitude of voltage gain is _________ when
given parameters of transistor are
IDSS = 10 mA, VGSoff = −5 Volt, rd = 50 kΩ
+12V

5MΩ 1.5kΩ
12. In the circuits shown the threshold voltage of
each NMOS transistor is 0.4 Volts. Ignoring the C Vo
effect of channel length modulation and body
C
bias the values of Vout1 and Vout2 respectively, +
in volts are
5MΩ
Circuit ① Vi 1kΩ
4V CS

−
+
3V − Vout1
15. Following circuit is given below, determine
Vo
the magnitude of voltage gain ( ). Assume
+ Vin
2.6V − C
that both transistors are in saturation region
and channel length modulation effect is
included (where rd1 is drain to source

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 MOSFET
resistance of MOSFET M1 , rd2 is drain to 1.8V
source resistance of MOSFET M2 ) .
VDD 1kΩ

M2 (g m2 ) M1

Vin Vo
1V +
−

M1 (g m1 )
If transistor operates at the edge of saturation,
then parameter W/L is nearly equal to
Vo (A) 20 (B) 10
(A) = −(g m1 + g m2 )(rd1 ∥ rd2 )
Vin (C) 33 (D) 40
Vo
(B) | | = (g m1 + g m2 )(rd1 ∥ rd2 ) 18. A N-channel MOSFET amplifier circuit is
Vin
shown in figure below.
Vo g m (rd × rd2 ) + g m2 (rd1 × rd2 )
(C) | |= 1 1 20V
Vin rd1 + rd2
2.7kΩ
(D) Both (B)and (C)
420kΩ Vo
16. In the circuit shown below, both the
4kΩ
enhancement mode NMOS transistor have
k n = 1.5 mA/V 2 , output resistance (rds = ∞)
and no body bias. The minimum supply
voltage Vdd (in volts) needed to ensure that 180kΩ 2.7kΩ
transistor operates in saturation region and Vs +
−
the AC output voltage if input
Vs (t) = 2 sin(100πt) is applied respectively
+Vdd Transistor parameters are given as
IDSS = 12 mA, VP = −4 V, λ = 0.008 V −1 the
M2 (g m2 = 0.5mA/V)
small signal transconductance g m is
VT = 0.6V (A) 9.01 mA/V (B) 1.5 mA/V
Vx (C) 4.5 mA/V (D) 2.98 mA/V
M1 (g m1 = 0.5mA/V)
VT = 0.6V 19. The depletion MOSFET is shown in figure
VS (t) ~ +
−
3V below. Where VGS = 0.5 V, and ID = 9 mA,
Vp = −4 V, λ0 = 10 μS. The magnitude of
voltage gain of following circuit is
15V
(A) 3 V, − sin(100πt)
(B) 5.4 V, −2 sin(100πt)
(C) 3 V, −2 sin(100πt) 15kΩ
(D) 5.4 V, − sin(100πt) 60MΩ
Vo

17. In the given circuit of figure, transistor IDSS = 10 mA

Vi
parameters are given as
VTH = 0.4 V, μn Cox = 200 μA/V 2
20MΩ 150Ω

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 MOSFET
(A) 100 (B) 200
(C) 73.35 (D) 400

20. Consider the circuit shown below, the

transistor parameters are as follows:
W
VTH = 2 V, k n = 80 μA/V 2 , = 4
L
Drain current ID of the circuit is 0.5 mA and
1
the current in resistor R 2 is of ID .
10
The value of resistor R1 and R 2 are
respectively
+5V

ID 10kΩ
R1

R2 2kΩ

−5V
(A) 95.4 kΩ, 104.6 kΩ
(B) 142.3 kΩ, 57.7 kΩ
(C) 57.7 kΩ, 142. 3 kΩ
(D) 104.6 kΩ, 95.4 kΩ

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 MOSFET
7. [Ans. *]Range: 12.10 to 12.50
Answer keys and Solutions VGS 2 −2 − 0 2
ID = IDSS [1 − ] = 6 mA (1 − ]
VGS off −3
Level-1 2 2 1
= 6 mA (1 − ) = 6 mA × = 0.66 mA
3 9
1. [Ans. B] ∴ 15 − VD = ID × 4 k = 0.666 m × 4 k
FET is a voltage controlled device. = 2.66 V
∴ VD = 15 − 2.666 = 12.33 Volts
2. [Ans. A]
VGS → Gate to source voltage always negative 8. [Ans. *]Range: 5.0 to 5.0
VG = VS = ID × 5 kΩ
3. [Ans. C] VD = 5 V
At VDS = VP , then ID = IDSS [constant] VGS = 0 and
VTH = +2 V, AS VGS < VTh , channel does not form
4. [Ans. A] ID = 0 mA, VDS = 5 − Vs = 5 − 0 = 5 V
VG = 2V, Vs = 0.5 V, VD = 1 V
∴ VGS = 2 − 0.5 = 1.5 Volt 9. [Ans. A]
VDS = 1 − 0.5 = 0.5 Volt
Vth = 0.5 V 10. [Ans. A]
here VGS > VGS th and VDS < VGS − VGS th Only P is right.
= (1.5 − 0.5)
So, transistor works, in linear region. 11. [Ans. A]
Both very high
5. [Ans. B]
12. [Ans. B]
ID = k n (VGS − VGS th )2 ⋯①
∆ID VGS = +Ve means in enhancement mode.
and g m = = 2 k n (VGS − VGS th ) ⋯ ②
∆VGS
13. [Ans. C]
from ①,
VGS 2 VGS
ID ID = IDSS (1 − ) ⇒ 1−
VGS − VGS th = √ VGS off VGS off
kn
VGS ID
1− = √( )
ID VGS off IDSS
∴ g m = 2k n √ = 2√ID k n
kn −2IDSS VGS
gm = (1 − )
VGS off VGS off
1 W VGS
= 2 √ ID × μ C ( ) = g mo (1 − )
2 n ox L VGS off
W ID ID
∴ gm ∝ √ g m = g mo √ = 10 ms √ = 5 ms.
L IDSS 4ID
W
(√ )
L √3
W 14. [Ans. B]
g mnew L
= new
= = √3 Transistor will operate in
gm w W
i. Linear if |VGS | > |VGS th | and
√L √
L
|VDS | < |VGS | − |VGS th |
∴ g mnew = √3 g m ii. Saturation If |VGS | > |VGS th | and
|VDS | > |VGS | − |VGS th |
6. [Ans. *]Range: 40 to 40 iii. Cut-off if |VGS | < |VGS th |
rd = 40 kΩ here |VGS | = |0 − 1| = 1,
The relation between, g m , rd and μ is |VDS | = |1 − 0.3| = 0.7 V
μ 120 |Vth | = 0.4
μ = rd × g m ⇒ rd = = = 40 kΩ
g m 3 × 10−3 ∴ 0.7 > 1 − 0.4 and 1 > 0.4
So, saturation region

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 MOSFET
15. [Ans. *]Range: 1.9 to 2.5 W
= 0.1 × 0.36 mA ( )
The power dissipated in the transistor = VDS ID L
Given Vth = 2 V, k n = 0.4 mA/V 2 W
ID = 0.036 mA ( ) , At the edge of saturation
0.4 mA L
∴ ID = (10 − 10 ID − 2)2 VDS = VGS , Vth = 1 − 0.4 = 0.6
V2
= 0.4 mA (8 − 10 ID )2 Apply KVL in outer loop
= 0.4 mA (64 + 100 ID2 − 160 ID ) 3.6 × VDS × ID × 1 kΩ = 0
5ID = 2(100 ID2 − 160 ID + 64) ID = 3 mA
⇒ 200 ID2 − 320 ID + 128 − 5 ID = 0 W
= 83.33
⇒ 200 ID2 − 325 ID + 128 = 0 L
325 ± √(325)2 − 4 × 128 × 200
ID = 2. [Ans. C]
2 × 200
325 ± 56.789 Common drain amplifier is voltage buffer. So
= = 0.9544 mA, 0.6705 mA (B) is wrong.
400
∴ VS = 10 k × ID = 10 k × 0.6705 mA
= 6.705 Volts 3. [Ans. *]Range: 2.0 to 2.0
∴ Power dissipated = VDS × ID 10V
= (10 − 6.705) × 0.6705 mA
= 2.21 mW 2.5k
Iref I
Vx = 5V
16. [Ans. B]

17. [Ans. A]
1
For source follower circuit, ro = ( ∥ rd )
gm
1
ro = ( ∥ 50 kΩ) = (5 kΩ ∥ 50 kΩ)
0.2 mS The given circuit is current mirror
250 10 − 5
= k = 4.545 kΩ So, Iref = I = = 2 mA.
55 2.5 k

18. [Ans. C] 4. [Ans. *]Range: 2.0 to 2.0

In D-MOSFET, we can apply negative, 0 or The given circuit is current mirror with 3
positive voltage at gate terminal. matched MOSFETS.
So, D-MOSFET can work in both modes. 12V
I
19. [Ans. A] 2.5mA 2k
We can apply only −ve voltage at gate
terminal of JFET. So it can work in depletion
mode only. Vx
I2
I1
20. [Ans. B]
Operates in linear region if
VGS > VGS th and VDS < VGS − VGS th

Level-2

1. [Ans. *]Range: 83.1 to 83.5 So, Iref = 2.5 mA = I1 = I2

Given VG = 1 V, VS = 0V, VD = 3.6 − ID × 1 k Now, I = I1 + I2 = 5 mA
1 W μA W So,
Vth = 0.4 V, k n = μ Cox ( ) = 100 2 ( ) 12 − Vx
2 L v L = 5 mA
2
W 2 2 kΩ
∴ ID = 0.1 mA/V ( ) × (1 − 0.4)
L ⇒ Vx = 12 − 10 = 2 Volts

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 MOSFET
5. [Ans. *]Range: 11.5 to 12.1 mA
= 2 × 0.5 (8 − 2ID 1k − 1)
18V V2
(16 − 6kID − 2kID )
ID = (7 − 2ID )(16 − 8ID )
3k
= 112 − 88ID + 16ID2
16ID2 − 89ID + 112 = 0
R th 89 ± √(89)2 − 4 × 112 × 16
ID =
32
Vth + 1k 89 ± 27.44
− = = 3.63 mA, 1.92 mA
32
MOSFET is in linear region. So, ID = 1.92 mA
The given circuit can be written as ∴ VS = 1.92 mA × 2 k = 3.84 Volts.
11
Vth = 18 × = 4.5 V
33 + 11 7. [Ans. *]Range: 1.7 to 2.0
R th = (33k ∥ 11k) For M1
Given Vth = 1 V VG = 5 V, VS = Vo and VD = 10 V
1 W 0.4 mA
k n = μCox ∙ ( ) = VGS = 5 − Vo and VGS th = 1 V, k n = 0.4 mA/V 2
2 L V2 For M2
∴ ID = k n (VGS − VGS th )2
VG = 0.8 V, VS = 0 ⇒ VGS = 0.8 V
= 0.4 mA (4.5 − ID × 1 k − 1)2
VGS th = 1 V So, VGS < VGS th
2
⇒ ID = (3.5 − ID )2 M2 → is in cut-off
5
⇒ 5ID = 2(12.25 + ID2 − 7ID ) ∴ ID for M1 , ID = 0.4 m(5 − Vo − 1)2
= 24.5 + 2ID2 − 14ID − 5ID = 0.4 m (4 − Vo )2
⇒ 2ID2 − 19ID + 24.5 = 0 Where Vo = ID × 1 k
∴ ID = 0.4 m (4 − ID × 1 k)2
19 ± √(19)2 − 4 × 2 × 24.5
⇒ ID = = 0.4 (16 + ID2 − 8ID )
4
19 ± 12.845 ID = 6.4 + 0.4 ID2 − 3.2 ID
= ⇒ 0.4 ID2 − 4.2 ID + 6.4 = 0
4
= 7.9613 mA, 1.53875 mA 4.2 ± √(4.2)2 − 4 × 0.4 × 6.4
⇒ ID =
So, ID = 1.53875 mA 2 × 0.4
VS = 1.53875 mA × 1 k = 1.53875 Volts 4.2 ± 2.72029
= = 8.65 mA, 1.85 mA.
VD = 18 − 3 k × 1.53875 = 13.38375 Volts 0.8
∴ VDs = VD − VS = 13.38375 − 1.53875 ∴ ID = 1.85 mA
= 11.845 Volts. ∴ Vo = 1.85 mA × 1 k = 1.85 V
So, zener will not work
6. [Ans. *]Range: 3.5 to 4.1 ∴ Vo = 1.85 Volts
+16V
8. [Ans. A]
6k
9. [Ans. *]Range: 1.4 to 1.6

VS
5M
2k
Vth

The equivalent circuit is IE

5
Vth = 16 × =8V
5+5
VG = 8 V, VS = ID × 2 k ID
MOSFET operates in linear region. So,
ID = 2k n (VGS − VGS th )VDS

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 MOSFET
∆ID The parameters are given as:
Transconductance, g m =
∆VGS W
In the given figure, Vth = 1.7 V, μN Cox ( ) = 0.8 mA/V 2
L
IE = ID ID = 0.8 mA, VD = 1 V
For composite figure From the figure
∆IC ∆IC ∆ID
g ′m = = × VD = 5 − ID × R D
∆VGS ∆ID ∆VGS
∆IC ∆ID 1 = 5 − 0.8 mA × R D
= × R D = 5 kΩ
∆IE ∆VGS
β Since MOSFET is in saturation region.
=( ) × gm W
β+1 μn Cox
L
199 mA So, ID = [VGS − VTH ]2 ⋯ ①
=( ) × 1.5 2
200 V
As from figure
= 1.4925 mA/V
[VGS = 5 − ID R S = 5 − 0.8 mA × R S ]
10. [Ans. *]Range: 1.8 to 2.2 From equation ①
5V 0.8 mA
0.8 mA = [5 − 0.8 mA × R S − 1.7]2
2
[3.3 − 0.8 mA × R S ]2 = 2
Take square root both sides
3.3 − 0.8 mA × R S = √2
Vo = 3 3.3 − 0.8 mA × R S = ±1.414
Take +Ve value 3.3 − 0.8 mA × R S = 1.414
2V
M2 R S = 2.35 kΩ

12. [Ans. B]
M2
For dc analysis, we redraw the given circuit as
VDS = 3, VGS = 2, VT = 0.8
VDS ≥ VGS − VT 5V +5V
3 ≥ 2 − 0.8 satisfies,
so, M2 operates in saturation region. 7kΩ ID
1 W 2
ID 2 = × μn Cox ( ) (VGS 2 − VT ) ⋯ ① VD
2 L 2 VG +
1 VDS
ID 2 = × 40 μ × 2(2 − 0.8)2 = 57.6 μA +
2 −Vo = 3
VGS − VS
1 W 2 20kΩ
ID1 = × μn Cox ( ) (VGS1 − VT )
2 L 1
1 W M2 0.5mA ID
57.6 μ = × 40 μ ( ) (2 − 0.8)2
2 L 1
W −5V
( ) =2
L 1 From the circuit, we have
Drain current ID = 0.5 mA
11. [Ans. B]
Gate voltage, VG = 0
+5V
So, we obtain the source voltage as
R D ID VS = VG − VGS = −VGS
VD Assume the MOSFET is operating in
saturation, so, the drain current is given by
2
IDQ = k n (VGSQ − VTN )
RS ID 2
50k or 0.5 = 1(VGSQ − 0.8)
or VGSQ = 1.51 V = −VS
−5V So, we obtain

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 MOSFET
VDSQ = 5 − (0.5m)(7k) + 1.51 = 3.01 V VDD
Therefore, we conclude that
VDS ≥ VGS − VTN 8kΩ
So, MOSFET is in saturation region (our ID
VD
assumption is correct). Also, we have IG = 0
VG +
λ=0
VDS
So, ro = ∞ + −
Therefore, we draw the small signal model of 50kΩ VGS − VS
given circuit as 100Ω
G D ID
Vo 250Ω
+

Vs +
~ 20k Vgs g m Vgs 7kΩ
− From the circuit, we have
− S Gate voltage, VG = 0
Source voltage,
VS = VG − VGS = −VGS
From the circuit, we have
Drain current
Output voltage, Vo = −g m Vgs (7k) VS − 0 VGS
ID = =−
At the input, Vgs = Vi 350 350
The current equation in MOSFET is given by
So, the voltage gain is
VGS 2
Vo ID = IDSS (1 − )
Av = = −g m (7k) ⋯ ① VP
Vs
VGS VGS 2
Also, we have the transconductance or − = IDSS (1 − )
350 VP
g m = 2k n (VGS − VTN ) 2
or 0.175 VGS + 1.7 VGS + 0.7 = 0
= 2(1m)(1.51 − 0.8) So, VGS = −0.431, −9.251
= 1.42 mS For VGS = −0.431, we have
Substituting it in equation ①, we get VGS > VP
i.e., MOSFET is ON. So, we obtain the
Av = −(1.42)(7k)
transconductance as
= −9.9 2IDSS VGS
gm = (1 − )
|VP | VP
13. [Ans. D] 2×2 −0.431
As we know = (1 − )
2 −2
VGS 2 = 1.57 mA/V
ID = IDSS (1 − )
VP
∂ID −2IDSS VGS 15. [Ans. *]Range: 2.15 TO 2.30
gm = = [1 − ]
∂VGS VP VP 22.5V
−2 × 6.8m 0.4
gm = [1 + ]
−3.5 3.5
g m = 4.33 mA/V = 4.33 mS RD

14. [Ans. A] R th
Given the transistor parameters,
IDSS = 2 mA, VP = −2, λ = 0
For dc analysis, we redraw the circuit as VS

VG = Vth RS

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 MOSFET
7 Given VGS off = −3.5 Volts.
Vth = 22.5 V × = 10.5 V
8+7 IDSS = 18 mA
R th = (8 M ∥ 7 M) VGS 2
Given, VS = +5 V and ID = IDSS (1 − )
VGS off
1 0 − VS 2
ID = (VGS − 1)2 mA = 18 mA (1 − )
2 −3.5
2
1 VS
= (10.5 − 5 − 1)2 = 2.25 mA = 18 mA (1 − )
2 3.5
∴ VS = ID × R S ID = 1.46938 (3.5 − VS )2 (mA)
8 mA
VS 5 = (3.5 − VS )2
⇒ RS = = = 2.222 kΩ 1.46938 mA
ID 2.25 mA
2.333 = 3.5 − VS
16. [Ans. *]Range: 2.0 to 2.0 VS = 1.1666 Volts.
+8V VD = 15 − 8 mA × 0.8 kΩ
= 8.6 Volts
1k ∴ VDS = VD − VS = 8.6 Volts − 1.166 Volts
= 7.4334 Volts

R th 19. [Ans. *]Range: 10.9 to 11.1

VS
Vth Given VG = 0 Volts, Vs = 0
1k VGS 2
ID = IDSS [1 − ]
VGS off
VS = ID × 1k 0−0 2
5M = 12 mA [1 − ] = 12 mA
Vth = 8 × = 5 Volts VGS off
5M + 3M ∴ VD = 18 − 620 × 12 mA
R th = (5M ∥ 3M) = 10.56 Volts
Given k ′ n = 0.5 mA⁄V 2 ∴ VDS = VD − VS = 10.56 Volts.
VTH = 1 V
∴ ID = k ′ n(VGS − VGS th )2 20. [Ans. D]
0.5 mA Equivalent ac circuit is as follows
= (5 − ID × 1 k − 1)2
V2 rd
ID = 0.5(4 − ID )2
g m Vgs
⇒ 2ID = 16 + ID2 − 8ID ⇒ ID2 − 10ID + 16 = 0 S Vo
ID2 − 8ID − 2ID + 16 = 0 +
(ID − 8)(ID − 2) = 0 ⇒ ID = 8 mA, 2 mA Vi RD = RL
As MOSFET works in saturation ID = 2 mA −
G
17. [Ans. C] D R
Vo g m R D + rd
=
18. [Ans. *]Range: 7.0 to 7.8 Vi R
[1 + D ]
rd
+15V
RL
Vo g m R L + rd
0.8kΩ = R = 27.37
Vi 1+ L
rd

VS Level-3
8mA
1. [Ans. A]
For dc analysis, we draw the equivalent circuit as
−15V

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 MOSFET
+10V 2. [Ans. D]
I D1 For dc analysis, we draw the equivalent circuit as
VD1
+5V +5V
M1
VG1 VS1
V1 I D2 ID1 ID2
VD2 40kΩ 40kΩ
M2 IG1 = 0 V1 V2 IG2 = 0
VG2 VS2
V2 I D3
M1 M2
VD3
M3
VG3 ID1 ID2
VS3
V3
Since, VTN = 1 V. so, each MOSFET is
200μA
N-channel enhancement type. In each
MOSFET, drain and gate are shorted, i.e.
VD = VG In both MOSFETs, gate voltage is VG = 0.
or VDS = VGS since, both MOSFETs are identical, so we have
or VDS > VGS − VTN ID1 = ID2
So, we conclude that each MOSFET is in Applying KCL at node V3 , We have
saturation. The drain current for the MOSFET ID1 + ID2 = 200 μA
is defined as 200
ID = k n (VGS − VTN )2 or ID1 = ID2 = = 100 μA
2
Since, we have In M1 , Voltage at drain terminal is obtained as
ID = 0.5 mA, V1 = 5 V, V2 = 2 V V1 = 5 − 40 k × ID1
So, VG1S1 = VG1 − VS1 = 5 − 40 k × 100 μ
= VD1 − V1 =1V
= 10 − 5 = 5 V Similarly, for M2 , we obtain
Therefore, we have V2 = 5 − 40 k × ID2 = 1 V
ID = k n1 (VG1S1 − VTN1 )2 Assume that MOSFET is in saturation, so we
W1 have
or 0.5 m = 36 μ (5 − 1)2
2L1 VD1 = V1 = 1 V
W VG1 = 0 V
or ( ) = 1.75
L 1 VS1 = V3
Similarly, for M2 , we obtain VGS1 = 0 − V3
VG2S2 = VG2 − VS2 The drain current for saturation region is
= V1 − V2 = 5 − 2 = 3 V defined as
So, ID = k n2 (VG2S2 − VTN )2 W
ID1 = k ′n ( ) (VGS1 − VTH1 )2
W2 2L 1
or 0.5 m = 36 μ × (3 − 1)2 Substituting the given values,
2L2
W 20
or ( ) = 6.94 100 μ = 100 μ (−V3 − VTH1 )2
L 2 2
Again, for M3 , we have or (−V3 − 1)2 = 1/10
VG3S3 = VG3 − VS3 or −V3 − 1 = 0.32
= V2 − 0 = 2 or V3 = −1.32 V
So, ID = k n3 (VG3S3 − VTN )2 Thus, VDS > VGS − VTH
W3 i.e. MOSFET in saturation (our assumption is
or 0.5 m = 36 μ × (2 − 1)2 true). Hence the obtained value of V3 is valid.
2 L3
W i.e.
or ( ) = 27.8 V3 = −1.32
L 3

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 MOSFET
3. [Ans. *]Range: 1.4 to 1.6 VGS = 2.63V, −1.13 V
For dc analysis, we have the circuit VGS = 2.63 Volt
+5V ID = (8 − 2.63)0.5 mA = 2.685 mA
Transconductance
g m = k n (VGS − VT )
50μA ID = 2(2.63 − 1) = 3.26 m℧
According to small signal analysis
VD G D
+
VDS + +
VG + − 20M
VGS − V = 0V 4kΩ
Vi VGS g m VGS
S 3

Given the threshold voltage, − −

VTN = 1.2 V S S
So, this is n-channel enhancement type Vo
∴ AV = = −g m (2kΩ ∥ 12kΩ)
MOSFET. In the circuit, drain and gate Vi
Vo
terminals are shorted, i.e. AV = = −3.26 m℧(1.71kΩ) = −5.58
VD = VG Vi
or VDS = VGS
or VDS > VGS − VTN 5. [Ans. C]
So, it is in saturation region. Therefore, the Apply DC Analysis
drain current is given as 10V
ID = k n (VGS − VTN )2
or 50 μ = 0.5 (VGS − 1.2)2 2kΩ
For n-channel enhancement type MOSFET, VGS V +
is positive, so, we get − SG +
VDS = VGS = 1.52 V VSD
−
4. [Ans. D] 500kΩ
Apply DC Analysis:
2.2kΩ
12V

2kΩ −10V 
10MΩ
From the figure: VSG = 10 − 2ID
10 − VSG
ID = ⋯①
2
For P MOSFET
20MΩ 2kΩ
kP
ID = [V − |VT |]2
2 SG
20MΩ × 12 20 × 12 10 − VSG 4
VG = = =8V ( ) = [VSG − 1.5]2
20MΩ + 10MΩ 30 2 2
VGS = VG − VS = 8 − ID × 2 kΩ 2
10 − VSG = 4[VSG + 2.25 − 3VSG ]
ID = (8 − VGS )0.5 mA VSG = 2.83 Volt, −0.08 Volt
Assume that MOSFET operates in saturation
VSG > |VT |, VSG = 2.83 Volt
region.
kn From equation ①
ID = (VGS − VT )2
2 10 − VSG 10 − 2.83
2 ID = = = 3.505 mA
(8 − VGS )0.5 = (VGS − 1)2 2 2
2 g m = k P [VSG − |VT |]
2
4 − 0.5VGS = VGS + 1 − 2VGS
2 g m = 4 mA/V 2 [2.83 − 1.5] = 5.32 m℧
VGS − 1.5VGS − 3 = 0

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 MOSFET
In the equation λ = 0, rd = ∞ Vo
= −g m1 g m4 (rd1 ∥ rd2 )(rd3 ∥ rd4 )
G D Vin
−
9. [Ans. *]Range: 6.9 to 7.1
Vi ~ 500k VGS g m VGS 2.2k
Vi (t) = 2 sin(2t) + 1 sin(2 × 108 t)
For ω1 = 2 r/sec
+
S S 1 1
Xc = = = 106 very high
AV = −g m × 2.2 kΩ = − 5.32 m℧ × 2.2kΩ ωC 2 × 500 × 10−9
= −11.7 This components of input is blocked by
|AV | = |−11.7| = 11.7 capacitor
For ω2 = 2 × 108 ,
6. [Ans. A] 1
XC = ≈ 0.01
+ VGS − 2 × 108 × 500 × 10−9
G S So, this component will be allowed by the
Io = −ID capacitor
Now the given amplifier is common source so
RG g m VGS RS rd
the voltage gain AV = −g m (rd ∥ R D )
ID = k n (VGS − VGS th )2
D D = 0.4 mA (8 − ID × 1k − 1)2
Where R G = R1 ∥ R 2 ID = 0.4 mA (7 − ID )2
μR S ID = 0.4 (49 + ID2 − 14 ID )
AV =
(μ + 1)R S + rd = 0.4 ID2 − 6.6 ID + 19.6 = 0
135 × 1 6.6 ± √(6.6)2 − 4 × 0.4 × 19.6
= = 0.839 ID =
136 × 1 + 25 0.8
6.6 ± 3.4928
= 3.88 mA, 12.6225 mA
7. [Ans. B] 0.8
rd 25 × 103 So, ID = 3.88 mA.
Zo = = ∴ ID = k n (VGS − VGS th )2
μ+1 136
= 184 Ω dID
= k n 2 (VGs − VGS th )
dVGS
8. [Ans. A] g m = 2 k n (VGS − VGS th )
In the above circuit the ac gate source voltages = 2 × 0.4 mA (8 − 3.88 − 1)
here of M2 and M3 are zero. It is significant = 0.8 (8 − 4.88) mA/V
that because the gate of a MOSFET has infinite = 2.496 mA/V
impedance, the second stage of amplifier does G D
+
not load the first stage, unlike bipolar
transistor amplifier circuits. The small signal Vi ~ 1M VGS g m VGS 3k 50k
model of circuit is given as:
−
S
rd2 rd4
G4 g m4 Vg 4 ∴ AV = −2.496 × (50k ∥ 3k)
G1 = −7.0641
Vg Vo
4 Vo
+ V rd1 rd3 ∴ AV = = −7.0641
in g m1 Vin Vi
−
∴ Vo = −7.0641 × Vi
= −7.0641 × 1 = −7.0641 Volts
∴ |Vo | = 7.0641 Volts
Vg = −g m1 (rd1 ∥ rd 2 ) Vin ⋯ ①
4
10. [Ans. C]
and Vo = −g m 4 (rd3 ∥ rd 4 ) Vg ⋯②
4 Apply DC Analysis
From equation ① and ②,

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 MOSFET
+5V Since, drain and gate are shorted, so we
conclude that both MOSFETs are in saturation.
Therefore, we obtain
VSGp = 3 − V
and VGSn = V − 0 = V
For the MOSFETs operating in saturation, we
200kΩ 1.2kΩ have
ID1 = ID2
ID
1 Wn
or (μn ∙ Cox ) (V − VTH )2
2 Ln GS
1 Wp
−5V = μp Cox (V + VTH )2
2 Lp SG
VG = 0 V 1 Wn
k ′n or μn Cox (V − 1)2
Current ID = (V − VT )2 2 Ln
2 GS 1 Wp
From the figure VS = 5 − ID × 1.2 kΩ = μp Cox [3 − V + (−1)]2
2 Lp
VGS = −VS = ID × 1.2 kΩ − 5
or 2.5 (V − 1)2 = (2 − V)2
ID = (5 + VGS )0.833 mA ⋯ ① or 1.58 (V − 1) = 2 − V
5mA
(5 + VGS )0.833 = (VGS − 1)2 or 2.58 V = 2 + 1.58
2 So, V = 1.39 V
(10 + 2VGS )mA
= 5mA(VGS − 1)2
1.2
10 + 2VGS = 6(VGS 2
+ 1.2VGS ) 12. [Ans. B]
2
= 6VGS + 6 − 12VGS For circuit ①
2
6VGS − 14VGS − 4 = 0 4V
VGS = 2.6 V, −0.25V I D1
5 + VGS VG2
VGS = 2.6 V, ID = ( ) mA M1
1.2 +
5 + 2.6 3V − ID2
=( ) mA = 6.33 mA M2
1.2 +
g m = 2√k n ID − 2.6V
g m = 2√5mA × 6.33 mA
g m = 11.25 mA/V VG1 = 4 V
VS1 = VG2 (Let)
11. [Ans. *]Range: 1.35 to 1.45 and, VD1 = 3 V
For dc analysis, we redraw the circuit as Now, current into gate terminal of M2 = 0
+3V 2
∴ ID1 = 0 = k n (4 − VG2 − 0.4)
Vs = 3V ∴ VG2 = 3.6 Volts
I Now for DC, C → open circuit, So, ID2 = 0
VG = V
ID1 ← P-MOSFET 2
∴ ID2 = 0 = k n (VG2 − VS2 − 0.4)
VDP = Vn = V ∴ (3.6 − Vout1 − 0.4)2 = 0
v V
⇒ Vout1 = 3.2 Volts.
I D2
For circuit ②
← N-MOSFET 4V 4V 4V
VG = V
Vout2
Vs = 0 M1 M2 M3
+ C
2.6V −
For both the MOSFETs in circuit, we have
VG = VD = V For DC,
C → open circuit ID3 = 0

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 MOSFET
∴ ID3 = 0 = k n (4 − Vout2 − 0.4)2 = 0 VGS 2
ID = 10 (1 + ) ⋯①
Vout2 = 3.6 Volts 5
Apply DC Analysis
13. [Ans. *]Range: 3 to 3 +12V

2mA
3.5k I = 2mA
1.5kΩ
5MΩ

5MΩ ID
1kΩ

Stage I 12 × 5M
VG = = 6V
The given circuit is current mirror. 10M
So, I = 2 mA VG − VGS − ID × 1 kΩ = 0
8 − Vx
Now = 2 mA VGS = 6 − ID × 1 kΩ
3.5 k
⇒ Vx = 1 V Put the value of VGS in equation ①
The gate voltage at M4 = 1 V and VS for
6 − ID × 1kΩ 2
M4 = 0 ID = 10 (1 + )
5
∴ VGS for M4 = 1 V but VGS th = 1.1
So, M4 is in cut-off 11 − ID 2
ID = 10 ( )
Now M3 is in saturation so, 5
ID = k n (VGS − VGS th )2 ID = 17.6 mA, 6.9 mA
0.5 mA ID = 6.9 mA (Because ID should be less
= (8 − ID × 5 k − 1)2 than IDSS )
V2
−2IDSS VGS
2ID = (7 − 5ID )2 = 49 + 25ID2 − 70ID gm = [1 − ]
VGS (off) VGS off
⇒ 25 ID2 − 72ID + 49 = 0
VGS = 6 − ID × 1kΩ
+72 ± √(72)2 − 4 × 25 × 49 [ ]
ID = VGS = 6 − 6.9 mA × 1kΩ = −0.9 V
50
72 ± 16.8522 −2 × 10mA −0.9
= mA gm = [1 − ]
50 −5 −5
= 1.77 mA, 1.1029 mA g m = 4 mA/V[1 − 0.18] = 3.28 mA/V
∴ ID = 1.1029 mA G D
+
∴ M4 is in cut-off. So, Vo = 1.1029 × 5 = 5.5 V
But due to zener, the output will saturate at 3
Volts
Vi ~ 2.5M VGS
g m VGS
rd 1.5k

∴ Vo = 3 V −
S
S
14. [Ans. *]Range: 4.65 to 4.95
|AV | = g m (rd ∥ R D ) = 3.28 mA/V (50k ∥ 1.5k)
This is depletion type NMOS transistor
|AV | = 4.77
The current equation
VGS 2
ID = IDSS (1 − ) 15. [Ans. D]
VGS off
Small signal model of following circuit is given
VGS 2 below.
ID = 10 (1 − )
−5

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 MOSFET
AC Analysis:
ID
g m2 Vgs2 rd2 + +
G1 , G2 Vo 1
Vs (t) +
− VGS g m2
+ V g m1 VGS
− in g m1 Vgs1 rd1
− −
Given rds = ∞(0.1)
S1 , S2 1 1
Apply KCL at output node (Vo ): Vo = −ID × = −ID × = −2000 ID
g m2 0.5 mA/V
Vo Vo
g m1 Vgs1 + g m2 Vgs1 + + =0 Vo −2000 ID
rd1 rd2 and AV = =
Vgs Vgs
[From figure Vgs1 = Vgs2 = Vin ] ID
Vo Vo ID = g m1 Vgs = = g m1
g m1 Vin + g m2 Vin + + =0 Vgs
rd 1 rd2 AV = −2000 × g m1 = −2000 × 0.5 mA/V
Vo AV = −1 V
= −(g m1 + g m2 )(rd1 ∥ rd2 )
Vin Vo
Vo = −1
Vs
| | = (g m1 + g m2 )(rd1 ∥ rd2 )
Vin Vo = −1 × 2 sin(100πt)
Vo g m (rd × rd2 ) + g m2 (rd1 × rd2 ) Vo = −2 sin(100πt)
(or) | | = 1 1
Vin rd1 + rd2
So, correct answer is (D). 17. [Ans. C]
For dc analysis, we draw the circuit as
16. [Ans. B] 1.8V
Apply DC Analysis:
+Vdd 1kΩ
ID1 + ID
VG = 1V
M2 VDS
Vx −
VS = 0
ID 2
1V + Loop
M1 −

3V Given the MOSFET parameters,

VTH = 0.4 V
μn Cox = 200 μA/V 2
I D1 = I D2
From the circuit, we have
k n (Vdd − Vx − 0.6)2 = k n (3 − 0 − 0.6)2 Gate voltage,
Vdd − Vx − 0.6 = 2.4 VG = 1 V
Vdd − Vx = 3 V Source voltage,
M1 is in saturation: VS = 0 V
Vx − 0 ≥ (3.0) − 0.6 So, gate to source voltage is
VGS = 1 − 0 = 1 V
Vx ≥ 2.4 V
Since the n-channel MOSFET operates at the
Now Vdd = 3 + Vx
edge of saturation, so we have
= 3 + 2.4 VDS = VGS − VTH
Vdd = 5.4 = 1 − 0.4 = 0.6 V
Minimum supply voltage (Vdd = 5.4 V) to Applying KVL in drain to source loop, we have
operate transistor is in saturation region. 1.8 − 1 k × ID − VDs = 0

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 MOSFET
or g m = 6 mA(0.495)(1.032)
1.8 − VDS 1.8 − 0.6 g m = 3.06 mA/V
ID = =
1k 1 kΩ
= 1.2 mA 19. [Ans. C]
Since, saturation current in MOSFET is given 2IDSS VGS
by gm = − (1 − )
VP VP
ID = k n (VGS − VTH )2
−2 × 10mA 0.5
1 W gm = (1 + ) = 5.625 mA/V
= μn Cox (VGS − VTH )2 −4 4
2 L
Substituting the obtained values in above G
expression, we have + +
1 W
1.2 m = × 200 μ × (1 − 0.4)2 15MΩ VGS ro 15kΩ Vo
2 L g m VGS
W 1.2 m × 2
So, = − −
L 200 μ × 0.6 × 0.6
= 33 S
1
AV = −g m (ro ∥ R D ), [ro == 0.1 MΩ]
18. [Ans. D] 10μs
VGS 2 AV = −5.625(0.1 MΩ ∥ 15 kΩ)
ID = IDSS (1 − ) (1 + λVDS ) AV = −5.625 mA/V(13.04 kΩ)
VP
VGS 2 AV = −73.35
ID = 12 (1 − ) (1 + 125 VDS ) |AV | = 73.35
−4
VGS 2
ID = 12 (1 + ) (1 + 125 VDs ) ⋯ ① 20. [Ans. D]
4
+5V
20 × 180 k
VG = =6V
180 k + 420 k
6 − VGS − ID × 2.7 kΩ = 0 10k
VGS = 6 − ID × 2.7 kΩ
Apply KVL in input loop
VDS = 20 − ID (2.7 + 2.7 )k
(R1 ∥ R 2 )
VDS = 20 − 5.4ID kΩ
Put the value of VGS and VDS in equation ① −5R1 + 5R 2
6 − 2.7 ID 2 2k
R1 + R 2
ID = 12 [1 + ] [1 + 0.008(20 − 5.4ID ]
4
ID = 0.75[10 − 2.7 ID ]2 [1 + 0.16 − 0.0432 ID ] −5V
ID = 0.75[100 + 7.29 ID2 − 54 ID ][1.16 80 μA W
− 0.0432 ID ] VTH = 2V, k n = , =4
V2 L
ID = 87 + 6.34 ID2 − 46.98 ID − 3.24 ID 1 80 μA
∴ k ′n = × ×4
− 0.237 ID3 + 1.75 I 2 D 2 V2
ID = 0.237 ID3 + 8.09 ID2 − 50.22 ID + 87 μA
= 160 2
−0.237 ID3 + 8.09 ID2 − 51.22 ID + 87 = 0 V
ID = 0.5 mA [Given]
ID = 26.50 mA, 2.97 mA, 4.65 mA
Take lower value ID = 2.97 mA ∴ I = Current through R 2 and R1 .
VDS = 20 − 5.4 × 2.97 = 3.96 10 1 10 1
= ID = = × 0.5 mA
R1 + R 2 10 R1 + R 2 10
VGS = 6 − 2.7 ID = 6 − 2.7 × 2.97 = −2.019 V
∴ R1 + R 2 = 200 kΩ
2ID −2IDSS VGS
gm = = (1 − ) (1 + 0.008 VDS ) ID = 0.5 mA
2VGS VP VP
−2 × 12mA 2.019 1 μA
gm = (1 − ) (1 + 0.008 × 3.96) = × 80 2 × 4 (VG − 2 k × 0.5 mA − 2 + 5)2
−4 4 2 V

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 MOSFET
0.5
⇒ = (VG + 2)2
0.16

50
⇒ VG + 2 = √ = 1.7677
16
∴ VG = −0.2322 Volts.
1
−5 + ID × × R 2 = −0.2322
10
1
⇒ ID × × R 2 = 4.7678
10
4.7678
R2 = = 95.356 kΩ
0.05 mA
∴ R1 = 200 − 95.356 kΩ
= 104.6 kΩ

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