UNIVERSIDAD DE GUAYAQUIL

FACULTAD DE CIENCIAS MATEMÁTICAS Y FÍSICAS

CARRERA DE INGENIERÍA EN NETWORKING Y TELECOMUNICACIONES

ASIGNATURA:
LABORATORIO DE ELECTRONICA DIGITAL

TEMA:
CIRCUITO COMBINACIONAL Y TEST BENCH

DOCENTE:
ING. JUAN CARLOS ITURRALDE
INTEGRANTES:
DAVID AGUILAR PAZMIÑO
ENZO BANCHON FRANCO
DAANNY IDROVO
KAREN PLÚAS
LEONELA RODRIGUEZ
EDUARDO CASTILLO

GRUPO:
7

CICLO I 2020-2021
 Laboratorio#6

1. Realice la programación del siguiente circuito utilizando las señales (signal) Y0, Y1 y Y2. (EDA
PLAYGROUND

-- Code your design here

library IEEE;
use IEEE.std_logic_1164.all;
entity Ejercicio1 is port (F,S,V,L : in std_logic; salida : out std_logic);
end Ejercicio1;
architecture operacion of Ejercicio1 is
begin
process (F,S,V,L) begin
salida <= ((not F and S) or (not S and V) or L);
end process;
end operacion;
--------------------------------------------------------------------------------------
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity Simulacion is end Simulacion;
architecture s of Simulacion is component Ejercicio1
port (F,S,V,L : in std_logic; salida : out std_logic);
end component;
signal F_s,S_s,V_s,L_s : std_logic:= '0';
signal salida_s : std_logic;
begin
U0: Ejercicio1 port map(
F => F_s,
S => S_s,
V => V_s,
L => L_s,
salida => salida_s
 );
process begin
F_s <= '0';
S_s <= '0';
V_s <= '0';
L_s <= '0';
wait for 50 ns;
F_s <= '0';
S_s <= '0';
V_s <= '0';
L_s <= '1';
wait for 50 ns;
F_s <= '0';
S_s <= '0';
V_s <= '1';
L_s <= '0';
wait for 50 ns;
F_s <= '0';
S_s <= '0';
V_s <= '1';
L_s <= '1';
wait for 50 ns;
F_s <= '0';
S_s <= '1';
V_s <= '0';
L_s <= '0';
wait for 50 ns;
F_s <= '0';
S_s <= '1';
V_s <= '0';
L_s <= '1';
wait for 50 ns;
F_s <= '0';
S_s <= '1';
V_s <= '1';
L_s <= '0';
wait for 50 ns;
F_s <= '0';
S_s <= '1';
V_s <= '1';
L_s <= '1';
wait for 50 ns;
F_s <= '1';
S_s <= '0';
 V_s <= '0';
L_s <= '0';
wait for 50 ns;
F_s <= '1';
S_s <= '0';
V_s <= '0';
L_s <= '1';
wait for 50 ns;
F_s <= '1';
S_s <= '0';
V_s <= '1';
L_s <= '0';
wait for 50 ns;
F_s <= '1';
S_s <= '0';
V_s <= '1';
L_s <= '1';
wait for 50 ns;
F_s <= '1';
S_s <= '1';
V_s <= '0';
L_s <= '0';
wait for 50 ns;
F_s <= '1';
S_s <= '1';
V_s <= '0';
L_s <= '1';
wait for 50 ns;
F_s <= '1';
S_s <= '1';
V_s <= '1';
L_s <= '0';
wait for 50 ns;
F_s <= '1';
S_s <= '1';
V_s <= '1';
L_s <= '1';
wait for 50 ns;
wait;
end process;
end s;
2. Utilizando señales en su código de programación y mediante el concepto de asignación
directa, encuentre las ecuaciones lógicas de las salidas X,Y y Z.(EDA PLAY GROUND).

 Para hallar las salidas.

AB (00) (01) (11) (10)

C (0) 1 1 0 1

(1) 0 1 0 0

ECUACION DE X

X= Á B+ B́ Ć
 Salida de Y

AB (00) (01) (11) (10)

C (0) 1 1 1 0
 (1) 0 1 1 1

ECUACIÓN DE Y
Y=B+ Á Ć +AC

 Salida para z

AB (00) (01) (11) (10)

C (0) 0 1 0 0

(1) 0 1 0 0

Ecuación para z= Á B // no se realiza simplificación por que perdemos una entrada

Ecuación para z = Á BĆ + Á BC

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Ejercisio2 is
Port ( A,B,C : in STD_LOGIC;
X,Y,Z : out STD_LOGIC

);
end Ejercisio2;

architecture operacion of Ejercisio2 is

-- COMPONENTS
-- SIGNALS
signal Y0,Y1,Y2,Y3,Y4,Y5 : STD_LOGIC;
begin
-- DISEÑO
Y0 <= (NOT A AND B);
Y1 <= (NOT B AND NOT C);
Y2 <= (NOT A AND NOT C);
Y3 <= (A AND C);
Y4 <= ((NOT A AND NOT C) AND B);
Y5 <= ((NOT A AND B)AND C );
X <= (Y0 OR Y1);
Y <= (Y2 OR Y3);
Z <= (Y4 OR Y5);
end operacion;
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity Simulacion is end Simulacion;

architecture s of Simulacion is component Ejercisio2

Port ( A,B,C : in STD_LOGIC;
X,Y,Z : out STD_LOGIC
);
end component;

-- Señales de las entradas

signal A_s,B_s,C_s: STD_LOGIC:= '0';

-- Señales de salidas
signal X_s,Y_s,Z_s : STD_LOGIC;

begin

UO: Ejercisio2 Port map (

A => A_s,
B => B_s,
C => C_s,
X => X_s,
Y => Y_s,
Z => Z_s
);

process begin
--- Estímulos de la simulación wait for 100 ns;

A_s <= '0';

B_s <= '0';
C_s <= '0';
wait for 100 ns;
A_s <= '0';
B_s <= '0';
C_s <= '1';
wait for 100 ns;
A_s <= '0';
B_s <= '1';
C_s <= '0';
wait for 100 ns;
A_s <= '0';
B_s <= '1';
C_s <= '1';
wait for 100 ns;
A_s <= '1';
B_s <= '0';
C_s <= '0';
wait for 100 ns;
A_s <= '1';
B_s <= '0';
C_s <= '1';
wait for 100 ns;
A_s <= '1';
B_s <= '1';
C_s <= '0';
wait for 100 ns;
A_s <= '1';
B_s <= '1';
C_s <= '1';
wait for 100 ns;
wait;
end process;
end s;
3. Escriba el código en VHDL de un sumador completo (USE COMPUERTAS LOGICAS).

X1

AC Cin Cout S
000 00
001 01
X2 010 01
011 10
X3 100 01
X4 101 10
110 10
111 11

Library ieee;
Entity Sumador is
Port ( a, b, co: in bit ;s , cout : out bit);
End sumador;
Architecture caso1 of sumador is
Begin
Process(a,b,cin)[poner las entradas]
Begin
If( a='1' and b='1' or
a='1' and co='1' or
b='1' and co='1')
Then cout <='1' ;
Else cout <='0';
End if;
If ( a='0' and b='0' and c='1' or
a='0' and b='1' and c='0' or
a='1' and b='0' and c='0' or
a='1' and b='1' and c='1')
Then s<='1';
Else s<='0';
End if;
End process;
End caso1;