39O PROCESSOR LOGIC DESIGN cH.

9
SEC.9-r0 DESIGNOFACCUMULATOR 39'
prooessors, it is customary not to change the value of carry bil C after an increment
The sequcncc of control words for the-system is stored in a control
or decrement operation as well. memory.
The outrrut of the control memory is appliid to the selectioo u"ribr",
If we want to piace the contents of a register into the shilter without changing processor. By reading consecutive control words from
of the
the carry bit, we can use the OR logic operation with the same register selected for mcmory, it is possible io
sequence the microoperations in the processor. Thus, the
both ALU inputs,{ and ,B. The operation: entire i!.rgo.i" u" aor.
by g.egns oI the register-transfer meitrod which, in this particulu.
il
il", is referred
R<-R[.R :! to es the microprogramming method. This mcthod of controlling
th, p;.;;;;t
:.1
is demonstrated in Section l0-5.
does.not change the value of register R. However, it does place the coutents of R ;i
into the inputs of the shifter, and it does not change the values of status bits C and
V.
i;
.l:
,li
9.10 DESIGN OF ACCUMUI-ATOR
The examples in Table 9-9 discussed thus far use the shift-select code 000 for i:,

the I/ field to indicate a no-shift operation. To shift the contents of a register, the Some processor units distinguish one register from all others and call
,1,
an it
ll;
value bf the register must be placed into the shifter without any change through the 'tr'
accumulator register. The organization of a processor unit with an accumulator
ALU. The shiftJeft microoPeration statement: . rti
ragister is shown in Fig. 9:4. The ALU asiociated with the register
;r;;
lil constructcd as a combinational
n,
circuit of the type discussed in Secti6n 9-5. In this
R3 eshl R3
''ti,
configuration, the accumulator register is essintiaily a bidirecrional shift register
with parallel load which is connected to an ALU. Because of the feedback
specifies thc code for the shift select but not the code for the ALU. The content$'of ' '-,iii
connection from the outpxt of the register to one of the inputs in the ALU,
i3 can be placed into the shiftcr by specifying an OR operation between R3 and , iiln
:,illl, rccumulator
register and its associated logic, when faken as one unit, constitute a
the
itself. The shifted information'returns to R3 if R3 is specilied as the destination .,,i;',
rquential circuit. Because of this property, an accumulator register can be de-
register. This requires that select fields l, B, aqd D have the code 0l I for R?, th1!
,,l,,:]
,:n dgned by sequential-circuit
techniques initcad of using a comiinational-circuit
tne nLU function code be 1000 for the OR operation, and that the shift-select ff 'rili:
{LU.
be 010 for the shiftleft.
The sircular shift.right with carry of register R I is symbolized by the
'1$
i,:s. q"
block diagram of an accumurator that forms a sequential circuit is shown
-. 9'-17. The regisler and the associated combinational
in Fig'
:m. I circuit constitute a
statement: ',r$i, rcquential
:iil. circuit. The combinational circuit replaccs thc ALU but cannot be
' nl <-crcRl "iLiilil *Raralgd. from. the register,
.rili) .since
it is only the combinationat_circuit part of a
j$ii' rcquential circuit. The I
register is referred to as thc rJlster and is
This statement specifies the code for the shifter, but not the code for the ALU' To pmetimes denoted by the symbol
.ai:li8'l
"""ornuluto,
AC. Here,, accumulator r"ra., to"uott ti.," ,r
llili
place the.contents of l(3 into thc output terminals of the ALU without affecting, 'rgister and its associated combinational circuit.
r'll. The externai i"p",r-t" rr,.
ih6 C Uit, we use the OR operation as before. In this way, the C bit is not affected i:ii
ili, :umulator are the data ingiuts from B and the controt variables ,r,"i a"r.r*ii. ,r" "*
by the ALU operation but may be changed because of the circular shift. l$j
The last example in Table 9-9 shows the control word for clearing a registcr l,$
to 0. To clear register R.2, the output bus is made to contain al 0's, with I1 = 0lt. tita)
li,l'r ;
:

The destination field D is made equal {o the code for register R2. ..i
It is obvious from these examples that many more microoperationS can b* ,ffi.
set of microoper''
$enerated in the processor unit. A processor unit with a complete
is
ations a general-purpose device that can be adapted for many applications- Tbt'' ,i,if'],
,,il+iit]

register+raisfer mitnoa is a convenient tool for specifying the operations k" $i

ryroUotic form in a digital system that employs a general-purpose processor uni*.' :$. ControI variables
The system is first dciined with a sequence of microoperation statemeqts.in t}ri r,:mri
rEgist;r-transfer method of irotation or in any other suitable eguivalent notation. Ii; ,$l
Control function here is repfesented not by d Boolean function, b'ut rather bv a' w
string of binary variables called a control word. The control word for ea$, '$i
B
Data inputs
micrioperationisderivedfromthefunctiontableoftheprocessor 'i{l
r!1,
li$r
'wi'
,
Flgurc 9.17 Block diagram of accumulator

&
-26t8 i$,.
 392 PROCESSOR LOGIC OESIGN CH.S Design Procedure
'li
microoperations for the register. The next state of register ,{ is a function of i&,,;11 The accumulator consists of n stages and n flip"flops, 11, A2,..,, 1,, numbered
consecutively starting from the rightmost position. It is convenient to partition the
In Chapter 7, we considered various registers that perform specific functionr ]i accumulator into n similar stages, with each stage consisting of one flip-flop
such as parallel load, shift operations, and counting. The accumulator is similar tc denoted by A,, one .data input denoted by &, and the combinational logit
these registers but is more general, since it can perform. not only the abow associated with the flip-flop. In the design procedure that foilows, we consider only
functions, but also otler data-processing operations..An accumulator is a mul6 l; one typical stage i with the understanding that an'n-bit accurnulator consists of n
function register that, by itself, can be made to perform all of the microopcrations ;: stages for i : 1,2, .. ., n.. Each stage ,4, is interconnected
'*'ith the neighboring
in a procCssor unit. The microoperations included in an accumulator depend on stage A,_, on its right and stage l,*, on its left. The first stage, 11, and the last
the opbrations that must be included in the particular processor" To demonstrati ;,r, stage, 1,, have no neighbors on one side and require special attgntion. The register
the logic desigp of a multipurpose operational register such as an accumulator, we will be designed
using "/(-type flip-flops.
will design the ciicuit with nine microoperations. The procedure outhned in thii Each control variable pi, :1,2,. ..,9, initiates a particular microopera-
"
i
section can be used to extend the register to other microoperations. ,;. tion. For the operation to bi meaningful; we must ensure that only one control
of for given in Table 9-l&
,/ Control variables p, through p, are generated by control loglc'circuits and shode variable
The set microoperations the accumulator is is enabled at any given time. since the control variables are mutually
,,ri,:

exclusive, it is possible to separate the combinational circuit of a stage into smalter

1it
-be
be considered as control functions that initiate the corresponding register-fans!ff .li circuits, one for each microoperation. Thus, the accumulator is to partitioned
operations. Register A is a source register in all the listed miirooperations. In i$ into n stages, aqd each stage is to be partitioned into those circuits that are needed
essence, this represents the present state of the sequential circuit. The B r€gist€r i$ rjil,rl Ior each microoferation. In this way, we can simplify the design process consider-
used as a second source rggister for microoperations that need two operands. fhal$ ably: once the various pieces are designed sepri"t.ly, it be possible to ;id
I register is assumed to be coffrected to the accumulator and supplies the inpus te :i;i combine them to obtain one typical stage of the accumulator and then io combine
the iequential circuit. The deitinaiion register for all microoperations is alwaW ijll the stages into a complete accumulator.
registerl. The new information transferred to A constitutes the next state of thfi 'ii$r
se[uential circuit. The nine control variables are also considered as inputs to rbr,,]it! Add ,
to A (pr): The add microoperation is initiated when pontrol variable
sequential circuit. These variables are mutually exclusive qnd only one variablc 1l' p, is l. This part of the accumulator can use a parallel addcr composed of
must be enabled when a clock pulse occurs. The last entry in Table 9-10 is a ' full-adder circuits as was done with the ALU. The full.adder in each stage i will
conditional conrol statement. It produces a binary I in an output variable Z wher lccept as inputs the present state of 1,, the data input Br, a-nd a previous Carry bit
,

the content of register,{ is 0, i.e., when all flip-nops in the regisier are cleared. m" sum bit generated in the full-adder must be tranifened to flip-flop e,iaad,
,.il 9.
the output carry C*, must be applied to the input carry of the nextitage. '
The internal construction of a full-adder circuit can be simpliiied if we
Tenr,s 9-10 List of microoperations for an accumulator consider that it operates as part of a sequential circuit. The stat; table of a
,ij
.triilt:
full-adder, when considered as a sequential circuit, is shown in Fig. 9-lg. The
Control value ofllip-flop A, before a clock pulse specifies the present state in the sequential
variable Microoperation Name circuit. The value of A, after the application of a clock pulse specifies the next
state' The next state of A, is a function of its present state and inputs g, and c,.
Pr A*.*A * B Add The present state and inputs in the state table correspond to t'he inputs of a
Pz A*0 Clear
ful'adder. The next state and output Q*, correspond to the outputs of a full-
Pt A*-F Complement adder. But because it is a sequential circuit, l, aipears in both the present and
Pt A<--A1\B AND next-s[ate columns. The next state of l, gives the sum bit that must be rransfened
Ps A+A\/ B OR ro the flip,flop.
A*-A@B Exclusive-OR
Po
,4 <-- shr A Shift-right
flipflop are listed in columns lA, and KA,,
The- excrtation inputs for the ,il(
Pt ,
These values are obtained by the method outlined in section a-7. Tie flipflop
Pa A <-shlA Shift-left
input functions and the Boolean function for the output are simplified in the-maps
Ps A<-A+l Increment
lf (A :0) then (Z : l) Check for zero
 itil

.!;
ili
ti..
\t. sEc.9-10 DESIGNOFACCUMULATOR g#
fl
Complement (p3): Control variablep, complemel! the state-of register l.
lr
Pressnt Next Flip-flop jir
inputs Output
state Inputs state
.ii To cause this transition in a tK flip-flop, we need to applyp, to both the ,I and X
At 8t ct At lAi KAt ct*t :,,11
inPuts:
0 00 0 0x 0 'lii
iti|:

*
0 0l I 1x 0
il
JAt Pt
I0 r0 I lx 0
- P'
ll 0 0x I ,rii KA'
I 00 I x0 0
)fi
I 01 0 xl I
i,ir AND (pj: The AND microoperation is initiated with control variable pa.
l0 0 xl I jgrj
This operation forms the logic AND operation between A, and B, and transfers the
I
I ll I x0 I i.,iJ
result to A,.'l\e excitation table for this operation is given in Fig.9-19(a). Th.e
iiil
lit next state of l, is I only when both A, and the present state of A, xe equal to l.
The flip-flop input functions which are simplified in the two nraps dictate that the
x x x x I
A _v_
I I I
l;T;l
ffi
I

ct
KAt B$i + Bi ci C1a1=Ap1 + Aiq+ BPt
l,l
lAi: O
^,1 EI:
K A,: p',.
JAt= B$i + Bict =

ngore 9-ft Excitation'tablc for add microopcration

(a) AND
K input d JAu and the
of Fig.9-18. The J input of flip-flop {r' felUnatedby
;t#"i"d;the conirol variable p'' These t$t
tt;-'il
flip-flop 1,, designatea;;
equations should
be ANDed witrr contioi
nip-fl9g only lJrenr' is enabled; thereforc'
rn.ct iiit -"iri"u[

associated with'the uaJ'***pt'otion

functions:
p; The pit or the combjnalional qircu&'
*n'Ut expressed with threc Booleaei
they shouH'

^,1
tr J:--
I;T;
l.l.l tll n,l
J:-

JA'o B'C1P'+ B!C'14 lAi: P' KAi: 6

KA': B'C!P' + BiC'1t1

Ci*t= AiBi+ Aiq+ BiCi
and they tp""tl, a cotrdition for
The first two equations are identical, B;
generates the carry for the next stage' -jj^
il-;,::Ti;-,hil4:"quution
l' cluse tl
(pJ: Control variable p2 clears all fliP-floPs in register to ]o K input
Ctear
transition in a JKnip-nrp,i" nlli"*rv "pprv
the flip-flop. rne "l inpii iil i" Lt*i'"d
["trdr varia6lep2 -the
io u" 0 if nothing is ipplied to it' T
,,1
EH, trtr
tAi: KAi:9,
i;il;fuffiil for thi clear microoperation are: B'

JA,: n
KA, = P2
nsgrr 9-19 Excitation iabtes for logic microopcrations

394
 PRocESsoR uoetc oEsrcu

enabled with-the complement val-r1e-of res[lli

K input of the flip-flop be 'J'
l,
This
:
ilil u"rifi"d from the conditions tisted in the state tatlc. If B-t the prcseml

;i.";#;;;;. ;f ;,;;;;' same, so the flipflop docs not haye.tg undergo

a:;

If B :'0,,, the next.tqi: o-f l,

1*t,-gL.1"..9::*l}-T-:Tffi-i
"i*ig"
;ii:ilfi;;;;;il;;t"
"rstate. iiip,, "i the nip-flop..rn. i"ggt functions.for the AND
initiates this rnicrooperatiou
[i"i""p"Ltion *,r-rt i""i"a"irt" control variablt th"t
JA,: g
KA,: Bipa
(pr): Control variablep, initiates the logi-c.OR tp"tlli"i l:l*een l' an$'
'OR-ti!'
4, *itt result transf e-rrJ to'l,' rig"* :l,"lt^*:^.1^":"*:1"*
equations in rhe u 1$.
nffi;; ;;;il;;d;, simplified
for this operation. The"9]-
dictate that the r.inpuiUi enabled when B, = l''This resul!ca1
!e fq$^l
the state table. When 4 : 0, the present state
iiil; =l;,r,; Jl;plit is enabrei and the next state of ,,! becomes l. The i E1: P9
functions for the OR microoperation are:
JAi = BiPs
Flgue 9.an 3-bit synchronous binary
KA:O counter

to the counter in Fig. 7-r7 sectionj-5, where the operalion of synchronous

. Exclusive.oR (p): This operaiion forms the
logic exclusive-oR betwcen binary counters are discussed.of
in detail. rrom ttre diagram,
pertinent information foi this operation we,."ir,",
and B,and transfers thJ;";"il;;" The
each stage is

;il*; in Fig. 9-19(c). The flip-flop input functions arel

complemented when al
input "irrv
r,:-i:'ffi;r"";;'il;;il;es
cany, E,*,, for the nexr siage on iti teit. The an outpur
first rtrg?i, i*""plion, since it is
- Blu complemented with the count-enabre pe. "i
The Boolean-functions fol a typicar stige
!!'
KA,: BiPo
can be expressed as follows:

tA,= E,
Shift-rtght (pr): This operation shifts the contents
of thc .{ rggryter
lr*1, which is M,= E;
position to the right This *'"""t ,t", the value of flip-flop
;::ffi *,t","ffi i'*ir"'"d into nip'nop r'' rhis transrer E,*, = E,A, i = 1,2,. .., n
';;;;;;;;;1u'
ixpressed by the inPut funitions:
JA, = A,nrP1 The input carry, E;, into the stage is used to
complement flip-frop 1,. Each stage
B,cnerates a carry for rhe nextrtage by ANDing the input
KA, = A!*rP,
carry into the first stage is "*1,
;;h;,. The.input
E, ind must be'equut tb *ntror u"riuit" p, which
one position 'to tfe
Shilt-left (pr): This operation shifts the z{ register enables the count.
position ro the right of stage i,
F", di;;;;-,rrx"""r"" 't f,_, "nrct is one
L.it"^r.". d to A,. Ttit tiioii* is expressed- by the input functions: Iot Tnro (2.): yanabre z is anoutput from
the accumutator used to
indicate a zero conren,
JA, = A,-1Ps i"-lL. rr r"gistei. rt ir lu,pu, is equar to binary r when a[
the flip-flops are cleared.. wr,*. frip-nop it ih comprement output, p,, is
Mi: Ai-Ps equal to l. Figure 9-21 shows the " first tt,'r"" rt"g.,
"r"ur"a,of the
accumulator that checks
for a zero content. Each srage genirates u ,uriiur.
ment output of A, to
,,;, Aii;i;!'tne .orpr.-
t
Increment(p):Thisoperationincrementsthecontentsofthelregistet an..infut-varitl" a. In rhis ;;y,;"fruir, o? AND gates
one; in other words, th";;;;;; tehaves like a synchr:l:T-Tf?::"i:1Y: It is
through all stages will indicaie if all flip-flc'ps are cleared. The Boolean
lff;,]}, iil'-rri.'" i-uir synchronous counteiis shown in Fis. 9-20. functions
_____24
I
I Stagc 3 it- I
L
Flgrrc 9.21 Chain of AND gtrcs for choctiag thc zcro coatcat
of a regirtcr

stagc can
zr*r: 2,A,, i- 1r2,...,n
' Zr:l-
..t -\ r .'.
"':
'...r
,;-...::'., , za+l:z
Ye1ie$g 7 bccomes I if te output signal from the last stagg
,: 4*,, is I.
One Stage of Accumulator

^-,rJpre4laequnuretor
stage consists of all the ciriuits thitG
rnolvlluar microoperatio.ns. contror vari@
*.'*'f ,the_mrr'esponaingr"l."ilffi ;'bt;;fr "j;"*T"ffi #nX:
produces a composire iet of input Boolean
f;d; i;;;i;i*ir;;",
. f,A,:\Cipt+ BiCStl* h* Bips* Bipa* At+rpt *A,_rps* E,
M1= B,Cipr* BiC,pr+pz+pt* Bipt* Bpo*A,i*rh :
* Ai-,Pr+ E,

C*f=AiBi+AiCi+8.C.
E,*, = E,A,
Zi*14 ziAi
lacrcment
Th" logrc 'diagram.of one tpforl stage of the accumurator
is shorm in rig" ,
9-22"1t is a dircct implementation or tr,i aoorean
i"i"rJil"iiii"i.abovc. Th*;.,r