Condition Pnemonics

CoIdt Function Flags

Equal 2
Eg
NE NotEqual z

CSHS 7o Emad
CarrysetHinghe C
CCLO Carryaearlknosignered c
1411 Minus Negative N
PL Plus live n
US Overflow V
VC No overflow V
HI Unsigned higher 2C
Unsigned lower 2 e
GE Greaterthantefsisned
NV nu
LT Less than signed Nu nV
GT Greaterthansigned NzVo nzV
LE Less than
Eq signed Nv Un Z
AL Always

Condition execution controls whether not core

execute
any in.st.rs Condition set execution starts if not
it doesn't change path
ofthe program
 Mechanism
Pipeline of RISC processor to execute in.st.in

ARM 7 3
stages

Itf
execution
Pipelining speeds up by fetching other in.I.is
while others
being executed
are
decoding

As pipeline length Tses amount

of worktodone in each
is reduced which allows attain
stage processor higher
Ises
operating range thus performance

ARM 9 5 stages
Fetch Decode Execute Memory I write

Exceptions Interrupts Vector Tables

Whenever exceptions interrupts occur processor set

PE to a specific
memory
address vector Table
Branch to specific routines to handle particular
exception interrupts
 Software Interrupt
Reset 1st location when power is applied Reset Vector
Undefined ln.st.tn Vector Processor can't decode the insta
undefined ln.st.in Vector
due
Prefetchabort vector when processor attempts tofetch
an in.SIn without valid access permission
Daiaqbortvectory When processor attempts to fetch
a data memory without valid access permission

Vectortabies

ExceptionInterrupt Abbrev Lower Higher

Reset RESET 0 00000000 OXFFFFOOOO
Undefined UNDER 0 00000004 OXFEFF0004
Software SDI 0 00000008 OXFFFF0008
Prefetch Abort PA13T 0110000000C OxffFF 000C
Data Abort DA BT 0 00000000 OXFFFF 0010
Reserved 0 00000014 OXFFFF0014

RG 112 0 00000018 OXFFFFO018

Fl Og Fl 0 0000001 C OXFFFFOOIC

ARM processor families

7,9
Ref Book 3
10 11 13 2.6.27
 2

ARM lns.tn set

ARM revisions support

diff instructions new
revisions add ingt.IS remain backwardly compatible

lns.tn Classes

Data Processing lnsII Branchln.sI.n LoadIsto

51W Interrupts Program Status

Manipulate Data within registers

Move
Arithmetic
Logical
Compare
Multiply
15 1 2020
Move instructions
Simplest one it copies n N into destination
register Rd where N is an immediate value register

MOV i Transfer a 32 bitvalue intoregister REN

MUN i Transfer a riot 32 bit value intoregisterRa uD
 I l 7
Pre Post
MOV r 7 r5 B 5 7 8 is r 5

to OX80000000 to 0 00000008
MOUS ro r 1St I 4 0 80000004 I 0 80000004
CPSR nzc
gift User CPSR n
gift user
copy of r is taken Left shift is made then it is
moved to Ro

MUN M RS r 5 Sir 7 8 r5 5
ft FF FF FF FA

Ba rrd hifter Register Rn is pre processed by

barrel shifter prior being used by data processor
Unique feature in ARM processor
Ability to shift 32 bit n saved in a source rig
left right specific n positions before entering into
ALU

MOL Multiply
L2 Count leading zero
QADD i Signed saturated 32 bit signed a.dd.tn
donot use the barrel shifter
En Pre Mov r7 rs LSL 2 Post
85 5 r7 8 r7 oxl4irS 5
Amounts'hittt
Barrel
Ahift operations Immediate
Val Val in

rOfLsL
Mnemonic bing.gsHesdhift
Description
Left shift logical
LSLY
LSR Shift
Logical KLSRY Right
ASR ArithmeticShift Right
KASRY
12012 Rotate Right 2
RORY
RRX Rotate Rightextended

Immediate value 32 bit

any
Register rp
RRn.GL
Logicalshift Lefthere lnzmeiRn.LsLRp
It Rightt.mn Rn.GR lmm.eiRn.LSRRp
Arithmetic shift Right Rn ASR Kp

Arithmetic Irish

Addition bit signed and

subtraction
of 32 value
unsigned

ADD i Add 2 32 bit values

 ADC i Rn Rn 1N 1C
RSB I Reverse Subtraction Rn N Rn
RSC i Rn N Rn C
SUB Rd Rd N
SBC i Rn Rn N C

Pre Post
r ox0 SUB ro r r fo 0 2 0 1
r Ox2 ro r rz to 0 1
t OH re 0 2 ifz 0X

ro 0 00 RSB ro r 0 to'OXFFFFFF89
r 0 77 fo O r

r _0 01 SUBS r r I 4 0 00
CPSR nzcvqift user
fir I CPsR n2cvqift_use

01101010
2 s complement 100101 0