Noise and Non-Linearity Analysis of a

Charge-Injection-Cell-Based 10-bit 50-MS/s

SAR-ADC

Marcel Runge, Student Member IEEE, Dario Schmock and Friedel Gerfers, Member IEEE
Chair Mixed Signal Circuit Design
Technische Universität Berlin, Germany
Email: marcel.runge@tu-berlin.de

Abstract—This paper presents a detailed noise and non- DAC+ MSB MSB-1
linearity analysis of a 10-bit 1.2 Vppd 50 MS/s charge-injection DAC-
based SAR-ADC designed in a 65 nm low power process. Being MSB-2
more area-efficient in contrast to a conventional capacitor DAC, a
charge-injection-cell-based DAC allows to reuse its DAC cells dur-

ADC output
ing binary search. Based on extensive calculations and transistor- CS CS t

Ser2Par
DAC+
level simulations, the charge-injection cell design tradeoffs are VIN+
analyzed and optimized to maximize the overall ADC linearity VIN- DAC-
and ADC input range. Extensive system level simulations in
MATLAB evaluate the jitter sensitivity of the ADC. Combining CIC-DAC
the transistor-level and system level simulations, a detailed noise
study of the 8.86-bit ENOB ADC completes the evaluation.
32CICs CMP-
I. I NTRODUCTION CIC CIC CIC CMP+
Transfer

With emerging wireless technologies, the demand for
medium-speed high-resolution low-power ADCs constantly
increases. In recent years, charge-redistribution SAR-ADCs
have become the choice for achieving highest conversion effi-
ciencies. However, the non-reusable nature of a conventional
capacitor DAC during binary search limits the SAR-ADC
from further reducing its area. Additionally, residual settling
from previous decisions during binary search limits the SAR-
ADC from achieving high resolution. By adding redundancy,
the SAR-ADC is able to recover from false decisions up
to a certain point since a conversion radix less than two is
used. However, this often implies a power and area hungry
digital code converter at the ADC output [1]. To overcome
those limitations, [2] introduced a very power and area-efficent
1 GS/s charge-injection-cell SAR (ciSAR) reusing the unary-
weighted cells in the DAC during binary search. With a
600 mVppd peak-to-peak input voltage an ENOB of 5.46-bit
was achieved. Based on the idea of [2], this paper presents
a 8.86-bit ENOB 50 MS/s SAR-ADC suitable for wireless
technologies demanding high resolution medium bandwidth
converters.
II. C HARGE -I NJECTION SAR-ADC ( CI SAR)
Fig. 1 depicts the charge-injection SAR-ADC described in
this paper. First, the differential input voltage is sampled onto
the sampling capacitors CS . Then during binary search, similar
to the set-and-down switching scheme presented in [3], charge
is deducted from either one of the sampling capacitors based
on the previous comparator decision. The amount of charge per
step is determined by a charge-injection cell DAC employing
32 unary-weighted charge-injection cells (CIC). In contrast
to a conventional capacitor array, the CICs can be reused
CmpClk
en en en
CLK Finite State Machine
Fig. 1: Charge-injection cell (CIC) based SAR inspired by [2].
The area-efficient CIC-DAC is formed by N reusable unary-
weighted cells each deducting a fixed charge from one of
the sampling capacitors if enabled during binary search. The
algorithm during binary search is similar to the set and down
capacitor switching presented in [3] as depicted in the transient
plot.
multiple times since they are reset after each step during binary
search. This reusability enables a large area-efficiency [2] and
is exemplary illustrated in the transient plot in Fig. 1. The MSB
is determined first. Then, all unary-weighted CICs are turned
on two times in a row deducting each time a fixed amount of
charge from the sampling capacitance. Subsequently, MSB-1
is resolved. The charge deducted from the sampling capacitor
for one binary search step is
QDAC = K · M · QCIC , (1)
where K denotes the number of repetitions, M the number of
CICs enabled, and QCIC the LSB charge from one charge-
injection cell. The in this paper presented 10-bit switching
scheme is depicted in Tab.I.

978-1-5090-6389-5/17/$31.00 ©2017 IEEE 1025

TABLE I: Switching scheme during binary search used for the
presented 10-bit ciSAR
901 500
QDAC /QCIC 256 128 64 32 16 8 4 2 1
KxM CICs 8x32 4x32 2x32 32 16 8 4 2 1

900

0
DAC- DAC+ 899
20 40 60 80 100
IDAC- IDAC+ CMP+
SW+ G3
M1 G1
Enable 30
SW- G2 G4
M2 CMP- 20

10
Vx
M3 Cu M4 0
VDD Transfer 20 40 60 80 100

1.5
Fig. 2: The charge-injection cell [2] employs two switch
transistors M1/M2, long-channel transisors M3 mainly defining 1
the parasitic capacitance Cu and reset transistor M4. Due to
the transfer pulse, a fixed amount of charge is subtracted from 0.5
either one of the samplings capacitors CS . Major Cu contrib-
utors are CDD,M3 = 420 aF and CWiring = 320 aF (layout 0
extracted) for a reservoir node voltage of Vx = 410 mV. 20 40 60 80 100

Fig. 3: Transistor level simulation showing one LSB (1.2 mV)

III. C HARGE - INJECTION C ELL D ESIGN charge subtraction QCIC from 1 pF large positive sampling
capacitor CS at 900.5 mV (top). 75 ps long transfer pulse
As depicted in Fig. 2, the CIC comprises two switches (bottom) subtracts the current IDAC+ (middle) composed of
M1 and M2 connecting the parasitic capacitance Cu to either IDS,M3 (middle), capacitive charging of Cu (Vx ) (top), and
the negative or positive sampling capacitor CS . The switch charge injection of M1.
selection is performed by the previous comparator decision and
enable signal from the finite state machine. The transfer signal
is high when idle and transistor M4 grounds the reservoir
voltage Vx . Once the transfer signal goes low, for time tpulse , As depicted in Fig. 3, not only the reservoir node capacitance
the reset transistor M4 closes and transistor M1/M2 starts Cu leads to a discharge of the sampling capacitor CS
conducting current as shown in Fig. 3. Subsequently, node  tpulse
Vx begins to rise. The total reservoir capacitance neglecting QCIC = IDAC (t) dt, (4)
junction capacitors is formed by 0
= Vx (tpulse ) · Cu (Vx (tpulse )) + QCI (5)
 tpulse
Cu (Vx ) = CSS,M1 (Vx ) + CSS,M2 (Vx ) (2) + IDS,M4 (t) + IDS,M3 (t) dt,
+ CDD,M3 (Vx ) + CDD,M4 (Vx ) + CW , 0

where QCI denotes charge-injection, mainly from the switches

where CSS,i and CDD,i concentrate all the parasitic capacitors
seen from the MOSFET’s source and drain terminal and
CW the routing cap of net Vx . In contrast to a conventional
metal-oxide-metal capacitor DAC, which shows a strong linear
behavior across voltage [4], the elements forming CSS,i , and
CDD,i such as junctions, gate-source, and gate-drain capacitors
depend on the MOS operating point given by the reservoir
voltage Vx (tpulse ). Thus, for designing a high linear charge-
injection cell, the design has to ensure that the reservoir voltage
is not data-dependent
Vx (tpulse ) = const.
M1/M2 and IDS the drain-source current. Leakage currents
are neglected. Since the gate-source voltage of long-channel
transistor M3 is held constant at VGS,M3 = VDD to minimize
the nonlinear gate-drain capacity CGD,M3 (Vx ), bias current
IDS,M3 discharges the sampling capacitor CS during transfer
phase. Thus, an optimal sizing of M1/M2 and M3 for optimal
linearity and maximum input range has to be found. The reset
transistor M4 is assumed to be sized minimal, fully resetting
node Vx in between two transfer pulses.
Since charge is only subtracted from either the positive
or negative sampling capacitor CS , the common mode volt-
(3) age (VDAC+ + VDAC− )/2, monotonically falls during binary

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 1.3 IV. N OISE -A NALYSIS
In order to calculate the SNDR of the presented ADC,
1.25 all noise sources in the ADC are referred to the ADC input,
leading to
1.2  
VS,RMS
 

  SN DR = 20 · log10 ∗ , (11)

1.15 VN,RMS
 
∗

  where VS,RMS denotes the rms input voltage and VN,RMS the
1.1

  input-referred rms noise voltage defined as

∗
1.05

  VN,RMS = νq2 + νq,NL


  
1
0.4 0.6 0.8 1 1.2



Fig. 4: LSB voltage across the sampling capacitor voltage
VDAC+ for the designed CIC seen in Fig. 4. The LSB is
calculated by Eq. 9. Below VDAC+ = 600 mV, the LSB starts
to degrade significantly. Since transistor M1 enters the triode
region, net Vx shows data dependency. Subsequently, LSB-
defining parameters such as the parasitic capacitance change.
search. For a constant LSB charge QCIC , net Vx must not
follow the common mode voltage as described in Eq. 3. Thus,
the transistors M1/M2 have to operate in saturation at the end
of the transfer pulse t = tpulse leading to
VDAC+ − Vx ≥ VDD − Vx − VTH,M1 .
With a switching scheme similar to the monotonic switching
scheme, the common mode voltage at the end of the binary
search is
VCM,min = VDD − Vinppd /2, (7)
where Vinppd denotes the differential ADC peak-to-peak input
voltage. Substituting VDAC+ in Eq. 6 by Eq. 7, the maximum
input voltage swing is
Vinppd ≈ 2 · VTH,M1 .
In order to maximize the input voltage swing and simultane-
ously minimize leackage current through M1 and M2, high
threshold voltage (HVT) devices are used. A maximum peak-
to-peak input voltage of Vinppd = 1.2 V is achieved with the
presented design as depicted in Fig. 4. Here, the LSB is shown
across VDAC+ . First, VDAC+ = 1.2 V is sampled onto the
positive sampling capacitor CS . Then, one CIC periodically
discharges the sampling capacitor by QCIC (VDAC+ ). The LSB
is defined as
LSB (VDAC+ (i)) = VDAC+ (i) − VDAC+ (i + 1)
CS
= ,
QCIC (VDAC+ )
where i denotes the consecutive iteration parameter. For a
peak-to-peak input voltage of Vinpp = 600 mV, the LSB
spreads by about ±5% across voltage. Additionally, the LSB
shows a low temperature dependency of only 50 μV across
temperature.
2 + νtj2 + νcmp
2 + νCIC
2 + νkT/C
2 .
(12)
Here, νq denotes the quantization noise, νtj the jitter in-
duced noise caused by the transfer pulse, νCIC the thermal
noise from the CIC-DAC, νcmp the input-referred thermal
comparator noise, and νkT/C the kT/C sampling capacitor
noise. Given the reuse of the CICs during binary search,
CIC non-linearities do not appear as harmonic distortions but
spread as spurs across frequency in spectral performance plots.
νq,NL denotes the additional quantization noise caused by CIC
non-linearities. Throughout the paper, all noise sources are
assumed uncorrelated. A noise-free transient simulation shows
58.5 dBFS SN DR√ at Vin = −1 dBFS. Given a quantization
noise νq = LSB/ 12 = 339 μV, the additional quantization
noise caused by CIC non-linearities is
 √
Vinppd /2/ 2
νq,NL = 58.5 − νq2 = 374 μV (13)
10 10
The comparator used in this design is a strong arm latch includ-
(6) ing a three-stage preamplifier. The input-referred comparator
noise νcmp is determined by the comparators probability
density function described in [5], leading to νcmp = 440 μV.
Given a differential sampling capacitor of CS = 1 pF, the kT/C
noise is νkT/C = 91 μV which is negligible compared to the
previous calculated noise sources.
In order to evaluate the impact of jitter-induced noise
caused by the transfer pulse, a high-level MATLAB model
is designed. Generally speaking, the transfer pulse jitter has
to be split into a jitter contribution acting locally within one
(8) CIC and a jitter contribution that is seen by all CICs at the
same time. The local jitter contribution is mainly defined by the
gates G1 and G2, respectively depicted in Fig. 2. However, the
local jitter contribution of 50 fs is significantly smaller than the
jitter of 400 fs induced by the global transfer pulse generation
circuit. Thus, the local jitter contribution is neglected in the
following modeling. The during binary search for one binary
decision subtracted charge QDAC is defined as
K

QDAC = QCIC−DAC (e, tj,pulse ) , (14)
n=1
(9) where K depicts the number of repetitions and tj,pulse the
transfer pulse jitter. Each element en in e enables (1) or
(10) disables (0) the corresponding CIC
eT = ( e1 , e2 , . . . , eN ) . (15)
Assuming that at the end of the transfer pulse, the CIC current
is mainly defined by IDS,M3 as shown in Fig. 3, QCIC−DAC
is defined as
QCIC−DAC = eT · 1 · (QCIC + IDS,M3 · rand (tj,pulse )) , (16)
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 62 0

61 -20

-40
60

-60
59
-80

58
-100
10-13 10-12 0 0.5 1 1.5 2 2.5
107
Fig. 5: Plot showing the SN DR degradation across the trans-
Fig. 6: Spectral performance of full ADC transistor-level sim-
fer pulse jitter tj,pulse . The MATLAB model is introduced in
ulation (1024 samples) with transient noise enabled (fmax =
Eq. 16. The charge depends on the equilibrium current IDS,M 3
40 GHz). 8.86-bit ENOB is achieved. The transfer pulse jitter
as seen in Fig. 3.
is tj,pulse = 400 fs.

where 1 depicts the unit vector. The function rand (tj,pulse ) 2

CIC
returns a Gaussian-distributed random number with standard 4% 2
deviation tj,pulse for every time the CIC-DAC subtracts charge 2
tj

from one of the sampling capacitors. With the above described q,NL
12%
26% 2
MATLAB model, the impact of the transfer pulse jitter tj,pulse kT/C
on the SN DR is evaluated in Fig. 5 for different currents 2%
IDS,M3 . For each pair of values, 1024 samples are digitized
per simulation and the obtained SN DR is averaged over 100
simulations. With the through transistor simulations obtained
transfer pulse jitter of tj,pulse = 400 fs and the equilibrium
current at t = tpulse of IDS,M3 ≈ 8 μA, a SN DR degradation
of 1.8 dB is expected. This corresponds to an input-referred 2
2
jitter-induced noise of νtj = 245 μV. To calculate the noise q
cmp
contribution of the CIC-DAC νCIC , a full-transistor simulation 20% 36%
with transient noise enabled is performed. As depicted in
Fig. 6, the 1024 point long simulation shows a spectral Fig. 7: Percentage contribution of calculated uncorrelated noise
performance of SN DR = 55.1 dBFS. Applying Eq. 12 to sources
Eq. 11, resolving for νCIC , and then applying the previously
calculated noise contributors results in a CIC-DAC thermal-
noise contribution of νCIC = 150 μV. Fig. 7 illustrates the contributions were calculated and transferred to the input
percentage contribution of each calulated noise source. revealing performance limiting factors.

V. C ONCLUSION
In this paper, a 10-bit 50MS/s charge-injection-based SAR-
ADC (ciSAR) design using 32 unary cells was presented. The
charge-injection DAC allows a reuse of its cells in contrast to a
conventional capacitive DAC. While being more area-efficient
than their counterparts, the LSB is defined by an operating-
point-dependent strong-nonlinear parasitic capacitance. Thus,
this paper developed a design strategy to maximize the ciSAR
input range to 1.2 Vppd and to minimize the non-linearites
caused by the voltage-dependent LSB. Based on an optimized
charge-injection cell design, the noise performance was ana-
lyzed. Due to the pulse-triggered nature of the charge-injection
cell, a system-level model of the ciSAR was developed tak-
ing into account the pulse width jitter. ADC transistor-level
simulations showed an ENOB of 8.86-bit. Lastly, all noise
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