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Notebook Toshiba Satellite L675 - Compal - La-6054p - r0.2 - Schematics PDF
Notebook Toshiba Satellite L675 - Compal - La-6054p - r0.2 - Schematics PDF
1 1
Compal confidential
2
Hamburg 10ADG 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 1 of 52
A B C D E
A B C D E
Page 35,36,37,38,39
HDMI Conn. 40,41,42,43
page 19
page 11,12,13,14,15
RTL 8105E 10/100 RJ45
PCIe port 3 page 26
2 2
A-Link Express II page 26
4X PCI-E
3 3
Clock Generator
SLG8SP626 HD Audio 3.3V 24.576MHz/48Mhz
page 16
LPC BUS
3.3V 33 MHz
RTC CKT. ODD/B MDC 1.5 Conn HDA Codec
page 20 page 25 ALC259Q
Debug Port ENE KB926 D3 page 32 page 29
page 32 page 31
Power On/Off CKT. Power/B
page 33
page 33
page 34
LED/B
page 33
Power Circuit DC/DC
4
page 44,45,46.47 Touch Pad/B 4
48,49,50,51 page 33
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 2 of 52
A B C D E
5 4 3 2 1
WOL_EN#
DESIGN CURRENT 330mA +3V_LAN
P-CHANNEL
AO3413
SUSP
N-CHANNEL DESIGN CURRENT 1.5A +3VS
SI4800 VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO3413
BT_PWR#
NALAE Hamburg AMD DIS DESIGN CURRENT 180mA +BT_VCC
C C
P-CHANNEL
AO3413
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A DESIGN CURRENT 36A +CPU_CORE_0
ISL6265A DESIGN CURRENT 4A
B +VDDNB B
SYSON
Ipeak = 11A, Imax = 7.7A, Iocp_min = 19.16A DESIGN CURRENT 11A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 5A +1.5VS
IRF8113
SUSP
Ipeak = 20A, Imax = 14A, Iocp_min = 20.14A DESIGN CURRENT 20A +VGA_CORE
APW7138NITRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 3 of 52
5 4 3 2 1
A B C D E
O : ON
: Digital Ground
X : OFF
GPU CPU NB VGA SB Comment
: Analog Ground S1G4 RS880M MADISON SB820M Madison@ or PARK@
Manhattan
+5VS S1G4 RS880M PARK SB820M +4PCS or 8PCS
1
+3VS S1G4 RS880M M96 SB820M M9X@+M96@ or M92@ 1
power M96/M92
plane +2.5VS S1G4 RS880M M92 SB820M +4PCS or 8PCS
+1.8VS
+1.5VS
@ : just reserve , no build Platform CPU NB VGA SB Comment
+1.1VS
B+ +5VALW
+1.05VS Danube
+3VL +3VALW +1.5V S1G4 RS880M NA SB820M
+0.75VS
+5VL +1.1VALW
State +VGA_CORE
+RTCVCC
+VDDNB
+CPU_CORE
+NB_CORE
BTO (Build-To-Order) Option Table
Function BLUE TOOTH HDMI
S0
O O O O Description (B) (Y)
S1 Explain
O O O O
2 2
BTO BT@ H@
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
SMBUS Control Table
CPU
SOURCE BATT SODIMM CLK LCD HDMI
THERMAL WLAN
I2C / SMBUS ADDRESSING I / II GEN DDC DDC
SENSOR ROM ROM
EC_SMB_CK1
DEVICE HEX ADDRESS KB926
V
EC_SMB_DA1
3
DDR SO-DIMM 0 A0 1010000X EC_SMB_CK2 3
KB926
DDR SO-DIMM 1 A2 1010001X EC_SMB_DA2 V
CLOCK GENERATOR (EXT.) D2 11010010 I2C_CLK
RS880M
I2C_DATA V
DDC_CLK0
RS880M
DDC_DATA0 V
SCL0
SB820
EC SM Bus1 address EC SM Bus2 address SDA0 V V
SCL1
Device HEX Address Device HEX Address SB820
SDA1 V
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
EC KB926D4 EC KB926D3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 4 of 52
A B C D E
A B C D E
+1.1VS
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
1 1
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
+1.1VS
+1.1VS
JCPUA
C7
D1 HT LINK AE2 +VLDT_B 1 2 10U_0805_10V4Z < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A0 VLDT_B0
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
FOX_PZ6382A-284S-41F_Champlian
+5VS
1A
2
+FAN1 C1119
JFAN +3VS
1
C1120 10U_0805_10V4Z +FAN1 1
1 1
2 2
1
10U_0805_10V4Z 2 3
2 U31 C1121 3 R795
1 8 @ 4
EN GND 1000P_0402_25V8J GND 10K_0402_5%
2 VIN GND 7 5 GND
1
3 6
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 5 of 52
A B C D E
A B C D E
< DDR2 VREF is 0.5 ratio > < Processor DDR3 Memory Interface >
+1.5V
2
R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1% MEM:DATA
DDR_A_D[63..0] <9>
< From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 6 of 52
A B C D E
A B C D E
JCPUD
< Filtered PLL Supply Voltage > +1.5V
+2.5VDDA F8 M11
VDDA1 VSS
F9 VDDA2 RSVD11 W18
+2.5VS +2.5VDDA CPU_SVC 1K_0402_5% 1 2 R19
VDDA=300mA CPU_CLKIN_SC_P A9 A6 CPU_SVC
L1 1 CLKIN_H SVC CPU_SVC <49>
2 FBM_L11_201209_300L_0805 +2.5VDDA CPU_CLKIN_SC_N A8 CLKIN_L SVD A4 CPU_SVD
CPU_SVD <49>
CPU_SVD 1K_0402_5% 1 2 R20
1 1 1 1
C12 C13 C14 LDT_RST# B7 < Serial VID Interface clock & data >
+ C11 H_PWRGD RESET_L R11
A7 PWROK
@ 4.7U_0805_10V4Z 3300P_0402_50V7-K 0.22U_0603_16V4Z LDT_STOP# F10 AF6 CPU_THERMTRIP#_R +1.5V 1 2 300_0402_5%
150U_B2_6.3VM_R45M 2 2 2 LDTSTOP_L THERMTRIP_L
T2 PAD C6 LDTREQ_L PROCHOT_L AC7 CPU_PROCHOT#
2 @R13
@ R13
MEMHOT_L AA8 PAD T3
+1.5V 1 2 CPU_SIC AF4 CPU_PROCHOT# 1 2 0_0402_5%
SIC H_PROCHOT# <19>
+1.5V R12 1 2 1K_0402_5% CPU_SID AF5
1 R14 1K_0402_5% SID THERMDC_CPU 1
AE6 ALERT_L THERMDC W7
W8 THERMDA_CPU
R15 CPU_HTREF0 THERMDA
< 200-MHz PLL Reference Clock > 1 2 44.2_0402_1% R6 HT_REF0
C16 +1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1
<19> CLK_CPU_BCLK 1 2 3900P_0402_50V7K CPU_CLKIN_SC_P route as differential
CPU_VDD0_RUN_FB_H F6 W9 as short as possible
<49> CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H testpoint under package
<49> CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L
1
R10 <49> CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H
VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H <49>
<49> CPU_VDD1_RUN_FB_L CPU_VDD1_RUN_FB_L AB6 G6 CPU_VDDNB_RUN_FB_L
VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L <49>
169_0402_1%
CPU_DBRDY G10
2
C15 CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10
<19> CLK_CPU_BCLK# 1 2 3900P_0402_50V7K CPU_CLKIN_SC_N CPU_TCK AC9 TCK
CPU_TRST# AD9 AE9 CPU_TDO
CPU_TDI TRST_L TDO
Address:100_1100 Place close to CPU wihtin 1.5" AF9 TDI
CPU_TEST23 AD7 J7
TEST23 TEST28_H R6 1
TEST28_L H8 +1.5V 2 10K_0402_5%
CPU_TEST18 H10
CPU_TEST19 TEST18 CPU_TEST17
G9 TEST19 TEST17 D7 PAD T4
E7 CPU_TEST16
TEST16 PAD T5
CPU_TEST25H E9 F7 CPU_TEST15 R7 1 2 1K_0402_5%
TEST25_H TEST15 PAD T6
2
B
CPU_TEST25L E8 C7 CPU_TEST14 Q1
TEST25_L TEST14 PAD T7
E
CPU_TEST21 AB8 C3 CPU_THERMTRIP#_R 3 1
TEST21 TEST7 H_THERMTRIP# <20>
C
CPU_TEST20 AF7 K8
CPU_TEST24 TEST20 TEST10 MMBT3904_NL_SOT23-3
AE7 TEST24
CPU_TEST22 AE8 C4
CPU_TEST12 TEST22 TEST8
AC8 TEST12
CPU_TEST27 AF8 TEST27 CPU_TEST29_H_FBCLKOUT_P
TEST29_H C9
2 CPU_TEST29_L_FBCLKOUT_N 2
1 2 R24 C2 TEST9 TEST29_L C8 2 1
+1.5V 0_0402_5% AA6 R25 80.6_0402_1%
TEST6
A3 RSVD1 RSVD10 H18
R22 2 1 510_0402_5% CPU_TEST25H A5 H19
RSVD2 RSVD9
B3 RSVD3 RSVD8 AA7
2 1 CPU_TEST27 B5 D5
R28 1K_0402_5% RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
+1.5VS
2
3 3
R17
300_0402_5%
1
LDT_RST#
<19> LDT_RST#
1
C17 < HDT Connector >
@
0.01U_0402_25V7K JP2
2
1 2
3 4
R40 CPU_DBREQ# 5 6
+1.5V 1 2 300_0402_5% 7 8
+1.5VS CPU_DBRDY
R39 220_0402_5% CPU_TCK 9 10
1 2 11 12
R38 1 2 220_0402_5% CPU_TMS
13 14
2
+1.5V
21 22 LDT_RST# +3VS < Thermal Sensor >
1
H_PWRGD 23 24 U1
<19,49> H_PWRGD 26 EC_SMB_CK2
1 1 VDD SCLK 8 EC_SMB_CK2 <30,42>
C19 1
@ @ SAMTEC_ASP-68200-07 C20 THERMDA_CPU 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <30,42>
0.1U_0402_16V7K
2 0.1U_0402_16V7K 1 2 C21 THERMDC_CPU 3 D- ALERT# 6
2 3300P_0402_50V7-K
@ 4 THERM# GND 5
+1.5VS
4 ADM1032ARM-1 ZREEL_MSOP8 4
2
R18
300_0402_5%
1
LDT_STOP#
<12,19> LDT_STOP#
1
C18
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
@
2
0.01U_0402_25V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 7 of 52
A B C D E
A B C D E
330U_X_2VM_R6M
330U_2.5V_M
330U_2.5V_M
1 1 1 1 1 1 1 1 1 1 1 M8 VDD0_19 VDD1_19 V8
C30 C31 C32 C33 C39 C40 C41 M10 V10
+@ + C89 + @C24 + C90 VDD0_20 VDD1_20
N7 VDD0_21 VDD1_21 V12
C23 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J N9 V14
2 2 2 2 2 2 2 +VDDNB VDD0_22 VDD1_22
N11 VDD0_23 VDD1_23 W4
2 2 2 2
VDD1_24 Y2
Near CPU Socket Under CPU Socket Under CPU Socket K16 VDDNB_1 VDD1_25 AC4
M16 AD2 +1.5V
VDDNB_2 VDD1_26
P16 VDDNB_3
T16 VDDNB_4 VDDIO27 Y25
+1.5V V16 V25
VDDNB_5 VDDIO26
VDDIO decoupling : DDR SDRAM I/O ring power H25
VDDIO25 V23
V21
+1.5V VDDIO1 VDDIO24
J17 VDDIO2 VDDIO23 V18
K18 VDDIO3 VDDIO22 U17
K21 VDDIO4 VDDIO21 T25
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23
C44 C45 C46 C47 C48 C50 K25 T21
VDDIO6 VDDIO19
L17 VDDIO7 VDDIO18 T18
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J M18 R17
2 2 2 2 2 2 VDDIO8 VDDIO17
M21 VDDIO9 VDDIO16 P25
Under CPU Socket M23 VDDIO10 VDDIO15 P23
M25 VDDIO11 VDDIO14 P21
N17 VDDIO12 VDDIO13 P18
+1.5V
FOX_PZ6382A-284S-41F_Champlian
2 2
1 1 1 1
C54 C51 C52 C53
JCPUF
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z AA4 J6
2 2 2 2 VSS1 VSS66
AA11 VSS2 VSS67 J8
Between CPU Socket and DIMM AA13 VSS3 VSS68 J10
AA15 VSS4 VSS69 J12
AA17 VSS5 VSS70 J14
+1.5V AA19 J16
VSS6 VSS71
AB2 VSS7 VSS72 J18
AB7 VSS8 VSS73 K2
1 1 AB9 VSS9 VSS74 K7
C64 C65 AB23 K9
VSS10 VSS75
AB25 VSS11 VSS76 K11
0.01U_0402_25V7K 0.01U_0402_25V7K AC11 K13
2 2 VSS12 VSS77
AC13 VSS13 VSS78 K15
Between CPU Socket and DIMM C56 Co-layout with C75 AC15 VSS14 VSS79 K17
AC17 VSS15 VSS80 L6
AC19 VSS16 VSS81 L8
+1.5V AC21 L10
+1.5V VSS17 VSS82
AD6 VSS18 VSS83 L12
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> 1 AD8 L14
VSS19 VSS84
AD25 VSS20 VSS85 L16
C56 + AE11 L18
1 1 1 1 VSS21 VSS86
C66 C67 C68 C69 AE13 M7
390U_2.5V_M_R10 VSS22 VSS87
2 C1124 Co-layout with C1125 AE15 VSS23 VSS88 M9
180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J AE17 AC6
2 2 2 2 VSS24 VSS89
AE19 VSS25 VSS90 M17
Between CPU Socket and DIMM +1.05VS AE21 N4
VSS26 VSS91
AE23 VSS27 VSS92 N8
1 B4 VSS28 VSS93 N10
+1.5V B6 N16
3 + C1124 VSS29 VSS94 3
B8 VSS30 VSS95 N18
1 390U_2.5V_M_R10 B9 P2
@ VSS31 VSS96
1 1 1 1 B11 VSS32 VSS97 P7
C71 C72 C73 C74 + C75 2
B13 VSS33 VSS98 P9
B15 VSS34 VSS99 P11
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z B17 P17
2 2 2 2 2 330U_D2E_2.5VM_R6M VSS35 VSS100
B19 VSS36 VSS101 R8
Between CPU Socket and DIMM B21 VSS37 VSS102 R10
B23 VSS38 VSS103 R16
B25 VSS39 VSS104 R18
D6 VSS40 VSS105 T7
D8 VSS41 VSS106 T9
+1.05VS
VDDR decoupling. D9
D11
VSS42 VSS107 T11
T13
VSS43 VSS108
D13 VSS44 VSS109 T15
1 1 1 1 1 1 1 1 D15 VSS45 VSS110 T17
C57 C58 C59 C60 C61 C62 C63 C70 D17 U4
VSS46 VSS111
D19 VSS47 VSS112 U6
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J +1.05VS D21 U8
2 2 2 2 2 2 2 2 VSS48 VSS113
D23 VSS49 VSS114 U10
330U_D2E_2.5VM
+ F2 U16
VSS52 VSS117
F11 VSS53 VSS118 U18
1 1 1 1 1 1 1 1 F13 VSS54 VSS119 V2
C76 C77 C78 C79 C80 C81 C82 C83 2
F15 VSS55 VSS120 V7
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J F17 V9
VSS56 VSS121
F19 VSS57 VSS122 V11
2 2 2 2 2 2 2 2
F21 VSS58 VSS123 V13
Near CPU Socket Left side F23 VSS59 VSS124 V15
@ F25 V17
VSS60 VSS125
H7 VSS61 VSS126 W6
4 4
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
+VDDNB decoupling : Northbridge power H23
J4
VSS64 VSS129 N6
+VDDNB VSS65
FOX_PZ6382A-284S-41F_Champlian
1 1 1
C42 C43 C49 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 8 of 52
A B C D E
A B C D E
+1.5V +1.5V
JDDRL
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
4.7U_0805_10V4Z VSS2 DQ4
0.01U_0402_25V7K
1000P_0402_25V8J
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS3 8
1 2 1 9 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_DQS#0 <6>
C84 C85 C10 DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0 DDR_A_DQS0 <6> DDR_A_D[0..63]
13 VSS5 VSS6 14 DDR_A_D[0..63] <6>
DDR_A_D2 15 16 DDR_A_D6
2 1 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 DDR_A_DM[0..7]
17 DQ3 DQ7 18 DDR_A_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_A_D8 DDR_A_D12 1
21 DQ8 DQ12 22
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13 DDR_A_MA[0..15]
25 VSS9 VSS10 26 DDR_A_MA[0..15] <6>
DDR_A_DQS#1 27 28 DDR_A_DM1
<6> DDR_A_DQS#1 DQS#1 DM1
DDR_A_DQS1 29 30 MEM_MA_RST#
<6> DDR_A_DQS1 DQS1 RESET# MEM_MA_RST# <6>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
<6> DDR_A_DQS#2 DQS#2 DM2
DDR_A_DQS2 47 48
<6> DDR_A_DQS2 DQS2 VSS17
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29 +1.5V
DDR_A_D25 DQ24 DQ29 +1.5V
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS#3 <6>
2
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 DDR_A_DQS3 <6>
2
65 66 R310
DDR_A_D26 VSS23 VSS24 DDR_A_D30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31 1K_0402_1%
DQ27 DQ31
71 72
1
VSS25 VSS26
1
+VREF_DQ +VREF_CA
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<6> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6>
75 VDD1 VDD2 76
2
77 78 DDR_A_MA15
NC1 A15
2
2 DDR_A_BS#2 DDR_A_MA14 R315 2
<6> DDR_A_BS#2 79 BA2 A14 80
81 82 R49 1K_0402_1%
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11 1K_0402_1%
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
1
A9 A7
87 88
1
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_A_CLK0 101 102 DDR_A_CLK1 < Close to JDDRH & JDDRL >
<6> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <6>
DDR_A_CLK#0 103 104 DDR_A_CLK#1
<6> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <6>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <6>
DDR_A_BS#0 109 110 DDR_A_RAS#
<6> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6>
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<6> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6>
DDR_A_CAS# 115 116 DDR_A_ODT0
<6> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDR_A_ODT1
A13 ODT1 DDR_A_ODT1 <6>
DDR_CS1_DIMMA# 121 122
<6> DDR_CS1_DIMMA# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 2
DDR_A_DQS#4 135 136 DDR_A_DM4 C235 C351 +1.5V
<6> DDR_A_DQS#4 DQS#4 DM4
DDR_A_DQS4 137 138 C680
<6> DDR_A_DQS4 DQS4 VSS31
139 140 DDR_A_D38 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 1
141 DQ34 DQ39 142 2 2 2 2 2 2 2 2 2 2
3 DDR_A_D35 3
143 DQ35 VSS33 144
145 146 DDR_A_D44 C87 C88 C640 C641 C642 C643 C644 C645 C646 C647
DDR_A_D40 VSS34 DQ44 DDR_A_D45 0.1U_0402_16V4Z
147 DQ40 DQ45 148
DDR_A_D41 1 1 1 1 1 1 1 1 1 1
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS36 DQS#5 DDR_A_DQS#5 <6>
DDR_A_DM5 153 154 DDR_A_DQS5
DM5 DQS5 DDR_A_DQS5 <6>
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
<6> DDR_A_DQS#6 DQS#6 DM6
DDR_A_DQS6 171 172
<6> DDR_A_DQS6 DQS6 VSS43
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 +0.75VS
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 0.1U_0402_16V4Z
VSS48 DQS#7 DDR_A_DQS#7 <6>
DDR_A_DM7 187 188 DDR_A_DQS7 2 2 1
DM7 DQS7 DDR_A_DQS7 <6>
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62 C665 C664 C961
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 1 2
195 VSS51 VSS52 196
197 198 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SA0 EVENT#
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <10,20>
201 SA1 SCL 202 SMB_CK_CLK0 <10,20>
+0.75VS 203 VTT1 VTT2 204 +0.75VS Place near DIMM1
1
4 C91 4
205 G1 G2 206
TYCO_2-2013289-1
0.1U_0402_16V4Z 2
+1.5V +1.5V
JDDRH
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
1000P_0402_25V8J
DDR_B_D1 7 8
DQ1 VSS3
0.1U_0402_16V4Z
4.7U_0805_10V4Z
9 10 DDR_B_DQS#0
VSS4 DQS#0 DDR_B_DQS#0 <6>
1 1 1 DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0 DDR_B_DQS0 <6> DDR_B_D[0..63]
C92 C93 C682 13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6 DDR_B_D[0..63] <6>
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7 DDR_B_DM[0..7]
2 2 2 DQ3 DQ7 DDR_B_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_B_D8 DDR_B_D12 1
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_MA[0..15] <6>
DQ9 DQ13 DDR_B_MA[0..15]
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
<6> DDR_B_DQS#1 DQS#1 DM1
DDR_B_DQS1 29 30 MEM_MB_RST#
<6> DDR_B_DQS1 DQS1 RESET# MEM_MB_RST# <6>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
<6> DDR_B_DQS#2 DQS#2 DM2
DDR_B_DQS2 47 48
<6> DDR_B_DQS2 DQS2 VSS17
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
VSS22 DQS#3 DDR_B_DQS#3 <6>
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3 DDR_B_DQS3 <6>
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<6> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <6>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
2 DDR_B_BS#2 NC1 A15 DDR_B_MA14 2
<6> DDR_B_BS#2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_B_CLK0 101 102 DDR_B_CLK1
<6> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <6>
DDR_B_CLK#0 103 104 DDR_B_CLK#1
<6> DDR_B_CLK#0 CK0# CK1# DDR_B_CLK#1 <6>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 <6>
DDR_B_BS#0 109 110 DDR_B_RAS#
<6> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <6>
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_CS0_DIMMB#
<6> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <6>
DDR_B_CAS# 115 116 DDR_B_ODT0
<6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 VDD15 VDD16 118
DDR_B_MA13 119 120 DDR_B_ODT1
A13 ODT1 DDR_B_ODT1 <6>
DDR_CS1_DIMMB# 121 122
<6> DDR_CS1_DIMMB# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
4.7U_0805_10V4Z
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 1
DDR_B_DQS#4 135 136 DDR_B_DM4
<6> DDR_B_DQS#4 DQS#4 DM4
DDR_B_DQS4 137 138
<6> DDR_B_DQS4 DQS4 VSS31
139 140 DDR_B_D38 C683 C352 C353
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2 2
141 DQ34 DQ39 142
3 DDR_B_D35 3
143 DQ35 VSS33 144
145 146 DDR_B_D44
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152 DDR_B_DQS#5 <6>
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5 DDR_B_DQS5 <6>
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 +1.5V
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166 2 2 2 2 2 2 2 2 2 2
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6 C666 C667 C668 C669 C670 C671 C672 C673 C674 C677
<6> DDR_B_DQS#6 DQS#6 DM6
DDR_B_DQS6 171 172
<6> DDR_B_DQS6 DQS6 VSS43 1 1 1 1 1 1 1 1 1 1
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184 C128 Co-layout with C86
185 186 DDR_B_DQS#7
VSS48 DQS#7 DDR_B_DQS#7 <6>
DDR_B_DM7 187 188 DDR_B_DQS7 +0.75VS
DM7 DQS7 DDR_B_DQS7 <6>
189 190 +1.5V +1.5V
VSS49 VSS50
330U_X_2VM_R6M
390U_2.5V_M_R10
DDR_B_D58 191 192 DDR_B_D62 0.1U_0402_16V4Z
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194 2 2 1 1 1
195 VSS51 VSS52 196
197 198 C676 C675 C925 + @C86 +
SA0 EVENT# C128
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <9,20> 1 1 2
201 SA1 SCL 202 SMB_CK_CLK0 <9,20>
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2 2
+0.75VS 203 VTT1 VTT2 204 +0.75VS
4 4
205 G1 G2 206
LOTES_AAA-DDR-111-K01
DIMM_B STD H:9.2 mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 10 of 52
A B C D E
A B C D E
U3B
PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N0 D4 A5 PCIE_MTX_GRX_P0 C95 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P[0..15]
<34> PCIE_GTX_C_MRX_P[0..15] GFX_RX0P GFX_TX0P PCIE_MTX_C_GRX_P[0..15] <34>
PCIE_GTX_C_MRX_P0 C4 PART 2 OF 6 B5 PCIE_MTX_GRX_N0 C96 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P1 GFX_RX0N GFX_TX0N PCIE_MTX_GRX_P1 C97 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N[0..15]
<34> PCIE_GTX_C_MRX_N[0..15] A3 GFX_RX1P GFX_TX1P A4 1 2 PCIE_MTX_C_GRX_N[0..15] <34>
PCIE_GTX_C_MRX_N1 B3 B4 PCIE_MTX_GRX_N1 C98 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N2 GFX_RX1N GFX_TX1N PCIE_MTX_GRX_P2 C99 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
C2 GFX_RX2P GFX_TX2P C3 1 2
PCIE_GTX_C_MRX_P2 C1 B2 PCIE_MTX_GRX_N2 C100 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_N3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C101 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
E5 GFX_RX3P GFX_TX3P D1 1 2
PCIE_GTX_C_MRX_P3 F5 D2 PCIE_MTX_GRX_N3 C102 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PCIE_GTX_C_MRX_N4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C103 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
G5 GFX_RX4P GFX_TX4P E2 1 2
PCIE_GTX_C_MRX_P4 G6 E1 PCIE_MTX_GRX_N4 C104 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_N5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C105 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
H5 GFX_RX5P GFX_TX5P F4 1 2
PCIE_GTX_C_MRX_P5 H6 F3 PCIE_MTX_GRX_N5 C106 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_P6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C107 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
J6 GFX_RX6P GFX_TX6P F1 1 2
1 PCIE_GTX_C_MRX_N6 PCIE_MTX_GRX_N6 C108 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 1
J5 GFX_RX6N GFX_TX6N F2 1 2
PCIE_GTX_C_MRX_N7 J7 H4 PCIE_MTX_GRX_P7 C109 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_P7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C110 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
J8 GFX_RX7N GFX_TX7N H3 1 2
PCIE_GTX_C_MRX_N8 L5 H1 PCIE_MTX_GRX_P8 C111 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_P8 GFX_RX8P GFX_TX8P PCIE_MTX_GRX_N8 C112 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
L6 GFX_RX8N GFX_TX8N H2 1 2
PCIE_GTX_C_MRX_N9 M8 J2 PCIE_MTX_GRX_P9 C113 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_P9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C114 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
L8 GFX_RX9N GFX_TX9N J1 1 2
880MR1@ RS780M_FCBGA528
U3A
H_CADOP[0..15] H_CADOP0 Y25 D24 H_CADIP0 H_CADIP[0..15]
H_CADOP[0..15] <5> HT_RXCAD0P HT_TXCAD0P H_CADIP[0..15] <5>
H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
H_CADON[0..15] H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1 H_CADIN[0..15]
H_CADON[0..15] <5> V22 HT_RXCAD1P HT_TXCAD1P E24 H_CADIN[0..15] <5>
H_CADON1 V23 E25 H_CADIN1
H_CADOP2 HT_RXCAD1N HT_TXCAD1N H_CADIP2
V25 HT_RXCAD2P HT_TXCAD2P F24
H_CADON2 V24 F25 H_CADIN2
H_CADOP3 HT_RXCAD2N HT_TXCAD2N H_CADIP3
U24 HT_RXCAD3P HT_TXCAD3P F23
H_CADON3 U25 F22 H_CADIN3
H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4
T25 HT_RXCAD4P HT_TXCAD4P H23
H_CADON4 T24 H22 H_CADIN4
HT_RXCAD4N HT_TXCAD4N
HYPER TRANSPORT CPU I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 11 of 52
A B C D E
A B C D E
CRT/TVOUT
F17 Y(DFT_GPIO2)
L4 F15 B18
0_0603_5% +AVDD2 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC)
TXOUT_U0N(NC) A18
1 1 G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
C142 C145 G17 B17
REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2)
E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
1 2.2U_0603_6.3V4Z 0.1U_0402_16V7K 1
F18 GREENb(NC) TXOUT_U2N(NC) D21
2 2
E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 D19 < LVDS dual channel : channel 2 >
BLUEb(NC) TXOUT_U3N(NC)
+1.8VS UMA_CRT_HSYNC A11 B16
<15> UMA_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
L6 UMA_CRT_VSYNC B11 A16
<15> UMA_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
1 2 BLM18PG121SN1D_0603 +AVDDQ F8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16
1 E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17
C148 +1.8VS
R65 1 2 715_0402_1% G14 L8
2.2U_0603_6.3V4Z DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLTP18 BLM18PG121SN1D_0603 1
VDDLTP18(NC) A13 2
2 +NB_PLLVDD A12
+NB_PLLVDD PLLVDD(NC) VSSLTP18(NC) B13 1
+NB_HTPVDD +NB_HTPVDD D14 C153
PLLVDD18(NC) +VDDLT18
B12 A15
LVTM
PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z
B15
PLL PWR
+1.1VS VDDLT18_2(NC) 2
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
L2 B14
+NB_PLLVDD VDDLT33_2(NC)
1 2 BLM18PG121SN1D_0603 +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
1 E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
C141 D15 +1.8VS
VSSLT2(VSS)
<15,19,25,27,30,31,34> PLT_RST#
R66 1 2 0_0402_5% NB_RESET# D8 SYSRESETb VSSLT3(VSS) C16 L10
2.2U_0603_6.3V4Z NB_PWRGD A10 C18 +VDDLT18 BLM18PG121SN1D_0603 1 2
2 <20> NB_PWRGD POWERGOOD VSSLT4(VSS)
NB_LDTSTOP# C10 C20 1 1
LDTSTOPb VSSLT5(VSS) C156 C157
C12 E20
PM
<19> CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
+1.8VS C25 0.1U_0402_16V7K 4.7U_0805_10V4Z
<19> HT_REFCLKP HT_REFCLKP 2 2
L5 C24
<19> HT_REFCLKN HT_REFCLKN
1 2 BLM18PG121SN1D_0603 +NB_HTPVDD
1 NB_REFCLK_P E11
<19> NB_REFCLK_P REFCLK_P/OSCIN(OSCIN)
CLOCKs
C146 NB_REFCLK_N F11 E9
<19> NB_REFCLK_N REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP) F7
2.2U_0603_6.3V4Z R69 1 2 4.7K_0402_5% T2 G12
2 2 R70 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) 2
1 2 4.7K_0402_5% T1 GFX_REFCLKN
U1 GPP_REFCLKP
U2 GPP_REFCLKN
3 +1.8VS 3
+1.8VS
R83
C149
R366 1 2 1K_0402_1% CPU_LDT_REQ# 2.2K_0402_5%
1 2
1
5
0.1U_0402_16V7K U2
2
P
B NB_LDTSTOP#
Y 4
<7,19> LDT_STOP# 1 A
G
NC7SZ08P5X_NL_SC70-5
3
1 2
R101 0_0402_5%
@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 12 of 52
A B C D E
2 1
U3D
PAR 4 OF 6
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
B B
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
880MR1@ RS780M_FCBGA528
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 13 of 52
2 1
A B C D E
U3E < Main IO power for PCI-E graphics, SB, and GPP interfaces >
2A < Digital IO power for HyperTransport interface >
+1.1VS 2 1 L11 0_0805_5% +VDDHT J17 A6 +VDDA11PCIE FBMA-L11-201209-221LMA30T_0805 1 2 L44 +1.1VS
VDDHT_1 VDDPCIE_1
1 1 1 1 1 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6
C1126
C173
C174
C160
C162
C163
C171
C172
C165 C166 C167 C168 C159 L16 C6 VDDA_12=2.5A
VDDHT_3 VDDPCIE_3
M16 VDDHT_4 VDDPCIE_4 D6
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K P16 E6 1 1 1 1 2 2
2 2 2 2 2 VDDHT_5 VDDPCIE_5
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
2A < IO power for HyperTransport receive interface > VDDPCIE_8 H8
2 2 2 2 1 1
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 L13 0_0805_5% +VDDHTRX H18 J9
VDDHTRX_1 VDDPCIE_9
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 G19 VDDHTRX_2 VDDPCIE_10 K9
C179 C164 C169 C170 C161 F20 M9
1 VDDHTRX_3 VDDPCIE_11 1
E21 VDDHTRX_4 VDDPCIE_12 L9
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K D22 P9
2 2 2 2 VDDHTRX_5 VDDPCIE_13
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
2A < IO power for HyperTransport transmit interface > VDDPCIE_16 V9
+1.1VS 2 1 L14 0_0805_5% +VDDHTTX AE25 U9
VDDHTTX_1 VDDPCIE_17
1 1 1 1 1 AD24 VDDHTTX_2
C1127 C175 C176 C177 C178 AC23 K12
VDDHTTX_3 VDDC_1
AB22 VDDHTTX_4 VDDC_2 J14
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AA21 U16 +NB_CORE
2 2 2 2 2 VDDHTTX_5 VDDC_3
Y20 VDDHTTX_6 VDDC_4 J11
W19 VDDHTTX_7 VDDC_5 K15 < Core power > VDD_CORE:GM=5A/PM=10A
POWER
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14
T17 L11 @
VDDHTTX_10 VDDC_8
C191
C182
C187
C193
C194
C180
C188
C183
C195
R17 VDDHTTX_11 VDDC_9 M13
C184
C196
C189
P17 VDDHTTX_12 VDDC_10 M15 1 C1129 Co-layout with C189
M17 VDDHTTX_13 VDDC_11 N12 2 2 2 2 2 2 2 2 2 1 1
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > N14 +
L15 0_0805_5% +VDDA18PCIE VDDC_12 +NB_CORE
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0805_10V4Z
10U_0805_10V4Z
330U_D2E_2.5VM
1 1 1 1 1 1 P10 VDDA18PCIE_2 VDDC_14 P13
C181 C1128 C185 C190 C186 C192 1 1 1 1 1 1 1 1 1 2 2 2
K10 VDDA18PCIE_3 VDDC_15 P14 1
M10 VDDA18PCIE_4 VDDC_16 R12
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K L10 R15 + C1129
2 2 2 2 2 2 VDDA18PCIE_5 VDDC_17 330U_2.5V_M
W9 VDDA18PCIE_6 VDDC_18 T11
H9 VDDA18PCIE_7 VDDC_19 T15
2
T10 VDDA18PCIE_8 VDDC_20 U12
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
2 2
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
< 1.8V IO transform power > VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
1 G9 VDD18_2
C197 AE11 H11 < 3.3V IO power >
VDD18_MEM1(NC) VDD33_1(NC)
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12 +3VS
1U_0402_6.3V4Z 1 1
2 880MR1@ RS780M_FCBGA528 C198 C199
0.1U_0402_16V4Z 0.1U_0402_16V4Z
U3F 2 2
GROUND
W22 VSSAHT23 VSSAPCIE23 U4
W24 VSSAHT24 VSSAPCIE24 V8
W25 VSSAHT25 VSSAPCIE25 V6
Y21 VSSAHT26 VSSAPCIE26 W1
AD25 VSSAHT27 VSSAPCIE27 W2
VSSAPCIE28 W4
L12 VSS11 VSSAPCIE29 W7
M14 VSS12 VSSAPCIE30 W8
N13 VSS13 VSSAPCIE31 Y6
P12 VSS14 VSSAPCIE32 AA4
P15 VSS15 VSSAPCIE33 AB5
R11 VSS16 VSSAPCIE34 AB1
R14 VSS17 VSSAPCIE35 AB7
T12 VSS18 VSSAPCIE36 AC3
U14 VSS19 VSSAPCIE37 AC4
U11 VSS20 VSSAPCIE38 AE1
U15 VSS21 VSSAPCIE39 AE4
V12 VSS22 VSSAPCIE40 AB2
W11 VSS23
W15 VSS24
AC12 VSS25 VSS1 AE14
AA14 VSS26 VSS2 D11
Y18 VSS27 VSS3 G8
AB11 VSS28 VSS4 E14
AB15 VSS29 VSS5 E15
AB17 VSS30 VSS6 J15
AB19 VSS31 VSS7 J12
AE20 VSS32 VSS8 K14
AB21 VSS33 VSS9 M11
4 4
K11 VSS34 VSS10 L15
880MR1@ RS780M_FCBGA528
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 14 of 52
A B C D E
A B C D E
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K > < VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >
< RS880 use register to control PCI-E configure > < DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
D1 RS880:SUS_STAT#
<12,20> SUS_STAT# @ 2 1 CH751H-40PT_SOD323-2 PLT_RST# <12,19,25,27,30,31,34>
1. Disable (RS880)
0 : Enable (RS880)
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 15 of 52
A B C D E
A B C D E
+5VS
D7 +R_CRT_VCC +CRT_VCC
< CRT CONNECTOR > 2 F1
1 1 2 1A_6VDC_MINISMDC110
3 1
C237
RB491D_SOT23-3 @ 0.1U_0402_16V4Z
2
1
D19 D20 D21
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
1 1
+3VS JCRT
6
3
RGND
11 ID0
RED_L 1 Red
7 GGND
D_DDCDATA 12
L22 GREEN_L SDA
2 Green
RED 1 2 NBQ100505T-800Y-N_2P RED_L 8
<35> RED BGND
HSYNC 13
L23 BLUE_L Hsync
3 Blue
GREEN 1 2 NBQ100505T-800Y-N_2P GREEN_L +CRT_VCC 9
<35> GREEN +5V
VSYNC 14
L24 Vsync
4 res
BLUE 1 2 NBQ100505T-800Y-N_2P BLUE_L 10
<35> BLUE SGND
D_DDCCLK 15 SCL
5 GND
1 1 1 1 1 1
1
1
C239 C240 C241 C242 C243 C244 16
R98 R99 R100 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K GND
17 GND
150_0402_1% 150_0402_1% 150_0402_1%
2 2 2 2 2 2
@ SUYIN_070546FR015S263ZR
2
+CRT_VCC
2 R817 2
C245 1 2 0.1U_0402_16V4Z 1 2 10K_0402_5%
5
1
P
OE#
R_HSYNC 2 4 D_HSYNC L25 1 2 10_0402_5% HSYNC
<35,42> R_HSYNC A Y
G
U5
SN74AHCT1G125GW_SOT353-5 < SYNC SIGNAL >
3
L26 1 2 10_0402_5% VSYNC
+CRT_VCC
1 1
C247 C248
@ 10P_0402_50V8J @ 10P_0402_50V8J
5
1
2 2
P
OE#
R_VSYNC 2 4 D_VSYNC
<35,42> R_VSYNC A Y
G
U6
SN74AHCT1G125GW_SOT353-5
3 +CRT_VCC
+3VS
3 3
1
1
R824 R825 +3VS
4.7K_0402_5% 4.7K_0402_5% R805 R806
2K_0402_1% 2K_0402_1%
5
2
Q32B
2
CRT_DATA 4 3 2N7002KDW_SOT363-6 D_DDCDATA
<35> CRT_DATA
1
C255
@ 33P_0402_50V8K
< Display Data Channel >
2
+3VS
2
Q32A
CRT_CLK 1 6 2N7002KDW_SOT363-6 D_DDCCLK
<35> CRT_CLK
1 1
1
2 2
4
FOR EMI 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 16 of 52
A B C D E
A B C D E
1
R90
R807 150_0603_5% 100K_0402_5%
1 1
2
C259
W=60mils
6 2
2
0.1U_0402_16V7K
Q33A 1
3
S
R91 G
2N7002KDW_SOT363-6 2 1 2 47K_0402_5% 2 Q4
1 +LCD_VDD
C260 D AO3413_SOT23
1
0.01U_0402_25V7K
W=60mils
2 Inrush current = 0A
3
1
C262
Q33B
ENVDD 5 0.1U_0402_16V7K
<35> VGA_ENVDD 2
2N7002KDW_SOT363-6
4
2
R3
10K_0402_5%
1
2 < LVDS Connector > 2
INT_MIC_DATA
0.1U_0402_16V4Z +3VS
1 2 INT_MIC_CLK
+3VS_LVDS_CAM C265
3
0_0603_5% W=20mils JLVDS D12 LCD_EDID_CLK 2.2K_0402_5% 2 1 R117
+3VS R808 1 2 2 1
USB20_P9_L 2 1
4 4 3 3 LCD_TXCLK+ <35>
USB20_N9_L 6 5 LCD_EDID_DATA 2.2K_0402_5% 2 1 R118
6 5 LCD_TXCLK- <35>
8 8 7 7
10 9 PACDN042Y3R_SOT23-3
<35> LCD_TXOUT0+ LCD_TZCLK+ <35>
1
10 9
<35> LCD_TXOUT0- 12 12 11 11 LCD_TZCLK- <35>
<35> LCD_TXOUT1+ 14 14 13 13
<35> LCD_TXOUT1- 16 16 15 15 LCD_EDID_CLK <35>
<35> LCD_TXOUT2+ 18 18 17 17 LCD_EDID_DATA <35>
<35> LCD_TXOUT2- 20 20 19 19 INT_MIC_CLK <28>
22 22 21 21 INT_MIC_DATA <28>
24 23 +3VS
<35> LCD_TZOUT0+ 24 23
26 25 INVT_PWM
<35> LCD_TZOUT0- 26 25
<35> LCD_TZOUT1+ 28 28 27 27
<35> LCD_TZOUT1- 30 30 29 29 1 1
32 31 +LCDVDD_R
<35> LCD_TZOUT2+ 32 31
34 33 BKOFF#_R @ C152 C264
<35> LCD_TZOUT2- 34 33
36 35 680P_0402_50V7K 0.1U_0402_16V4Z
36 35 B+ 2 2
38 38 37 37 +LCD_INV
3 Rated Current MAX:3000mA 3
+LCD_INV 40 40 39 39
42 41 L45 2 1
GND GMD FBMA-L11-201209-221LMA30T_0805
ACES_87242-4001-09 1 1 1
@ C151
C268 C263 @ 680P_0402_50V7K
68P_0402_50V8J 0.1U_0402_25V6
2 2 2
BKOFF#_R 33_0402_5% 2 1 R9
BKOFF# <30>
1
R200
10K_0402_5%
1.5A
2
L12
L20 +LCDVDD_R 2 1 0_0805_5% +LCD_VDD
4 3 USB20_P9_L
<20> USB20_P9 4 3 EC_INVT_PWM 1 2 INVT_PWM 1 1
<30> EC_INVT_PWM
@ R96 0_0402_5% C266 C267
1
1 2 USB20_N9_L
<20> USB20_N9 1 2
1 2 R319 0.1U_0402_16V7K 4.7U_0805_10V4Z
<35> VGA_INVT_PWM 2 2
R97 0_0402_5% 10K_0402_5%
WCM-2012-900T_0805
2
4 10P_0402_50V8J 10_0402_5% 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 17 of 52
A B C D E
A B C D E
H@ F2
+5VS H@ D11 2 1 2 1 1.1A_6V_MINISMDC110F-2 +HDMI_5V_OUT
RB161M-20_SOD123-2 1
C22
H@
R121 R125 0.1U_0402_16V7K
HDMI_TX0- @ 0_0402_5% HDMI_R_D0- HDMI_TX1- @ 0_0402_5% HDMI_R_D1- 2
1 2 1 2
4 4 3 3 4 4 3 3
1 1
H@ OCE2012120YZF_0805 H@ OCE2012120YZF_0805 < HDMI Connector >
H@ C275 1 2 0.1U_0402_16V7K HDMI_TX1+
<35> HDMI_TXD1+
H@ C276 1 2 0.1U_0402_16V7K HDMI_TX1- R122 R126 JHDMI
<35> HDMI_TXD1-
HDMI_TX0+ @ 1 2 0_0402_5% HDMI_R_D0+ HDMI_TX1+ @ 1 2 0_0402_5% HDMI_R_D1+ HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16
R123 R127 HDMI_SCLK SDA
15 SCL
H@ C277 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_TX2- @ 1 2 0_0402_5% HDMI_R_D2- HDMI_CLK- @ 1 2 0_0402_5% HDMI_R_CK- 14
<35> HDMI_TXD2+ Reserved
H@ C274 1 2 0.1U_0402_16V7K HDMI_TX2- 13
<35> HDMI_TXD2- CEC
HDMI_R_CK- 12 20
CK- GND
11 CK_shield GND 21
L18 L16 HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
1 1 2 2 1 1 2 2 9 D0- GND 23
8 D0_shield
H@ C278 1 2 0.1U_0402_16V7K HDMI_CLK+ HDMI_R_D0+ 7
<35> HDMI_CLK0+ D0+
H@ C279 1 2 0.1U_0402_16V7K HDMI_CLK- 4 3 4 3 HDMI_R_D1- 6
<35> HDMI_CLK0- 4 3 4 3 D1-
5 D1_shield
H@ OCE2012120YZF_0805 H@ OCE2012120YZF_0805 HDMI_R_D1+ 4
HDMI_R_D2- D1+
3 D2-
R124 R128 2
HDMI_TX2+ @ 0_0402_5% HDMI_R_D2+ HDMI_CLK+ @ 0_0402_5% HDMI_R_CK+ HDMI_R_D2+ D2_shield
1 2 1 2 1 D2+
@ SUYIN_100042MR019S153ZL
2 2
< Close to Connector >
+3VS
+3VS +HDMI_5V_OUT
1
H@ H@
1
R826 R827
4.7K_0402_5% 4.7K_0402_5% R53 HDMI_R_D0- H@ R104 1 2 499_0402_1%
2
H@ 2.2K_0402_5%
G
BSH111_SOT23-3
2
3 1 HDMI_SDATA
<35> HDMIDAT_VGA
S
1
2
H@ R54
G
Q26 2.2K_0402_5%
BSH111_SOT23-3 H@
3 1 HDMI_SCLK
2
<35> HDMICLK_VGA HDMI_R_D1- H@ R108 1 2 499_0402_1%
S
3 3
Q34A
HDMI_R_D2+ H@ R114 1 2 499_0402_1% 6 1
2N7002KDW_SOT363-6
HDMI_R_D2- H@ R116 1 2 499_0402_1%
2
< Hot-plug detection & level shift > +5VS
+5VS
R120 1K_0402_5%
HDMI_HPD_R 1 2 HDMI_HPD
2
+3VS
2
R110 C281
H@ H@
1
100K_0402_5% 0.1U_0402_16V4Z
R113 1
1
2.2K_0402_5%
2 H@
C280
2
5
1
H@
0.1U_0402_16V4Z
P
OE#
1
2 A Y 4 HPD <35>
G
H@ U7
R119
3
100K_0402_5%
4 4
1
SN74AHCT1G125GW_SOT353-5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 18 of 52
A B C D E
A B C D E
R325 33_0402_5% P1
SB800 Part 1 of 5
W2
A_RST# PCIE_RST# PCICLK0
2 1 L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 <23>
PCI CLKS
PCICLK2/GPO37 W3 PCI_CLK2 <23>
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4 PCI_CLK3 <23>
<11> SB_RX0P A_TX0P PCICLK3/GPO38
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 PCI_CLK4 <23>
<11> SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
<11> SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2
<11> SB_RX1N A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K SB_RX2P_C AB29
<11> SB_RX2P A_TX2P
C580 1 2 0.1U_0402_16V7K SB_RX2N_C AB28
<11> SB_RX2N A_TX2N
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1
<11> SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
1 <11> SB_RX3N A_TX3N AD1/GPIO1 1
AD2/GPIO2 AA3
<11> SB_TX0P AE24 A_RX0P AD3/GPIO3 AB1
<11> SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5
<11> SB_TX1P AD25 AB2
B GPP_RX3P AD30/GPIO30
Y 4 PLT_RST# <12,15,25,27,30,31,34> W25 GPP_RX3N AD31/GPIO31 AH3
A_RST# 1 AA8
A CBE0#
G
PCI INTERFACE
NC7SZ08P5X_NL_SC70-5 AD5
2 CBE1# 2
AD8
3
@ CBE2#
2 1 CBE3# AA10
R328 8.2K_0402_5% AE8
FRAME#
DEVSEL# AB9
<12> CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
<12> CLK_SBSRC_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
NB_REFCLK_P U29 AF5
<12> NB_REFCLK_P NB_DISP_CLKP STOP#
NB_REFCLK_N U28 AE6
<12> NB_REFCLK_N NB_DISP_CLKN PERR#
SERR# AE4
+3VS HT_REFCLKP T26 AE11
+1.8VS <12> HT_REFCLKP NB_HT_CLKP REQ0#
HT_REFCLKN T27 AH5
<12> HT_REFCLKN NB_HT_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AH4
2
1 2 CLK_48M_CR_R L25
<26> CLK_48M_CR 14M_25M_48M_OSC
Y5 R370
1M_0402_5% R112 0_0402_5% C1 SB_32KHI
32K_X1
1
1
B2 +RTCVCC
25M_CLK_X2 INTRUDER_ALERT# D8
L27 25M_X2 VDDBT_RTC_G B1
BAS40-04_SOT23-3
@ R332 20M_0402_5%
@R332
1 2 SB820M_FCBGA605 W=20mils
1 2 1 2 1 2 +CHGRTC
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1 1 1
C582 1 2 18P_0402_50V8J SB_32KHI J1 C583
2
C584 C585 @ JUMP_43X39
4 Y3 4
1
2 2 2
20M_0603_5%
1
4 OSC NC 3
Close to SB for Clear CMOS
1
R335 1 2
OSC NC
2
32.768KHZ_12.5PF_Q13MC14610002
C586 1 2 SB_32KHO
18P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 19 of 52
A B C D E
A B C D E
U8D
J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 PAD T20
K1 RI#/GEVENT22#
D3 G19 USB_RCOMP 1 2
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 11.8K_0402_1% R338
<30> PM_SLP_S3# F1 SLP_S3#
<30> PM_SLP_S5# H1 SLP_S5#
USB 2.0
<9,10> SMB_CK_DAT0 SMB_CK_DAT0 AE22 G14
SMB_CK_CLK1 SDA0/GPIO47 USB_HSD7N
<27> SMB_CK_CLK1 F5 SCL1/GPIO227
2
GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_P5 <26>
AJ21 C16 USB20_N5 USB-4 Card Reader (3 IN 1)
USB20_N5 <26>
1
2 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N 2
H4 DDR3_RST#/GEVENT7#
HDMI_DET D5 B14
GBE_LED0/GPIO183 USB_HSD4P
D7 GBE_LED1/GEVENT9# USB_HSD4N A14
2
G5 GBE_LED2/GEVENT10#
R107 K3 E18
@ GBE_STAT0/GEVENT11# USB_HSD3P
10K_0402_5% AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
EHCI1 / OHCI1
J16 USB20_P2
USB20_P2 <24>
1
USB_HSD2P USB20_N2
H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18 USB20_N2 <24> USB-2 USB/eSATA <Wake Up support>
EC_LID_OUT# D1
<30> EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6#
E4 B17 USB20_P1
USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USB20_P1 <29>
USB OC
D4 A17 USB20_N1 USB-1 Right side
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USB20_N1 <29>
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC#2 F7 A16 USB20_P0
<24,30> USB_OC#2 USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 <29>
E7 B16 USB20_N0 USB-0 Right side
USB_OC1#/TDI/GEVENT13# USB_HSD0N USB20_N0 <29> +3VALW
@ R80 USB_OC#0 F8
<29,30> USB_OC#0 USB_OC0#/TRST#/GEVENT12#
@C143
@ C143 2 1 10P_0402_50V8J 2 1 AZ_BITCLK_HD
R345 1 2 33_0402_5%
<28> AZ_BITCLK_HD
10_0402_5% <31> HDA_BITCLK_MDC R136 1 2 33_0402_5%
@C147
@ C147 2 1 10P_0402_50V8J HDA_BITCLK_MDC <28> AZ_SDOUT_HD R346 1 2 33_0402_5% M3 D25
R138 33_0402_5% AZ_BITCLK SCL2/GPIO193
<31> HDA_SDOUT_MDC 1 2 N1 AZ_SDOUT SDA2/GPIO194 F23
2
L2 B26 SB_SIC
<23> HDA_SDOUT AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
@C223
@ C223 2 110P_0402_50V8J AZ_BITCLK_HD M2 E26 SB_SID @ R73 @ R75
@R75 R78
HD AUDIO
<28> AZ_SDIN0_HD AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
<31> HDA_SDIN1 M1 F25 10K_0402_5% 10K_0402_5% 10K_0402_5%
R347 33_0402_5% AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
<28> AZ_SYNC_HD 1 2 M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
<31> HDA_SYNC_MDC R142 1 2 33_0402_5% N2 F22 GPIO199 <23>
1
R348 33_0402_5% AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO201
<31> HDA_RST#_MDC
R144
1 2
33_0402_5%
P2 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 E21 GPIO200 <23> STRAP PIN GPIO202
<28> AZ_RST_HD# 1 2
G24 GPIO201 GPIO203
GBE_COL KSI_0/GPIO201 GPIO202
T1 GBE_COL KSI_1/GPIO202 G25
2
GBE_CRS T4 E28 GPIO203
GBE_CRS KSI_2/GPIO203
2
+3VALW L6 E29 GPIO204 R74 R77 @ R79
@R79
3 GBE_MDIO GBE_MDCK KSI_3/GPIO204 GPIO205 1K_0402_1% 1K_0402_1% 10K_0402_5% 3
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
1 2 GBE_MDIO U1 C29
1
R352 10K_0402_5% GBE_RXD3 KSI_6/GPIO207
U3 C28
1
GBE_PHY_INTR GBE_RXD2 KSI_7/GPIO208
1 2 T2 GBE_RXD1
GBE LAN
R358 10K_0402_5% U2 B28 GPIO201 GPIO202 GPIO203
GBE_COL GBE_RXD0 KSO_0/GPIO209
1 2 T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
EMBEDDED CTRL
R353 10K_0402_5% GBE_RXERR V5 B27
GBE_CRS GBE_RXERR KSO_2/GPIO211
1 2 P5 GBE_TXCLK KSO_3/GPIO212 D26 High High High Nile-M
R354 10K_0402_5% M5 A26 Nile
GBE_RXERR GBE_TXD3 KSO_4/GPIO213
1 2 P9 GBE_TXD2 KSO_5/GPIO214 C26
R356 10K_0402_5% T7 A24 High High Low Nile-S
GBE_TXD1 KSO_6/GPIO215
P7 GBE_TXD0 KSO_7/GPIO216 B25
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
Low Low Low +3VALW
P4 GBE_PHY_PD KSO_9/GPIO218 D24 Danube Marseille
M9 GBE_PHY_RST# KSO_10/GPIO219 B24 Danube
+3VALW GBE_PHY_INTR V7 C24
GBE_PHY_INTR KSO_11/GPIO220
KSO_12/GPIO221 B23 Low Low High Danube Hamburg
E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
EMBEDDED CTRL
2
KSO_17/GPIO226 B22
R95 D27 4PCS@ @ R56
+3VALW 10K_0402_5% PS2KB_DAT/GPIO189 R51
F28 PS2KB_CLK/GPIO190
Low Low Madison LP 10K_0402_5%
F29 10K_0402_5%
PS2M_DAT/GPIO191
E27
1
1
PS2M_CLK/GPIO192 GPIO204
Low High None
CIR_EN# GPIO205
SB820M_FCBGA605
2
1 2 EC_LID_OUT# High Low Park XT
2
1
R360 2.2K_0402_5%
1
1 2 H_THERMTRIP#
R361 10K_0402_5%
1 2 SMB_CK_CLK1
R362 2.2K_0402_5%
1
R363
2
2.2K_0402_5%
SMB_CK_DAT1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 20 of 52
A B C D E
A B C D E
U8B
SATA_STX_DRX_P0 AH9
SB800 AH28
1 <24> SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
SATA_STX_DRX_N0 AJ9 Part 2 of 5 AG28
<24> SATA_STX_DRX_N0 SATA_TX0N FC_FBCLKOUT
HDD AJ8
FC_FBCLKIN AF26
<24> SATA_RXN0_C SATA_RX0N
<24> SATA_RXP0_C AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
SATA_STX_DRX_P1 AH10 AG26
<24> SATA_STX_DRX_P1 SATA_TX1P FC_WE#/GPIOD148
SATA_STX_DRX_N1 AJ10 AF27
<24> SATA_STX_DRX_N1 SATA_TX1N FC_CE1#/GPIOD149
AE29
ODD AG10
FC_CE2#/GPIOD150
AF29
<24> SATA_RXN1_C SATA_RX1N FC_INT1/GPIOD144
<24> SATA_RXP1_C AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
FLASH
<24> SATA_RXP3_C SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17
SERIAL ATA
SATA_RX4P
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
R364 2 1 1K_0402_1% SATA_CALRP AB14 W8
SATA_CALRP FANIN2/GPIO58
+1.1VS_SATA R365 2 1 931_0402_1% SATA_CALRN AA14 SATA_CALRN
TEMPIN0/GPIO171 B6
A6 R43 1 2 150K_0402_5% +3VALW
TEMPIN1/GPIO172
<32> SATA_LED# AD11 SATA_ACT#/GPIO67 TEMPIN2/GPIO173 A5
TEMPIN3/TALERT#/GPIO174 B5
TEMP_COMM C7 2 1 D22 ACIN <30,32,43>
+3VS R367 1 2 10K_0402_5% CH751H-40PT_SOD323-2
VIN0/GPIO175 A3
SATA_X1
HW MONITOR
AD16 SATA_X1 VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
A7 MEM_1V5
@C588
@ C588 1 VIN4/GPIO179
2 27P_0402_50V8J SATA_X1
VIN5/GPIO180 B7
VIN6/GBE_STAT3/GPIO181 B8
SATA_X2 AC16 A8
SATA_X2 VIN7/GBE_LED3/GPIO182
1
2
@
@ R368
Y4 10M_0402_5%
DO J5 G27
1
DI SPI_DI/GPIO164 NC1
25MHZ_20PF_7A25000012 E2 Y2
SPI ROM
SATA_X2 CLK SPI_DO/GPIO163 NC2
1 2 K4 SPI_CLK/GPIO162
@C589
@ C589 27P_0402_50V8J CS# K9 SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161
SB820M_FCBGA605
3 +3VALW 3
20mils U47
8 VCC VSS 4
1
C445 3 W
0.1U_0402_16V4Z 7
2 HOLD
CS# 1 S
CLK 6 C
DI 5 2 DO
D Q
MX25L1605DM2I-12G_SO8-200mil
MEM_1V5 is for gating the
2
0.1U_0402_16V4Z
5
1 @U23
@U23
MEM_1V5 2
P
C155 B
Y 4 1 2 VDDR_SW <48>
10P_0402_50V8J 1 2 1 @ R424 33_0402_5%
<19,23> PCI_AD24 A
G
2 @R422
@ R422 0_0402_5%
@ 2
NC7SZ08P5X_NL_SC70-5
3
@ C689
150P_0402_50V8J
1
1 @ 2
4 R423 0_0402_5% 4
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 21 of 52
A B C D E
A B C D E
+1.1VS_VDDC U8E
510mA
1 2 +1.1VS
U8C R369 0_0805_5%
Part 3 of 5
SB800
131mA SB800 10U_0805_10V4Z C590
Y14 VSSIO_SATA_1 VSS_1 AJ2
+3VS AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 1 2 Y16 VSSIO_SATA_2 VSS_2 A28
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AB16 VSSIO_SATA_3 VSS_3 A2
1 2 Y19 N17 1U_0402_6.3V4Z 2 1 C596 AC14 E5
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_4 VSS_4
CORE S0
C591 22U_0805_6.3V6M AE5 U13 1U_0402_6.3V4Z 2 1 C594 AE12 D23
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_5 VSS_5 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AE14 VSSIO_SATA_6 VSS_6 E25
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF9 E6
VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_7 VSS_7
PCI/GPIO I/O
C599 1 2 0.1U_0402_16V4Z AB4 V18 AF11 F24
VDDIO_33_PCIGP_7 VDDCR_11_7 VSSIO_SATA_8 VSS_8
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AF13 VSSIO_SATA_9 VSS_9 N15
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AF16 VSSIO_SATA_10 VSS_10 R13
AA9 VDDIO_33_PCIGP_10 AG8 VSSIO_SATA_11 VSS_11 R17
+1.1VS_CKVDD L69
AF7 VDDIO_33_PCIGP_11 400mA AH7 VSSIO_SATA_12 VSS_12 T10
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH11 VSSIO_SATA_13 VSS_13 P10
K29 FBMA-L11-201209-221LMA30T_0805 AH13 V11
VDDAN_11_CLK_2 VSSIO_SATA_14 VSS_14
VDDAN_11_CLK_3 J28
22U_0805_6.3V6M C595
External Clock, connect to +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
VDDAN_11_CLK_4 K26 1 2 AJ7 VSSIO_SATA_16 VSS_16 M18
71mA J21 directly, no need thick trace AJ11 V19
CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_17 VSS_17
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 AJ13 VSSIO_SATA_18 VSS_18 M11
FLASH I/O
AE25 K21 1U_0402_6.3V4Z 2 1 C601 check can be removed? AJ16 L12
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_SATA_19 VSS_19
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 2 1 VSS_20 L18
1 2 AC22 0.1U_0402_16V4Z 2 1 C603 A9 J7
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_1 VSS_21
B10 VSSIO_USB_2 VSS_22 P3
VDDRF_GBE_S V1 1 2 K11 VSSIO_USB_3 VSS_23 V4
R372 0_0402_5% B9 AD6
POWER VDDIO_33_GBE_S M10 1 2 D10
VSSIO_USB_4
VSSIO_USB_5
VSS_24
VSS_25 AD4
43mA R373 0_0402_5% D12 AB7
VSSIO_USB_6 VSS_26
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE D14 VSSIO_USB_7 VSS_27 AC9
GBE LAN
D17 VSSIO_USB_8 VSS_28 V8
L70 +1.1VS_PCIE
600mA E9 VSSIO_USB_9 VSS_29 W9
PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F9 VSSIO_USB_10 VSS_30 W10
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% F12 AJ28
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_11 VSS_31
V26 VDDAN_11_PCIE_3 F14 VSSIO_USB_12 VSS_32 B29
C604 1 2 22U_0805_6.3V6M V27 F16 U4
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_13 VSS_33
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 C9 VSSIO_USB_14 VSS_34 Y18
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% G11 Y10
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_15 VSS_35
GROUND
1 2 W22 VDDAN_11_PCIE_7 F18 VSSIO_USB_16 VSS_36 Y12
W26 VDDAN_11_PCIE_8 D9 VSSIO_USB_17 VSS_37 Y11
2 2
H12 VSSIO_USB_18 VSS_38 AA11
+VDDPL_3V_SATA H14 VSSIO_USB_19 VSS_39 AA12
+3VALW
93mA H16 VSSIO_USB_20 VSS_40 G4
L71 +1.1VS_SATA
AD14 VDDPL_33_SATA 32mA H18 VSSIO_USB_21 VSS_41 J4
VDDIO_33_S_1 A21 J11 VSSIO_USB_22 VSS_42 G8
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 J19 VSSIO_USB_23 VSS_43 G9
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K12 M12
SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 2.2U_0603_6.3V4Z C609 VSSIO_USB_24 VSS_44
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 1 2 K14 VSSIO_USB_25 VSS_45 AF25
3.3V_S5 I/O
C610 1 2 22U_0805_6.3V6M AG19 L10 K16 H7
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_26 VSS_46
1 2 AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 K18 VSSIO_USB_27 VSS_47 AH29
C612 1 2 1U_0402_6.3V4Z AD18 T6 +1.1VALW H19 V10
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_28 VSS_48
1 2 AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 VSS_49 P6
C614 1 2 0.1U_0402_16V4Z N4
VSS_50
Y4 EFUSE VSS_51 L4
check 220ohm bead 113mA C615 2 1 1U_0402_6.3V4Z L8
+AVDD_USB VSS_52
CORE S5
L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5% +1.5VS
1 2
1 1 1 R52 0_0402_5%
C636 @
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 22 of 52
A B C D E
A B C D E
PULL LOW POWER ALLOW PCIE WATCHDOG USE Inter CLK EC CLOCKGEN
HIGH MODE GEN2 TIMER DEBUG Gen Mode ENABLE ENABLE H,H = Reserved
ENABLE STRAP Enable
1 DEFAULT 1
H,L = SPI ROM (Default )
DEFAULT
PULL Performance FORCE PCIE WATCHDOG IGNORE Inter CLK EC CLOCKGEN L,H = LPC ROM
LOW MODE GEN1 TIMER DEBUG Gen Mode DISABLE DISABLE L,L = FWH ROM
DISABLE STRAP Disable
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R385
R377
R378
R379
R380
R381
R382
R383
R384
2
2
@ @ @ @ @
<20> HDA_SDOUT @
<19> PCI_CLK1
<19> PCI_CLK2
<19> PCI_CLK3
<19> PCI_CLK4
<19,30> CLK_PCI_EC
<19,31> CLK_PCI_SIO
<20> GPIO200
2 <20> GPIO199 2
2.2K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R393
R394
R386
R387
R388
R389
R390
R391
R392
2
2
@ @ @
+3VS +3VS
DEBUG STRAPS
10K_0402_5%
10K_0402_5%
1
1
R395
R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI <19> PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT <19> PCI_AD28
HIGH <19> PCI_AD27
<19> PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<19> PCI_AD25
<19,21> PCI_AD24
<19> PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R397
R398
R399
R400
R401
2
2
Check AD29,AD28 strap function @ @ @ @ @
check default
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 23 of 52
A B C D E
A B C D E
< SATA HDD Conn > < SATA ODD Conn >
+5VS +3VS JODDB
+5VS
1.2A Place closely JHDD SATA CONN. +3VS rail reserve for SSD GND 14
13 C225
GND
1 1 1 1 1 1 1 1 12 12
C201 C202 C203 C204 C205 C206 C207 C208 11 1 2 0.1U_0402_16V7K
@ @ @ @ 11
10 10
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 9
2 2 2 2 2 2 2 2 9
8 8
7 7
1 SATA_IRX_DTX_P1 C213 1
6 6 1 2 0.01U_0402_25V7K SATA_RXP1_C <21>
5 SATA_IRX_DTX_N1 C214 1 2 0.01U_0402_25V7K
5 SATA_RXN1_C <21>
4 4
3 SATA_TXN1 C215 1 2 0.01U_0402_25V7K
3 SATA_STX_DRX_N1 <21>
JHDD 2 SATA_TXP1 C216 1 2 0.01U_0402_25V7K
2 SATA_STX_DRX_P1 <21>
1 1
GND 1
2 SATA_TXP0 C209 1 2 0.01U_0402_25V7K ACES_88058-120N
A+ SATA_STX_DRX_P0 <21>
3 SATA_TXN0 C210 1 2 0.01U_0402_25V7K
A- SATA_STX_DRX_N0 <21>
GND 4 @
5 SATA_IRX_DTX_N0 C211 1 2 0.01U_0402_25V7K
B- SATA_RXN0_C <21>
6 SATA_IRX_DTX_P0 C212 1 2 0.01U_0402_25V7K
B+ SATA_RXP0_C <21>
GND 7
V33 8 +3VS
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14 +5VS
V5 15
V5 16
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 GND V12 22
2 @ SUYIN_127072FR022G210ZR_RV 2
2A W=60mils
U11
W=60mils
1
3 @C373
@ C373 1 3
1 GND VOUT 8 2 4.7U_0805_10V4Z 1 1
2 7 + C376 C377 C378
+5VALW VIN VOUT
3 6 @ D14
VIN VOUT 220U_6.3V_M 0.1U_0402_16V7K 1000P_0402_50V7K
<29,30> USB_EN# 4 EN FLG 5 USB_OC#2 <20,30> 2
2 2 2
1
G547E2P11U_SO8 3
PJDLC05_SOT23-3
JESATA
1 USB
USB20_N2_R_S VBUS
2 D-
USB20_P2_R_S 3 D+
Reserve for EMI request 4 GND
5 GND
@ R196 1 2 0_0402_5% C379 1 2 0.01U_0402_25V7K SATA_TXP3 6
<21> SATA_STX_DRX_P3 A+
C380 1 2 0.01U_0402_25V7K SATA_TXN3 7 ESATA
<21> SATA_STX_DRX_N3 A-
8 GND
WCM-2012-900T_0805 C381 2 1 0.01U_0402_25V7K SATA_RXN3 9
<21> SATA_RXN3_C B-
C382 2 1 0.01U_0402_25V7K SATA_RXP3 10
<21> SATA_RXP3_C B+
1 2 USB20_N2_R_S 11
<20> USB20_N2 1 2 GND
12 GND
4 3 USB20_P2_R_S 13
<20> USB20_P2 4 3 GND
14 GND
L33 15 GND
@ TYCO_1759576-1
1 2
@R198
@ R198 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 24 of 52
A B C D E
5 4 3 2 1
UL1
<11> PCIE_PTX_C_IRX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P3 22 HSOP LED3/EEDO 31 LL1,CL13 will be changed to CL4,CL5,CL6,CL7 close to
37 LAN_SK_LINK# +LAN_VDD10
CL2 LED1/EESK 2.2uH&4.7uF after EVT test Pin 27,39,47,48
<11> PCIE_PTX_C_IRX_N3 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N3 23 HSON LED0 40 LAN_ACTIVITY#
LL1 +3V_LAN
17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2
<11> PCIE_ITX_C_PRX_P3 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2K-N
<11> PCIE_ITX_C_PRX_N3 HSIN EEDI/SDA
1 2 1 2
Layout Note: LL1 must be 0.1U_0402_16V4Z CL4
RL19 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36, CL13 CL9 1 2
<20> CLKREQ_LAN# CLKREQB MDIP0
D 2 LAN_MDI0- CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL5 D
MDIN0 LAN_MDI1+ 200mil to LL1 2 1
<12,15,19,27,30,31,34> PLT_RST# 25 PERSTB MDIP1 4 1 2
5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL6
MDIN1
<19> CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7 1 2
20 8 0.1U_0402_16V4Z CL7
<19> CLK_PCIE_LAN# REFCLK_N NC/MDIN2
NC/MDIP3 10
NC/MDIN3 11
+3V_LAN LAN_X1 43 CKXTAL1
1 2 EC_SWI# LAN_X2 44 CKXTAL2 DVDD10 13 +LAN_VDD10
RL3 100K_0402_5% 29 +LAN_VDD10 +LAN_EVDD10
DVDD10
@ DVDD10 41
EC_SWI# 28 2 1
<20> EC_SWI# LANWAKEB 0_0603_5% LL2 1 2 CL19,CL20,CL21,CL22 close to
+3VS ISOLATEB 26 27
ISOLATEB DVDD33 +3V_LAN Pin 3,13,29,45
39 CL18 CL17
DVDD33 1U_0402_6.3V4Z 0.1U_0402_16V4Z +LAN_VDD10
1
2 1
14 NC/SMBCLK AVDD33 12 +3V_LAN
RL6 15 42 +3V_AVDDXTAL 1 2
1K_0402_1% NC/SMBDATA AVDD33
+3V_LAN 1 RL22 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 0.1U_0402_16V4Z CL19
AVDD33 48 1 2
0.1U_0402_16V4Z CL20
2
ISOLATEB ENSWREG 33 1 2
ENSWREG 0.1U_0402_16V4Z CL21
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG 1 2
35 3 +LAN_VDD10 0.1U_0402_16V4Z CL22
RL7 VDDREG AVDD10
AVDD10 6
15K_0402_5% 9 +3V_LAN +LAN_VDDREG
AVDD10
1 2 46 RSET AVDD10 45
C RL5 2.49K_0402_1% 2 1 C
24 36 +LAN_REGOUT 0_0603_5% LL3 1 2
GND REGOUT
49 PGND CL28 CL29
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RTL8105E-GR QFN _6X6 2 1
Vgs=-4.5V,Id=3A,Rds<97mohm 1 150_0402_5%
RL25 2 1 11 16
100K_0402_5% ENSWREG CL11 +3V_LAN RL17 150_0402_5% Amber LED+ SHLD4
2
CL12 0.1U_0402_16V4Z 8 15
0.1U_0402_16V7K QL1 2 PR4- SHLD3
1
S
RL23 CL11 close to pin42 7
1 G PR4+
<30> WOL_EN# 1 2 2 0_0402_5%
RL16 47K_0402_5% @ RJ45_MIDI1- 6
D PR2-
1
1
CL14 AO3413_SOT23 5
+3V_LAN YL1 PR3-
0.01U_0402_25V7K
LAN_X1 2 1 LAN_X2 4
2 PR3+
25MHZ_20PF_7A25000012 RJ45_MIDI1+ 3 PR2+
B
1 1 1 1 B
RJ45_MIDI0- 2
CL15 CL8 1U_0402_6.3V4Z CL26 CL27 PR1-
SHLD2 14
4.7U_0805_10V4Z 27P_0402_50V8J 27P_0402_50V8J RJ45_MIDI0+ 1
@ 2 2 2 2 PR1+
LAN_SK_LINK# 2 RL14 1 LAN_SK_LINK#_R 10 13
150_0402_5% Green LED- SHLD1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 25 of 52
5 4 3 2 1
5 4 3 2 1
D D
@ CC1
1 2 100P_0402_50V8J
RC1
6.19K_0402_1% UC1
2 1 1 REFE
17 CR_LED#
GPIO0 CR_LED# <32>
USB20_N5 2
+3VS_CR <20> USB20_N5 DM
USB20_P5 3 24 CLK_48M_CR < 48MHz >
<20> USB20_P5 DP CLK_IN CLK_48M_CR <19>
EPAD
SD_DATA0 11 14
MS_DATA3_SD_DATA7 SP4 SP7 SDCD#
12 SP5 SP6 13
RTS5138-GR_QFN24_4X4
25
C C
B @TAITW_R009-025-LR_NR B
10P_0402_50V8J 10_0402_5%
10P_0402_50V8J 10_0402_5%
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 26 of 52
5 4 3 2 1
A B C D E
< BlueTooth Interface, USB port6 > < Bluetooth Connector >
(MAX=200mA)
+3VS +3VS
+BT_VCC
1 1
2
2 C488 C487
R199 BT@ BT@
BT@C383
BT@C383 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2
1 100K_0402_5% 0.1U_0402_16V7K 2 2 1
1 @ R50
1
3
S
BT@R201
BT@R201 BT@ 0_0603_5% @ ACES_87213-0600G
G
<19> BT_PWR# 1 2 47K_0402_5% 2 1 1
1 Q27 2
1
USB20_P6 2
D
<20> USB20_P6 3
1
BT@C386
BT@C386 AO3413_SOT23 USB20_N6 3
<20> USB20_N6 4 4
0.01U_0402_25V7K <19> BT_RST# BT@ R442 1 2 0_0402_5% 5 7
2 5 G1
+BT_VCC 1 <19> BT_DET# 6 6 G2 8
2 2
+1.5VS +3VS
1 1 1 1 1 1
CM1 CM2 CM3 CM4 CM5 CM6
+1.5VS +3VS
JWLAN
1 1 2 2
3 3 4 4
3 BT_CTRL 3
5 5 6 6
<20> CLKREQ_MCARD2# 7 7 8 8
9 9 10 10
1
D
<19> CLK_PCIE_MCARD2# 11 11 12 12
BT_PWR# 2 Q8 13 14
<19> CLK_PCIE_MCARD2 13 14
G 15 16
2N7002_SOT23-3 15 16
S 17 18
3
17 18
19 19 20 20 WL_OFF# <30>
21 22 PLT_RST#
21 22 PLT_RST# <12,15,19,25,30,31,34>
<11> PCIE_PTX_C_IRX_N2 23 23 24 24
BT BT <11> PCIE_PTX_C_IRX_P2 25 25 26 26
on module on module 27 27 28 28
29 30 SMB_CK_CLK1
29 30 SMB_CK_CLK1 <20>
Enable Disable 31 32 SMB_CK_DAT1 SMB_CK_DAT1 <20>
<11> PCIE_ITX_C_PRX_N2 31 32
<11> PCIE_ITX_C_PRX_P2 33 33 34 34
35 36 USB20_N8 USB20_N8 <20>
35 36 USB20_P8
BT_CRTL HI LO 37 37 38 38 USB20_P8 <20>
+3VS 39 39 40 40
41 41 42 42
BT_PWR# LO HI 43 43 44 44
45 45 46 46
47 47 48 48
E51_TXD RM1 1 2 0_0402_5% E51_TXD_R 49 50
<30> E51_TXD E51_RXD RM2 E51_RXD_R 49 50
<30> E51_RXD 1 2 0_0402_5% 51 51 52 52
53 GND1 GND2 54
@ FOX_AS0B226-S40N-7F
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 27 of 52
A B C D E
5 4 3 2 1
2
RA1 JA1 2 2 2 2
2
+3VS 2 1 0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
0_0603_1%
1
1 1 @ place close to chip
@ RA19 CA2 CA1
1
+1.5VS 2 1
D 0_0603_1% 10U_0805_10V4Z +3VS_DVDD RA11 D
2 2 +PVDD2 0.1U_0402_16V4Z
2 1 +5VS
1 1 0_0603_1% 1 1
RA17 0.1U_0402_16V4Z CA61 @ CA62
+3VS 2 1 35 mA @ CA63 @ @ CA58
0_0603_1% 1 1 0.1U_0402_16V4Z
2 2 2 2
CA8 CA7 +AVDD 10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z RA3
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS
0_0603_1%
39
46
25
38
1 1 1 1
9
UA1 CA3 CA4 CA5 CA6
DVDD_IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
2 2 2 2 place close to chip
10U_0805_10V4Z 0.1U_0402_16V4Z
SPDIFO 48
1 2 MONO_IN 12
CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
1
1
SENSE_A 13 SENSE A RA12 CA18
MIC2_VREFO 29
18 10K_0402_5% 0.1U_0402_16V4Z
SENSE B 2
30 +MIC1_VREFO_R CA28 10U_0805_10V4Z
2
MIC1_VREFO_R
1 2 36 CBP LDO_CAP 28 1 2
CA15
2.2U_0603_6.3V4Z 35 27 AC_VREF
CBN VREF
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF
1 1
43 34 1 2 @
PVSS2 CPVEE CA14 2.2U_0603_6.3V4Z CA17 CA16
42 PVSS1
B CA47 1 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 10U_0805_10V4Z
2 2
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
CA49 1 2 0.1U_0603_50V7K
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA18 0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 28 of 52
5 4 3 2 1
Speaker Connector HeadPhone/LINE Out JACK
L35
4 3 USB20_P1_R
<20> USB20_P1 4 3
1 2 USB20_N1_R
<20> USB20_N1 1 2
WCM-2012-900T_0805
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 29 of 52
A B C D E
111
125
22
33
96
67
9
U14
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
@C55
@ C55 2 1 @R44
@ R44 1 2 CLK_PCI_EC
GATEA20 1 21
1 10P_0402_50V8J 10_0402_5% <20> GATEA20 R330 1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 1
<20> KB_RST# 2 0_0402_5% 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 EC_BEEP# <28>
SERIRQ 3 26
<19,31> SERIRQ SERIRQ# FANPWM1/GPIO12
LPC_FRAME# 4 27 ACOFF C389
<19,31> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <45>
<19,31> LPC_AD3 LPC_AD3 5 1 2 100P_0402_50V8J ECAGND
LPC_AD2 LAD3
<19,31> LPC_AD2 7 LAD2 PWM Output
<19,31> LPC_AD1 LPC_AD1 8 63 BATT_TEMPA
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <44>
LPC_AD0 R208
<19,31> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65 1 2 100K_0402_5% ADP_I <45>
CLK_PCI_EC 12 AD Input 66
<19,23> CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V <45>
R8 1 2 0_0402_5% 13 75 C387
<12,15,19,25,27,31,34> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VL R209 1 2 47K_0402_5% ECRST# 37 76 1 2 0.22U_0603_16V4Z
EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<20> EC_SCI# 20 SCI#/GPIO0E
C388 2 1 0.1U_0402_16V4Z <32> WL_BT_LED# WL_BT_LED# 38 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68
70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <5>
DA Output 71 IREF
IREF/DA2/GPIO3E IREF <45>
KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <45>
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <28>
KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <24,29>
KSI5 60 85
EC_SMB_DA2 R210 1 KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
2 2.2K_0402_5% +3VS 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <32> EC_MUTE#
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <32>
EC_SMB_CK2 R211 1 2 2.2K_0402_5% KSO1 40 KSO1/GPIO21
1
KSI[0..7] KSO2 41
<31,32> KSI[0..7] KSO2/GPIO22
KSO3 42 97 R64
KSO[0..17] KSO3/GPIO23 SDICS#/GPXOA00 VGATE <33,49>
EC_SMB_DA1 R212 1 2 2.2K_0402_5% +3VL KSO4 43 98 4.7K_0402_5%
<31,32> KSO[0..17] KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# <25>
KSO5 R137
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 VLDT_EN <33>
45 KSO6/GPIO26 Matrix 109 1 2 LID_SW#_R <32>
2
EC_SMB_CK1 R213 1 SDIDI/GPXID0
2 2.2K_0402_5% KSO7 46 KSO7/GPIO27 SPI Device Interface
2 KSO8 1K_0402_5% 2
47 KSO8/GPIO28
KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <31>
KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <31>
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <31>
KSO12 51 128
KSO12/GPIO2C SPICS# SPI_CS# <31>
KSO13 52
TP_CLK R215 1 KSO13/GPIO2D
2 4.7K_0402_5% +5VS KSO14 53 KSO14/GPIO2E
KSO15 54 73
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
TP_DATA R216 1 2 4.7K_0402_5% KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <45>
90 BATT_FULL_LED#
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <32>
CAPS_LED#/GPIO53 91 CAPS_LED# <31>
EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
<44> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <32>
EC_SMB_DA1 78 93
<44> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# <32>
EC_SMB_CK2 79 SM Bus 95 SYSON
<7,42> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <33,47>
SYSON R217 1 2 10K_0402_5% EC_SMB_DA2 80 121 VR_ON
<7,42> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <33,49>
127 ACIN_D
AC_IN/GPIO59 R219
SUSP# R218 1 2 10K_0402_5% 2 1 10K_0402_5%
PM_SLP_S3# 6 100 EC_RSMRST#
<20> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <20>
PM_SLP_S5# 14 101
<20> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <20>
LID_SW#_R R220 2 1 100K_0402_5% +3VALW EC_SMI# 15 102
<20> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <32>
<45> 75W_65W 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103
17 104 SB_PWRGD
SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# SB_PWRGD <20>
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <17>
ON/OFFBTN# R221 2 1 100K_0402_5% +3VL 19 GPIO 106 WL_OFF#
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <27>
<17> EC_INVT_PWM 25 EC_THERM#/GPIO11 GPXO10 107
FAN_SPEED1 28 108 EC_SEL
<5> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
KSO1 R222 2 1 47K_0402_5% 29
E51_TXD FANFB2/GPIO15
<27> E51_TXD 30 EC_TX/GPIO16
E51_RXD 31 110
KSO2 R223 <27> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1
2 1 47K_0402_5% <32> ON/OFFBTN#
ON/OFFBTN# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL
ENBKL <35>
3 PWR_SUSP_LED# USB_OC#2 3
<32> PWR_SUSP_LED# 34 PWR_LED#/GPIO19 GPXID3 114 USB_OC#2 <20,24>
NUM_LED# 36 GPI 115
<31> NUM_LED# NUMLED#/GPIO1A GPXID4
116 SUSP#
GPXID5 SUSP# <33,45,48,50>
117 PBTN_OUT#
GPXID6 PBTN_OUT# <20>
E51_TXD R782 1 2 100K_0402_5% 118 USB_OC#0
GPXID7 USB_OC#0 <20,29>
C390 1 2 15P_0402_50V8J CRY1 122
PLT_RST# R783 XCLK1
2 1 100K_0402_5% 123 XCLK0 V18R 124 C391 2 1 4.7U_0805_10V4Z
1
AGND
Y10
GND
GND
GND
GND
GND
2 NC OSC 1
@ R224
3 4 20M_0402_5% KB926QFE0_LQFP128_14X14
11
24
35
94
113
69
NC OSC
2
32.768KHZ_12.5PF_Q13MC14610002
ECAGND
C392 1 2 15P_0402_50V8J CRY2 +3VL
1
1 2 150K_0402_5% +3VL
C393 @ R270
+EC_AVCC 1 2 0.1U_0402_16V4Z 100K_0402_5%
HIGH KB926D3
2
ACIN_D 2 1 D15 0_0603_5% 1 2 L38
ACIN <21,32,43>
CH751H-40PT_SOD323-2 EC_SEL LOW KB926E0
+3VL_EC
C394
1
2 1 R272
1 1 1 1 1 100K_0402_5%
4 100P_0402_50V8J C395 C396 C397 C398 C399 4
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K
2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 30 of 52
A B C D E
A B C D E
+3VL
< ROM Part > < MDC 1.5 Conn >
U46 JMDC
SPI_CS# 1 8
<30> SPI_CS# CS# VCC
1 GND1 RES0 2 +MDC_VCC
10P_0402_50V8J
10P_0402_50V8J
0.1U_0402_16V4Z
<20> HDA_SDOUT_MDC HDA_SDOUT_MDC 3 4
IAC_SDATA_OUT RES1
<30> EC_SI_SPI_SO 2 SO HOLD# 7 5 GND2 3.3V 6 +3VALW
1 1 1 <20> HDA_SYNC_MDC HDA_SYNC_MDC 7 8
IAC_SYNC GND3
@C400
@C400 @ <20> HDA_SDIN1 R231 1 2 33_0402_5%HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10
+3VL 3 6 EC_SPICLK C402 C401 <20> HDA_RST#_MDC 11 12 HDA_BITCLK_MDC <20>
WP# SCLK SPI_CLK <30> IAC_RESET# IAC_BITCLK
1
2 2 2
4 5 R232
GND
GND
GND
GND
GND
GND
1 GND SI EC_SO_SPI_SI <30> +MDC_VCC 1
@
0_0603_5% 10_0402_5%
MX25L2005CMI-12G_SO8 +3VALW R81 1 2 @ ACES_88018-124G
13
14
15
16
17
18
2
1 1 1 2
0_0603_5% C404
+1.5VS @ R82 1 2 C405 C406 C407 Connector for MDC Rev1.5 @
R230 C403 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 10P_0402_50V8J
EC_SPICLK 1 2 2 2 1
2 10_0402_5% 1 2 10P_0402_50V8C
H50
+3VS 6 5
SERIRQ 7 4 PLT_RST#
<19,30> SERIRQ PLT_RST# <12,15,19,25,27,30,34>
LPC_AD3 8 3 LPC_AD2
<19,30> LPC_AD3 LPC_AD2 <19,30>
2 2
LPC_AD1 9 2 LPC_AD0
<19,30> LPC_AD1 LPC_AD0 <19,30>
LPC_FRAME# 10 1
<19,30> LPC_FRAME# CLK_PCI_SIO <19,23>
2
R234
@ DEBUG_PAD
22_0402_5%
1
2
C408
22P_0402_50V8J
1
KSI[0..7]
< KEYBOARD Conn > KSI[0..7] <30,32> < For EMI >
KSO[0..17]
KSO[0..17] <30,32>
JKB
300_0402_5% 1 2 R235 +3VS
34 KSO16 KSO16 C438 1
33 2 100P_0402_50V8J
KSO17 C439 1 2 100P_0402_50V8J
32 KSO17
3 31 3
30 KSO2 C409 100P_0402_50V8J
29 1 2
KSO2 KSO1 C410 1 2 100P_0402_50V8J
28 KSO1 KSO0 C411 100P_0402_50V8J
27 1 2
KSO0 KSO4 C412 1 2 100P_0402_50V8J
26 KSO4 KSO3 C413 100P_0402_50V8J
25 1 2
KSO3 KSO5 C414 1 2 100P_0402_50V8J
24 KSO5 KSO14 C418 100P_0402_50V8J
23 1 2
KSO14 KSO6 C419 1 2 100P_0402_50V8J
22 KSO6 KSO7 C420 100P_0402_50V8J
21 1 2
KSO7 KSO13 C421 1 2 100P_0402_50V8J
20 KSO13 KSO8 C422 100P_0402_50V8J
19 1 2
KSO8 KSO9 C423 1 2 100P_0402_50V8J
18 KSO9 KSO10 C424 100P_0402_50V8J
17 1 2
KSO10 KSO11 C425 1 2 100P_0402_50V8J
16 KSO11 KSO12 C426 100P_0402_50V8J
15 1 2
KSO12 KSO15 C427 1 2 100P_0402_50V8J
14 KSO15 KSI7 C428 100P_0402_50V8J
13 1 2
KSI7 KSI2 C429 1 2 100P_0402_50V8J
12 KSI2 KSI3 C430 100P_0402_50V8J
11 1 2
KSI3 KSI4 C431 1 2 100P_0402_50V8J
10 KSI4 KSI0 C432 100P_0402_50V8J
9 1 2
KSI0 KSI5 C433 1 2 100P_0402_50V8J
8 KSI5 KSI6 C434 100P_0402_50V8J
7 1 2
KSI6 KSI1 C435 1 2 100P_0402_50V8J
6 KSI1 CAPS_LED# C436 100P_0402_50V8J
5 1 2
300_0402_5% 2 1 R252 +3VS NUM_LED# C437 1 2 100P_0402_50V8J
4
3 CAPS_LED# <30>
2
1 NUM_LED# <30>
@ ACES_88170-3400
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 31 of 52
A B C D E
A B C D E
< Power Button for Debug > < Power Button Circuit > < TP on & off BTN on M/B>
51_ON# <43>
@ SW1 Q17B
3
1 3 ON/OFFBTN# 2N7002KDW_SOT363-6 SW2
KSI6 1 3 KSO0
<30,31> KSI6 KSO0 <30,31>
2 4
<30> EC_ON 5 2 4
6 SMT1-05-A_4P
5
2
1 SMT1-05-A_4P 1
6
5
R786
10K_0402_5%
1
Sub-B Connector
JLEDB
1 1
2 2
<30> LID_SW#_R 3 3
ACIN_LED# 4 @ P-TWO_161021-06021
4
<30> PWR_ON_LED# 5 5 6 6 G8 8
6 SW_R 5 7
<30> PWR_SUSP_LED# 6 5 G7
HDD_LED# 7 JPOWER SW_L 4
7 ON/OFFBTN# 4
<26> CR_LED# 8 8 <30> ON/OFFBTN# 1 1 <30> TP_DATA 3 3
9 2 2 2 JTPB
<30> BATT_FULL_LED# 9 <30> TP_CLK 2
10 3 3 1 1 KSO0
<30> BATT_CHG_LOW_LED# 10 +5VS 1 1
SW_L 11 KSI6
11 GND 17 4 4 2 2
2
SW_R 12 D23 JTOUCH
12 GND 18 5 G1 3 3
0.1U_0402_16V7K
<30> WL_BT_LED# 13 13 6 G2 4 4
10P_0402_50V8J
10P_0402_50V8J
+3VALW 14 14 GND 5
+5VS 15 ACES_85201-0405N @ 1 2 1 6
2 15 @ @ GND 2
+5VALW 16 16 PACDN042Y3R_SOT23-3 C221 C222 @ P-TWO_161011-04021
1
@ ACES_85201-1605N C224
3
2 1 2
D10
BATT_CHG_LOW_LED# 2 1@ C220 SW_L 2 1@
@C218
C218
10P_0402_50V8J 10P_0402_50V8J
1
PACDN042Y3R_SOT23-3
SW_R 2 1@ C219 ACIN_LED# 2 1@
@C217
C217
10P_0402_50V8J 10P_0402_50V8J
LED Circuit
ACIN <21,30,43>
3 3
+3VS 2 R779 1 6 1
2
10K_0402_5%
5
Q31A
ACIN_LED# 6 1 2N7002KDW_SOT363-6
HDD_LED# 3 4
Q17A
2N7002KDW_SOT363-6 Q31B 2N7002KDW_SOT363-6
SCREW
H2 H3 H4 H5 H13 H14 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27
H_4P7 H_4P2 H_4P2X4P7 H_4P2X4P7 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_6P8 H_2P7X3P3N H_2P7N H_2P7X3P3N
1
1
4 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 4
@ @ @ @ @ @ @ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 32 of 52
A B C D E
A B C D E
+1.5V +1.5VS
< +5VALW TO +5VS > < +1.5V TO +1.5VS > Q5
IRF8113PBF_SO8
Inrush current = 0A
8 1
+5VS 7 2 1 2
+5VALW +5VS 6 3 C462 C463
5
2
Q2 Inrush current = 0A 1 1U_0402_6.3V4Z 10U_0805_10V4Z
2
R250 C464 2 1
8 1
4
D S R305
7 D S 2 1 1
6 3 C449 C450 470_0805_5% 4.7U_0805_10V4Z
D S RUNON 2 R285 470_0805_5%
5 4
1
D G 1U_0402_6.3V4Z 4.7U_0805_10V4Z 1.5VS_ENABLE 750K_0402_1% +VSB
1 1 2
1
C452 SI4800BDY_SO8 2 2
1
1
3
1 4.7U_0805_10V4Z R286 C466 1
2 Q11B
SUSP 2N7002KDW_SOT363-6 10M_0402_5% 0.01U_0402_25V7K
5
Q34B 2 SUSP 2N7002KDW_SOT363-6
2 5
2
4
Q11A
4
2N7002KDW_SOT363-6
< +3VALW TO +3VS > < +1.1VALW TO +1.1VS > BOOT_ON_1.1V @R62
@ R62 2 1 0_0402_5% SUSP
+1.1VALW
+3VALW +3VS +1.1VS BOOT_ON_1.1V R63 2 1 0_0402_5% VLDT_EN#
Q6
Q3 IRF8113PBF_SO8 BOOT_ON_1.1V @R67
@ R67 2 1 0_0402_5% VGATE#
Inrush current = 0A Inrush current = 0A
390U_2.5V_M_R10
8 D S 1 8 1 1
7 D S 2 1 1 7 2 1 1
6 3 C468 C469 6 3 C471 C472 +
D S
2
5 4 5 @ C158
D G 1U_0402_6.3V4Z 4.7U_0805_10V4Z R251 1U_0402_6.3V4Z 4.7U_0805_10V4Z
1 2 2 2 2 2
C470 SI4800BDY_SO8
2
R287 470_0805_5% 1
4.7U_0805_10V4Z RUNON 2 1 750K_0402_1% +VSB C475 R300
1
2 R290
4.7U_0805_10V4Z 2 1 330K_0402_5% +VSB 470_0805_5%
6
3
2
3 1
1
1 Q14B 1
6
C474 R291 C476
2 SUSP 5 2N7002KDW_SOT363-6 Q12B
0.01U_0402_25V7K 10M_0402_5% 0.01U_0402_25V7K
2 Q14A 2 BOOT_ON_1.1V 2N7002KDW_SOT363-6
2 5
1
2
2 2N7002KDW_SOT363-6 2
Q12A
4
2N7002KDW_SOT363-6
< +1.1VALW TO +NB_CORE > < Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
+1.1VALW
+NB_CORE
Q7
IRF8113PBF_SO8 +5VALW +5VALW
Inrush current = 0A +5VALW
8 1
7 2 1 1
1
6 3 C479 C478
1
5 R814 R245
1U_0402_6.3V4Z 4.7U_0805_10V4Z
2 2 100K_0402_5% 100K_0402_5% R816
4
1 100K_0402_5%
2
C480 R306
2
R292 SYSON# SUSP
SUSP <48>
4.7U_0805_10V4Z 2 1 330K_0402_5% +VSB 470_0805_5% VLDT_EN#
2
3 1
1
6
1
6
2N7002KDW_SOT363-6
1
Q13A
1
2N7002KDW_SOT363-6
3 3
+5VALW +5VALW
R802 R803
2
2
2
100K_0402_5% 100K_0402_5% R253
R257 R258
2
470_0805_5%
VGATE# VR_ON# 470_0805_5% 470_0805_5%
VR_ON# <48>
1
1
1
3
1
Q35B D D D
2N7002KDW_SOT363-6 Q35A SYSON#2 Q9 SUSP 2 Q10 SUSP 2 Q23
5 2N7002KDW_SOT363-6 G G G
<30,49> VGATE
2 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3
VR_ON <30,49>
3
3
4
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 33 of 52
A B C D E
5 4 3 2 1
PCIE_GTX_C_MRX_P[0..15]
<11> PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] UV1A
<11> PCIE_GTX_C_MRX_N[0..15]
CLOCK
<19> CLK_PCIE_VGA AB35 PCIE_REFCLKP
<19> CLK_PCIE_VGA# AA36 PCIE_REFCLKN
CALIBRATION
AJ21 Y30 RV1 1 2 1.27K_0402_1%
MANHA@ NC#1 PCIE_CALRP
AK21 NC#2
RV133 1 2 10K_0402_5% AH16 Y29 RV2 1 2 2K_0402_1% +1.0VS
NC_PWRGOOD PCIE_CALRN
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 34 of 52
5 4 3 2 1
5 4 3 2 1
UV1B
UV1G
TXCAP_DPA3P AU24
AV23 LVDS CONTROL AK27
TXCAM_DPA3N VARY_BL VGA_INVT_PWM <17>
DIGON AJ27 VGA_ENVDD <17>
TX0P_DPA2P AT25
MUTI GFX AR24
DPA TX0M_DPA2N
TX1P_DPA1P AU26
+3VS_DELAY AV25 AK35
TX1M_DPA1N TXCLK_UP_DPF3P LCD_TZCLK+ <17>
TXCLK_UN_DPF3N AL36 LCD_TZCLK- <17>
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27
10K_0402_5% 2 1 RV30 @ VGA_PWRSEL0 AU8 AR26 AJ38 LCD_TZOUT0+ <17>
DVPCNTL_MVP_1 TX2M_DPA0N TXOUT_U0P_DPF2P
AP8 DVPCNTL_0 TXOUT_U0N_DPF2N AK37 LCD_TZOUT0- <17>
10K_0402_5% 2 1 RV131 @ VGA_PWRSEL1 AW8 AR30 HDMI_CLK0+ <18>
DVPCNTL_1 TXCBP_DPB3P
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 HDMI_CLK0- <18> TXOUT_U1P_DPF1P AH35 LCD_TZOUT1+ <17>
10K_0402_5% 2 1 RV32 THERM#_VGA AR1 AJ36 LCD_TZOUT1- <17>
D DVPCLK TXOUT_U1N_DPF1N D
<42> VRAM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31 HDMI_TXD0+ <18>
10K_0402_5% 2 1 RV33 M9X@ GPIO23_CLKREQ# <42> VRAM_ID1 AU3 DVPDATA_1 TX3M_DPB2N AU30 HDMI_TXD0- <18> TXOUT_U2P_DPF0P AG38 LCD_TZOUT2+ <17>
AW3 DPB AH37 LCD_TZOUT2- <17>
<42> VRAM_ID2 DVPDATA_2 TXOUT_U2N_DPF0N
10K_0402_5% 2 1 RV34 @ R_AC_IN AP6 AR32 HDMI_TXD1+ <18>
DVPDATA_3 TX4P_DPB1P
AW5 DVPDATA_4 TX4M_DPB1N AT31 HDMI_TXD1- <18> TXOUT_U3P AF35
10K_0402_5% 2 1 RV35 @ GENERIC_C AU5 AG36
DVPDATA_5 TXOUT_U3N
AR6 DVPDATA_6 TX5P_DPB0P AT33 HDMI_TXD2+ <18>
AW6 DVPDATA_7 TX5M_DPB0N AU32 HDMI_TXD2- <18>
AU6 LVTMDP
DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13 TXCLK_LP_DPE3P AP34 LCD_TXCLK+ <17>
AN7 DVPDATA_11 TXCLK_LN_DPE3N AR34 LCD_TXCLK- <17>
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14 TXOUT_L0P_DPE2P AW37 LCD_TXOUT0+ <17>
AR10 DVPDATA_14 TXOUT_L0N_DPE2N AU35 LCD_TXOUT0- <17>
AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 DVPDATA_16 TX1M_DPC1N AV15 TXOUT_L1P_DPE1P AR37 LCD_TXOUT1+ <17>
AP10 DVPDATA_17 TXOUT_L1N_DPE1N AU39 LCD_TXOUT1- <17>
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L2P_DPE0P AP35 LCD_TXOUT2+ <17>
AR12 DVPDATA_20 TXOUT_L2N_DPE0N AR35 LCD_TXOUT2- <17>
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19 TXOUT_L3P AN36
AP12 DVPDATA_23 TXOUT_L3N AP37
TX3P_DPD2P AT21
TX3M_DPD2N AR20
DPD AU22
TX4P_DPD1P
TX4M_DPD1N AV21
216-0729002 A12 M96_BGA962
I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22 @
LCD_EDID_CLK
LCD <17> LCD_EDID_CLK
<17> LCD_EDID_DATA LCD_EDID_DATA
AK26
AJ26
SCL
SDA
AD39 Near UV1
GENERAL PURPOSE I/O R RED <16>
RB AD37
C GPU_GPIO0 AH20 C
<42> GPU_GPIO0 GPIO_0
GPU_GPIO1 AH18 AE36 RED 1 2
<42> GPU_GPIO1 GPIO_1 G GREEN <16>
GPU_GPIO2 AN16 AD35 RV11 150_0402_1%
<42> GPU_GPIO2 GPIO_2 GB
AH23 GREEN 1 2
GPIO_3_SMBDATA RV12 150_0402_1%
AJ23 GPIO_4_SMBCLK B AF37 BLUE <16>
R_AC_IN AH17 AE38 BLUE 1 2
RV17 1 ENBKL GPIO_5_AC_BATT DAC1 BB
2 10K_0402_5% AJ17 GPIO_6
RV13 150_0402_1%
<30> ENBKL
SOUT_GPIO8
AK17
AJ13
GPIO_7_BLON HSYNC AC36
AC38
R_HSYNC <16,42> CRT
<42> SOUT_GPIO8 GPIO_8_ROMSO VSYNC R_VSYNC <16,42>
SIN_GPIO9 AH15
<42> SIN_GPIO9 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
GPU_GPIO11 AK16 AB34 1 2
<42> GPU_GPIO11 GPIO_11 RSET
GPU_GPIO12 AL16 RV18 499_0402_1%
<42> GPU_GPIO12 GPIO_12
GPU_GPIO13 AM16 AD34 +AVDD_VGA
<42> GPU_GPIO13 GPIO_13 AVDD
AM14 AE34 BLM18PG121SN1D_0603
VGA_PWRSEL0
T15 PAD
AM13
GPIO_14_HPD2 AVSSQ +AVDD_VGA 70mA 2 1 +1.8VS
<50> VGA_PWRSEL0 GPIO_15_PWRCNTL_0
AK14 AC33 +VDD1DI 1 1 1 LV1
THERM#_VGA GPIO_16_SSIN VDD1DI
<42> THERM#_VGA AG30 GPIO_17_THERMAL_INT VSS1DI AC34
AN14 CV33 CV35 CV34
GPIO_18_HPD3 1U_0402_6.3V4Z 10U_0603_6.3V6M
AM17 GPIO_19_CTF
VGA_PWRSEL1 2 2 2
<50> VGA_PWRSEL1 AL13 GPIO_20_PWRCNTL_1 R2 AC30
AJ14 AC31 0.1U_0402_16V4Z
ROMSE_GPIO22 GPIO_21_BB_EN R2B
<42> ROMSE_GPIO22 AK13 GPIO_22_ROMCSB
GPIO23_CLKREQ# AN13 AD30
GPIO_23_CLKREQB G2
T16 PAD AM23 JTAG_TRSTB G2B AD31
T9 PAD AN23 JTAG_TDI
AK23 AF30 BLM18PG121SN1D_0603
T17 PAD
AL24
JTAG_TCK B2
AF31 +VDD1DI 45mA 2 1 +1.8VS
T18 PAD JTAG_TMS B2B
AM24 1 1 1 LV2
T10 PAD JTAG_TDO
AJ19 GENERICA
AK19 AC32 CV36 CV37 CV38
GENERIC_C GENERICB C 1U_0402_6.3V4Z 10U_0603_6.3V6M
AJ20 GENERICC Y AD32
2 2 2
AK20 GENERICD COMP AF32
AJ24 0.1U_0402_16V4Z
GENERICE_HPD4 DAC2
AH26 GENERICF
AH24 GENERICG H2SYNC AD29 HSYNC_DAC2 <42>
+1.8VS AC29
V2SYNC VSYNC_DAC2 <42>
B B
<18> HPD AK24 HPD1 45mA
1
AG33 +A2VDD
2
A2VDD
+VGA_VREF AD33 +A2VDDQ
+VGA_VREF AH13 A2VDDQ BLM18PG121SN1D_0603
VREFG 10mA
1
2 2 2 2
YV1 0.1U_0402_16V4Z
DDC/AUX CRT_CLK
2 1 150mA PLL/CLOCK DDC1CLK AM26
AN26 CRT_DATA
CRT_CLK <16>
CRT_DATA <16>
CRT
27MHZ_16PF_X5H027000FG1H +DPLL_PVDD DDC1DATA
AM32 DPLL_PVDD
AN32 DPLL_PVSS AUX1P AM27
CV324 CV323 AL27
300mA AUX1N
18P_0402_50V8J 18P_0402_50V8J +DPLL_VDDC HDMICLK_VGA
AN31 DPLL_VDDC DDC2CLK AM19
AL19 HDMIDAT_VGA
HDMICLK_VGA <18>
HDMIDAT_VGA <18>
HDMI
DDC2DATA
27MCLK AV33 AN20
XTALOUT AU34 XTALIN AUX2P
XTALOUT AUX2N AM20
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
DDCCLK_AUX4P AL29
BLM18PG121SN1D_0603 AF29 AM29
<42> GPU_THERMAL_D+ DPLUS THERMAL DDCDATA_AUX4N
<42> GPU_THERMAL_D- AG29 DMINUS
+1.8VS 2 1 0.1U_0402_16V4Z +DPLL_PVDD AN21
LV3 DDCCLK_AUX5P
1 1 1 20mA DDCDATA_AUX5N AM21
CV42 AK32
CV41 1U_0402_6.3V4Z +TSVDD TS_FDO
A AJ32 TSVDD DDC6CLK AJ30 A
CV40 AJ33 AJ31
2 2 2 TSVSS DDC6DATA
10U_0603_6.3V6M AK30
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N AK29
BLM18PG121SN1D_0603
+1.0VS BLM18PG121SN1D_0603 216-0729002 A12 M96_BGA962
2 1 0.1U_0402_16V4Z +DPLL_VDDC 2 1 0.1U_0402_16V4Z +TSVDD
LV5 1
CV43
1 1
+1.8VS
LV7 1 1 1
CV52
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
CV44 CV45 CV51 1U_0402_6.3V4Z
2 2 2 1U_0402_6.3V4Z 2
CV50
2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
10U_0603_6.3V6M 10U_0603_6.3V6M DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 35 of 52
5 4 3 2 1
5 4 3 2 1
BLM18PG121SN1D_0603
+1.8VS 2 1 +DPC_VDD18 BLM18PG121SN1D_0603
MANHA@ LV33 +DPA_VDD18 1 2 +1.8VS
10U_0603_6.3V6M
10U_0603_6.3V6M
LV35 MANHA@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
2 2 2
MANHA@ MANHA@ MANHA@ 2 2 2
CV309 CV308 CV310 MANHA@ MANHA@ MANHA@
CV314 CV315
1 1 1 UV1H CV316
1 1 1
D DP C/D POWER DP A/B POWER D
200mA
+1.0VS 1 2 +DPC_VDD10 AP13 AP31 +DPA_VDD10 1 2 +1.0VS BLM18PG121SN1D_0603
LV8 0_0603_5% DPC_VDD10#1 DPA_VDD10#1 LV9 0_0603_5% +DPB_VDD18
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32 1 2 +1.8VS
10U_0603_6.3V6M
LV36 MANHA@
BLM18PG121SN1D_0603
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.8VS 2 1 +DPD_VDD18 AN17 AN27 2 2 2
MANHA@ LV34 DPC_VSSR#1 DPA_VSSR#1
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
10U_0603_6.3V6M
0.1U_0402_16V4Z
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
2 2 2 AW14 AW24 CV319 CV317 MANHA@
MANHA@ MANHA@ MANHA@ DPC_VSSR#4 DPA_VSSR#4 1 1 1
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
CV312 CV311 CV313
1 1 1
+DPD_VDD18 AP22 AP25 +DPB_VDD18
NC_DPD_VDD18#1 NC_DPB_VDD18#1
AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26
BLM18PG121SN1D_0603
+1.0VS 1 2 +DPD_VDD10 AP14 AN33 +DPB_VDD10 20mA 2 1 +1.0VS
LV10 0_0603_5% DPD_VDD10#1 DPB_VDD10#1 LV11
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33 2 2 2
H@
10U_0603_6.3V6M CV53 CV54 CV55
0.1U_0402_16V4Z
1 1 1 H@
AN19 DPD_VSSR#1 DPB_VSSR#1 AN29
AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
C AP19 AP30 1U_0402_6.3V4Z C
DPD_VSSR#3 DPB_VSSR#3 H@
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
BLM18PG121SN1D_0603
+1.8VS 2 1 +DPE_VDD18 RV36 150_0402_1%
LV12 2 2 2 2 1 AW18 AW28 1 2
DPCD_CALR DPAB_CALR RV37 150_0402_1%
10U_0603_6.3V6M CV56 CV57 CV58
200mA
1 1 1 +DPE_VDD18 AH34
DP E/F POWER DP PLL POWER
AU28 +DPA_PVDD +DPA_PVDD 20mA 1 2 +1.8VS
1U_0402_6.3V4Z DPE_VDD18#1 DPA_PVDD LV13 0_0603_5%
AJ34 DPE_VDD18#2 DPA_PVSS AV27
0.1U_0402_16V4Z
100mA
+DPE_VDD10 AL33 AV29 +DPB_PVDD
DPE_VDD10#1 DPB_PVDD
AM33 DPE_VDD10#2 DPB_PVSS AR28
BLM18PG121SN1D_0603
2 1 +DPE_VDD10 AN34 AU18 +DPC_PVDD BLM18PG121SN1D_0603
+1.0VS
LV15 2 2 2 AP39
DPE_VSSR#1 DPC_PVDD
AV17 +DPB_PVDD 20mA 2 1 +1.8VS
DPE_VSSR#2 DPC_PVSS LV14
AR39 DPE_VSSR#3 2 2 2
10U_0603_6.3V6M CV60 CV64 CV61 AU37 DPE_VSSR#4 10U_0603_6.3V6M CV59 CV62 CV63
AW35 DPE_VSSR#5
1 1 1 +DPD_PVDD 0.1U_0402_16V4Z
DPD_PVDD AV19
1U_0402_6.3V4Z 1 1 1
200mA DPD_PVSS AR18
0.1U_0402_16V4Z
+DPF_VDD18 AF34 1U_0402_6.3V4Z
DPF_VDD18#1
AG34 DPF_VDD18#2
AM37 +DPE_PVDD
B DPE_PVDD B
100mA DPE_PVSS AN38 20mA
+DPC_PVDD 1 2 +1.8VS
+DPF_VDD10 AK33 LV16 0_0603_5%
BLM18PG121SN1D_0603 DPF_VDD10#1
AK34 DPF_VDD10#2
+1.8VS 2 1 +DPF_VDD18 AL38
LV17 NC_DPF_PVDD
2 2 2 NC_DPF_PVSS AM35
BLM18PG121SN1D_0603 @
+1.0VS 2 1 +DPF_VDD10
LV19 BLM18PG121SN1D_0603
2 2 2
+DPE_PVDD 20mA 2 1 +1.8VS
10U_0603_6.3V6M CV68 CV69 CV70 1 1 1 LV20
1 1 1 0.1U_0402_16V4Z CV71 CV72 CV73
1U_0402_6.3V4Z 10U_0603_6.3V6M
0.1U_0402_16V4Z 2 2 2
1U_0402_6.3V4Z
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 36 of 52
5 4 3 2 1
5 4 3 2 1
UV1E
+1.5VS +PCIE_VDDR_VGA
MEM I/O
PCIE 500mA
4A AC7 AA31 1 2 +1.8VS
VDDR1#1 PCIE_VDDR#1
330U_X_2VM_R6M
390U_2.5V_M_R10
1 1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 2
CV74 10U_0603_6.3V6M CV75 1U_0402_6.3V4Z CV76 1U_0402_6.3V4Z AG10 AA34 CV77 10U_0603_6.3V6M
+@ + VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
CV192 CV79 10U_0603_6.3V6M CV80 1U_0402_6.3V4Z CV81 1U_0402_6.3V4Z AK8 W29 CV82 1U_0402_6.3V4Z
CV78 VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 2 CV83 10U_0603_6.3V6M CV84 1U_0402_6.3V4Z CV85 1U_0402_6.3V4Z CV86 1U_0402_6.3V4Z
G11 VDDR1#8 PCIE_VDDR#8 Y31
1 2 1 2 1 2 G14 VDDR1#9 1 2
D CV87 10U_0603_6.3V6M CV88 1U_0402_6.3V4Z CV89 1U_0402_6.3V4Z G17 CV90 1U_0402_6.3V4Z D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
CV91 10U_0603_6.3V6M CV92 1U_0402_6.3V4Z CV93 1U_0402_6.3V4Z G23 G31 CV94 1U_0402_6.3V4Z
1 2 1 2 G26
VDDR1#12 PCIE_VDDC#2
H29
2A +1.0VS 1 2
CV95 1U_0402_6.3V4Z CV96 1U_0402_6.3V4Z VDDR1#13 PCIE_VDDC#3 CV97 1U_0402_6.3V4Z
G29 VDDR1#14 PCIE_VDDC#4 H30
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
CV98 1U_0402_6.3V4Z CV99 1U_0402_6.3V4Z J7 J30 CV100 10U_0603_6.3V6M CV101 0.1U_0402_16V4Z
VDDR1#16 PCIE_VDDC#6
1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
CV102 1U_0402_6.3V4Z CV103 1U_0402_6.3V4Z K11 M28 CV104 1U_0402_6.3V4Z CV105 0.1U_0402_16V4Z
VDDR1#18 PCIE_VDDC#8
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
CV106 1U_0402_6.3V4Z CV107 1U_0402_6.3V4Z K8 R28 CV108 1U_0402_6.3V4Z
1 2 1 2 L12
VDDR1#20 PCIE_VDDC#10
T28 1 2
25A +VGA_CORE
CV109 1U_0402_6.3V4Z CV110 1U_0402_6.3V4Z VDDR1#21 PCIE_VDDC#11 CV111 1U_0402_6.3V4Z
L16 VDDR1#22 PCIE_VDDC#12 U28
330U_X_2VM_R6M
330U_X_2VM_R6M
390U_2.5V_M_R10
390U_2.5V_M_R10
L21 VDDR1#23 1 2 1 1 1 1
L23 CV112 1U_0402_6.3V4Z
VDDR1#24 + @ + + @ +
L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 CV113 1U_0402_6.3V4Z CV116 CV326 CV114 CV325
VDDR1#26 VDDC#2
M11 VDDR1#27 VDDC#3 AA20 1 2
CV115 1U_0402_6.3V4Z 2 2 2 2
N11 VDDR1#28 VDDC#4 AA22
P7 VDDR1#29 VDDC#5 AA24 1 2
R11 AA27 CV118 1U_0402_6.3V4Z
VDDR1#30 VDDC#6
U11 VDDR1#31 VDDC#7 AB13
U7 VDDR1#32 VDDC#8 AB16
Y11 VDDR1#33 VDDC#9 AB18 1 2 1 2 1 2
Y7 AB21 CV120 10U_0603_6.3V6M CV121 1U_0402_6.3V4Z CV122 1U_0402_6.3V4Z
VDDR1#34 VDDC#10
VDDC#11 AB23 1 2 1 2 1 2
AB26 CV124 10U_0603_6.3V6M CV125 1U_0402_6.3V4Z CV126 1U_0402_6.3V4Z
VDDC#12
VDDC#13 AB28 1 2 1 2 1 2
AC12 CV128 10U_0603_6.3V6M CV129 1U_0402_6.3V4Z CV130 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 LEVEL VDDC#14
136mA VDDC#15 AC15 1 2 1 2 1 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
TRANSLATION AC17 CV132 10U_0603_6.3V6M CV133 1U_0402_6.3V4Z CV134 1U_0402_6.3V4Z
+1.8VS VDDC#16
POWER
C 2 1 2 2 2 1 2 +VDD_CT AF26 AC20 1 2 1 2 1 2 C
LV22 VDD_CT#1 VDDC#17 CV136 10U_0603_6.3V6M CV137 1U_0402_6.3V4Z CV138 1U_0402_6.3V4Z
AF27 VDD_CT#2 VDDC#18 AC22
CV119 CV123 CV127 CV131 CV135 AG26 AC24 1 2 1 2 1 2
VDD_CT#3 VDDC#19 CV139 10U_0603_6.3V6M CV140 1U_0402_6.3V4Z CV141 1U_0402_6.3V4Z
1U_0402_6.3V4Z AG27 VDD_CT#4 VDDC#20 AC27
1 1 1 2 1
VDDC#21 AD13 1 2 1 2 1 2
AD16 CV142 10U_0603_6.3V6M CV143 1U_0402_6.3V4Z CV144 1U_0402_6.3V4Z
I/O VDDC#22
60mA VDDC#23 AD18 1 2 1 2 1 2
+3VS_DELAY AF23 AD21 CV145 1U_0402_6.3V4Z CV146 1U_0402_6.3V4Z CV147 1U_0402_6.3V4Z
VDDR3#1 VDDC#24
1 2 AF24 VDDR3#2 VDDC#25 AD23 1 2 1 2 1 2
CV148 10U_0603_6.3V6M AG23 AD26 CV149 1U_0402_6.3V4Z CV150 1U_0402_6.3V4Z CV151 1U_0402_6.3V4Z
VDDR3#3 VDDC#26
1 2 AG24 VDDR3#4 VDDC#27 AF17 1 2 1 2 1 2
BLM18PG121SN1D_0603 CV152 1U_0402_6.3V4Z AF20 CV153 1U_0402_6.3V4Z CV154 1U_0402_6.3V4Z CV155 1U_0402_6.3V4Z
0.1U_0402_16V4Z +VDDR5 VDDC#28
+1.8VS 2 1 1 2 VDDC#29 AF22 1 2 1 2
LV23 CV158 1U_0402_6.3V4Z AF13 AG16 CV159 1U_0402_6.3V4Z CV160 1U_0402_6.3V4Z
1 1
CV156 CV157
1
CV161 1 2
170mA AF15
VDDR5#1 VDDC#30
AG18 1 2 1 2
CV162 1U_0402_6.3V4Z +VDDR5 VDDR5#2 VDDC#31 CV163 1U_0402_6.3V4Z CV164 1U_0402_6.3V4Z
AG13 VDDR5#3 VDDC#32 AG21
10U_0603_6.3V6M 1U_0402_6.3V4Z AG15 AH22 1 2 1 2
2 2 2 VDDR5#4 VDDC#33 CV165 1U_0402_6.3V4Z CV166 1U_0402_6.3V4Z
VDDC#34 M16
170mA VDDC#35 M18 1 2 1 2
AD12 M23 CV167 1U_0402_6.3V4Z CV168 1U_0402_6.3V4Z
+VDDR4 VDDR4#1 VDDC#36
AF11 VDDR4#2 VDDC#37 M26 1 2 1 2
AF12 N15 CV169 1U_0402_6.3V4Z CV170 1U_0402_6.3V4Z
VDDR4#3 VDDC#38
AG11 VDDR4#4 VDDC#39 N17 1 2 1 2
N20 CV174 1U_0402_6.3V4Z CV175 1U_0402_6.3V4Z
VDDC#40
VDDC#41 N22 1 2 1 2
BLM18PG121SN1D_0603 N24 CV176 1U_0402_6.3V4Z CV177 1U_0402_6.3V4Z
0.1U_0402_16V4Z +VDDR4 BLM18PG121SN1D_0603 MEM CLK VDDC#42
+1.8VS 2 1 VDDC#43 N27 1 2 1 2
LV24 1 1 1 +1.5VS 2 1 +VDDRHA M20 R13 CV178 1U_0402_6.3V4Z CV179 1U_0402_6.3V4Z
CV171 CV172 CV173 M9X@ LV25 VDDRHA VDDC#44
M21 VSSRHA VDDC#45 R16 1 2 1 2
R18 CV181 1U_0402_6.3V4Z CV182 1U_0402_6.3V4Z
10U_0603_6.3V6M 1U_0402_6.3V4Z VDDC#46
VDDC#47 R21 1 2 1 2
B 2 2 2 +VDDRHB CV183 1U_0402_6.3V4Z CV184 1U_0402_6.3V4Z B
V12 VDDRHB VDDC#48 R23
U12 VSSRHB VDDC#49 R26
VDDC#50 T15
VDDC#51 T17
VDDC#52 T20
VDDC#53 T22
BLM18PG121SN1D_0603 PLL T24
+1.8VS 2 1 0.1U_0402_16V4Z 68mA +PCIE_PVDD AB37
VDDC#54
T27
LV27 PCIE_PVDD VDDC#55
1 1 1 VDDC#56 U16
CV186 CV187 CV188 MPV18 H7 U18
MPV18 NC_MPV18#1 VDDC#57
H8 NC_MPV18#2 VDDC#58 U21
10U_0603_6.3V6M 1U_0402_6.3V4Z U23
2 2 2 VDDC#59
VDDC#60 U26
SPV18 AM10 V15
MANHA@LV28
MANHA@ LV28 1U_0402_6.3V4Z NC_SPV18 VDDC#61
414mA VDDC#62 V17
+1.0VS 2 1 +SPV10 AN9 V20
BLM18PG121SN1D_0603 SPV10 VDDC#63
1 1 2 VDDC#64 V22
CV189 CV190 CV191 AN10 V24
M9X@ LV37 SPVSS VDDC#65
VDDC#66 V27
+VGA_CORE 2 1 VDDC#67 Y16
BLM18PG121SN1D_0603 BLM18PG121SN1D_0603 2 2 1
VDDC#68 Y18
+1.8VS 2 1 MPV18 10U_0603_6.3V6M 0.1U_0402_16V4Z Y21
BACK BIAS VDDC#69
10U_0603_6.3V6M
MANHA@ LV30
1U_0402_6.3V4Z
0.1U_0402_16V4Z
VDDC#70 Y23
VDDC#71 Y26
1 1 1 +VGA_CORE AA13 BBP#1 VDDC#72 Y28
MANHA@ MANHA@ MANHA@ Y13 AH27
CV304 CV303 CV302 BBP#2 VDDC#73
2 1 VDDC#74 AH28
CV195 CV196
2 2 2
M15 +VDDCI 1U_0402_6.3V4Z 1 2
4A +VGA_CORE
ISOLATED VDDCI#1 N13 1 1 1 1 LV29 PBY201209T-300Y-N_2P
1 2 CORE I/O VDDCI#2 R12 CV197 CV198 CV199
A VDDCI#3 A
0.1U_0402_16V4Z 1U_0402_6.3V4Z T12 CV200
BLM18PG121SN1D_0603 VDDCI#4
SPV18 2 2 2 2
+1.8VS 2 1
10U_0603_6.3V6M
CV307
MANHA@
CV305
CV306 Security Classification @ Compal Secret Data Compal Electronics, Inc.
2 2 2 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 37 of 52
5 4 3 2 1
5 4 3 2 1
UV1F
F15 GND#101
GND GND#40
GND#41
GND#42
AG17
AG2
C C
F17 GND#102 GND#43 AG20
F19 GND#103 GND#44 AG22
F21 GND#104 GND#45 AG6
F23 GND#105 GND#46 AG9
F25 GND#106 GND#47 AH21
F27 GND#107 GND#48 AH29
F29 GND#108 GND#49 AJ10
F31 GND#109 GND#50 AJ11
F33 GND#110 GND#51 AJ2
F7 GND#111 GND#52 AJ28
F9 GND#112 GND#53 AJ6
G2 GND#113 GND#54 AK11
G6 GND#114 GND#55 AK31
H9 GND#115 GND#56 AK7
J2 GND#116 GND#57 AL11
J27 GND#117 GND#58 AL14
J6 GND#118 GND#59 AL17
J8 GND#119 GND#60 AL2
K14 GND#120 GND#61 AL20
K7 GND#121 GND#62 AL21
L11 GND#122 GND#63 AL23
L17 GND#123 GND#64 AL26
L2 GND#124 GND#65 AL32
L22 GND#125 GND#66 AL6
L24 GND#126 GND#67 AL8
L6 GND#127 GND#68 AM11
M17 GND#128 GND#69 AM31
M22 GND#129 GND#70 AM9
M24 GND#130 GND#71 AN11
N16 GND#131 GND#72 AN2
N18 GND#132 GND#73 AN30
N2 GND#133 GND#74 AN6
B B
N21 GND#134 GND#75 AN8
N23 GND#135 GND#76 AP11
N26 GND#136 GND#77 AP7
N6 GND#137 GND#78 AP9
R15 GND#138 GND#79 AR5
R17 GND#139 GND#80 AW34
R2 GND#140 GND#81 B11
R20 GND#141 GND#82 B13
R22 GND#142 GND#83 B15
R24 GND#143 GND#84 B17
R27 GND#144 GND#85 B19
R6 GND#145 GND#86 B21
T11 GND#146 GND#87 B23
T13 GND#147 GND#88 B25
T16 GND#148 GND#89 B27
T18 GND#149 GND#90 B29
T21 GND#150 GND#91 B31
T23 GND#151 GND#92 B33
T26 GND#152 GND#93 B7
U15 GND#153 GND#94 B9
U17 GND#154 GND#95 C1
U2 GND#155 GND#96 C39
U20 GND#156 GND#97 E35
U22 GND#157 GND#98 E5
U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13
U6 GND#160
V11 GND#161
V16 GND#162
V18 GND#163
V21 GND#164
V23 GND#165
A A
V26 GND#166
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24 AW1
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3 AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#175 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
V13 GND#176
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
216-0729002 A12 M96_BGA962 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@ Date: Wednesday, May 19, 2010 Sheet 38 of 52
5 4 3 2 1
5 4 3 2 1
MDB[0..63]
MDA[0..63] MDB[0..63] <41>
MDA[0..63] <40>
MEMORY INTERFACE A
MDA2 A35 H24 MAA2 MDB1 C3 T9 MAB1
DQA_2 MAA_2 DQB_1 MAB_1
MEMORY INTERFACE B
MDA3 E34 J24 MAA3 MDB2 E3 P9 MAB2
MDA4 DQA_3 MAA_3 MAA4 MDB3 DQB_2 MAB_2 MAB3
G32 DQA_4 MAA_4 H26 E1 DQB_3 MAB_3 N7
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
MDA6 DQA_5 MAA_5 MAA6 MDB5 DQB_4 MAB_4 MAB5
F32 DQA_6 MAA_6 H21 F3 DQB_5 MAB_5 N9
MDA7 E32 G21 MAA7 MDB6 F5 U9 MAB6
MDA8 DQA_7 MAA_7 MAA8 MDB7 DQB_6 MAB_6 MAB7
D31 DQA_8 MAA_8 H19 G4 DQB_7 MAB_7 U8
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 DQA_9 MAA_9 MAA10 MDB9 DQB_8 MAB_8 MAB9
C30 DQA_10 MAA_10 L13 H6 DQB_9 MAB_9 W9
MDA11 A30 G16 MAA11 A_BA[2..0] MDB10 J4 AC8 MAB10
DQA_11 MAA_11 A_BA[2..0] <40> DQB_10 MAB_10
MDA12 F28 J16 MAA12 MDB11 K6 AC9 MAB11
MDA13 DQA_12 MAA_12 A_BA2 MDB12 DQB_11 MAB_11 MAB12
C28 DQA_13 MAA_13/BA2 H16 K5 DQB_12 MAB_12 AA7
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2 B_BA[2..0]
DQA_14 MAA_14/BA0 DQB_13 MAB_13/BA2 B_BA[2..0] <41>
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
MDA16 DQA_15 MAA_15/BA1 MDB15 DQB_14 MAB_14/BA0 B_BA1
D27 DQA_16 M1 DQB_15 MAB_15/BA1 AA9
MDA17 F26 A32 DQMA#0 MDB16 M3
DQA_17 DQMA_0 DQMA#[7..0] <40> DQB_16
MDA18 C26 C32 DQMA#1 MDB17 M5 H3 DQMB#0
DQA_18 DQMA_1 DQB_17 DQMB_0 DQMB#[7..0] <41>
MDA19 A26 D23 DQMA#2 MDB18 N4 H1 DQMB#1
MDA20 DQA_19 DQMA_2 DQMA#3 MDB19 DQB_18 DQMB_1 DQMB#2
F24 DQA_20 DQMA_3 E22 P6 DQB_19 DQMB_2 T3
MDA21 C24 C14 DQMA#4 MDB20 P5 T5 DQMB#3
MDA22 A24
DQA_21
DQA_22
DQMA_4
DQMA_5 A14 DQMA#5 Close to pin Y12 MDB21 R4
DQB_20
DQB_21
DQMB_3
DQMB_4 AE4 DQMB#4
MDA23 E24 E10 DQMA#6 +1.5VS MDB22 T6 AF5 DQMB#5
C MDA24 DQA_23 DQMA_6 DQMA#7 MDB23 DQB_22 DQMB_5 DQMB#6 C
C22 DQA_24 DQMA_7 D9 T1 DQB_23 DQMB_6 AK6
MDA25 A22 MDB24 U4 AK5 DQMB#7
DQA_25 DQB_24 DQMB_7
1
MDA26 F22 C34 QSA0 MDB25 V6
DQA_26 QSA_0/RDQSA_0 QSA[7..0] <40> DQB_25
MDA27 D21 D29 QSA1 MANHA@ RV42 MDB26 V1 F6 QSB0
DQA_27 QSA_1/RDQSA_1 DQB_26 QSB_0/RDQSB_0 QSB[7..0] <41>
MDA28 A20 D25 QSA2 RV42 100_0402_1% MDB27 V3 K3 QSB1
Close to pin L18 MDA29 F20
DQA_28
DQA_29
QSA_2/RDQSA_2
QSA_3/RDQSA_3 E20 QSA3 40.2_0402_1% M9X@ MDB28 Y6
DQB_27
DQB_28
QSB_1/RDQSB_1
QSB_2/RDQSB_2 P3 QSB2
+1.5VS MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
2
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB30 DQB_29 QSB_3/RDQSB_3 QSB4
E18 DQA_31 QSA_5/RDQSA_5 E12 Y3 DQB_30 QSB_4/RDQSB_4 AB5
MDA32 C18 J10 QSA6 +MVREFDB MDB31 Y5 AH1 QSB5
DQA_32 QSA_6/RDQSA_6 DQB_31 QSB_5/RDQSB_5
1
1
40.2_0402_1% 100_0402_1% MDA35 D17 A34 QSA#0 CV203 MDB34 AB1
DQA_35 QSA_0B/WDQSA_0 QSA#[7..0] <40> DQB_34
M9X@ MDA36 A16 E30 QSA#1 RV44 0.1U_0402_16V4Z MDB35 AB3 G7 QSB#0
DQA_36 QSA_1B/WDQSA_1 DQB_35 QSB_0B/WDQSB_0 QSB#[7..0] <41>
MDA37 F16 E26 QSA#2 MDB36 AD6 K1 QSB#1
2
2
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 MDB39 DQB_38 QSB_3B/WDQSB_3 QSB#4
F14 DQA_40 QSA_5B/WDQSA_5 C12 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
1 MDA41 D13 J11 QSA#6 100_0402_1% MDB40 AF1 AH3 QSB#5
DQA_41 QSA_6B/WDQSA_6 DQB_40 QSB_5B/WDQSB_5
1
1
MDA51 H11 H14 CLKA1# MDB50 AG8 AD8 CLKB1
DQA_51 CLKA1B CLKA1# <40> DQB_50 CLKB1 CLKB1 <41>
MDA52 G10 MANHA@ RV46 MDB51 AG7 AD7 CLKB1#
B DQA_52 DQB_51 CLKB1B CLKB1# <41> B
MDA53 G8 K23 RASA0# RV46 100_0402_1% MDB52 AK9
DQA_53 RASA0B RASA0# <40> DQB_52
MDA54 K9 K19 RASA1# 40.2_0402_1% M9X@ MDB53 AL7 T10 RASB0#
DQA_54 RASA1B RASA1# <40> DQB_53 RASB0B RASB0# <41>
MDA55 K10 MDB54 AM8 Y10 RASB1#
RASB1# <41>
2
MDA56 DQA_55 CASA0# +MVREFSB MDB55 DQB_54 RASB1B
G9 DQA_56 CASA0B K20 CASA0# <40> AM7 DQB_55
MDA57 A8 K17 CASA1# MDB56 AK1 W10 CASB0#
DQA_57 CASA1B CASA1# <40> DQB_56 CASB0B CASB0# <41>
MDA58 C8 MDB57 AL4 AA10 CASB1#
DQA_58 DQB_57 CASB1B CASB1# <41>
1
MDA59 E8 K24 CSA0#_0 1 MDB58 AM6
DQA_59 CSA0B_0 CSA0#_0 <40> DQB_58
MDA60 A6 K27 RV52 CV205 MDB59 AM1 P10 CSB0#_0
DQA_60 CSA0B_1 DQB_59 CSB0B_0 CSB0#_0 <41>
MDA61 C6 MDB60 AN4 L10
MDA62 DQA_61 CSA1#_0 0.1U_0402_16V4Z MDB61 DQB_60 CSB0B_1
E6 DQA_62 CSA1B_0 M13 CSA1#_0 <40> AP3 DQB_61
MDA63 2 MDB62 CSB1#_0
A5 K16 AP1 AD10 CSB1#_0 <41>
2
DQA_63 CSA1B_1 MDB63 DQB_62 CSB1B_0
AP5 DQB_63 CSB1B_1 AC10
+MVREFDA L18 K21 CKEA0 100_0402_1%
+1.5VS MVREFDA CKEA0 CKEA0 <40>
+MVREFSA L20 J20 CKEA1 U10 CKEB0
MVREFSA CKEA1 CKEA1 <40> CKEB0 CKEB0 <41>
+MVREFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <41>
MANHA@1 RV48 2 243_0402_1% L27 K26 WEA0# +MVREFSB AA12
NC_MEM_CALRN0 WEA0B WEA0# <40> +3VS_DELAY MVREFSB
MANHA@1 RV49 2 243_0402_1% N12 L15 WEA1# N10 WEB0#
NC_MEM_CALRN1 WEA1B WEA1# <40> WEB0B WEB0# <41>
MANHA@1 RV50 2 243_0402_1% AG12 AB11 WEB1#
NC_MEM_CALRN2 WEB1B WEB1# <41>
AF28
Close to pin L20 RSVD#1
1
MANHA@ RSVD#6 TESTEN M9X@ RV129 4.7K_0402_5% CLKTESTB DRAM_RST MANHA@ RV132 51_0402_5%
1
68P_0402_50V8J
RV45 RV45 T8 MAB13 1
RSVD#9
1
2
216-0729002 A12 M96_BGA962 216-0729002 A12 M96_BGA962
2
0.01U_0402_25V7K
1
1
RV47 CV204 @ @
100_0402_1%
2 Security Classification Compal Secret Data Compal Electronics, Inc.
2
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<39> ODTA0 ODT VDDQ ODT VDDQ <39> ODTA1 ODT VDDQ ODT VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
A_BA[2..0] <39> CSA0#_0 CS VDDQ CS VDDQ <39> CSA1#_0 CS VDDQ CS VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<39> A_BA[2..0] <39> RASA0# RAS VDDQ RAS VDDQ <39> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
<39> CASA0# CAS VDDQ CAS VDDQ <39> CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<39> WEA0# WE VDDQ WE VDDQ <39> WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
1
J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1
RV61 L1 B9 RV62 L1 B9 RV63 L1 B9 RV64 L1 B9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8
T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9
8PCS@ G1 8PCS@ G1 8PCS@ G1 8PCS@ G1
VSSQ VSSQ VSSQ VSSQ
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
1
1
8PCS@ 8PCS@ RV67 8PCS@ RV68 8PCS@ RV69 8PCS@ RV70 8PCS@ RV71 8PCS@ RV72 8PCS@
B RV65 RV66 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B
4.99K_0402_1% 4.99K_0402_1%
2
2
+VREFC_A2 +VREFD_A2 +VREFC_A3 +VREFD_A3 +VREFC_A4 +VREFD_A4
2
+VREFC_A1 +VREFD_A1
1
1
1 1 1 1 1 1
1
1 1 RV77 CV207 RV78 CV211 RV79 CV208 RV74 CV212 RV75 CV213 RV80 CV214
RV73 CV209 RV76 CV210 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 0.1U_0402_16V4Z 4.99K_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2 2 2
2
2
2 2
2
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@
CV218
CV219
CV220
CV221
CV222
CV223
CV224
CV237
CV225
CV226
CV238
CV239
CV227
CV240
CV228
CV241
CV229
CV242
CV243
CV230
8PCS@ 1 1 1 1 1 1 1
CV231
CV215
CV232
CV216
CV233
CV235
CV236
CLKA0# 1 2 1
RV82 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV234 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
8PCS@
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@8PCS@8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 40 of 52
5 4 3 2 1
5 4 3 2 1
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<39> ODTB0 ODT VDDQ ODT VDDQ <39> ODTB1 ODT VDDQ ODT VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<39> CSB0#_0 CS VDDQ CS VDDQ <39> CSB1#_0 CS VDDQ CS VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<39> RASB0# RAS VDDQ RAS VDDQ <39> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<39> CASB0# CAS VDDQ CAS VDDQ <39> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
<39> WEB0# WE VDDQ WE VDDQ <39> WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
C C
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<39,40> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9
1
1
J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1
RV85 L1 B9 RV86 L1 B9 RV87 L1 B9 RV88 L1 B9
4PCS@ NC VSSQ 4PCS@ NC VSSQ 4PCS@ NC VSSQ 4PCS@ NC VSSQ
243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8
T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
1
B RV89 RV90 RV91 RV92 4PCS@ RV93 4PCS@ @ RV94 4PCS@ RV95 4PCS@ RV96 4PCS@ B
4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2
2
+VREFC_B1 +VREFD_B1 +VREFC_B2 +VREFD_B2 +VREFC_B3 +VREFD_B3 +VREFC_B4 +VREFD_B4
1
1
1 1 1 1 1 1 1 1
RV97 CV253 RV98 CV254 RV99 CV255 RV100 CV256 RV101 CV257 RV102 CV258 RV103 CV259 RV104 CV260
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2
2
2
4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
CV272
CV273
CV274
CV275
CV287
CV276
CV277
CV278
CV279
CV280
CV281
CV282
CV283
CV284
CV288
CV285
CV286
4PCS@
CLKB0# 1 2
RV106 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
CV289 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS +1.5VS 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
4PCS@
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 1 1 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
4PCS@ CV193 + + CV290
330U_X_2VM_R6M
+1.5VS 10U_0603_6.3V 10U_0603_6.3V 390U_2.5V_M_R10 @ +1.5VS 10U_0603_6.3V 10U_0603_6.3V
CLKB1 2 2
1 2 1 1 1 1 1 1 1 1
A RV107 56_0402_1% A
CLKB1# 2 2 2 2 4PCS@ 2 2 2 2
1 2
RV108 56_0402_1% 1 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
4PCS@ CV299 4PCS@ 4PCS@ 4PCS@
4PCS@
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 41 of 52
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS
STRAPS +3VS_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
<35> GPU_GPIO0 GPU_GPIO0 @ RV109
@RV109 2 1 10K_0402_5%
GPU by the system BIOS GPU by VBIOS <35> GPU_GPIO1 GPU_GPIO1 @RV110
@ RV110 2 1 10K_0402_5% STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
<35> GPU_GPIO2 GPU_GPIO2 @RV111
@ RV111 2 1 10K_0402_5%
<35> SOUT_GPIO8 SOUT_GPIO8 @RV112
@ RV112 2 1 10K_0402_5%
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1) <35> SIN_GPIO9 SIN_GPIO9 @RV113
@ RV113 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0
<35> ROMSE_GPIO22 @RV114
@ RV114 2 1 10K_0402_5%
GPIO[13:11] MEMORY SIZE GPIO[13:11] <35> GPU_GPIO11 GPU_GPIO11 RV115 2 1 10K_0402_5% TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
<35> GPU_GPIO12 GPU_GPIO12 @RV116
@ RV116 2 1 10K_0402_5%
D GPU_GPIO13 @RV117
@ RV117 D
128MB 2 1 10K_0402_5%
0 0 0 <35> GPU_GPIO13
BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 0
256MB
1 0 0
0 0 1
64MB
(M25P05A) H@ RV118 10K_0402_5% BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
0 1 0 <16,35> R_VSYNC
<16,35> R_HSYNC H@ RV119
2
2
1
1 10K_0402_5%
<35> HSYNC_DAC2 @RV120
@ RV120 2 1 10K_0402_5%
<35> VSYNC_DAC2 @RV121
@ RV121 2 1 10K_0402_5% BIF_VGA DIS GPIO9 VGA Controller ENABLED 0 (Enable)
GPIO5_AC_BATT TEST
1
2 1 AUD[1] HSYNC 0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
M9X@ RV136 0.1U_0402_16V4Z AUD[0] VSYNC 1 0 Audio for DisplayPort only
100K_0402_5% 1 1 Audio for both DisplayPort and HDMI
RV134
2
2
S
G MANHA@
1 2 2 QV1 RSVD HSYNC_DAC2 0
0_0603_5%
AO3413_SOT23
1
D D RV3
M9X@
1
M9X@ QV2 47K_0402_5% RSVD GENERICC 0
<48> PCIE_OK 1 2 2
1
C M9X@ RV60 0_0402_5% G M9X@ M9X@ 100mA C
CV322
1
S SSM3K7002FU_SC70-3
3
1 2
M9X@ RV135
100K_0402_5% AMD RESERVED CONFIGURATION STRAPS
0.01U_0402_25V7K
2
+3VS_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
HSYNC_DAC2 GENERICC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
+1.8VS
GPIO_28_TDO GPIO21_BB_EN
1
VRAM_ID0 <35>
VRAM_ID1 <35> 512M 64Mx16 (x4) HYN H5TQ1G63BFR-12C SA000032400 000
B B
VRAM_ID2 <35>
512M 64Mx16 (x4) SAM K4W1G1646E-HC12 SA000035700 001
1
Park M2
RV126 RV127 RV128
10K_0402_5% 10K_0402_5% 10K_0402_5% 1G 128Mx16 (x4) HYN 0 1 0 (Reserve)
@ @ @
2
1 2
RV130 0_0402_5%
1
A A
CV300 M92 XTX Madison Park
UV11 M92@ MADISON@ PARK@
0.1U_0402_16V4Z 2
1 VDD SCLK 8 EC_SMB_CK2 <7,30>
2200P_0402_50V7K
D- ALERT# THERM#_VGA <35> Security Classification Compal Secret Data Compal Electronics, Inc.
<35> GPU_THERMAL_D- 4 THERM# GND 5 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
ADM1032ARMZ-2REEL_MSOP8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 42 of 52
5 4 3 2 1
A B C D
VS
VIN PR1
VIN 1M_0402_1%
PL1
PF1
DC30100A700 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2
1
1
PJP1 SMB3025500YA_2P N1 PR2
1 10A_125V_451010MRL PR3 5.6K_0402_5% PR4
+ 84.5K_0402_1% 10K_0402_1%
1
1 1
2 1 2
2
+ PC1 PC2 PC3 PC4 PR5 ACIN <21,30,32>
8
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 22K_0402_1% PU1A
2
-
1 2 3
P
+ PACIN
- 4 O 1
2 PACIN <45>
-
G
@ SINGA_2DW-0005-B03
1
PR6 LM393DG_SO8
4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%
2
2
2
2 1 +CHGRTC
PR8
VIN 10K_0402_1%
3.3V Vin Detector
2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976
1
PD3
BATT+ 2 1
1
RLS4148_LL34-2 PR9 PR10
68_1206_5% 68_1206_5%
PQ1
PU2 G920AT24U_SOT89-3 PR11 TP0610K-T1-E3_SOT23-3
3.3V PR18
2
200_0603_5%
2
3 2 N2 1 2 CHGRTCP 1 2 N1 3 1 VS
2
+CHGRTC OUT IN
200_0603_5%
1
1
GND
1
PC9 PC10 PC8 PR13 1K_1206_5%
10U_0805_10V4Z 1 PR12 0.1U_0603_25V7K 1 2
2
2
0.22U_0603_25V7K PD4 PR14 1K_1206_5%
2
2
2 1 N3 1 2
<32> 51_ON# 1 2
VIN B+
PR15 RLS4148_LL34-2 PR16 1K_1206_5%
22K_0402_1% 1 2
RTC Battery
1
PR19 PR20
100K_0402_1% 2.2M_0402_5% PR17
1 2 2 1 499K_0402_1%
VL
- +
2
PBJ1 PR21 PR22
560_0603_5% 560_0603_5%
2 1 1 2 1 2 +RTCBATT +RTCBATT PD5 LM393DG_SO8
8
RB715F_SOT323-3 PU1B
2 5
P
<46> EN0 1 7
+
@ MAXEL_ML1220T10 O
3 6 2 1 +CHGRTC
<45> ACON -
1
G
1
PR23 PR24 PC11
1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K
1
PC12 PR26
SP093MX0000
2
PC13 @ PR25 191K_0402_1%
2
3 3
2
PR27
PJ3
1
PJ1 PJ2 D 47K_0402_1%
+3VALWP 2 1 +3VALW +1.1VALWP 2 1 +1.1VALW +3VLP 2 1 +3VL 2 2 1 PACIN
2 1 2 1 2 1 G
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39 S PQ2
3
(5A,200mils, Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2) SSM3K7002FU_SC70-3
1
2 2 1 1
OCP(min) = 7.7A
@ JUMP_43X118
(12A,480mils, Via NO.= 24)
PJ5 PJ18 2 +5VALWP
+5VALWP 2 2 1 1 +5VALW OCP(min) = 18.7A +1.0VSP 2 2 1 1 +1.0VS
@ JUMP_43X118 @ JUMP_43X79 PQ3
(5A,200mils, Via NO.= 10) PJ7 (2.5A,100mils, Via NO.= 5) DTC115EUA_SC70-3
3
+1.5VP 2 1 +1.5V
2 1
OCP(min) = 7.9A
@ JUMP_43X118
PJ8 PJ9
PJ19 PJ20
2 1 2 2 +VGA_COREP +VGA_CORE
+VSBP 2 1 +VSB 1 1 +2.5VSP 2 2 1 1 +2.5VS 2 2 1 1
PJ13
+1.05VSP 2 2 1 1 +1.05VS Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X79 Issued Date 2008/9/25 Deciphered Date 2009/9/25 Title
(1.5A,60mils, Via NO.= 3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 43 of 52
A B C D
A B C D
VMB
1
PF2 PL2
Rset = 3 * Rtmh 1
PJP2
BATT_S1
15A_65V_451015MRL SMB3025500YA_2P Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
1 1 1 2 1 2 BATT+
2 2
3 BATT_P3 1 2 1 2
3 +3VLP
BATT_P4 PR28 PR29
4 4 Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K
1
5 BATT_P5 1K_0402_1% 47K_0402_1%
5 EC_SMDA PC14 PC15
10
11
GND 6 6
7 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K Rset = 3 * 7.87K = 23.61K ==> 23.7K
2
GND 7
12 GND 8 8 Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
1
13 GND 9 9
PR32
1
SUYIN_200045MR009G171ZR @PD6
@ PD6 1K_0402_1%
@
PJSOT24C_SOT23-3
2
VL
3
PD8
@
23.7K_0402_1%
2
1
1
PR31
3 PC16 PR30
0.1U_0603_25V7K 23.7K_0402_1%
2
PJSOT24C_SOT23-3
2
PR37 PU3
6.49K_0402_1% 1 8
VCC TMSNS1
2 1 +3VLP
2
2
2 GND RHYST1 7
PR38 PR39 PR33
100_0402_1% 100_0402_1% <46> VS_ON 3 6 11.3K_0402_1%
2 OT1 TMSNS2 2
1
2
4 5
1
1
PR40 OT2 RHYST2 PR34
1K_0402_1% G718TM1U_SOT23-8 11.3K_0402_1%
2
1
PH1
BATT_TEMPA <30>
100K_0402_1%_NCP15WF104F03RC
2
PH2
EC_SMB_DA1 <30>
100K_0402_1%_NCP15WF104F03RC
EC_SMB_CK1 <30>
2
PQ6
TP0610K-T1-E3_SOT23-3
+VSBP
B+ 3 1 PH2 near main Battery CONN :
100K_0402_1%
3 3
PR43
@ PC20
Recovery at 56 degree C
@ PC19
@PC19
2
PR45 0.22U_0603_25V7K
2
22K_0402_1%
VL 1 2
2
PR47
100K_0402_1%
PR48
1
0_0402_5% D
1 2 2 PQ7
<46,47> POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K
S
3
1
@ PC22
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 44 of 52
A B C D
A B C D
PC163
10U_1206_25V6M PQ8
1 2 AO4407A_SO8
6 3 3 6 0.015_2512_1% PJ22
4
VIN 5 5 1 4 2 2 1 1 PQ11
AO4407A_SO8
2 3 @ JUMP_43X79 CSIN 1 8
4
2 7
3 6
10U_1206_25V6M
10U_1206_25V6M
CSIP 5
1
1 1
1
PQ12 TP0610K-T1-E3_SOT23-3 PR51
4
3
PC23
PC24
PQ13 PR50 10_0603_5%
2
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN
2
PC25 P3 PR54
2
1
1
2 5600P_0402_25V7K PQ14 47K_0402_1%
1
PC26 PR53 DTC115EUA_SC70-3 1 2
PR52 0.1U_0603_25V7K 100K_0402_1% VIN
2
47K_0402_1% PD10
PR55 2 FSTCHG
2
2
100K_0402_1% 2 1
1
2
1
2.2U_0603_6.3V6K
1SS355_SOD323-2
1
PC27
2 PR57 PR58
1
PQ15 10K_0402_1% 200K_0402_1%
1
DTC115EUA_SC70-3 2 1 PU4 PC29 1 2 VIN
<30> FSTCHG 0.1U_0603_25V7K
2
1
100K_0402_1%
1 2 1 24 DCIN 2 1
3
VDD DCIN
1
1
2 PQ17 PQ16 PD13
PR60
G SSM3K7002FU_SC70-3 PC28 DTC115EUA_SC70-3 2 1 2
S PR59 .1U_0402_16V7K 2 23
3
2
6251_EN 3 22 1 2 CSON
3
EN CSON
1
PC30 D
5
6
7
8
1
0.047U_0603_16V7K PC32 2 PACIN
4 21 1 2 CSOP 0.1U_0603_25V7K G
1
CELLS CSOP PR62 PQ19 PQ18
S
3
PC33 6800P_0402_25V7K 20_0603_5% AO4466_SO8 SSM3K7002FU_SC70-3
2 2
1 2 5 ICOMP CSIN 20 2 1
1
2
D PR63 4
2 PQ20 PC35 PR64 6.81K_0402_1% PC34 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2 PL4
1
PR66 VCOMP CSIP 10U_LF919AS-100M-P3_4.5A_20% PR67
S
3
3
2
1
PR68 PC36 1 2 7 18 LX_CHG 2.2_0603_5% 1 2CHG 1 4
22K_0402_5% @ 100P_0402_50V8J ICM PHASE
5
6
7
8
10U_1206_25V6M
10U_1206_25V6M
PACIN 1 2 1 2 2 3
<43> PACIN
10U_1206_25V6M
10U_1206_25V6M
6251VREF 8 17 DH_CHG @PR69
@ PR69
PC37 .1U_0402_16V7K VREF UGATE PR70 PC38 4.7_1206_5%
<43> ACON
1
PC166
PC167
PR71 2.2_0603_5% 0.1U_0603_25V7K
<30> ADP_I
1
PC39
PC40
154K_0402_1% 9 16 BST_CHG 1 2 BST_CHGA 2 1
1 2
CHLIM BOOT
1
1
PQ22 2 1 4 PQ21
2
<30> IREF
0.01U_0402_25V7K
2
53.6K_0402_1% 10 15 6251VDDP RB751V-40TE17_SOD323-2 680P_0603_50V7K
ACLIM VDDP
1
6251VREF 1 2 6251aclim
2
1
PC42
5.49K_0402_1%
3
2
1
1
120K_0402_1% 11 14 DL_CHG
VADJ LGATE
2
PR35
PR74
2
4.7_0603_5%
2
12 13 PC43
3
1
GND PGND
SSM3K7002FU_SC70-3
4.7U_0805_6.3V6K
1 2
20K_0402_1%
D
PR75
ISL6251AHAZ-T_QSOP24
PQ5
2
<30> 75W_65W G
S
3
3
PR76 3
15.4K_0402_1% VIN
1 2 VADJ
<30> CHGVADJ
1
1
PR77 PR78
31.6K_0402_1% 309K_0402_1%
PR79
2
2
10K_0402_1%
1 2
CP mode ADP_V <30>
Vaclim=2.39*(Rb//152K/(Rt//152K+Rb//152K))
1
1
Iinput=(1/PR49)((0.05*Vaclm)/2.39+0.05) @ PD15 PR80
GLZ4.3B_LL34-2 47K_0402_1% PC44
where Vaclm=0.6221V, Iinput=3.15A
.1U_0402_16V7K
2
Vaclm=1.09986V, Iinput=3.65A
(75W) Iin = 2.512 ADP_I
2
Vaclm=0.7717V, Iinput=4.41A
Vaclm=0.4204V, Iinput=5.88A (120W) Iin = 3.35 ADP_I
Vin = 7.57 ADP_V
CC=0.25A~3.6A CHGVADJ=(Vcell-4)*9.445
IREF=0.9133*Icharge Vcell CHGVADJ
Iada=0~3.421A(65W) CP=3.15A PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=high
IREF=0.228V~3.29V 4V 0V
Iada=0~3.947A(75W) CP=3.63A PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=low
VCHLIM need over 95mV 4.2V 1.898V
4
Iada=0~4.737A(90W) CP=4.36A PR49=0.015, PR72=53.6k, PR75=20k, PR35=unpop, PQ5=unpop 4
4.35V 3.315V
Iada=0~6.316A(120W) CP=5.81A PR49=0.015, PR72=8.25k, PR75=26.7k, PR35=unpop, PQ5=unpop
CP= 92%*Iada
CELLS VDD GND Float
CELL number 4 3 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/9/25 Deciphered Date 2009/9/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 45 of 52
A B C D
5 4 3 2 1
1U_0603_10V6K
Ipeak = 5A Ipeak = 5A
Imax = 3.5A Imax = 3.5A
1
D D
F = 305K F = 245K
PC45
2
PR81 PR82
13K_0402_1% 30K_0402_1%
1 2 1 2
PR83 PR84
B++
20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++
PJ24
ENTRIP2
B+ 2 2 1 1 +3VLP
ENTRIP1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
10U_1206_25V6M
1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
150K_0402_1% 150K_0402_1%
1
PC46
PC47
PC48
4.7U_0805_10V6K
1 2 1 2
1
PC168
5
6
7
8
PC49
PC50
PC51
PC52
2
8
7
6
5
1
2
PQ23
AO4466_SO8
1
PQ24 PU5
C AO4466_SO8 4 C
ENTRIP2
REF
FB2
FB1
ENTRIP1
TONSEL
4
25 P PAD
POK <44,47>
3
2
1
7 24
1
2
3
VO2 VO1
PL6 PC53 8 23 PC54 PL7
4.7UH_SIL104R-4R7PF_5.7A_30% .1U_0402_16V7K PR87 VREG3 PGOOD PR88 .1U_0402_16V7K 4.7UH_SIL104R-4R7PF_5.7A_30%
1 2 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 1 2
+3VALWP 0_0603_5% BOOT2 BOOT1 0_0603_5%
UG_3V 10 21 UG_5V +5VALWP
UGATE2 UGATE1
8
7
6
5
5
6
7
8
1
1
PQ25 LX_3V 11 20 LX_5V
PHASE2 PHASE1
220U_6.3VM_R15
@ PR89 AO4712_SO8 @ PR90
220U_6.3VM_R15
SKIPSEL
+ +
PC55
PC56
4 4
VREG5
1 2
1 2
GND
VIN
@ PC57 RT8205EGQW_WQFN24_4X4
NC
EN
2 680P_0603_50V7K @ PC58 2
<43> EN0 680P_0603_50V7K
2
1
2
3
13
14
15
16
17
18
3
2
1
2
PR91
499K_0402_1%
B+ 1 2
1
100K_0402_1%
1U_0402_6.3V6K
1
PR92
PC59
1
ESR = 15mohm ENTRIP1 ENTRIP2
PC60
4.7U_0805_10V6K
PR93
2
@ 0_0402_5%
Total capacitor 220uF
2
ESR = 15mohm
B++
1
1
D D
0.1U_0603_25V7K
PQ27 2 2 PQ28
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
2
PC61
S S
3
2VREF_51125
VL 2 1
PR94
100K_0402_1%
1
<44> VS_ON
PQ29
VS 1 2 2
DTC115EUA_SC70-3
PR95
A A
1
100K_0402_1%
PR96
3
42.2K_0402_1%
2
PJ25
1.1V_B+ 2 1 B+
2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
Ipeak = 12A
1
PC62
PC63
Imax = 8.4A
2
F = 315K
D D
PR97
255K_0402_1%
1 2
4 Total capacitor 720uF
PR98 PR99 PQ30 ESR = 6.3mohm
0_0402_5% 0_0603_5% TPCA8030-H_SOP-ADV8-5
<44,46> POK 1 2 1 2
3
2
1
1
PL9
15
14
PC65
1
@ PC64 PU6 1UH_FDUE1040D-1R0M-P3_21.3A_20%
.1U_0402_16V7K BST_1.1V 1 2 1 2
NC
EN/DEM
BOOT
+1.1VALWP
4.7_1206_5%
PR101 3 12 LX_1.1V
VOUT PHASE
@ PR100
100_0603_1% 1
390U_2.5V_M
+5VALW 1 2 4 11 1 2 +5VALW PQ31
VDD CS
PC66
PR102 +
2
5 10 6.19K_0402_1%
FB VDDP
1
1
DL_1.1V 2
6 PGOOD LGATE 9 4
PGND
680P_0603_50V7K
PC67
GND
@ PC68
4.7U_0603_6.3V6K @ PC70
2
2
47P_0402_50V8J PC69
1 2 RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K TPCA8028-H_SOP-ADVANCE8-5
3
2
1
PR103
4.75K_0402_1%
1 2
C C
1
PR104
10K_0402_1%
2
PJ26
1.5V_B+ 2 1 B+
2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC71
PC72
Ipeak = 11A
5
Imax = 7.7A
2
F = 315K
PR105
255K_0402_1% 4
1 2
PR107
PR106
0_0603_5% PQ32
Total capacitor 1390uF
<30,33> SYSON 1 2 1 2 TPCA8030-H_SOP-ADV8-5 ESR = 2.73mohm
3
2
1
0_0402_5%
1
PL11
15
14
PC74
1
BOOT
+1.5VP
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON UGATE
1
PR109 3 12 LX_1.5V @ PR108
VOUT PHASE
5
100_0603_1% 4.7_1206_5% 1
220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ33
VDD CS +
PC75
PR110
2
5 10 6.19K_0402_1%
FB VDDP
1
1
DL_1.5V 2
6 PGOOD LGATE 9 4
PGND
680P_0603_50V7K
PC76
GND
@ PC77
4.7U_0603_6.3V6K @ PC79
2
2
47P_0402_50V8J PC78
1 2 RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K TPCA8028-H_SOP-ADVANCE8-5
7
3
2
1
PR111 PU8
10K_0402_1% APL5508-25DC-TRL_SOT89-3
PJ14
1 2 +3VS
1 1 2 2 2 IN OUT 3 +2.5VSP
1
@ JUMP_43X39
PR112 GND
1
10K_0402_1%
PC80 1 PC81
2
1U_0603_10V6K 4.7U_0805_6.3V6K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 47 of 52
5 4 3 2 1
5 4 3 2 1
D D
+1.5V
1
VDDR_SW VDDR
PJ15
1
@ JUMP_43X79
HIGH 1.05V PR114
2
200K_0402_1%
1 2 SUSP# <30,33,45,50>
2
LOW 0.9V
2
1
1
4.7U_0805_6.3V6K PR116
PR193 PR118 PC83
2
2
1 6 +5VALW 2 1 1 10
2
@ PR194
1U_0603_6.3V6M
10K_0402_1% PQ48 2 5 PC85 2 9 PL18
GND NC GND GND
1
1
D
PC82
.1U_0402_16V7K 2.2UH_FMJ-0630T-2R2 HF_8A_20%
2
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
S PR113 4 8 1 2 4 7
3
VOUT NC 1 2 IN IN
B340A_SMA2
PR195 6.98K_0402_1%
1
PD16
PC88
PC89
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_25V6
10K_0402_1% 9 1 2 5 6 PR165
2
2
PC127
PC128
PC129
RT9173DPSP_SO8 0_0402_5% 11 @
2
1 2
2
TP
.1U_0402_16V7K
C C
2
1
1
1
D
PC86
2
1
G
2
1
S PQ4 PC87
3
.1U_0402_16V7K
2
+1.5V
1
+1.5V +5VALW PJ17
1
@ JUMP_43X79
1U_0603_6.3V6M
1
2
1
PC132
@ PJ23 PU11
1
2
JUMP_43X79 1 6 +3VALW
+3VS VIN VCNTL
2
2
2 GND NC 5
1
B PU14 PC92 B
2
1
1
APL5930KAI-TRG_SO8 4.7U_0805_6.3V6K 3 7 PC93
PR119 REFEN NC 1U_0603_6.3V6M
6
2
VCNTL
1
9
2
2
GND
1
1
0.01U_0402_25V7K
8 PR168
EN
PC134
.1U_0402_16V7K
0_0402_5% 22U_0805_6.3V6M
2
1
1 2 PR121 +0.75VSP
<30,33,45,50> SUSP#
2
1
D
PC94
0_0402_5% PR120
1
1
1 2 2 1K_0402_1%
<33> SUSP
1
1
@ PC136 G
2
1
.1U_0402_16V7K PR170 S PQ34 PC95
2
2
7.32K_0402_1% @ PC96 SSM3K7002FU_SC70-3 10U_0805_6.3V6M
2
.1U_0402_16V7K
2
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 48 of 52
5 4 3 2 1
A B C D E
CPU_B+ PL12
HCB4532KF-800T90_1812
PC97 1 2 B+
10U_1206_25V6M
33P_0402_50V8J
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
2 1 1 1 1 1
5
6
7
8
PC99
1
+ + + +
PC101
PC98
@ PC160
@ PC161
2 1 2 1
2
PR122 PC100 2 2 2 2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 PQ35
PR123 AO4466_SO8
1 2_0603_5% 1
3
2
1
2 1 PHASE_NB 1 2 +VDDNBP
PR124
5
6
7
8
1
PC103 PR126 2.2_0603_1%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 @ PR125 1
Ipeak = 36A
2 1 4.7_1206_5% Imax = 25.2A
2
PR187 PC104 + PC105
10_0402_1% 0.22U_0603_10V7K PQ36 220U_D2_4VM F = 300K
1 2
1 2 +VDDNB LGATE_NB 4 AO4712_SO8
PR128 @ PC106 2
CPU_B+ 1 2
0_0402_5% 680P_0603_50V7K
PR127 2 1 CPU_VDDNB_RUN_FB_H <7>
2
2_0603_5% PR129
Total capacitor 1320uF
3
2
1
+5VS +3VS 11K_0402_1%
2 1 PHASE_NB ESR = 2.22mohm
LGATE_NB
1
PC107 PR188 CPU_B+
0.1U_0603_25V7K PHASE_NB 10_0402_1%
1
1
1 2
2
1
PR130 UGATE_NB
10U_1206_25V6M
10U_1206_25V6M
0_0402_5% @PR131
@ PR131
1
5
PR132 105K_0402_1% 2 1 CPU_VDDNB_RUN_FB_L <7>
105K_0402_1% PR133 PQ37
2
1
PC108
PC109
0_0402_5%
2
@ PR134
10K_0402_1%
2
2
1
UGATE0 4
PR135
48
47
46
45
44
43
42
41
40
39
38
37
<30,33> VGATE @ 105K_0402_1% PU12
2 PHASE0 PL14 2
FB_NB
COMP_NB
FSET_NB
VSEN_NB
OCSET_NB
LGATE_NB
VIN
VCC
RTN_NB
PGND_NB
PHASE_NB
UGATE_NB
PR137 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
3
2
1
0_0603_5%
1 2 1 36 BOOT_NB BOOT0 1 2 1 2 1 4 +CPU_CORE
<7,19> H_PWRGD @PR136
@ PR136 0_0402_5% OFS/VFIXEN BOOT_NB
BOOT0 PC110
TPCA8028-H_SOP-ADVANCE8-5
TPCA8028-H_SOP-ADVANCE8-5
2 PGOOD BOOT0 35 2 3
5
1 2 0.22U_0603_10V7K
1
<19> H_PWRGD_L PR138 0_0402_5% ISL6265_PWROK 3 34 UGATE0
PWROK UGATE0
2
@ PR139
<7> CPU_SVD 2 1 4 33 PHASE0 4.7_1206_5% PR141
<7> CPU_SVC SVD PHASE0
PQ38
@ PQ39
PR140 16.5K_0402_1%
0_0402_5%2 1 5 32 4 4
1 2
<30,33> VR_ON PR142 SVC PGND0 +5VS
1
PR143 PR144 0_0402_5% 6 31 LGATE0 @ PC111 PC112
21.5K_0402_1% 95.3K_0402_1% ENABLE ISL6265AHRTZ-T_TQFN48_6X6 LGATE0 680P_0603_50V7K 2 1
2 1 2 1 7 30
3
2
1
3
2
1
2
RBIAS PVCC 0.1U_0603_16V7K
8 29 LGATE1
OCSET LGATE1
1
PC113 2 1
9 28 1U_0603_10V6K
VDIFF0 PGND1 LGATE0 PR145
ISN0
ISP0
10 27 PHASE1 4.02K_0402_1%
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1
VW0 BOOT1
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
ISN0
ISN1
ISP0
VW1
ISP1
FB1
10U_1206_25V6M
10U_1206_25V6M
TP
5
PR189 PQ40
13
14
15
16
17
18
19
20
21
22
23
24
49
1
PC114
PC115
+CPU_CORE 2 1
3 ISP0 3
10_0402_1% PR146 ISN0
2
ISN1
ISP1
0_0402_5% UGATE1 4
2 1 VSEN0
<7> CPU_VDD0_RUN_FB_H 0_0402_5%
2 PR147 1 RTN0 PHASE1 PL15
<7> CPU_VDD0_RUN_FB_L PR190 PR149 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
10_0402_1% 0_0603_5%
2 1 BOOT1 1 2 1 2 1 4 +CPU_CORE
1RTN1 PC116
TPCA8028-H_SOP-ADVANCE8-5
@ TPCA8028-H_SOP-ADVANCE8-5
2 2 3
5
<7> CPU_VDD1_RUN_FB_L @ PR191
@PR191 0.22U_0603_10V7K
2
1
1K_0402_1%
2
PR150
2 1 @ PR151
4.7_1206_5% PR152
PQ41
PQ42
PR192 16.5K_0402_1%
+CPU_CORE 2 1 4 4
1
1 2
+1.5V
1
10_0402_1% PR153 @ PC117 PC118
0_0402_5% 680P_0603_50V7K 2 1
<7> CPU_VDD1_RUN_FB_H 2 1 VSEN1
3
2
1
3
2
1
2
0.1U_0603_16V7K
ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K 4.02K_0402_1%
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
PR163 PR164
@ 36.5K_0402_1% @ 36.5K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/9/25 Deciphered Date 2009/9/25 Title
SCHEMATIC,MB A6054
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 49 of 52
A B C D E
5 4 3 2 1
B+ 1 2 B+_core
PL16 LX_VCORE
HCB4532KF-800T90_1812
10U_1206_25VAK
4.7U_0805_25V6-K
10U_1206_25VAK
DH_VCORE
1
PC139
PC137
PC138
1 2 1 2
BST_VCORE
2
PR171 PC143
0_0603_5% 0.1U_0603_25V7K
D
Ipeak =20A D
+5VALW
Imax = 14A
1
F = 231K
5
PR172
0_0603_5% PQ43
27138_VCC
16
15
1
2
8
1
PU15
PR173 4
Total capacitor 1170uF
PHASE
BOOT
UG
GND
PGOOD
4.7_0603_5% ESR = 3.33mohm
3 VIN PVCC 14 1 2 PC146
TPCA8030-H_SOP-ADV8-5
3
2
1
2.2U_0603_6.3V6K
PL17
2.2U_0603_6.3V6K
PC147
7138_VCC 4 13 DL_VCORE +VGA_COREP
VCC LG 0.56UH_ETQP4LR56WFC_21A_20%
1
1 2
APW7138NITRL_SSOP16
1
TPCA8028-H_SOP-ADVANCE8-5
TPCA8028-H_SOP-ADVANCE8-5
12
2
PGND
390U_2.5V_M
@ PR174
10U_1206_25VAK
10U_1206_25VAK
4.7_1206_5% 1
PR175
PQ45
PC148
1
1 2 5 11 ISEN_VCORE 1 2 +
1 2
EN ISEN
2
<30,33,45,48> SUSP#
0_0402_5%
PQ44
@ PC149
PC150
4 4 @
1
PR177
0_0402_5% .1U_0402_16V7K PR176 @ PC153
FSET
2
2
PC152
5.36K_0402_1%
NC
VO
FB
680P_0603_50V7K
2
2
C C
10
3
2
1
3
2
1
1
PR178
57.6K_0402_1%
2 1 +VGA_CORE
49.9K_0402_1%
1
10_0402_1%
1
@ PR179
PR180
@ PC155
0.01U_0402_25V7K
2
2
2
1
1
@ PC154
2200P_0402_25V7K
22P_0402_50V8J @PC157
@ PC157
2
2
1
1000P_0402_50V7K
@ PC156
2
4.22K_0402_1%
2
2
1
PR181
PR182 PR183
@ PC165 5.9K_0402_1% 28K_0402_1%
B 1000P_0402_50V7K B
2
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)
1
1
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PR185 PR186
1
D 10K_0402_1% D 10K_0402_1%
Madison/Park M96/M92
PQ46
PQ47
2 1 2 2 1 2
SEL1 SEL0 voltage voltage G G
1
3
1
1
PR184 PC158 PC159
L L 1.2 1.2 4.22K_0402_1% 2 .1U_0402_16V7K .1U_0402_16V7K
2
2
L H 1.12 1.0
H L 0.95 0.95
H H 0.9 0.9
FSW=1/(75E-12*57.6K)=231.48KHz
Madison M96
Park M92
A A
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 51 of 52
5 4 3 2 1
5 4 3 2 1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6054
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401871 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 19, 2010 Sheet 52 of 52
5 4 3 2 1
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