ELECTRICAL AND ELECTRONICS ENGINEERING

&
COMPUTER ENGINEERING

EEE 248 CNG 232

Logic Design

Dr. Gürtaç Yemişçioğlu

FALL 2020
HW2
Number of Questions: 4

December 28, 2020

Good Luck

Student Number:
Full Name:

Question Achieved Points

1 24
2 36
3 20
4 20
Total 100
 EEE 248 CNG 232
Logic Design
Fall 2020 - 2021 HW2 28 December 2020

Question 1 (24 pts.):

a. (4 pts.) Determine the timing diagram shown below
i. (2 pts.) For output Q for gated S-R latch. Assume that Q is initially LOW.

ii. (2 pts.) Given a positive edge triggered JK flip-flops.

Dr. Gürtaç Yemişcioğlu Page| 2

 EEE 248 CNG 232
Logic Design
Fall 2020 - 2021 HW2 28 December 2020

b. (20 pts) Analyse the circuit given below.

SET A
J Q

CLR
K Q

SET B
J Q
x
CLR
K Q

SET C
J Q

CLR
K Q

CLK

i. (8 pts.) Derive the next state equations for each flip-flop.

ii. (6 pts.) Tabulate the state table.

iii. (6 pts.) Draw the corresponding state diagram.

Dr. Gürtaç Yemişcioğlu Page| 3

 EEE 248 CNG 232
Logic Design
Fall 2020 - 2021 HW2 28 December 2020

Question 2 (36 pts.):

a. (6 pts) Determine the functional behaviour of the circuit shown below. Assume that
input w is driven by a square wave signal.

b. (30 pts.) The state diagram of a synchronous sequential circuit is shown below.

00/0 1
0

0
1
11/1 01/1
1

0
0
10/0

a. (2 pts.) Is this a Mealy or Moore model, Why?

b. (4 pts.) Starting from state 00 determine state transitions and output sequence
that will be generated when an input sequence of 001001001110000 is
applied.
c. (12 pts.) Design a sequential circuit using T flip-flops.
d. (12 pts.) Design a sequential circuit using JK-flip-flops. For J-K implementation,
J-K inputs must be determined by tabulating a new state table.

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 EEE 248 CNG 232
Logic Design
Fall 2020 - 2021 HW2 28 December 2020

Question 3 (20 pts.):

a. (6 pts) The contents of a four-bit register is initially 1001. The register is shifted 10
cycles to the right with the serial input being 1100101001. What is the content of
the register after each shift?
b. (6 pts) The serial adder shown below uses two four-bit registers. Register A holds
the binary number 0011 and register B holds 1000. The carry flip-flop is initially
reset to 0. List the binary values in register A and the carry flip-flop after each shift.

Cycle no. regA regB x y J K carry sum

1
2
3
4
5

c. (8 pts) We build a new type of flip-flop as shown below.

A
B
S ET

D Q Qo
CLK
C LR
Q

ii. (4 pts.) Write the characteristic equation of this flip-flop.

iii. (4 pts.) Given the following waveforms for A, B and CLK (rising edge activated),
draw the waveform for Qo.

1
CLK
0

1
A
0

1
B
0

1
Q0
0

Dr. Gürtaç Yemişcioğlu Page| 5

 EEE 248 CNG 232
Logic Design
Fall 2020 - 2021 HW2 28 December 2020

Question 4 (20 pts.): The data path is given for a 4-bit multiplier. It consists of a 4-bit adder,
a 4-bit register, and a 9-bit shift register. The latter shifts right when its Sh input is
asserted (assume that 0's are entered at the left for this operation). A new value is loaded
into the high-order 5 bits of the shift register when Ld is asserted. The same 5 bits are
zeroed when Cl is asserted These signals are synchronous. Design the control for a
sequential 4-bit multiplier.
4-bit
Multiplier

Sh
M
Ld
Cl

Shift
4-bit right
Multiplicand
Control S
Unit
4

Sh
Ld
Cl
Carry Out
+

a. (10 pts.) Sketch a complete state diagram for the operation of the Control Unit.
b. (10 pts.) Sketch a logic implementation of the Control Unit using D-type flip-flops
and logic gates of your choice using one-hot state assignment. You do not have to
show the transition/state tables.

Dr. Gürtaç Yemişcioğlu Page| 6