2408 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 37, NO.
11, NOVEMBER 1990
remaining in a 60 A film would be sufficient to contaminate a 5000
A film. In practice, no evidence has been found for contamination
of the PMMA.
It should be pointed out that while the PPAP is specifically re-
ported in relation to its usefulness for PMMA processing that it is
also useful for other resist systems. In particular, this process has
been successfully applied to i-line photoresists which have excel-
lent resolution but poor adhesion. The only change to the process
was to bake the PPAP at 180°C for 5 min as opposed to the normal
40-s, 110°C bake.
IV. S U M M A R Y
A positive photoresist has successfully been used as an adhesion
promoter for PMMA resist on GaAs wafers. It can be used with
PMMA for both e-beam direct write patterning and deep-UV pat-
terning levels. It is able to maintain resist adhesion during wet
chemical etching, as well as plasma etching, and will clean up with
standard metallization liftoff techniques.
It recently has been applied to other non-PMMA resist systems
as well. Anywhere there are adhesion problems in photoresist pro-
cessing the PPAP should be considered as a possible solution.
It should be noted that the originial experiments were performed
before the PPAP had been installed on the SVG production equip-
ment (i.e., the PPAP was dispensed on a manual spinner). Subse-
quent to the initial experiments the PPAP has been plumbed into
the SVG track. The PPAP process is now fully automated and run-
ning in production.
ACKNOWLEDGMENT
The authors wish to thank F. Fleming for help with this manu-
script.
REFERENCES
[ l ] M. Levinson and C. W. Wilkins, “GaAs process compatible adhesion
promoter for PMMA resists,” J . Electrochem. Soc., Solid-State Sri.
and Tech., vol. 133, no. 3, p. 619, 1986.
121 K. L. Mittal, “Factors affecting adhesion of lithographic materials,”
Solid State Technol.. p. 93, May 1979.
[3] R. E. Williams, GaAs Processing Techniques. Dedham, MA: Artech
House, 1984, p. 137.
141 L. F. Thompson, C. G. Willson, and M. J. Bowden, Introduction to
Microlithography (ACS Symp. Ser., vol. 219), 1983, p. 91.
[ 5 ] B . J. Lin, V. Bassous, V. Chao, and K. Petrillo, “Practicing the no-
volac deep-UV portable conformable masking technique,” J . Vac. Sci.
Techol., vol. 19, no. 4, p. 135, Nov./Dec. 1981.
The Effects of Source/Drain Resistance on Deep
Submicrometer Device Performance
MIN-CHIE JENG, JAMES E. CHUNG, PING-KEUNG KO, AND
CHENMING HU
Abstract-As MOSFET channel lengths approach the deep-submi-
crometer regime, performance degradation due to parasitic source/
Manuscript received January 17, 1990; revised April 3, 1990. This proj-
ect was funded by JSEP under Contract F49620-84-C-0057, Signetics, the
California State MICRO program. The review of this brief was arranged
by Associate Editor A. F. Tasch, Jr.
The authors are with the Department of Electrical Engineering and
Computer Sciences, Electronics Research Laboratory, Univeristy of Cali-
fornia, Berkeley, CA 94720.
IEEE Log Number 9036875.
0018-9383/90/1100-2408$01.00 0 1990 IEEE
drain resistance ( R s d ) becomes an important factor to consider in de-
vice scaling. This brief examines the effects of Rsd on the device per-
formance of deep-submicrometer non-LDD n-channel MOSFET’s. Re-
duction in the measured saturation drain current (Rid = 600 11 . pm)
relative to the ideal saturation current (Rsd = 0.0 11 . pm) is about 4%
for Le,, = 0.7 pm and To, = 15.6 nm, and 10% for L,,, = 0.3 pm and
To, = 8.6 qm. Reduction of current in the linear regime and reduction
of the simulated ring oscillator speed are both about 3 times higher.
Silicidization of the source/drain is estimated to eliminate as much as
50% of the performance degradation.
I. INTRODUCTION
As MOSFET channel lengths are scaled down to the deep-sub-
micrometer regime, the performance reduction due to parasitic
source/drain resistance ( R s d )becomes an important factor to con-
sider in device scaling [ 11. A quantitative study of Rsd effects is
essential since it can provide guidelines for both MOSFET scaling
and contact technology development. However, because the mag-
nitude of Rrd is technology-dependent, previous reports [2], [3] on
this subject based on near-micrometer technology may not be ap-
plicable to deep-submicrometer devices; some of the conclusions
of these previous studies have already been shown to be incorrect
[4]. Recently, Ng and Lynch [4] using computer simulations stud-
ied Rsd effects in the deep-submicrometer regime. In this brief, we
experimentally study Rsd effects in deep-submicrometer n-channel
non-LDD MOSFET’s. Reduction in device current and ring oscil-
lator speed for various channel lengths and Rsd values is examined.
The effect of salicide technologies on device performance is dis-
cussed. Projections are made of the ultimate achievable device per-
formance.
11. EXPERIMENTAL
PROCEDURE
A . Device Fabrication
The devices used in this study were fabricated using a photore-
sist ashing technique [5]; performance and reliability characteris-
tics of these devices have been previously reported [6]. The gate
oxide thickness (Tax) ranges from 5 to 15.6 nm; the effective chan-
nel length (&) ranges from 0.15 to 1.2 pm. The junction depth
is 0.18 pm and the channel doping concentrations were adjusted
such that the long-channel threshold voltages for all oxide thick-
nesses are around 0.65 V . Since the characteristics of submicro-
meter devices are very sensitive to the channel length, several
methods [7]-[9] were used to extract the effective channel length
and parasitic resistance. An uncertainty of at least 0.05 pm exists
in Leff;an uncertainty of at least 10 fl pm exists in Rsd.
B. Intrinsic Device Performance Measurement Procedure
In order to determine the amount of performance reduction due
to Rsd, the following calibration procedure was performed. The
drain current in the linear (ZdItn)
and saturation (I,,,,) regions and
the maximum saturation transconductance (g, sat) were measured.
Fig. 1 plots the measured Idsa[ versus Rsd. The different RSdvalues
were achieved by attaching external resistors ( R , , , ) to the device,
equally divided between the source and drain (i.e., Rsd = RsdO +
R e x t ) .The circles indicate measured data. The solid lines represent
a theoretical drain current model valid in the deep-submicrometer
regime [lo]. A calibration constant (in the range between 1.0 to
1.1 for all devices) was multiplied to this model to fit the measured
data for each channel length. To obtain higher accuracy, parasitic
resistance effects were included in the drain current model through
iteration; the model also includes the parasitic resistance-induced
body effect, which was neglected in 141. The value of the theoret-
ical drain current at R,, = 0 is defined as the intrinsic current ( I d , , , , ,
and I d s a [ , , ) . The alternated curve shows the amount of drain current
T
IEEE T R A N S A C T I O N S O N E L E C T R O N DEVICES. V O L 37. NO I I . N O V E M B E R 1990 2409

To,= 8.6nm To. Data Model

L,, =0.3p 5bm 0

I
P

,
I

86nm o ----
15bnm A -
, , I ,
; _’ , 0

&’
+”,

I’
0.0 lM00 ZwO.0 3wO.O 4Mo.O
v,, = 3.3v v,, = 3.3v

Parasitic resistance (Qpn) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Fig. 1 . Drain saturation current versus parasltic resistance lor various
channel lengths. The circles are measured data. The sol~dcurves arc the
calibrated model. The alternated curves arc the corresponding percent
drain current reduction.
Effective channel length (pm)
Fig. 2. Drain saturation current versus effective channel length for R,,, =
600 fl . pm.The symbols are measured data. The curves are the calcu-
lated intrinsic drain currents and the corresponding current figure merit.

reduction from the intrinsic value ( I - f~,,itl/fc,,al,,)

as a function
of R.,,,.

111. R E s u L n
A . Saturation Region
Fig. 2 plots versus L C f for
f a power supply of 3.3 V . The
symbols indicate measured data. The solid curves indicate the cal-
culated intrinsic drain current (R,,/ = 0) obtained in the manner
shown in Fig. I . The alternated curves indicate a figure of merit
for the current defined as / ~ / , d l / f ~ / , aBecause
l,,. of the slightly dif-
ferent parasitic resistance between wafers, R,, values were adjusted
to be about 600 R . pni for all oxide thicknesses using cxtcrnal
resistors. In Fig. 2, the current figure of merit is about 87% at Lett
= 0.2 pm. Note that the current (transconductance) figure of merit
decreases as Lettand/or T,,, is reduced. This is because the debias-
ing (source-follower) effect of R,<,becomes stronger as I,/, ( g,,,,i,l )
increases. As shown in Fig. 3, similar results can be obtained for
the saturation transconductance.
0.0 0.2 0.4 0.6 a8 1.0 12 1.4
B. Linear Region Effective channel length (pn)
Fig. 4 plots f,,,, versus LCf,at = 0.05 V and V,, = 3.3 V .
Fig. 3 . Saturation transconductance versus effective channel length for R,,,
The R,, value was adjusted to 600 R . p m . At Lett = 0.2 pm. the = 600 fl . pm. The symbols are measured data. The curves are the
current figure of merit can be as low as 50%. In the linear region. calculated intrinsic transconductance and the corresponding transcon-
R,, affects performance through reducing both the effective Vv\ and ductance figure of merit.
ifdy;in the saturation region, R,,, only affects the current through
reducing the effective Vv,. This explains why the reduction of drain
current due to R,,) is significantly lower in the linear regime than in to that of rather than it is to that of I(i\,l. This observation
the saturation regime. In addition, as Le,, decreascs, the enhanced differs from previous conclusions [4]. This is because, according
current drive increases the amount of dcbiasing due to R,,). to the SPICE results, devices in the ring oscilltor do not spend as
much time in the saturation region as originally assumed in [4].
C. Switching Speed
Depending on the circuit configuration. the switching speed fig-
ure of merit should lie somewhere between the linear and saturation 1v. DlsCUSsION
current figures of merit shown in Figs. 2 and 4. Fig. S plots the The sourceidrain resistance is usually divided into four compo-
SPICE simulated delay time ( 7 )of CMOS ring oscillators versus nents. the contact (Rc,,),the diffusion sheet ( R,h). the spreading
Rsd for T , , = 8.6 nm. The widths of the n- and p-channel devices (R,,,), and the accumulation (Rat) resistances [4]. For the devices
are 15 and 30 p m , respectively. The loading capacitance is 0.1 pF in this study, a 200-nm polysilicon film was used between the AI
per stage. The simultion results show that 7 increases roughly as a and Si layers to prevent junction spiking; the value of R,,) is typi-
linear function of RA,. For 0.25 p m < Letf< 1 . S p m and 5 . 6 nm cally 500-600 fl * pm. The contact-to-gate spacing is about 0.7
< T,,, < 15.6 nm, the delay time is increased by 10-40%/kfl . pm. With similar contact-to-gate spacing, an R,, value as low as
p m of Rxd.At 600 R . p m and for T,, = 8 . 6 nm, the switching 300 fl . p m (Rc,, = 100, Rsh = 50, R,, R,, = 150) can be +
speed figure of merit is about 6 0 % for Leff = 0.2 p m and 85% for theoretically achieved [4]. This R,,(/value corresponds to a figure
LCfr= 1 p m . One observes that the speed figure of merit is closer of merit of 9 5 % in 79% in and 8 5 % in switching speed
I

2410 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 31. NO. 11, NOVEMBER 1990

TOX

v,, = 3.3v v,, = 0.05v

0.0 0.2 0.4 0.6 0.8 1.0 13 1.4

Effective channel length (m)

Fig. 4. Drain current in the linear region versus effective channel length
for R,, = 600 Q . pm.The symbols are measured data. The curves are
the calculated intrinsic drain currents and the corresponding current fig- Fig. 6. Drain current and speed figure of merit versus parasitic resistance
for a device with Leff = 0.3 pm and T,,, = 8.6 nm. Typical parasitic
ure of ment.
resistance ranges for four different technologies are also indicated.

04
0.0 1ooo.o m.0 m.0 4om.o m.0
Parasitic resistance (am)
Fig. 5. SPICE simulted CMOS ring oscillator delay time versus parsitic
resistance for three channel lengths.
for Le, = 0.3 p m and To, = 8.6 nm. Fig. 6 displays the drain
current and speed figures of merit for a device with Leff = 0.3 p m
and To, = 8.6 nm. Because of hot-camer effects, LDD structures
will likely be used in scaled MOSFET’s; this introduces an addi-
tional 100-400 a . p m of RSddepending o n the particular device
design and bias condition [ 1 I]. As shown in Fig. 6, the additional
LDD resistance further degrades the figure of merit for Idsal by about
2-5%, Idlin by 9-17%, and speed by 5-15%. In the L D D switching
speed analysis, the Miller capacitances were assumed to be un-
changed; since the actual capacitance values are sensitive functions
of the particular LDD design (the spacer thickness, the n- doping,
the amount of gateljunction overlap), the results in Fig. 6 are only
rough estimates. Finally, as shown in Fig. 6, the ultimately achiev-
able benefit of employing a salicide technology can be estimated
by assuming a n ideal salicide technology which totally eliminates
R,, and Rsh.This should increase I d s a t , Id,,,,, and 7 by about 2.5,
12, and 7.5%, respectively, for both the L D D and non-LDD de-
vices.
V . CONCLUSION
The effect of parasitic source/drain resistance o n drain current
and transconductance has been characterized based o n measure-
ments of deep-submicrometer MOSFET’s. With the help of a cal-
ibrated MOSFET drain current model, a n estimate is made of how
different MOSFET designs (conventional versus LDD) and how
different contact technologies (salicide versus nonsalicide) affect
device performance is estimated.
REFERENCES
[ l ] Y . El-Mansy, “MOS device and technology constraints in VLSI,”
IEEE Trans. Electron Devices, vol. ED-29, p. 567, 1982.
[2] P. K. Chattejee, W. R. Hunter, T. C. Holloway, and Y. T. Lin,
“The impact of scaling laws on the choice of n-channel or p-channel
for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, p. 220,
1980.
131 H. Shichijo, “A re-examination of practical performance limits of
scaled n-channel and p-channel MOS devices for VLSI,” Solid-State
Electron., vol. 26, p. 969, 1983.
141 K. K. Ng and W.T. Lynch, “The impact of intrinsic series resistance
on MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-34,
p. 503, 1987.
(51 J . Chung, M.-C. Jeng, J. E. Moon, A . T. Wu, T. Y. Chan, P. K .
KO, and C. Hu,“Deep-submicrometer MOS device fabrication using
a photoresist-ashing technique,” IEEE Electron Device Let!. , vol. 9,
p. 186, 1988.
[6] M . X . Jeng, J. Chung, A. T. Wu, T. Y. Chan, J. Moon, C. May, P.
K. KO, and C. Hu, ‘‘Performance and hot-electron reliability of deep-
submicron MOSFETs,” in IEDM Tech. D i g . , p. 710, 1987.
171 J. G. J. Chern, P. Chang, R. F. Motta, and N . Godinho, “A new
method to determine MOSFET channel length,” IEEE Electron De-
vice Lett., vol. EDL-l, p. 170, 1980.
[SI P. I.Suciu and R. L. Johnston, “Experimental derivation of source
and drain resistances of MOS transistors,” IEEE Trans. Electron De-
vices, vol. ED-27, p. 1846, 1980.
[9] B. Sheu and P. K. KO, “A new method to determine the effective
channel length of MOSFETs,” IEEE Trans. Electron Devices, vol.
ED-27, p. 1846, 1980.
[IO] K. Y. Toh, P. K. KO, and R. G. Meyer, “An engineering model for
short-channel MOS devices,” IEEE J. Solid-state Circuits, vol. 23,
p. 950, 1988.
[ I I] K. Mayaram, J. Lee, and C. Hu, “A model for the electric field in
lightly doped drain structures,” IEEE Trans. Electron Devices, vol.
ED-34, p. 1509, 1987.