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TABLE I
COMPARISON OF DEVICE STRESS UNDER SAME OUTPUT POWER
Fig. 5. Topology of the proposed interleaved DAB-based CESS. Fig. 7. Control block diagram for the IPOS interleaved DAB converter.
Fig. 10. SOC of all the batteries (a) with equal discharge current and (b) with
their discharge current proportional to their SOCs.
Fig. 9. Dynamic response for a step change in current demand from the CESS
system (Case I).
the output voltage is well regulated. The current drawn from the
V. EXPERIMENTAL RESULTS
BAT1 is slowly increased, while currents from ultracapacitor
To illustrate the basic principles of proposed energy man- interfacing converters meet load dynamic response. This verifies
agement controller, two converters interfacing batteries and the dynamic power-allocation scheme proposed earlier.
two converters interfacing ultracapacitors are implemented, as Fig. 17 shows the experimental results of the battery shutdown
shown in Fig. 13. A picture of the lab prototype is shown in process. To replace BAT1, its power is made zero by bringing
Fig. 14. A low-voltage laboratory prototype is built to prove the down its current to zero. The current drawn from the BAT2
concept where nominal battery and ultracapacitor voltages are is increased to compensate for the loss of power drawn from
kept at 24 V, and the total dc-link voltage across the load is rated BAT1. Currents from two ultracapacitor interfacing converters
at 200 V. The controller is implemented in dSPACE 1104 and change accordingly to regulate the dc-link voltage.
the gating signals are generated by field-programmable gate Fig. 18 shows the ultracapacitor charging process from the
array (FPGA) board. The schematic of the experimental con- battery. To charge the ultracapacitor from 15 to 20 V, a constant
troller setup is shown in Fig. 15. Table. II lists all experimental charging current value is added to the battery-current references.
parameters. Similar to the analysis of Section IV, the direction The ultracapacitor-interfacing converter currents become nega-
of current flowing out of battery and ultracapacitor is taken as tive to regulate the dc-link voltage, and hence, in this process,
positive. the ultracapacitor gets charged. Once the ultracapacitor voltage
Fig. 16 is recorded when load steps between 300 and 600 W. reaches 20 V, the charging current reference is removed and the
As shown in Fig. 16, when step load is applied to the system, charging also stops, as seen in Fig. 18.
ZHOU et al.: CESS INVOLVING BATTERY AND ULTRACAPACITOR WITH DYNAMIC ENERGY MANAGEMENT IN MICROGRID APPLICATIONS 929
Fig. 16. Experimental result showing dynamic response when load power
steps between 300 and 600 W (Case I).
case, ultracapacitor itself can support the dc bus during the bat-
tery replacement period, and the power flow from other batteries
through three power conversion stages can be avoided.
VI. CONCLUSION
This paper proposes a CESS for microgrid application. This
CESS interfaces battery as a high energy density storage, and
ultracapacitor as a high power density storage to the dc bus.
The dc–dc converter structure is formed using DAB modules
whose terminals are connected in series or parallel depending
on feasibility. The proposed modular dc–dc converter topology
along with its energy management scheme can flexibly share
the power between different batteries and ultracapacitor. The
scheme is validated using simulation and experiments in this
paper.
APPENDIX
The converters connected to batteries and ultracapacitor are
denoted with superscripts I and II, respectively. Hence, their
currents and input–output phase shifts are also denoted by same
superscripts. As, the dc-link voltage is common for both sides,
no such superscript is used to represent it. The subscripts in and
o denote the converter input and output variables, respectively.
Fig. 17. Experimental result showing the response of the CESS system when The subscript f signifies that the variable is output of a LPF.
output power of BAT1 is made zero. (a) Converter currents. (b) Output voltage The superscript ∗ is used to represent reference values for a
(Case II). particular variable. If there are n converter modules then they
can be identified by subscripts 1 to n, respectively.
The voltage controller Cv and current controller Ci shown in
Till now, the results for energy management of CESS system
Fig. 7 are designed as
are presented to show the capability of the proposed modular
power converter structure. In practice, the energy management 1
of a CESS system should be planned by a proper scheduler as Cv = Kcv 1 +
sTiv
shown in [22]. Then, we can avoid circulation of power between
battery and ultracapacitor up to a large extent, e.g., ultracapac- 1
Ci = Kci 1 + . (1)
itor charging can be scheduled when whole CESS system is sTii
storing energy and the power converter losses for energy shuf-
The LPF for the current feedback signals are designed as
fling between battery and ultracapacitor can be avoided. One
more situation can be battery replacement. It can be scheduled 2πfcf
when current demand from the CESS system is very low. In that Gf = (2)
s + 2πfcf
930 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 3, MARCH 2011
where fcf is the low-pass filter cutoff frequency. Similarly, the [21] J. Guerrero, J. Vasquez, J. Matas, M. Castilla, and L. de Vicuna, “Con-
LPF shown in Fig. 8 is in the same format as in (2). All the trol strategy for flexible microgrid based on parallel line-interactive ups
systems,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 726–736, Mar.
experimental parameters used in this paper are defined in Ta- 2009.
ble II. Parameters of interleaved DAB converters for interfacing [22] D. Tran, H. Zhou, and A. M. Khambadkone, “Energy management and
the battery are given here. Same parameters are used for the dynamic control in composite energy storage system for micro-grid appli-
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interleaved converter interfacing the ultracapacitor.
Haihua Zhou (S’07) received the B.E. degree in
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(ECCE 2009), pp. 1808–1811. the Outstanding Educator Award in 2008 from the National University of
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