ECE3002

VLSI SYSTEM DESIGN

LAB TASK 2

Name : Meghna Biswas

Reg. No : 18BEC0761
Slot : L1+L2
Faculty : Prof. Jagannadha Naidu

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 Part A – CMOS Inversion

Aim
Using CMOS PTL logic,
1. Find Wp value to form symmetric inverter. (DC analysis)
2. Propagation delay when Bn=Bp. (Transient analysis)
3. Average power dissipation. (Transient analysis) Circuit.

Circuit Diagram

1) DC analysis with wp=wn

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2) DC analysis with variable wp

3) Transient Analysis

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 Observations

1. a) Vout vs Vin for wp=wn

1. b) Vout vs Vin for variable wp

For wp = 1.87u, we get Vout = Vdd/2 = .8968V (0.9V approx.)

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2. A) Transient Analysis (Input – Green, Output – Red)

2. B) Fall Delay

Tout = t2 = 200.00973ns

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Tin = t1 = 200.0005ns
tpdf = t2 – t1 = 0.00968ns = 9.68ps

2. C) Rise Delay

Tout = t2 = 250.00818ns

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Tin = t1 = 250.0015ns
Tpdr = t2 – t1= 0.00668ns = 6.68ps

3. Power Dissipation of NMOS And PMOS

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a) PMOS

b) NMOS

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 Calculations

1. Wp using DC analysis
Wp = 1.87u

2. Tpdr = 0.00968ns
Tpdf = 0.00668ns
Tpd = (tpdr + tpdf)/2

Tpd = 0.00818ns = 8.18ps

3. Power Dissipation
Ppmos = 75.571nW
Pnmos = 77.16nW

Pavg = 152.731nW

Results

Following Results were obtained

1. Wp = 1.87u
2. Tpd = 8.18ps
3. Pavg = 152.731nW

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 Part B NAND/NOR Implementation

Aim
Using NAND/NOR PTL logic, for Bn=Bp Wn=500n
Wp=1.87*2=3.74u
1. Check Functionality (Transient analysis)
2. Propagation delay (Transient analysis)
3. Average power (Transient analysis)

Circuit Diagram

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 Observations

1. Functionality

2. Propagation Delay
a) For A=0
i) Fall Delay

Tout = t2 = 200.01817ns
Tin = t1 = 200.00050ns
Tpdf1 = t2 – t1 = 0.01767ns = 17.67ps

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 ii) Rise Delay

Tout = t2 = 250.01865ns
Tin = t1 = 250.00150ns
Tpdr1 = t2 – t1 = 0.01715ns = 17.15ps

b) For B=0
i) Fall Delay

Tout = t2 = 200.04809ns
Tin = t1 = 200.00050ns
Tdpf2 = t2 – t1 = 0.04759ns = 47.59ps

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 ii) Rise Delay

Tout = t2 = 300.02795ns
Tin = t1 = 300.00150ns
Tpdr2 = t2 – t1 = 0.02645ns = 26.45ps

3. Average Power

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a) NMOS 1 power

b) NMOS 2 power

c) PMOS 1 power

d) PMOS 2 power

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 Calculations

1. Functionality – Verified
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

2. Tpd = (tpdf + tpdr)/2

Tpdf1 = 0.01767ns = 17.67ps

Tpdr1 = 0.01715ns = 17.15ps
Tpd1 = 0.01741ns = 17.41ps

Tpdf2 = 0.04759ns = 47.59ps

Tpdr2 = 0.02645ns = 26.45ps
Tpd2 = 0.03702ns = 37.02ns

3. Power Dissipation
Pnmos1=126.98pW
Pnmos2=135.68nW
Ppmos1=58.967nW
Ppmos2=104.94nW

Pavg = Pnmos1+Ppmos1+Pnmos2+Ppmos2
= 0.0127+58.967+135.68+104.94 = 299.6nW

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 Results
From the above observations and calculations, functionality was verified
and following results were obtained

1. When logic A = 0,
Tpd = 17.41ps

2. When logic B=0,

Tpd = 37.02ps

3. Average Power,
Pavg = 299.6nW

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