Mechatronics

MME205: Advanced Microprocessor and

Microcontroller
Lecture #6: Timing diagram 8085 microprocessor

Prepared by:
Dr. Ahmed Hassan M. Hassan
Associate Professor
dr.ahmed@mashreq.edu.sd

www.mashreq.edu.sd
 Main Contents
Architecture
 Internal Register Organization and Pin Configuration
 Instruction Set of 8085
 addressing modes
 instruction machine cycles with states and timing
diagram.
 8085 assembly language programming
 Examples
 Control Signal
and Status signal
ALE: (Address latch enable)
- It’s active high signal
- It’s used to De-multiplex AD0-AD7 lines

 If ALE = 1  AD0-AD7 = A0 – A7
 If ALE = 0  AD0-AD7 = D0 – D7
.
S1 and S0 : (Status signals)
IO/M S0 S1
Opcode Fetch 0 1 1
Mem. Read 0 1 0
Mem. Write 0 0 1
IO Read 1 1 0
IO Write 1 0 1
Interrupt ACK 1 1 1
HALT Z 0 0
HOLD Z X X
RESET Z x x
Z High impedance
X Don’t care
 Generation of control signal
using NAND Gate

8085
microprocessor
 Generation of control signal
using Decoder

O1
O2
I1 I2 I3
I1 O3 0 0 0 O1 x
8085 3X8 O4 0 0 1 O2 MERD

microprocessor I2 Decoder O5 0 1 0 O3 MEWD

O6 0 1 1 O4 x
I3 O7 1 0 0 O5 x
O8
1 0 1 O6 IOR

1 1 0 O7 IOW

1 1 1 O8 x
 Generation of control signal
using De-Multiplexer
 AD0 – AD7 is time multiples address data lines
 To interface 8085 with memory , input and output device is compulsory to
de-Multiples address and Data

Higher address lines

A15
A8 (A15 – A8)
Active High (in machine cycle, during T1  ALE =1)
8085 E
microprocessor (A7 – A0)
Latch
AD0
AD7
74LS373
(D7 – D0)
Active Low (in machine cycle, during T2 & T3  ALE =0)
 Timing Diagram
8085 Microprocessor
Terms Definition:
• INSTRUCTION CYCLE: The time required to execute an
instruction is called instruction cycle.

• MACHINE CYCLE: The time required to access the

memory or input/output devices is called machine cycle

• T-STATE MACHINE CYCLE: The machine cycle and

instruction cycle takes multiple clock periods. A portion
of an operation carried out in one system clock period is
called as T-state.
Note: Time Period, T = 1/f; where f = Internal clock frequency
 MACHINE CYCLES OF 8085

The 8085 microprocessor has 5 basic machine

cycles.
1. Opcode fetch cycle (4T/6T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
• The processor takes a definite time to execute the
machine cycles. The time taken by the processor
to execute a machine cycle is expressed in T-
states.

• One T-state is equal to the time period of the

internal clock signal of the processor.

• The T-state starts at the falling edge of a clock.

 TIMING DIAGRAM

• Timing Diagram is a graphical representation.

• It represents the execution time taken by each

instruction in a graphical format.

• The execution time is represented in T-states.

Timing Diagram
 CONTROL SIGNALS
S1 S2 Data Bus Status
(Output)
0 0 0 Halt
0 0 1 Memory Write
0 0 0 Memory Read
1 1 1 IO Write
1 0 0 IO Read
0 1 1 Opcode
1 1 1 Interrupt ACK
 OPCODE FETCH MACHINE CYCLE OF 8085

Each instruction of the processor has one byte

opcode.
The opcodes are stored in memory. So, the processor
executes the opcode fetch machine cycle to fetch the
opcode from memory.
Hence, every instruction starts with opcode fetch
machine cycle.
The time taken by the processor to execute the
opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching
the opcode from memory and the remaining T-states
are used for internal operations by the processor.
 OPCODE FETCH MACHINE CYCLE OF 8085

Clock

(A15 – A8) Higher Order Memory Address unspecified

Lower Order
(AD7 – AD0) Memory Address
Opcode D0 – D7

(ALE)
 MEMORY READ MACHINE CYCLE OF 8085

The memory read machine cycle is executed by the

processor to read a data byte from memory.

The processor takes 3T states to execute this cycle

The instructions which have more than one byte

word size will use the machine cycle after the
opcode fetch machine cycle.
MEMORY READ MACHINE CYCLE OF 8085
 MEMORY WRITE MACHINE CYCLE OF 8085

The memory write machine cycle is executed by

the processor to write a data byte in a memory
location.

The processor takes, 3T states to execute this

machine cycle
MEMORY WRITE MACHINE CYCLE OF 8085
 I/O READ CYCLE OF 8085

The I/O Read cycle is executed by the processor

to read a data byte from I/O port or from the
peripheral.

The processor takes 3T states to execute this

machine cycle.

The IN instruction uses this machine cycle during

the execution.
I/O READ CYCLE OF 8085
 I/O WRITE CYCLE OF 8085

The I/O write machine cycle is executed by the

processor to write a data byte in the I/O port or to a
peripheral, which is I/O, mapped in the system.

The processor takes, 3T states to execute this machine

cycle.
I/O WRITE CYCLE OF 8085
 Examples (1):
Instruction: T1 T2 T3 T4

A000h MOV A,B A0h

A1515--A
A A88(H
(Higher Order Address bus)
Corresponding Coding: 00h 78h

A000h 78

ALE

RD

OFC WR

I I O/M
8085 Memory
Op-code fetch Cycle
 Examples (2):
Instruction:
A000h MVI A,45h
Corresponding Coding:
A000h 3E
A001h 45

OFC

MEMR

8085 Memory
 T5 T6 T7
T1 T2 T4

A0h A0h
A15- A8 (Higher Order Address bus)
00h 3Eh 01h 45h
DA7-DA0 ( Lower er address/data Bus)
Instruction: ord
ALE
A000h MVI A,45h
Corresponding Coding:
RD
A000h 3E
A001h 45
WR

I I O/M

Op-Code Fetch Cycle Memory Read Cycle

 Home Work (1)

Instruction:
A000h LXI A,FO45h
OFC

Corresponding Coding: MEMR

A000h 21 MEMR

A001h 45 Memory
8085
A002h F0
 Home Work (2)

Instruction:
A000h MOV A,M OFC

Corresponding Coding: MEMR

A000h 7E
8085 Memory
 Home Work (3)

Instruction:
A000h MOV M,A OFC

Corresponding Coding: MEMW

A000h 77
8085 Memory