Supertex inc.

VN10K

N-Channel Enhancement-Mode
Vertical DMOS FET
Features General Description
►► Free from secondary breakdown This enhancement-mode (normally-off) transistor utilizes
►► Low power drive requirement a vertical DMOS structure and Supertex’s well-proven,
►► Ease of paralleling silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
►► Low CISS and fast switching speeds
of bipolar transistors and the high input impedance and
►► Excellent thermal stability positive temperature coefficient inherent in MOS devices.
►► Integral source-drain diode Characteristic of all MOS structures, this device is free
►► High input impedance and high gain from thermal runaway and thermally-induced secondary
breakdown.
Applications
►► Motor controls Supertex’s vertical DMOS FETs are ideally suited to a
►► Converters wide range of switching and amplifying applications where
►► Amplifiers very low threshold voltage, high breakdown voltage, high
►► Switches input impedance, low input capacitance, and fast switching
►► Power supply circuits speeds are desired.
►► Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)

Ordering Information Product Summary

Part Number Package Option Packing RDS(ON) IDSS
BVDSS/BVDGS
VN10KN3-G TO-92 1000/Bag (max) (min)

VN10KN3-G P002 60V 5.0Ω 750mA

VN10KN3-G P003
VN10KN3-G P005 TO-92 2000/Reel Pin Configuration
VN10KN3-G P013
VN10KN3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
DRAIN
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
SOURCE
Absolute Maximum Ratings
Parameter Value GATE
Drain-to-source voltage BVDSS TO-92
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±30V Product Marking
Operating and storage temperature -55 C to +150 C
O O

Absolute Maximum Ratings are those values beyond which damage to the device may
SiVN YY = Year Sealed
occur. Functional operation under these conditions is not implied. Continuous operation 1 0 K WW = Week Sealed
of the device at the absolute rating level may affect device reliability. All voltages are YYWW
referenced to device ground. = “Green” Packaging

Package may or may not include the following marks: Si or

Typical Thermal Resistance
TO-92
Package θja
TO-92 132OC/W

Doc.# DSFP-VN10K
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Supertex inc.
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 VN10K
Thermal Characteristics
ID ID Power Dissipation
Package @TC = 25OC
IDR† IDRM
(continuous)† (pulsed)

TO-92 310mA 1.0A 1.0W 310mA 1.0A

Notes:
† ID (continuous) is limited by max rated Tj . (VN0106N3 can be used if an ID (continuous) of 500mA is needed.)

Electrical Characteristics (T A
= 25OC unless otherwise specified)

Sym Parameter Min Typ Max Units Conditions

BVDSS Drain-to-source breakdown voltage 60 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage 0.8 - 2.5 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - -3.8 - mV/ C VGS = VDS, ID= 1.0mA
O

IGSS Gate body leakage - - 100 nA VGS = 15V, VDS = 0V

- - 10 VGS = 0V, VDS = 45V
IDSS Zero gate voltage drain current µA VGS = 0V, VDS = 45V,
- - 500
TA = 125°C
ID(ON) On-state drain current 0.75 - - A VGS = 10V, VDS = 10V
- - 7.5 VGS = 5.0V, ID = 200mA
RDS(ON) Static drain-to-source on-state resistance Ω
- - 5.0 VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature - 0.7 - %/OC VGS = 10V, ID = 500mA
GFS Forward transductance 100 - - mmho VDS = 10V, ID = 500mA
CISS Input capacitance - 48 60 VGS = 0V,
COSS Common source output capacitance - 16 25 pF VDS = 25V,
CRSS Reverse transfer capacitance - 2.0 5.0 f = 1.0MHz

t(ON) Turn-on time - - 10 VDD = 15V,

ns ID = 600mA,
t(OFF) Turn-off time - - 10 RGEN = 25Ω
VSD Diode forward voltage drop - 0.8 - V VGS = 0V, ISD = 500mA
trr Reverse recovery time - 160 - ns VGS = 0V, ISD = 500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10V 90% VDD
INPUT Pulse RL
10% Generator
0V OUTPUT
t(ON) t(OFF)
RGEN
td(ON) tr td(OFF) tf

VDD INPUT D.U.T.

10% 10%
OUTPUT
0V 90% 90%

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 VN10K
Typical Performance Curves
BVDSS Variation with Temperature On-Resistance vs. Gate-to-Source Voltage
100
VDS = 0.1V
1.1
BVDSS (normalized)

RDS(ON) (ohms)
1.0 10

0.9

1.0
-50 0 50 100 150 1.0 10 100

Tj (OC) VGS (volts)

Transfer Characteristics Output Conductance vs Drain Current

1.0 1.0
VDS = 25V
VDS = 10V 80µs, 1%
300µs, 2% Duty Cycle,
0.8 Duty Cycle, Pulse Test
Pulse Test

Reduction
ID (amperes)

0.6 Due to
GFS (mhos)

Heating
0.1

0.4

0.2

0 0.01
0 2.0 4.0 6.0 8.0 10 0.01 0.1 1.0
VGS (volts) ID (amperes)

Capacitance vs. Drain-to-Source Voltage Transconductance vs Gate-Source Voltage

50 250
CISS
VDS = 10V
3000µs, 2%
40 200 Duty Cycle
Pulse Test
C (picofarads)

30 150
Gfs (m )
Ω

20 100

COSS
10 50

CRSS
0 0
0 10 20 30 40 50 0 2.0 4.0 6.0 8.0 10
VDS (volts) VGS (volts)

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 VN10K
Typical Performance Curves (cont.)
Output Characteristics Saturation Characteristics
1.0 1.0
VGS = 10V 8V 7V VGS = 10V 7V

9V
0.8 0.8
8V
6V 6V

ID (amperes)
ID (amperes)

0.6 0.6
5V

5V
0.4 0.4

4V

4V
0.2 0.2
3V 3V
2V 2V
0 0
0 10 20 30 40 50 0 2.0 4.0 6.0 8.0 10
VDS (volts) VDS (volts)

Transconductance vs. Drain Current Power Dissipation vs. Case Temperature

250 2.0

200

150
PD (watts)
GFS (m )
Ω

TO-92
1.0

100

VDS = 10V
50
300µs, 2%
Duty Cycle,
Pulse Test
0 0
0 200 400 600 800 1000 0 25 50 75 100 125 150
ID (mA) TC (OC)

Maximum Rated Safe Operating Area Switching Waveform

10 10
Output Voltage

TC = 25OC
(volts)

5.0

1.0
ID (amperes)

TO-92 (DC)

15
Input Voltage

0.1
10
(volts)

5.0

0.01
1.0 10 100 1000 0 10 20 30 40 50
VDS (volts) t – Time (ns)

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 VN10K
3-Lead TO-92 Package Outline (N3)
D

A
Seating
Plane 1 2 3

b c
e1
e

Front View Side View

E
E1
1 3

Bottom View

Symbol A b c D E E1 e e1 L
MIN .170 .014† .014† .175 .125 .080 .095 .045 .500
Dimensions
NOM - - - - - - - - -
(inches)
MAX .210 .022† .022† .205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Doc.# DSFP-VN10K Tel: 408-222-8888
B031411 5 www.supertex.com