HP Dv4 Intel Series Compal La4042p Laptop Schematics

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : JAL21
1 1
PCB NO : LA-4042P (DAA00000T0L)

BOM P/N : 43153331L01
M09 Maybach DIS

2
uFCPGA Mobile Penryn 2
Intel Cantiga PM + ICH9M
2007-10-30
REV : 0.1
3
@ : Nopop Component 3
4 4
MB PCB
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DAA00000R0L PCB 03P LA-4051P REV0 M/B
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
401533
Date: Monday, December 17, 2007 Sheet 1 of 56
A B C D E
A B C D E
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Block Diagram BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Compal confidential FAN Thermal Pentium-M Clock Generator

Model : JAL22 +FAN1_VOUT GUARDIAN III Penryn -4MB (Socket P) CPU ITP Port CK505
page 18 +1.5V_RUN
EMC4002 uFCPGA CPU SLG8LP554
+3.3V_SUS page 18 +1.05V_VCCP +1.05V_VCCP page 7 +3.3V_M page6
+VCC_CORE 478pin page 7,8,9
1 CRT CONN 1
+5V_RUN page 20 Video Switch VGA H_A#(3..35) H_D#(0..63)
TS3DV520 System Bus
VGA/SVID NV G98
+3.3V_RUN page 20 SVID FSB 1066 MHz DDRII-DIMM X2
+FBVDDQ BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+3.3V_RUN PCIE-E 16X page 16,17
INTEL
LVDS +1.1V_GFX_PCIE +0.9V_DDR_VTT
LVDS CONN Memory BUS (DDR2)
+5V_ALW
+GPU_CORE Cantiga +1.8V_MEM
+1.5V_RUN +1.8V_MEM 667/800 MHz Trough LVDS Cable
+3.3V_RUN on M/B Board DPC page 51,52,53,54,55,56
+1.8V_MEM 1329pin BGA
+PWR_SRC page 19
+1.05V_VCCP USB[11] USB Port
+3.3V_RUN Camera
page 19
DP Switch +1.05V_M page 10,11,12,13,14,15
DPB
TS2DP512 E-SATA
+5V_RUN page 21 DMI USB[2,3] LEFT SIDE USB Port1 X1 SATA4
PCI BUS +3VRUN 33MHz
2
+1.5V_RUN Charger USB Port X1 2
IDSEL:AD17
(GNT#1,REQ#1) 100MHz +5V_ALW page 33
DOCKING (PIRQD#,PIRQB#,PIRQC#)
DP CONN
PORT +5V_RUN CardBus 48MHz USB[0,1] RIGHT SIDE
+PWR_SRC page 21 +5V_ALW INTEL USB Ports X2
+1.8V_LAN_M page 35 R5C847 +5V_RUN
ICH9-M GLCI/LCI +5V_ALW
+3.3V_RUN page 31,32 SNIFFER +RTC_CELL On IO/B
DAI Azalia I/F
SD CONN IEEE1394
page 31
+3.3V_RUN
676pin BGA
SATA5 +3.3V_RUN USB[7] +3.3V_ALW_ICH
page 31 Intel Boazman LAN Switch
Through FPC to IO Board +1.5V_RUN S-ATA(4)
USB[8,9] +3.3V_ALW 82567LF P13L500
Through FPC to SD Board +1.05V_VCCP +3.3V_LAN
PCI Express BUS page 22,23,24,25 +1.8V_LAN_M page 30
SATA1 SATA0 +1V_LAN_M page 29
PCIE3 PCIE2 PCIE1
Mini Card 3 Mini Card 2 Mini Card 1 LPC BUS E-Module S-HDD
+3.3V_RUN
WPAN/BT/Robson WLAN WWAN +3V_RUN +5V_MOD Azalia Codec AMP & INT. RJ45
SIM card page 26 +5V_HDD page 26
3
+3.3V_RUN +3.3V_WLAN +3.3V_RUN 33MHz 92HD71B Speaker 3
+1.5V_RUN page 34 +1.5V_RUN page 34 +1.5V_RUN page 34 page 34
+3.3V_RUN +5V_RUN page 28 On IO/B
SPI +VDDA page 27
USB[6] USB[4] USB[5] LPC BUS W25X32VSSIG Trough LVDS Cable
+3.3V_LAN
page 24
RFID USH I/F Dig. MIC
BCM5880 SMSC KBC 32Mbit +VDDA
page 36
TPM 1.2 USB[10]
DC IN +3.3V_RUN MEC5035 W25X32VSSIG
+2.5V_AVDD_5880 +RTC_CELL +3.3V_LAN
BATT IN page 43 +1.2V_AVDD_5880 page 24 DAI
page 36 +3.3V_ALW page 38
SCREW HOLE 73S8009CN SSM2602
LED 3V/5V +3.3V_RUN page 27
page 42
+3.3V_RUN SPI SST25VF MDC
page 44 page 36 16Mbit DOCKING
ME & LED HeadPhone &
USBH SMBus +3.3V_ALW +3V_SUS
GPUCORE / 1.1V page 38 MIC Jack
1.5V/1.05V Smart Card page 42 BC +3.3V_RUN
On IO/B
page 41 page 45 page 36
BC BUS Expend GPIO
4 ECE1088 4
+3.3V_ALW
Selector 1.8V/0.9V Biometric ECE1077 Touch Pad page 39 RJ11 Through Cable
page 40 page 46 +3.3V_ALW
+3.3V_RUN page 33 page 39 DELL CONFIDENTIAL/PROPRIETARY
BC BUS SMSC SIO DOCK LPC BUS Compal Electronics, Inc.
CHARGER VCORE (IMVP-6) ECE5028 Title
page 48 page 47 Int.KBD & +3.3V_ALW SCHEMATIC, MB A4042

page 37 Size Document Number Rev
Stick page 39 Stick 401533 A
Trough Cable
A B C D E
5 4 3 2 1
POWER STATES USB PORT# DESTINATION

Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE 0 JUSB1 (Ext Right Side Top)
D
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON 1 JUSB1 (Ext Right Side Bottom) D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF ON 2 JESA1 (Ext Left Side Bottom)
S4 (Suspend to DISK) / M1 LOW HIGH HIGH LOW HIGH ON ON ON OFF ON 3 JESA1 (Ext Left Side TOP)
S5 (SOFT OFF) / M1 LOW HIGH LOW LOW HIGH ON ON ON OFF ON 4 WLAN

ICH9-M
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF 5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF 6 WPAN
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF 7 Card Bus/Express card
8 DOCKING
C
PM TABLE 9 DOCKING C
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M 10 USH->BIO

+5V_ALW +1.8V_MEM +3.3V_RUN +1.05V_M +1.05V_M
+3.3V_ALW_ICH +2.5V_RUN (M-OFF)
power 11 Camera
plane +3.3V_RTC_LDO +1.5V_RUN
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
+1.05V_VCCP PCI EXPRESS DESTINATION
State
+FBVDDQ
+1.1V_GFX_PCIE Lane 1 MINI CARD-1 WWAN
S0 ON ON ON ON ON
Lane 2 MINI CARD-2 WLAN
S3 ON ON OFF ON OFF
Lane 3 MINI CARD-3 BT/UWB
B
S5 S4/AC ON OFF OFF ON OFF
Lane 4 EXPRESS CARD B
S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 5 None
Lane 6 10/100/1G LAN
PCI TABLE
PCI DEVICE IDSEL REQ#/GNT# PIRQ
R5C847 AD17 REQ#1 / GNT#1 PIRQ[B..D]
A A
401533
5 4 3 2 1
5 4 3 2 1
RUN_ON SI3457
+INV_PWR_SRC
( Q17 )
ADAPTER
D D
GFX_CORE_CNTRL MAX17007
+GPU_COREP
(PU13)
+PWR_SRC
BATTERY
CHARGER
ISL6260 TPS51116 SN0608098 SN0608098
(PU7) (PU4) (PU3) (PU2) ALWON
C C
+3.3V_ALW
IMVP_VR_ON
0.9V_DDR_VTT_ON
1.5V_RUN_ON
DDR_ON
3.3V_RUN_ON
M_ON
M_ON
ICH_ALW_ON
ENAB_3VLAN
SUS_ON
ALW_ON
SN0608098
+VCC_CORE +1.8V_MEM +0.9V_DDR_VTT +1.05V_M +1.5V_RUN
(PU2) +15V_ALW STS11NF30L SI3456BDV SI3456BDV
STS11NF30L SI4336DY
RUN_ON (Q44) (Q61) (Q60) (Q54) (Q54)
GFX_CORE_PWRGD
STS11NF30L +5V_RUN
1.05V_RUN_ON
(Q55)
+5V_ALW
+3.3V_SUS +3.3V_ALW_ICH +3.3V_M
B +3.3V_LAN +3.3V_RUN B
REGCTL_PNP18
MODC_EN
HDDC_EN
STS11NF30L SI4336DY
RUN_ON
(Q116) (Q67)
BCP69
SI3456BDV SI3456BDV MAX9789A (Q45)
(Q32) (Q29) (U22)
+FBVDDQ +1.05V_VCCP
A +1.8V_LAN_M A
+5V_HDD +5V_MOD +VDDA

401533
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3.3V_ALW_ICH +3.3V_M
2.2K 2.2K
G16 ICH_SMBCLK MEM_SCLK 197
2N7002 MEM_SDATA
A13 ICH_SMBDATA 195 DIMMA SMBUS Address [TBD]
2N7002
10K
ICH9-M 197
D
10K
+3.3V_ALW_ICH 195
SMBUS Address [TBD] D
DIMMB
C17 AMT_SMBCLK
B18 AMT_SMBDAT
8.2K
93 94 8.2K +5V_ALW
2A 2A 6 DOCK_SMB_CLK 6
1A
5 DOCK_SMB_DAT 5 DOCKING SMBUS Address [TBD]
1A
8.2K
8.2K
+3.3V_ALW
8 LCD_SMBCLK 6
1B INVERTER
C 7 C
LCD_SMDATA 5 SMBUS Address [TBD]
1B (JLVDS)
2.2K
+3.3V_ALW
2.2K
1C 112 PBAT_SMBCLK 100 ohm 3
PBAT_SMBDAT
BATTERY SMBUS Address [TBD]
1C 111 100 ohm 4
CONN
SIO
2.2K
+3.3V_SUS
2.2K
10
1D EXP_SMBCLK 7
9 2N7002
1D EXP_SMBDATA 8 Express card SMBUS Address [TBD]
2N7002
100
1E 2.2K
99 +3.3V_WLAN
1E 2.2K
B 30 B
WLAN_SMBCLK
1F 98 CARD_SMBCLK
2N7002 WLAN_SMBDATA 32 WLAN SMBUS Address [TBD]
1F 97 CARD_SMBDAT
2N7002
2.2K
MEC 5035 2.2K
+3.3V_RUN
96 2N7002 MINI_SMBCLK 30
1G
95 MINI_SMBDATA 32 BT/UWB SMBUS Address [TBD]
1H 2N7002
32 30
SMBUS Address [TBD]

2.2K WWAN
2.2K
+3.3V_ALW +3.3V_M
2.2K 2.2K
12 CKG_SMBDAT CLK_SDATA
1H 17
2N7002
13 CKG_SMBCLK CLK_SCLK 16 CLK GEN SMBUS Address [TBD]
1H 2N7002
9 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
A
Charger 2N7002 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
A
106 10 USH
1J PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
105 2N7002
1J
Dedicated JTAG SMBUS Address [TBD]
SMBUS Address [TBD]
2.2K
DAI
103
+3.3V_RUN Title
2.2K
1K SMBUS Address [TBD]
102 Dedicated JTAG SCHEMATIC, MB A4042
1K Size Document Number Rev
A
401533
5 4 3 2 1
5 4 3 2 1
+3.3V_M +CK_VDD_MAIN
+3.3V_M +CK_VDD_MAIN
1 2
2.2K_0402_5%~D
2.2K_0402_5%~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
L1
1
1 BLM21AG601SN1D_0805~D 1 1 1 1 1 1
0_0805_5%~D
2
R1
R2
C1
C2
C3
C4
C5
C6
C7
1 2
+3.3V_RUN
R851
@ R3
@R3
0_0402_5%~D 2 2 2 2 2 2 2
2
6 1 CLK_SDATA +CK_VDD_MAIN2 MINI1CLK_REQ# 1 2
<27,38,48> CKG_SMBDAT
1
R4 10K_0402_5%~D
Q1A 1 2 MINI2CLK_REQ# 1 2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2N7002DW-T/R7_SOT363-6~D @ L2
@L2 R5 10K_0402_5%~D
2
+3.3V_M BLM21PG600SN1D_0805~D 1 1 1 CLK_3GPLLREQ# 1 2
D @ R6 10K_0402_5%~D D
C8
C9
C10
Q1B SATA_CLKREQ# 1 2
2N7002DW-T/R7_SOT363-6~D R7 10K_0402_5%~D
CLK_SCLK +CK_VDD_48 +CK_VDD_REF 2 2 2 MINI3CLK_REQ#
<27,38,48> CKG_SMBCLK 3 4 1 2
R8 10K_0402_5%~D
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V7K~D
EXPCLK_REQ# 1 2
1 2 1 1 1 R356 10K_0402_5%~D
@R9
@R9 @
C11
C12
C13
0_0402_5%~D
1 2 +CK_VDD_A
2 2 2
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
R10 2.2_0603_5%~D
1 1
C14
C15
U1
2 2
FSC FSB FSA CPU SRC PCI 1 7
VDD_SRC VDD_A
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 49 VDD_SRC
54
65
VDD_SRC
VDD_SRC
SLG8LP554VTR VSS_A 8
0 0 0 266 100 33.3

* PCI_STP# 25 H_STP_PCI#
H_STP_PCI# <24>
30 VDD_PCI
0 0 1 133 100 33.3 36 24 H_STP_CPU#
VDD_PCI CPU_STP# H_STP_CPU# <24>
12 VDD_CPU
0 1 0 200 100 33.3 X1 11 MCH_BCLK 1 2 CLK_MCH_BCLK
CPU_1 CLK_MCH_BCLK <10>
14.31818MHz_20P_1BX14318CC1A~D 1 2 +CK_VDD_REF 18 R11 33_0402_5%~D
R12 0_0603_5%~D VDD_REF MCH_BCLK# CLK_MCH_BCLK#
2 1 CPU_1# 10 1 2 CLK_MCH_BCLK# <10>
0 1 1 166 100 33.3 C16 1 2 +CK_VDD_48 40 VDD_48
R13 33_0402_5%~D
1
33P_0402_50V8J~D R14 0_0603_5%~D
C CPU_BCLK CLK_CPU_BCLK C
CPU_0 14 1 2 CLK_CPU_BCLK <7>
1 0 0 333 100 33.3 Place crystal within CLK_XTAL_IN 20 R15 33_0402_5%~D
C17 XTAL_IN CPU_BCLK# CLK_CPU_BCLK#
500 mils of CK505 13 1 2 CLK_CPU_BCLK# <7>
2
33P_0402_50V8J~D CPU_0# R16 33_0402_5%~D
1 0 1 100 100 33.3 2 1 1 2 CLK_XTAL_OUT 19
R17 0_0402_5%~D XTAL_OUT CPU_ITP CLK_CPU_ITP
CPU_ITP/SRC_10 6 1 2 CLK_CPU_ITP <7>
R18 33_0402_5%~D
1 1 0 400 100 33.3 CLK_ICH_48M R19 2 1 33_0402_5%~D FSA 41 5 CPU_ITP# 1 2 CLK_CPU_ITP#
<24> CLK_ICH_48M USB_48MHz/FSLA CPU_ITP#/SRC_10# CLK_CPU_ITP# <7>
<8,10> CPU_MCH_BSEL0 CPU_MCH_BSEL0 R22 1 2 2.2K_0402_5%~D R21 33_0402_5%~D
<8,10> CPU_MCH_BSEL1 CPU_MCH_BSEL1 45 FSL_B/TEST_MODE PCIE_MINI1 CLK_PCIE_MINI1
SRC_9 3 1 2 CLK_PCIE_MINI1 <34>
<8,10> CPU_MCH_BSEL2 CPU_MCH_BSEL2 R24 1 2 10K_0402_5%~D FSC 23 R23 33_0402_5%~D
REF_0/FSL_C/TEST_SEL PCIE_MINI1# CLK_PCIE_MINI1#
SRC_9# 2 1 2 CLK_PCIE_MINI1# <34>
R25 33_0402_5%~D
+3.3V_M CLK_PCI_5028 R26 2 1 33_0402_5%~D PCI_SIO 34 72 MINI1CLK_REQ# MINI1CLK_REQ# <34>
<37> CLK_PCI_5028 PCICLK4/FCT_SEL CLKREQ_9#
CLK_PCI_TPM R29 1 2 22_0402_5%~D PCI_TPM 33 70 PCIE_MINI2 1 2 CLK_PCIE_MINI2
<36> CLK_PCI_TPM PCICLK3 SRC_8 CLK_PCIE_MINI2 <34>
1
R28 33_0402_5%~D
@ R51
@R51 CLK_PCI_PCM R30 2 1 22_0402_5%~D PCI_PCM 32 69 PCIE_MINI2# 1 2 CLK_PCIE_MINI2#
<31> CLK_PCI_PCM PCICLK2/TME SRC_8# CLK_PCIE_MINI2# <34>
10K_0402_5%~D CLK_PCI_DOCK R27 1 2 22_0402_5%~D R31 33_0402_5%~D
<35> CLK_PCI_DOCK
CLK_PCI_5035 R32 2 1 33_0402_5%~D PCI_EC 27 71 MINI2CLK_REQ# MINI2CLK_REQ# <34>
<38> CLK_PCI_5035 PCICLK1 CLKREQ_8#
2
FSA 66 PCIE_ICH 1 2 CLK_PCIE_ICH

SRC_7 CLK_PCIE_ICH <24>
CLK_ICH_14M R33 1 2 22_0402_5%~D CLKREF 22 R34 33_0402_5%~D
<24> CLK_ICH_14M REF_1
1
CLK_SIO_14M R35 1 2 22_0402_5%~D 67 PCIE_ICH# 1 2 CLK_PCIE_ICH#

<37> CLK_SIO_14M SRC_7# CLK_PCIE_ICH# <24>
@ R55
@R55 R36 33_0402_5%~D
10K_0402_5%~D CLK_NV_27M R37 2 1 33_0402_5%~D CLK_NV 43 38
<51> CLK_NV_27M DOT_96/27M CLKREQ_7#
CLK_NVSS_27M R38 1 2 33_0402_5%~D CLK_NVSS 44 63 PCIE_MINI3 1 2 CLK_PCIE_MINI3
<51> CLK_NVSS_27M CLK_PCIE_MINI3 <34>
2
DOT_96#/27M_SS SRC_6 R39 33_0402_5%~D

64 PCIE_MINI3# 1 2 CLK_PCIE_MINI3#
SRC_6# CLK_PCIE_MINI3# <34>
CLK_PCI_ICH R41 2 1 33_0402_5%~D PCI_ICH 37 R40 33_0402_5%~D
B <22> CLK_PCI_ICH PCICLK_F0/ITP_EN B
62 MINI3CLK_REQ# MINI3CLK_REQ# <34>
CLKREQ_6#
+3.3V_RUN CLK_PWRGD 39 60 PCIE_VGA 1 2 CLK_PCIE_VGA
<24> CLK_PWRGD CKPWRGD/PD# SRC_5 CLK_PCIE_VGA <51>
R42 33_0402_5%~D
10K_0402_5%~D
61 PCIE_VGA# 1 2 CLK_PCIE_VGA#
SRC_5# CLK_PCIE_VGA# <51>
2
9 R44 33_0402_5%~D
NC
R43
TME PIN 32 CLKREQ_5# 29
0 overclocking enabled 58 PCIE_EXP 1 2 CLK_PCIE_EXP

SRC_4 CLK_PCIE_EXP <32>
CLK_SCLK 16 R408 33_0402_5%~D
1
SMBCLK PCIE_EXP# CLK_PCIE_EXP#

1 overclocling disabled 59 1 2
PCI_PCM * SRC_4#
EXPCLK_REQ#
R415 33_0402_5%~D
CLK_PCIE_EXP# <32>
CLKREQ_4# 57 EXPCLK_REQ# <32>

+3.3V_RUN CLK_SDATA 17 SMBDAT MCH_3GPLL CLK_MCH_3GPLL
SRC_3 55 1 2 CLK_MCH_3GPLL <10>
10K_0402_5%~D
R45 33_0402_5%~D
2
4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# <10>

VSS_SRC SRC_3#
R46
ITP_EN PIN 37 R47 33_0402_5%~D

15 28 CLK_3GPLLREQ#_R 1 2 CLK_3GPLLREQ# CLK_3GPLLREQ# <10>
VSS_CPU CLKREQ_3# R48 475_0402_1%~D
0 Pin 5/6 as SRC_10
21 52
1
VSS_REF SRC_2
1 Pin 5/6 as CPU_ITP
PCI_ICH * 31 VSS_PCI SRC_2# 53
+3.3V_RUN 35 26
VSS_PCI CLKREQ_2#
10K_0402_5%~D
42 50 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA <23>

VSS_48 SRC_1/SATA
2
R49 33_0402_5%~D
R50
68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# <23>

VSS_SRC SRC_1#/SATA# R52 33_0402_5%~D
46 SATA_CLKREQ#_R 1 2 SATA_CLKREQ# <24>
CLKREQ_1# R53 475_0402_1%~D
FCTSEL1 PIN43 PIN44 PIN47 PIN48 73
1
A PCI_SIO THRM_PAD A
LCD_CLK/SRC_0 47
10K_0402_5%~D
1
@ 0=UMA DOT96T DOT96C 96/100M_T 96/100M_C 48

LCD_CLK#/SRC_0#
R54
1=DIS 27M_out 27M SSout SRCT0 SRCC0 DELL CONFIDENTIAL/PROPRIETARY

* SLG8LP554VTR_QFN72_10X10~D
2

0=UMA TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1=Disc. GRFX down BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
401533
Date: Tuesday, December 18, 2007 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
Place near JITP
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1
+1.05V_VCCP
29
<10> H_A#[3..35]
C19
C20
JCPU1A JITP1
H_A#3 J4 H1 H_ADS#
GND6
A[3]# ADS# H_ADS# <10> 2 2
ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 28
A[4]# BNR# H_BNR# <10> VTT1
H_A#5 L4 G5 H_BPRI# 27
A[5]# BPRI# H_BPRI# <10> VTT0
H_A#6 K5 26 JCPU1D
H_A#7 A[6]# H_DEFER# ITP_DBRESET# VTAP
M3 A[7]# DEFER# H5 H_DEFER# <10> 25 DBR# A4 VSS[001] VSS[082] P6
H_A#8 N2 F21 H_DRDY# 24 A8 P21
A[8]# DRDY# H_DRDY# <10> DBA# VSS[002] VSS[083]
H_A#9 J1 E1 H_DBSY# ITP_BPM#0 23 A11 P24
D A[9]# DBSY# H_DBSY# <10> BPM0# VSS[003] VSS[084] D
H_A#10 N3 22 A14 R2
H_A#11 A[10]# H_BR0# ITP_BPM#1 GND5 VSS[004] VSS[085]
P5 A[11]# BR0# F1 H_BR0# <10> 21 BPM1# A16 VSS[005] VSS[086] R5
H_A#12 P2 20 A19 R22
A[12]# GND4 VSS[006] VSS[087]
CONTROL
H_A#13 L2 D20 H_IERR# 2 1 +1.05V_VCCP ITP_BPM#2 19 A23 R25
H_A#14 A[13]# IERR# H_INIT# R56 56_0402_5%~D BPM2# VSS[007] VSS[088]
P4 A[14]# INIT# B3 H_INIT# <23> 18 GND3 AF2 VSS[008] VSS[089] T1
H_A#15 P1 ITP_BPM#3 17 B6 T4
H_A#16 A[15]# H_LOCK# BPM3# VSS[009] VSS[090]
R1 A[16]# LOCK# H4 H_LOCK# <10> 16 GND2 B8 VSS[010] VSS[091] T23
H_ADSTB#0 M1 ITP_BPM#4 15 B11 T26
<10> H_ADSTB#0 ADSTB[0]# BPM4# VSS[011] VSS[092]
C1 H_RESET# 14 B13 U3
RESET# H_RESET# <10> GND1 VSS[012] VSS[093]
H_REQ#0 K3 F3 H_RS#0 ITP_BPM#5 13 B16 U6
<10> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <10> BPM5# VSS[013] VSS[094]
H_REQ#1 H2 F4 H_RS#1 H_RESET# 1 2 12 B19 U21
<10> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <10> RESET# VSS[014] VSS[095]
H_REQ#2 K2 G3 H_RS#2 R57 1K_0402_5%~D ITP_TCK 11 B21 U24
<10> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <10> FBO VSS[015] VSS[096]
H_REQ#3 J3 G2 H_TRDY# 10 B24 V2
<10> H_REQ#3 REQ[3]# TRDY# H_TRDY# <10> GND0 VSS[016] VSS[097]
H_REQ#4 L1 CLK_CPU_ITP 9 C5 V5
<10> H_REQ#4 REQ[4]# <6> CLK_CPU_ITP BCLKP VSS[017] VSS[098]
G6 H_HIT# CLK_CPU_ITP# 8 C8 V22
HIT# H_HIT# <10> <6> CLK_CPU_ITP# BCLKN VSS[018] VSS[099]
H_A#17 Y2 E4 H_HITM# ITP_TDO 1 2 7 C11 V25
A[17]# HITM# H_HITM# <10> TDO VSS[019] VSS[100]
H_A#18 U5 R989 22.6_0402_1%~D 6 C14 W1
H_A#19 A[18]# ITP_BPM#0 ITP_TCK NC2 VSS[020] VSS[101]
R3 A[19]# BPM[0]# AD4 5 TCK C16 VSS[021] VSS[102] W4
ADDR GROUP_1
H_A#20 W6 AD3 ITP_BPM#1 4 C19 W23
H_A#21 A[20]# BPM[1]# ITP_BPM#2 ITP_TRST# NC1 VSS[022] VSS[103]
U4 A[21]# BPM[2]# AD1 3 TRST# C2 VSS[023] VSS[104] W26
H_A#22 Y5 AC4 ITP_BPM#3 ITP_TMS 2 C22 Y3
A[22]# BPM[3]# TMS VSS[024] VSS[105]
GND7
XDP/ITP SIGNALS
H_A#23 U1 AC2 ITP_BPM#4 ITP_TDI 1 C25 Y6
H_A#24 A[23]# PRDY# ITP_BPM#5 +1.05V_VCCP TDI VSS[025] VSS[106]
R4 A[24]# PREQ# AC1 D1 VSS[026] VSS[107] Y21
H_A#25 T5 AC5 ITP_TCK D4 Y24
H_A#26 A[25]# TCK ITP_TDI MOLEX_52435-2891_28P~D VSS[027] VSS[108]
T3 AA6 D8 AA2
30
A[26]# TDI VSS[028] VSS[109]
1
H_A#27 W2 AB3 ITP_TDO D11 AA5
H_A#28 A[27]# TDO ITP_TMS R59 VSS[029] VSS[110]
W5 A[28]# TMS AB5 D13 VSS[030] VSS[111] AA8
H_A#29 Y4 AB6 ITP_TRST# 56_0402_5%~D D16 AA11
H_A#30 A[29]# TRST# ITP_DBRESET# VSS[031] VSS[112]
U2 A[30]# DBR# C20 ITP_DBRESET# <24,37> D19 VSS[032] VSS[113] AA14
H_A#31 V4 +3.3V_ALW D23 AA16
2
H_A#32 A[31]# VSS[033] VSS[114]
W3 A[32]# D26 VSS[034] VSS[115] AA19
H_A#33 AA4 THERMAL EC_CPU_PROCHOT# E3 AA22
C H_A#34 A[33]# VSS[035] VSS[116] C
AB2 A[34]# E6 VSS[036] VSS[117] AA25
H_A#35 AA3 D21 H_THERMDA E8 AB1
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA <18> VSS[037] VSS[118]
<10> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 2 E11 VSS[038] VSS[119] AB4
1
B25 @ C18 E14 AB8
H_A20M# THERMDC 100P_0402_50V8K~D R941 VSS[039] VSS[120]
<23> H_A20M# A6 A20M# width / Spacing = 10 / 10 mil E16 VSS[040] VSS[121] AB11
ICH
H_FERR# A5 C7 100K_0402_5%~D E19 AB13

<23> H_FERR# H_IGNNE# FERR# THERMTRIP# H_THERMDC 1 @ VSS[041] VSS[122]
<23> H_IGNNE# C4 IGNNE# H_THERMDC <18> E21 VSS[042] VSS[123] AB16
E24 AB19
2
H_STPCLK# H_THERMTRIP# VSS[043] VSS[124]
<23> H_STPCLK# D5 STPCLK# H_THERMTRIP# <18> F5 VSS[044] VSS[125] AB23
H_INTR C6 H CLK F8 AB26
<23> H_INTR LINT0 <37> QUAD_DET VSS[045] VSS[126]
H_NMI B4 A22 CLK_CPU_BCLK F11 AC3
<23> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <6> +1.05V_VCCP VSS[046] VSS[127]
H_SMI# A3 A21 CLK_CPU_BCLK# R976 R977 F13 AC6
<23> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <6> VSS[047] VSS[128]
0_0402_5%~D 51_0402_1%~D Pin F8 F16 AC8
ITP_BPM2#1 ITP_BPM#0 VSS[048] VSS[129]
<18> H_THERMDA1 M4 RSVD[01] 1 @ 2 ITP_BPM2#0 @
Dual Core: GND (internal) F19 VSS[049] VSS[130] AC11
C227 2 ITP_BPM2#0 N5 R978 R979 F2 AC14
@ RSVD[02] 0_0402_5%~D 51_0402_1%~D Quad Core: Floating (internal) VSS[050] VSS[131]
width / Spacing = 10 / 10 mil T2 RSVD[03] F22 VSS[051] VSS[132] AC16
V3 +1.05V_VCCP ITP_BPM#1 1 @ 2 ITP_BPM2#1 @ F25 AC19
RSVD[04] VSS[052] VSS[133]
RESERVED
100P_0402_50V8K~D ITP_BPM2#2 B2 R980 R981 G4 AC21

1 RSVD[05] H_RESET# 0_0402_5%~D 51_0402_1%~D VSS[053] VSS[134]
<18> H_THERMDC1 D2 RSVD[06] G1 VSS[054] VSS[135] AC24
+V_CPU_GTLREF_2 D22 R973 51_0402_1%~D ITP_BPM#2 1 @ 2 ITP_BPM2#2 @ G23 AD2
RSVD[07] R982 R983 VSS[055] VSS[136]
D3 RSVD[08] G26 VSS[056] VSS[137] AD5
F6 RSVD[09] 1 2 H_THERMTRIP# 0_0402_5%~D 51_0402_1%~D H3 VSS[057] VSS[138] AD8
R984 R61 56_0402_5%~D ITP_BPM#3 1 @ 2 ITP_BPM2#3 @ H6 AD11
51_0402_5%~D VSS[058] VSS[139]
QC: H21 VSS[059] VSS[140] AD13
+1.05V_VCCP 1 @ 2 ES1: POP ALL H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
QC: POP TYCO_1-1674770-2_Penryn~D ES2: POP 0 ohm ONLY J5 AD22
+1.05V_VCCP VSS[062] VSS[143]
DC: DEPOP DC: DEPOP ALL J22 VSS[063] VSS[144] AD25
R785 J25 AE1
51_0402_5%~D VSS[064] VSS[145]
K1 VSS[065] VSS[146] AE4
1@ 2 ITP_BPM#5 K4 VSS[066] VSS[147] AE8 ITP_BPM2#3
+3.3V_ALW_ICH K23 AE11
B VSS[067] VSS[148] B
Pin D22 Place close to CPU within 200 mil K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
Dual Core: 0 V 1 2 ITP_DBRESET# L6 AE19
R60 10K_0402_5%~D VSS[070] VSS[151]
Quad Core: 2/3 VTT L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
Place close to JITP within 1ns = 5000 mil M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
+1.05V_VCCP +3.3V_ALW +1.05V_VCCP N23 AF19
R62 VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
+1.05V_VCCP 51_0402_5%~D P3 A25
VSS[081] VSS[162]
1
R65 1 2 ITP_TDO AF25

@ 51_0402_5%~D VSS[163]
R942 1 2 ITP_TDI R64 TYCO_1-1674770-2_Penryn~D
1
+V_CPU_GTLREF_2 1K_0402_1%~D +3.3V_ALW 51_0402_5%~D

R943 R66 1 2 ITP_TMS
2
100K_0402_5%~D 51_0402_5%~D
@ 1 2 ITP_TRST# R67
1
51_0402_5%~D
2
@ Q129 ITP_TCK
1 2
1
R944 D BSS138_SOT23~D
2K_0402_1%~D @
2 R945
G 100K_0402_5%~D Place close to CPU within 200ps = 1000 mil Place close to JITP within 200ps = 1000 mil
2
S @
3
R946
2
10K_0402_5%~D
1
C
Layout close CPU PIN D22 @
2 2 1 QUAD_REF_EN <37>
B
A
50 ohm, 0.5 inch (max) E MMST3904-7-F_SOT323-3~D
Depop JITP1,C19,C20,R64,R67,R785,R65,R66 when not supported for cost saving. A
3
@ Q14
Quad Core support circuit PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATIC, MB A4042
Size Document Number Rev
A
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401533
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
JCPU1C
A7 VCC[001] VCC[068] AB20
A9 VCC[002] VCC[069] AB7
A10 VCC[003] VCC[070] AC7
A12 VCC[004] VCC[071] AC9
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 VCC[007] VCC[074] AC15
A18 VCC[008] VCC[075] AC17
A20 VCC[009] VCC[076] AC18
B7 VCC[010] VCC[077] AD7
D D
<10> H_D#[0..63] B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10
B12 VCC[013] VCC[080] AD12
JCPU1B B14 AD14
H_D#0 H_D#32 VCC[014] VCC[081]
E22 D[0]# D[32]# Y22 B15 VCC[015] VCC[082] AD15
H_D#1 F24 AB24 H_D#33 B17 AD17
H_D#2 D[1]# D[33]# H_D#34 VCC[016] VCC[083]
E26 D[2]# D[34]# V24 B18 VCC[017] VCC[084] AD18
DATA GRP 0
H_D#3 G22 V26 H_D#35 B20 AE9
D[3]# D[35]# VCC[018] VCC[085]
DATA GRP 2
H_D#4 F23 V23 H_D#36 C9 AE10
H_D#5 D[4]# D[36]# H_D#37 VCC[019] VCC[086]
G25 D[5]# D[37]# T22 C10 VCC[020] VCC[087] AE12
H_D#6 E25 U25 H_D#38 C12 AE13
H_D#7 D[6]# D[38]# H_D#39 VCC[021] VCC[088]
E23 D[7]# D[39]# U23 C13 VCC[022] VCC[089] AE15
H_D#8 K24 Y25 H_D#40 C15 AE17
H_D#9 D[8]# D[40]# H_D#41 VCC[023] VCC[090]
G24 D[9]# D[41]# W22 C17 VCC[024] VCC[091] AE18
H_D#10 J24 Y23 H_D#42 C18 AE20
H_D#11 D[10]# D[42]# H_D#43 VCC[025] VCC[092]
J23 D[11]# D[43]# W24 D9 VCC[026] VCC[093] AF9
H_D#12 H22 W25 H_D#44 D10 AF10
H_D#13 D[12]# D[44]# H_D#45 VCC[027] VCC[094]
F26 D[13]# D[45]# AA23 D12 VCC[028] VCC[095] AF12
H_D#14 K22 AA24 H_D#46 D14 AF14
H_D#15 D[14]# D[46]# H_D#47 VCC[029] VCC[096]
H23 D[15]# D[47]# AB25 D15 VCC[030] VCC[097] AF15
<10> H_DSTBN#0 H_DSTBN#0 J26 Y26 H_DSTBN#2 H_DSTBN#2 <10> D17 AF17
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[031] VCC[098]
<10> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <10> D18 VCC[032] VCC[099] AF18
H_DINV#0 H25 U22 H_DINV#2 E7 AF20
<10> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <10> VCC[033] VCC[100]
E9 VCC[034]
E10 VCC[035] VCCP[01] G21 +1.05V_VCCP
H_D#16 N22 AE24 H_D#48 E12 V6
H_D#17 D[16]# D[48]# H_D#49 VCC[036] VCCP[02]
K25 D[17]# D[49]# AD24 E13 VCC[037] VCCP[03] J6
220U_D2_4VY_R15M~D
H_D#18 P26 AA21 H_D#50 E15 K6 1
H_D#19 D[18]# D[50]# H_D#51 VCC[038] VCCP[04]
R23 D[19]# D[51]# AB22 E17 VCC[039] VCCP[05] M6
H_D#20 L23 AB21 H_D#52 E18 J21 +
D[20]# D[52]# VCC[040] VCCP[06]
DATA GRP 1
C21
H_D#21 M24 AC26 H_D#53 E20 K21
D[21]# D[53]# VCC[041] VCCP[07]
H_D#22 L22 D[22]# DATA GRP 3
D[54]# AD20 H_D#54 F7 VCC[042] VCCP[08] M21
2
C H_D#23 H_D#55 C
M23 AE22 F9 N21
H_D#24 P25
D[23]#
D[24]#
D[55]#
D[56]# AF23 H_D#56 F10
VCC[043]
VCC[044]
VCCP[09]
VCCP[10] N6 CRB was 270uF
H_D#25 P23 AC25 H_D#57 F12 R21
H_D#26 D[25]# D[57]# H_D#58 VCC[045] VCCP[11]
P22 D[26]# D[58]# AE21 F14 VCC[046] VCCP[12] R6
H_D#27 T24 AD21 H_D#59 F15 T21
H_D#28 D[27]# D[59]# H_D#60 VCC[047] VCCP[13]
R24 D[28]# D[60]# AC22 F17 VCC[048] VCCP[14] T6
H_D#29 L25 AD23 H_D#61 F18 V21
H_D#30 D[29]# D[61]# H_D#62 VCC[049] VCCP[15]
T25 D[30]# D[62]# AF22 F20 VCC[050] VCCP[16] W21
H_D#31 N25 AC23 H_D#63 AA7
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[051]
<10> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <10> AA9 VCC[052] VCCA[01] B26 +1.5V_RUN
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
<10> H_DSTBP#1 H_DSTBP#1 M26 AF24 H_DSTBP#3 H_DSTBP#3 <10> AA10 C26
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[053] VCCA[02]
<10> H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 <10> AA12 VCC[054]
AA13 AD6 VID0
VCC[055] VID[0] VID0 <47>
+V_CPU_GTLREF AD26 R26 COMP0 AA15 AF5 VID1 1 1
GTLREF COMP[0] VCC[056] VID[1] VID1 <47>
TEST1 C23 MISC U26 COMP1 AA17 AE5 VID2
TEST1 COMP[1] VCC[057] VID[2] VID2 <47>
C22
C23
TEST2 D25 AA1 COMP2 AA18 AF4 VID3
TEST2 COMP[2] VCC[058] VID[3] VID3 <47>
TEST3 C24 Y1 COMP3 AA20 AE3 VID4
TEST3 COMP[3] VCC[059] VID[4] VID4 <47> 2 2
PAD~D T153 TEST4 AF26 AB9 AF3 VID5
TEST4 VCC[060] VID[5] VID5 <47>
49.9_0402_1%~D
24.9_0402_1%~D
49.9_0402_1%~D
24.9_0402_1%~D
TEST5 AF1 E5 H_DPRSTP# AC10 AE2 VID6
TEST5 DPRSTP# H_DPRSTP# <10,23,47> VCC[061] VID[6] VID6 <47>
1
PAD~D T138 TEST6 A26 B5 H_DPSLP# AB10
TEST6 DPSLP# H_DPSLP# <23> VCC[062]
R68
R69
R70
R71
PAD~D T4 TEST7 C3 D24 H_DPWR# AB12
CPU_MCH_BSEL0 TEST7 DPWR# H_PWRGOOD H_DPWR# <10> VCC[063] VCCSENSE
<6,10> CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <23> AB14 VCC[064] VCCSENSE AF7 VCCSENSE <47>
CPU_MCH_BSEL1 B23 D7 H_CPUSLP# AB15
<6,10> CPU_MCH_BSEL1 BSEL[1] SLP# H_CPUSLP# <10> VCC[065]
CPU_MCH_BSEL2 C21 AE6 H_PSI# AB17
H_PSI# <47>
2
<6,10> CPU_MCH_BSEL2 BSEL[2] PSI# VCC[066] VSSSENSE
AB18 VCC[067] VSSSENSE AE7 VSSSENSE <47>
TYCO_1-1674770-2_Penryn~D
TYCO_1-1674770-2_Penryn~D
Resistor placed within 0.5" of

CPU pin.Trace should be at least Length match within 25 mils, Z0=27.4 ohm
B 25 mils away from any other B
toggling signal. COMP0, COMP2
trace should be 25 ohm. COMP1,
TEST1 COMP3 should be 50 ohm.
TEST2 Place R75 and R76 near CPU
(Quad Core design)
PAD~D T154 TEST3
PAD~D T3 TEST5
+VCC_CORE
Dual Core Should follow Quad Core value
1K_0402_5%~D
1K_0402_5%~D
2
2
@R72
@
@R73
@
For the purpose of testability, route these signals Avia should support Quad / Dual Core CPU
R72
R73
1 2 VCCSENSE 1 2
through a ground referenced Z0 = 50ohm trace that R75 100_0402_1%~D @R833
@ R833 27.4_0402_1%~D
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
1
Reserve for testing

1 2 VSSSENSE
R76 100_0402_1%~D only
FSB BCLK BSEL2 BSEL1 BSEL0 +1.05V_VCCP
Route VCCSENSE and VSSSENSE trace at

1
533 133 0 0 1 27.4 ohms, 7 mils spacing and the placement should be within 1 inch (max)
R77
+V_CPU_GTLREF 1K_0402_1%~D
667 166 0 1 1
2
800 200 0 1 0
1
A A
1067 266 0 0 0 R78

2K_0402_1%~D
2
Layout close CPU PIN AD26 Compal Electronics, Inc.
Title
50 ohm, 0.5 inch (max) PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
SCHEMATIC, MB A4042
A
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(North side C24 C25 C26 C27 C28 C29 C30 C31 C32 C33
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
D 2 2 2 2 2 2 2 2 2 2 D
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(Sorth side C34 C35 C36 C37 C38 C39 C40 C41 C42 C43
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1

socket cavity on L8
(North side C44 C45 C46 C47 C48 C49
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

socket cavity on L8
(Sorth side C50 C51 C52 C53 C54 C55
C Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D C
2 2 2 2 2 2
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
1 1 1 1 1 1
@
@
+ + + + + +
C58
C61
C56
C59
C60
C57
2 2 2 2 2 2
ESR <= 1.5m ohm
Capacitor > 1320uF
Board Bottom Side Board Top Side
B B
+1.05V_VCCP
1 1 1 1 1 1
Place these inside
C62 C63 C64 C65 C66 C67 socket cavity on L8
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D (North side
2 2 2 2 2 2 Secondary)
A A
401533
5 4 3 2 1
5 4 3 2 1
U2B
M36 TP_MCH_RSVD1 T172PAD~D

M_CLK_DDR0 RSVD1 TP_MCH_RSVD2
DDR CLK/ CONTROL/COMPENSATION

<16> M_CLK_DDR0 AP24 SA_CK_0 RSVD2 N36 T173PAD~D
M_CLK_DDR1 AT21 R33 TP_MCH_RSVD3 T174PAD~D
<16> M_CLK_DDR1 SA_CK_1 RSVD3
M_CLK_DDR2 AV24 T33 TP_MCH_RSVD4 T175PAD~D
<17> M_CLK_DDR2 SB_CK_0 RSVD4
M_CLK_DDR3 AU20 AH9 TP_MCH_RSVD5 T176PAD~D
<17> M_CLK_DDR3 SB_CK_1 RSVD5
AH10 TP_MCH_RSVD6 T177PAD~D
M_CLK_DDR#0 RSVD6 TP_MCH_RSVD7
<16> M_CLK_DDR#0 AR24 SA_CK#_0 RSVD7 AH12 T178PAD~D
M_CLK_DDR#1 AR21 AH13 TP_MCH_RSVD8 T179PAD~D
<16> M_CLK_DDR#1 SA_CK#_1 RSVD8
M_CLK_DDR#2 AU24 K12 TP_MCH_RSVD9 T5 PAD~D
<17> M_CLK_DDR#2 SB_CK#_0 RSVD9
M_CLK_DDR#3 AV20 AL34 ME_JTAG_TCK @ R804 1 2 100_0402_5%~D T123PAD~D
<17> M_CLK_DDR#3 SB_CK#_1 RSVD10
AK34 ME_JTAG_TDI @ R805 1 2 100_0402_5%~D T124PAD~D
DDR_CKE0_DIMMA RSVD11 ME_JTAG_TDO @ R806 100_0402_5%~D
H_A#[3..35] <7> <16> DDR_CKE0_DIMMA BC28 SA_CKE_0 RSVD12 AN35 1 2 T125PAD~D
U2A DDR_CKE1_DIMMA AY28 AM35 ME_JTAG_TMS @ R807 1 2 100_0402_5%~D T126PAD~D
<8> H_D#[0..63] <16> DDR_CKE1_DIMMA SA_CKE_1 RSVD13
A14 H_A#3 DDR_CKE2_DIMMB AY36 T24
H_A#_3 <17> DDR_CKE2_DIMMB SB_CKE_0 RSVD14
D H_D#0 F2 C15 H_A#4 DDR_CKE3_DIMMB BB36 D
H_D#_0 H_A#_4 <17> DDR_CKE3_DIMMB SB_CKE_1
RSVD
H_D#1 G8 F16 H_A#5 B31 TP_MCH_RSVD15 T6 PAD~D Reserve 100ohm and Test
H_D#2 H_D#_1 H_A#_5 H_A#6 DDR_CS0_DIMMA# RSVD15 TP_MCH_RSVD16
F8 H_D#_2 H_A#_6 H13 <16> DDR_CS0_DIMMA# BA17 SA_CS#_0 RSVD16 B2 T7 PAD~D point for ME JTAG debug
H_D#3 E6 C18 H_A#7 DDR_CS1_DIMMA# AY16 M1 TP_MCH_RSVD17 T8 PAD~D
H_D#_3 H_A#_7 <16> DDR_CS1_DIMMA# SA_CS#_1 RSVD17
H_D#4 G2 M16 H_A#8 DDR_CS2_DIMMB# AV16
H_D#_4 H_A#_8 <17> DDR_CS2_DIMMB# SB_CS#_0
H_D#5 H6 J13 H_A#9 DDR_CS3_DIMMB# AR13
H_D#_5 H_A#_9 <17> DDR_CS3_DIMMB# SB_CS#_1
H_D#6 H2 P16 H_A#10 AY21 TP_MCH_RSVD20 T9 PAD~D
H_D#7 H_D#_6 H_A#_10 H_A#11 M_ODT0 RSVD20
F6 H_D#_7 H_A#_11 R16 <16> M_ODT0 BD17 SA_ODT_0
H_D#8 D4 N17 H_A#12 M_ODT1 AY17
H_D#_8 H_A#_12 +1.8V_MEM <16> M_ODT1 SA_ODT_1
H_D#9 H3 M13 H_A#13 M_ODT2 BF15
H_D#_9 H_A#_13 <17> M_ODT2 SB_ODT_0
H_D#10 M9 E17 H_A#14 M_ODT3 AY13 BG23 TP_MCH_RSVD22 T10 PAD~D
H_D#_10 H_A#_14 <17> M_ODT3 SB_ODT_1 RSVD22
H_D#11 M11 P17 H_A#15 2 1 SMRCOMP BF23 TP_MCH_RSVD23 T11 PAD~D
H_D#12 H_D#_11 H_A#_15 H_A#16 R79 80.6_0402_1%~D SMRCOMP RSVD23 TP_MCH_RSVD24
J1 H_D#_12 H_A#_16 F17 BG22 SM_RCOMP RSVD24 BH18 T12 PAD~D
H_D#13 J2 G20 H_A#17 2 1 SMRCOMP# SMRCOMP# BH21 BF18 TP_MCH_RSVD25 T182PAD~D
H_D#14 H_D#_13 H_A#_17 H_A#18 R80 80.6_0402_1%~D SM_RCOMP# RSVD25
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19 SMRCOMP_VOH BF28
H_D#16 H_D#_15 H_A#_19 H_A#20 SMRCOMP_VOL SM_RCOMP_VOH
P2 H_D#_16 H_A#_20 E20 BH28 SM_RCOMP_VOL
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22 +V_DDR_MCH_REF
R2 H_D#_18 H_A#_22 J20 +V_DDR_MCH_REF AV42 SM_VREF
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_D#19 N9 L17 H_A#23 SM_PWROK AR36
H_D#20 H_D#_19 H_A#_23 H_A#24 R81 499_0402_1%~D SM_PWROK
L6 H_D#_20 H_A#_24 A17 1 2 BF17 SM_REXT
H_D#21 M5 B17 H_A#25 1 1 PAD~D T13 TP_SM_DRAMRST# BC36
H_D#22 H_D#_21 H_A#_25 H_A#26 SM_DRAMRST#
J3 H_D#_22 H_A#_26 L16
C68
C69
H_D#23 N2 C21 H_A#27 B38
H_D#24 H_D#_23 H_A#_27 H_A#28 DPLL_REF_CLK
R1 H_D#_24 H_A#_28 J17 A38 DPLL_REF_CLK#
H_D#25 H_A#29 2 2
N5 H_D#_25 H_A#_29 H20 E41 DPLL_REF_SSCLK
H_D#26 N6 B18 H_A#30 F41
H_D#27 H_D#_26 H_A#_30 H_A#31 DPLL_REF_SSCLK#
P13 H_D#_27 H_A#_31 K17
H_D#28 H_A#32 CLK_MCH_3GPLL
CLK
N8 H_D#_28 H_A#_32 B20 <6> CLK_MCH_3GPLL F43 PEG_CLK
H_D#29 L7 F21 H_A#33 <6> CLK_MCH_3GPLL# CLK_MCH_3GPLL# E43
H_D#30 H_D#_29 H_A#_33 H_A#34 PEG_CLK#
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS# H_ADS# <7> DMI_MRX_ITX_N0 AE41
H_D#_33 H_ADS# <24> DMI_MRX_ITX_N0 DMI_RXN_0
H_D#34 Y6 B16 H_ADSTB#0 DMI_MRX_ITX_N1 AE37
C H_D#_34 H_ADSTB#_0 H_ADSTB#0 <7> <24> DMI_MRX_ITX_N1 DMI_RXN_1 C
H_D#35 Y10 G17 H_ADSTB#1 DMI_MRX_ITX_N2 AE47
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <7> <24> DMI_MRX_ITX_N2 DMI_RXN_2
H_D#36 Y12 A9 H_BNR# H_BNR# <7> DMI_MRX_ITX_N3 AH39
H_D#_36 H_BNR# <24> DMI_MRX_ITX_N3 DMI_RXN_3
H_D#37 Y14 F11 H_BPRI# H_BPRI# <7>
H_D#38 H_D#_37 H_BPRI# H_BR0# DMI_MRX_ITX_P0
Y7 G12 AE40
HOST
H_D#_38 H_BREQ# H_BR0# <7> <24> DMI_MRX_ITX_P0 DMI_RXP_0

H_D#39 W2 E9 H_DEFER# H_DEFER# <7> DMI_MRX_ITX_P1 AE38 T25
H_D#_39 H_DEFER# <24> DMI_MRX_ITX_P1 DMI_RXP_1 CFG_0 CPU_MCH_BSEL0 <6,8>
H_D#40 AA8 B10 H_DBSY# H_DBSY# <7> DMI_MRX_ITX_P2 AE48 R25
H_D#_40 H_DBSY# <24> DMI_MRX_ITX_P2 DMI_RXP_2 CFG_1 CPU_MCH_BSEL1 <6,8>
H_D#41 Y9 AH7 CLK_MCH_BCLK DMI_MRX_ITX_P3 AH40 P25
H_D#_41 HPLL_CLK CLK_MCH_BCLK <6> <24> DMI_MRX_ITX_P3 DMI_RXP_3 CFG_2 CPU_MCH_BSEL2 <6,8>
H_D#42 AA13 AH6 CLK_MCH_BCLK# CLK_MCH_BCLK# <6> P20 T14 PAD~D
H_D#43 H_D#_42 HPLL_CLK# H_DPWR# DMI_MTX_IRX_N0 CFG_3
AA9 H_D#_43 H_DPWR# J11 H_DPWR# <8> <24> DMI_MTX_IRX_N0 AE35 DMI_TXN_0 CFG_4 P24 T15 PAD~D
H_D#44 AA11 F9 H_DRDY# DMI_MTX_IRX_N1 AE43 C25 CFG5 CFG5 <12>
H_D#_44 H_DRDY# H_DRDY# <7> <24> DMI_MTX_IRX_N1 DMI_TXN_1 CFG_5
H_D#45 AD11 H9 H_HIT# H_HIT# <7> DMI_MTX_IRX_N2 AE46 N24 CFG6 CFG6 <12>
H_D#_45 H_HIT# <24> DMI_MTX_IRX_N2 DMI_TXN_2 CFG_6
H_D#46 AD10 E12 H_HITM# H_HITM# <7> DMI_MTX_IRX_N3 AH42 M24 CFG7 CFG7 <12>
H_D#_46 H_HITM# <24> DMI_MTX_IRX_N3 DMI_TXN_3 CFG_7
H_D#47 AD13 H11 H_LOCK# H_LOCK# <7> E21 T16 PAD~D
H_D#_47 H_LOCK# CFG_8
DMI CFG
H_D#48 AE12 C9 H_TRDY# H_TRDY# <7> DMI_MTX_IRX_P0 AD35 C23 CFG9 CFG9 <12>
H_D#_48 H_TRDY# <24> DMI_MTX_IRX_P0 DMI_TXP_0 CFG_9
H_D#49 AE9 DMI_MTX_IRX_P1 AE44 C24 T17 PAD~D
H_D#_49 <24> DMI_MTX_IRX_P1 DMI_TXP_1 CFG_10
H_D#50 AA2 DMI_MTX_IRX_P2 AF46 N21 T18 PAD~D
H_D#51 AD8 DMI_MTX_IRX_P3 AH43 P21 T19 PAD~D
H_D#52 AA3 T21 T20 PAD~D
H_D#53 H_D#_52 H_DINV#0 CFG_13
AD3 H_D#_53 H_DINV#_0 J8 H_DINV#0 <8> CFG_14 R20 T21 PAD~D
H_D#54 AD7 L3 H_DINV#1 M20 T22 PAD~D
H_D#_54 H_DINV#_1 H_DINV#1 <8> CFG_15
H_D#55 AE14 Y13 H_DINV#2 L21 CFG16 CFG16 <12>
H_D#56 AF3 Y1 H_DINV#3 H21 T23 PAD~D
H_D#57
GRAPHICS VID
AC1 H_D#_57 CFG_18 P29 T24 PAD~D
H_D#58 AE3 L10 H_DSTBN#0 H_DSTBN#0 <8> R28 CFG19 CFG19 <12>
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 GFX_VID0 CFG_19 CFG20
AC3 H_D#_59 H_DSTBN#_1 M7 H_DSTBN#1 <8> PAD~D T25 B33 GFX_VID_0 CFG_20 T28 CFG20 <12>
H_D#60 AE11 AA5 H_DSTBN#2 H_DSTBN#2 <8> PAD~D T26 GFX_VID1 B32
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3 GFX_VID2 GFX_VID_1
AE8 H_D#_61 H_DSTBN#_3 AE6 H_DSTBN#3 <8> PAD~D T27 G33 GFX_VID_2
H_D#62 AG2 PAD~D T28 GFX_VID3 F33
H_D#63 H_D#_62 H_DSTBP#0 GFX_VID4 GFX_VID_3 PM_SYNC#
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 <8> PAD~D T29 E33 GFX_VID_4 PM_SYNC# R29 PM_SYNC# <24>
M8 H_DSTBP#1 H_DSTBP#1 <8> B7 H_DPRSTP# H_DPRSTP# <8,23,47>
H_DSTBP#_1 H_DSTBP#2 PM_DPRSTP#
H_DSTBP#_2 AA6 H_DSTBP#2 <8> PM_EXT_TS#_0 N33
H_SWNG C5 AE5 H_DSTBP#3 H_DSTBP#3 <8> P32 PM_EXTTS# PM_EXTTS# <18>
H_SWING H_DSTBP#_3 PM_EXT_TS#_1
PM
1 2 +H_RCOMP E3 PAD~D T30 GFX_VR_ON C34 AT40 ICH_PWRGD
H_RCOMP +1.05V_M GFX_VR_EN PWROK ICH_PWRGD <24,41>
R82 24.9_0402_1%~D B15 H_REQ#0 AT11 PLTRST1#_R
H_REQ#_0 H_REQ#0 <7> RSTIN#
B K13 H_REQ#1 T20 THERMTRIP_MCH# THERMTRIP_MCH# <18> B
H_REQ#_1 H_REQ#1 <7> THERMTRIP#
1K_0402_1%~D
F13 H_REQ#2 R32 DPRSLPVR DPRSLPVR <24,47>

H_REQ#_2 H_REQ#2 <7> DPRSLPVR
1
B13 H_REQ#3
H_REQ#_3 H_REQ#3 <7>
<7> H_RESET# H_RESET# C12 B14 H_REQ#4 CL_CLK0 AH37
H_CPURST# H_REQ#_4 H_REQ#4 <7> <24> CL_CLK0 CL_CLK
R83
H_CPUSLP# E11 CL_DATA0 AH36

<8> H_CPUSLP# H_CPUSLP# <24> CL_DATA0 CL_DATA
B6 H_RS#0 ICH_CL_PWROK AN36 BG48
H_RS#_0 H_RS#0 <7> <24,38> ICH_CL_PWROK CL_PWROK NC_1
F12 H_RS#1 CL_RST0# AJ35 BF48 +3.3V_RUN
H_RS#1 <7> <24> CL_RST0#
2
H_RS#_1 CL_RST# NC_2
ME
C8 H_RS#2 +CL_VREF AH34 BD48
H_RS#_2 H_RS#2 <7> CL_VREF NC_3
A11 H_AVREF NC_4 BC48
0.1U_0402_16V4Z~D
+H_VREF B11 BH47

H_DVREF NC_5
2
1 NC_6 BG47
CANTIGA ES_FCBGA1329~D R87 PAD~D T31 DDPC_CTRLCLK N28 BE47 PM_EXTTS# 2 1
DDPC_CTRLCLK NC_7
C70
499_0402_1%~D <12> DDPC_CTRLDATA DDPC_CTRLDATA M28 BH46 R85 10K_0402_5%~D

+1.8V_MEM DDPC_CTRLDATA NC_8
G36 SDVO_CTRLCLK NC_9 BF46
2
NC
E36 BG45
1
CLK_3GPLLREQ# SDVO_CTRLDATA NC_10

<6> CLK_3GPLLREQ# K36 CLKREQ# NC_11 BH44
1
<24> MCH_ICH_SYNC# MCH_ICH_SYNC# H36 BH43 SM_PWROK 2 1

R88 ICH_SYNC# NC_12 R86 0_0402_5%~D
BH6
MISC
+1.05V_VCCP +1.05V_VCCP 1K_0402_1%~D NC_13
NC_14 BH5
MCH_TSATN# B12 BG4
TSATN# NC_15
BH3 Use for DDR3 signls,
2
SMRCOMP_VOH NC_16
BF3
NC_17 if support DDR2 need
1
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
NC_18 BH2
R90 R91 1 1 PAD~D T32 ICH_AZ_MCH_BITCLK B28 HDA_BCLK NC_19 BG2 connect to GND
1K_0402_1%~D 221_0402_1%~D PAD~D T33 ICH_AZ_MCH_RST# B30 BE2
HDA_RST# NC_20
1
C71
C72
PAD~D T34 ICH_AZ_MCH_SDIN2 B29 BG1

ICH_AZ_MCH_SDOUT HDA_SDI NC_21
PAD~D T35 C29 BF1
2
R93 2 2 ICH_AZ_MCH_SYNC HDA_SDO NC_22
HDA
PAD~D T36 A28 HDA_SYNC NC_23 BD1
+H_VREF H_SWNG 3.01K_0402_1%~D BC1
+3.3V_RUN NC_24
F1
2
NC_25
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
NC_26 A47
1
1
100_0402_1%~D
1 1
@ C73
R95
1K_0402_5%~D
R94 SMRCOMP_VOL CANTIGA ES_FCBGA1329~D

C74
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
2K_0402_1%~D
1
1
1K_0402_5%~D
A 2 2 1 1 A
R99
R97
2
+1.05V_VCCP
C75
C76
1K_0402_1%~D PLTRST1#_R 2 1 PLTRST1# <22,32,51>

R98
R100 100_0402_5%~D
2 2
MCH_TSATN_EC <37>
2
1 2
1
R101 C THERMTRIP_MCH# 1
R102
2
56_0402_5%~D
+1.05V_VCCP DELL CONFIDENTIAL/PROPRIETARY
54.9_0402_1%~D 2
B
1
C E
2
MCH_TSATN# 2 1 1 2 2
R103 R104 B Q3 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
0_0402_5%~D 330_0402_5%~D E MMST3904-7-F_SOT323-3~DTRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
SCHEMATIC, MB A4042
3
Q4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

MMST3904-7-F_SOT323-3~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
401533
5 4 3 2 1
5 4 3 2 1
D D
DDR_A_D[0..63] <16> DDR_B_D[0..63] <17>

U2D U2E
DDR_A_BS0 BD21 AJ38 DDR_A_D0 DDR_B_BS0 BC16 AK47 DDR_B_D0
<16> DDR_A_BS0 SA_BS_0 SA_DQ_0 <17> DDR_B_BS0 SB_BS_0 SB_DQ_0
DDR_A_BS1 BG18 AJ41 DDR_A_D1 DDR_B_BS1 BB17 AH46 DDR_B_D1
DDR_A_BS2 AT25 AN38 DDR_A_D2 DDR_B_BS2 BB33 AP47 DDR_B_D2
AM38 DDR_A_D3 AP46 DDR_B_D3
DDR_A_RAS# SA_DQ_3 DDR_A_D4 SB_DQ_3 DDR_B_D4
<16> DDR_A_RAS# BB20 SA_RAS# SA_DQ_4 AJ36 SB_DQ_4 AJ46
DDR_A_CAS# BD20 AJ40 DDR_A_D5 DDR_B_RAS# AU17 AJ48 DDR_B_D5
<16> DDR_A_CAS# SA_CAS# SA_DQ_5 <17> DDR_B_RAS# SB_RAS# SB_DQ_5
DDR_A_WE# AY20 AM44 DDR_A_D6 DDR_B_CAS# BG16 AM48 DDR_B_D6
<16> DDR_A_WE# SA_WE# SA_DQ_6 <17> DDR_B_CAS# SB_CAS# SB_DQ_6
AM42 DDR_A_D7 DDR_B_WE# BF14 AP48 DDR_B_D7
SA_DQ_7 <17> DDR_B_WE# SB_WE# SB_DQ_7
AN43 DDR_A_D8 AU47 DDR_B_D8
SA_DQ_8 DDR_A_D9 SB_DQ_8 DDR_B_D9
<16> DDR_A_DM[0..7] SA_DQ_9 AN44 SB_DQ_9 AU46
AU40 DDR_A_D10 BA48 DDR_B_D10
SA_DQ_10 <17> DDR_B_DM[0..7] SB_DQ_10
DDR_A_DM0 AM37 AT38 DDR_A_D11 AY48 DDR_B_D11
DDR_A_DM1 SA_DM_0 SA_DQ_11 DDR_A_D12 DDR_B_DM0 SB_DQ_11 DDR_B_D12
AT41 SA_DM_1 SA_DQ_12 AN41 AM47 SB_DM_0 SB_DQ_12 AT47
DDR_A_DM2 AY41 AN39 DDR_A_D13 DDR_B_DM1 AY47 AR47 DDR_B_D13
DDR_A_DM3 SA_DM_2 SA_DQ_13 DDR_A_D14 DDR_B_DM2 SB_DM_1 SB_DQ_13 DDR_B_D14
AU39 SA_DM_3 SA_DQ_14 AU44 BD40 SB_DM_2 SB_DQ_14 BA47
DDR_A_DM4 BB12 AU42 DDR_A_D15 DDR_B_DM3 BF35 BC47 DDR_B_D15
DDR_A_DM5 SA_DM_4 SA_DQ_15 DDR_A_D16 DDR_B_DM4 SB_DM_3 SB_DQ_15 DDR_B_D16
AY6 SA_DM_5 SA_DQ_16 AV39 BG11 SB_DM_4 SB_DQ_16 BC46
DDR_A_DM6 AT7 AY44 DDR_A_D17 DDR_B_DM5 BA3 BC44 DDR_B_D17
SA_DM_6 SA_DQ_17 SB_DM_5 SB_DQ_17
A
DDR_A_DM7 AJ5 BA40 DDR_A_D18 DDR_B_DM6 AP1 BG43 DDR_B_D18
B
SA_DM_7 SA_DQ_18 DDR_A_D19 DDR_B_DM7 SB_DM_6 SB_DQ_18 DDR_B_D19
<16> DDR_A_DQS[0..7] SA_DQ_19 BD43 AK2 SB_DM_7 SB_DQ_19 BF43
DDR_A_DQS0 AJ44 AV41 DDR_A_D20 BE45 DDR_B_D20
C SA_DQS_0 SA_DQ_20 <17> DDR_B_DQS[0..7] SB_DQ_20 C
DDR_A_DQS1 AT44 AY43 DDR_A_D21 DDR_B_DQS0 AL47 BC41 DDR_B_D21
DDR_A_DQS2 SA_DQS_1 SA_DQ_21 DDR_A_D22 DDR_B_DQS1 SB_DQS_0 SB_DQ_21 DDR_B_D22
BA43 SA_DQS_2 SA_DQ_22 BB41 AV48 SB_DQS_1 SB_DQ_22 BF40
MEMORY
DDR_A_DQS3 BC37 BC40 DDR_A_D23 DDR_B_DQS2 BG41 DDR_B_D23
MEMORY
SA_DQS_3 SA_DQ_23 SB_DQS_2 SB_DQ_23 BF41
DDR_A_DQS4 AW12 AY37 DDR_A_D24 DDR_B_DQS3 BG37 BG38 DDR_B_D24
BC8 SA_DQS_5 SA_DQ_25 BD38 BH9 SB_DQS_4 SB_DQ_25 BF38
DDR_A_DQS6 AU8 AV37 DDR_A_D26 DDR_B_DQS5 BB2 BH35 DDR_B_D26
<16> DDR_A_DQS#[0..7] AM7 SA_DQS_7 SA_DQ_27 AT36 AU1 SB_DQS_6 SB_DQ_27 BG35
DDR_A_DQS#0 AJ43 AY38 DDR_A_D28 DDR_B_DQS7 AN6 BH40 DDR_B_D28
SA_DQS#_0 SA_DQ_28 <17> DDR_B_DQS#[0..7] SB_DQS_7 SB_DQ_28
DDR_A_DQS#1 AT43 BB38 DDR_A_D29 DDR_B_DQS#0 AL46 BG39 DDR_B_D29
DDR_A_DQS#2 SA_DQS#_1 SA_DQ_29 DDR_A_D30 DDR_B_DQS#1 SB_DQS#_0 SB_DQ_29 DDR_B_D30
BA44 SA_DQS#_2 SA_DQ_30 AV36 AV47 SB_DQS#_1 SB_DQ_30 BG34
DDR_A_DQS#3 BD37 AW36 DDR_A_D31 DDR_B_DQS#2 BH41 BH34 DDR_B_D31
AY12 SA_DQS#_4 SA_DQ_32 BD13 BH37 SB_DQS#_3 SB_DQ_32 BH14
DDR_A_DQS#5 BD8 AU11 DDR_A_D33 DDR_B_DQS#4 BG9 BG12 DDR_B_D33
AU9 SA_DQS#_6 SA_DQ_34 BC11 BC2 SB_DQS#_5 SB_DQ_34 BH11
DDR_A_DQS#7 AM8 BA12 DDR_A_D35 DDR_B_DQS#6 AT2 BG8 DDR_B_D35
SYSTEM
<16> DDR_A_MA[0..14] SA_DQS#_7 SA_DQ_35 SB_DQS#_6 SB_DQ_35

DDR_A_D36 DDR_B_DQS#7 DDR_B_D36
SYSTEM
SA_DQ_36 AU13 <17> DDR_B_MA[0..14] AN5 SB_DQS#_7 SB_DQ_36 BH12
DDR_A_MA0 BA21 AV13 DDR_A_D37 BF11 DDR_B_D37
DDR_A_MA1 SA_MA_0 SA_DQ_37 DDR_A_D38 DDR_B_MA0 SB_DQ_37 DDR_B_D38
BC24 SA_MA_1 SA_DQ_38 BD12 AV17 SB_MA_0 SB_DQ_38 BF8
DDR_A_MA2 BG24 BC12 DDR_A_D39 DDR_B_MA1 BA25 BG7 DDR_B_D39
DDR_A_MA3 SA_MA_2 SA_DQ_39 DDR_A_D40 DDR_B_MA2 SB_MA_1 SB_DQ_39 DDR_B_D40
BH24 SA_MA_3 SA_DQ_40 BB9 BC25 SB_MA_2 SB_DQ_40 BC5
DDR_A_MA4 BG25 BA9 DDR_A_D41 DDR_B_MA3 AU25 BC6 DDR_B_D41
BA24 SA_MA_5 SA_DQ_42 AU10 AW25 SB_MA_4 SB_DQ_42 AY3
DDR_A_MA6 BD24 AV9 DDR_A_D43 DDR_B_MA5 BB28 AY1 DDR_B_D43
BG27 SA_MA_7 SA_DQ_44 BA11 AU28 SB_MA_6 SB_DQ_44 BF6
DDR_A_MA8 BF25 BD9 DDR_A_D45 DDR_B_MA7 AW28 BF5 DDR_B_D45
AW24 SA_MA_9 SA_DQ_46 AY8 AT33 SB_MA_8 SB_DQ_46 BA1
DDR_A_MA10 BC21 BA6 DDR_A_D47 DDR_B_MA9 BD33 BD3 DDR_B_D47
DDR
BG26 SA_MA_11 SA_DQ_48 AV5 BB16 SB_MA_10 SB_DQ_48 AV2

DDR_A_MA12 DDR_A_D49 DDR_B_MA11 DDR_B_D49
DDR
BH26 SA_MA_12 SA_DQ_49 AV7 AW33 SB_MA_11 SB_DQ_49 AU3
DDR_A_MA13 BH17 AT9 DDR_A_D50 DDR_B_MA12 AY33 AR3 DDR_B_D50
AY25 SA_MA_14 SA_DQ_51 AN8 BH15 SB_MA_13 SB_DQ_51 AN2
AU5 DDR_A_D52 DDR_B_MA14 AU33 AY2 DDR_B_D52
B SA_DQ_52 DDR_A_D53 SB_MA_14 SB_DQ_52 DDR_B_D53 B
SA_DQ_53 AU6 SB_DQ_53 AV1
AT5 DDR_A_D54 AP3 DDR_B_D54
SA_DQ_55 AN10 SB_DQ_55 AR1
AM11 DDR_A_D56 AL1 DDR_B_D56
SA_DQ_57 AM5 SB_DQ_57 AL2
AJ9 DDR_A_D58 AJ1 DDR_B_D58
SA_DQ_59 AJ8 SB_DQ_59 AH1
AN12 DDR_A_D60 AM2 DDR_B_D60
SA_DQ_61 AM13 SB_DQ_61 AM3
AJ11 DDR_A_D62 AH3 DDR_B_D62
SA_DQ_63 AJ12 SB_DQ_63 AJ3
CANTIGA ES_FCBGA1329~D CANTIGA ES_FCBGA1329~D
A A
401533
5 4 3 2 1
5 4 3 2 1
+VCC_PEG Strap Pin Table

Low = DMI x 2
CFG5 DMI X2 Select
1
High = DMI x 4 (Default)
U2C R105
49.9_0402_1%~D iTPM Host Low = iTPM enable
CFG6 Interface
High = iTPM disable(Defult)
2
L32 L_BKLT_CTRL
G32 T37 PEGCOMP Management Low = TLS cipher suite with no confidentiality
L_BKLT_EN PEG_COMPI
D
M32 L_CTRL_CLK PEG_COMPO T36 CFG7 Engine Crypto D
High = TLS cipher suite with
M33 Strap
K33
L_CTRL_DATA
H44 PEG_MRX_GTX_N0
PEG_MRX_GTX_N[0..15] <51> confidentiality(Default)
L_DDC_CLK PEG_RX#_0 PEG_MRX_GTX_N1
J33 L_DDC_DATA PEG_RX#_1 J46 PCI Express Low = Reverse Lane
L44 PEG_MRX_GTX_N2 CFG9
PEG_RX#_2 PEG_MRX_GTX_N3 Graphic Lane
PEG_RX#_3 L40 High = Normal Operation(Default)
M29 N41 PEG_MRX_GTX_N4
L_VDD_EN PEG_RX#_4 PEG_MRX_GTX_N5
C44 LVDS_IBG PEG_RX#_5 P48
B43 N44 PEG_MRX_GTX_N6 FSB Dynamic Low=Dynamic ODT Disable
LVDS_VBG PEG_RX#_6 PEG_MRX_GTX_N7
E37 LVDS_VREFH PEG_RX#_7 T43 CFG16 ODT
E38 U43 PEG_MRX_GTX_N8 High=Dynamic ODT Enable(default)
LVDS_VREFL PEG_RX#_8
LVDS
C41 Y43 PEG_MRX_GTX_N9
LVDSA_CLK# PEG_RX#_9 PEG_MRX_GTX_N10
C40 LVDSA_CLK PEG_RX#_10 Y48 CFG19 DMI Lane Low=Normal (default)
B37 Y36 PEG_MRX_GTX_N11
LVDSB_CLK# PEG_RX#_11 PEG_MRX_GTX_N12 Reversal
A37 LVDSB_CLK PEG_RX#_12 AA43 High=Lane Reversed
AD37 PEG_MRX_GTX_N13
PEG_RX#_13 PEG_MRX_GTX_N14
H47 LVDSA_DATA#_0 PEG_RX#_14 AC47 Low=Only digital display port (SDVO/DP/iHDMI) or
E46 AD39 PEG_MRX_GTX_N15 Digital Display
LVDSA_DATA#_1 PEG_RX#_15 PEG_MRX_GTX_P[0..15] <51> PCIe is operational (default)
G40 LVDSA_DATA#_2 CFG20 Port
A40 H43 PEG_MRX_GTX_P0 High = Digital display port (SDVO/DP/iHDMI) and
GRAPHICS
LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1 J44 PEG_MRX_GTX_P1 Concurrent PCIe are operating simultaneously via the PEG
H48 L43 PEG_MRX_GTX_P2
LVDSA_DATA_0 PEG_RX_2 PEG_MRX_GTX_P3
Operation port
D45 LVDSA_DATA_1 PEG_RX_3 L41
F40 N40 PEG_MRX_GTX_P4
LVDSA_DATA_2 PEG_RX_4 PEG_MRX_GTX_P5
B40 LVDSA_DATA_3 PEG_RX_5 P47 SDVO_CRTL_DATA Low=No SDVO Device Present
N43 PEG_MRX_GTX_P6
A41
PEG_RX_6
T42 PEG_MRX_GTX_P7 (default)
LVDSB_DATA#_0 PEG_RX_7 PEG_MRX_GTX_P8
H38 LVDSB_DATA#_1 PEG_RX_8 U42 High=SDVO Device Present
G37 Y42 PEG_MRX_GTX_P9
LVDSB_DATA#_2 PEG_RX_9 PEG_MRX_GTX_P10
J37 LVDSB_DATA#_3 PEG_RX_10 W47 Low=DisplayPort disabled (default)
Y37 PEG_MRX_GTX_P11 DDPC_CTRLDATA
PEG_RX_11 PEG_MRX_GTX_P12
C
B42 LVDSB_DATA_0 PEG_RX_12 AA42 High=DisplayPort device present C
G38 AD36 PEG_MRX_GTX_P13
LVDSB_DATA_1 PEG_RX_13 PEG_MRX_GTX_P14
F37 LVDSB_DATA_2 PEG_RX_14 AC48
PCI-EXPRESS
K37 AD40 PEG_MRX_GTX_P15
LVDSB_DATA_3 PEG_RX_15 PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_C_N0 PEG_MTX_GRX_P[0..15] <51>
PEG_TX#_0 J41
M46 PEG_MTX_GRX_C_N1 PEG_MTX_GRX_N[0..15]
PEG_TX#_1 PEG_MTX_GRX_C_N2 PEG_MTX_GRX_N[0..15] <51>
F25 TVA_DAC PEG_TX#_2 M47
H25 M40 PEG_MTX_GRX_C_N3
TVB_DAC PEG_TX#_3 PEG_MTX_GRX_C_N4
K25 TVC_DAC PEG_TX#_4 M42
TV
R48 PEG_MTX_GRX_C_N5
PEG_TX#_5 PEG_MTX_GRX_C_N6 PEG_MTX_GRX_C_P0 C77 PEG_MTX_GRX_P0
H24 TV_RTN PEG_TX#_6 N38 2 1 0.1U_0402_10V7K~D
T40 PEG_MTX_GRX_C_N7 PEG_MTX_GRX_C_N0 C78 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N0
PEG_TX#_7 PEG_MTX_GRX_C_N8
PEG_TX#_8 U37
U40 PEG_MTX_GRX_C_N9 PEG_MTX_GRX_C_P1 C79 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P1
PEG_TX#_9 PEG_MTX_GRX_C_N10 PEG_MTX_GRX_C_N1 C80 2
C31 TV_DCONSEL_0 PEG_TX#_10 Y40 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N1
E32 AA46 PEG_MTX_GRX_C_N11
TV_DCONSEL_1 PEG_TX#_11 PEG_MTX_GRX_C_N12 PEG_MTX_GRX_C_P2 C81
PEG_TX#_12 AA37 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P2
AA40 PEG_MTX_GRX_C_N13 PEG_MTX_GRX_C_N2 C82 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N2
PEG_TX#_13 PEG_MTX_GRX_C_N14
PEG_TX#_14 AD43
AC46 PEG_MTX_GRX_C_N15 PEG_MTX_GRX_C_P3 C83 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P3
PEG_TX#_15 PEG_MTX_GRX_C_N3 C84 2 PEG_MTX_GRX_N3
1 0.1U_0402_10V7K~D
E28 J42 PEG_MTX_GRX_C_P0
CRT_BLUE PEG_TX_0 PEG_MTX_GRX_C_P1 PEG_MTX_GRX_C_P4 C85
PEG_TX_1 L46 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P4
<10> CFG5
@ R106 1 2 2.21K_0402_1%~D
G28 M48 PEG_MTX_GRX_C_P2 PEG_MTX_GRX_C_N4 C86 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N4
CRT_GREEN PEG_TX_2 PEG_MTX_GRX_C_P3 @ R107 1
PEG_TX_3 M39 <10> CFG6 2 2.21K_0402_1%~D
J28 M43 PEG_MTX_GRX_C_P4 PEG_MTX_GRX_C_P5 C87 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P5
CRT_RED PEG_TX_4
VGA
R47 PEG_MTX_GRX_C_P5 PEG_MTX_GRX_C_N5 C88 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N5 @ R108 1 2 2.21K_0402_1%~D

PEG_TX_5 <10> CFG7
G29 N37 PEG_MTX_GRX_C_P6
CRT_IRTN PEG_TX_6 PEG_MTX_GRX_C_P7 PEG_MTX_GRX_C_P6 C89 PEG_MTX_GRX_P6
PEG_TX_7 T39 2 1 0.1U_0402_10V7K~D <10> CFG9
@ R109 1 2 2.21K_0402_1%~D
H32 U36 PEG_MTX_GRX_C_P8 PEG_MTX_GRX_C_N6 C90 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N6
CRT_DDC_CLK PEG_TX_8 PEG_MTX_GRX_C_P9 @ R110 1
J32 CRT_DDC_DATA PEG_TX_9 U39 <10> CFG16 2 2.21K_0402_1%~D
J29 Y39 PEG_MTX_GRX_C_P10 PEG_MTX_GRX_C_P7 C91 2 1 0.1U_0402_10V7K~D PEG_MTX_GRX_P7
B CRT_HSYNC PEG_TX_10 PEG_MTX_GRX_C_P11 PEG_MTX_GRX_C_N7 C92 2 B
E29 CRT_TVO_IREF PEG_TX_11 Y46 1 0.1U_0402_10V7K~D PEG_MTX_GRX_N7
L29 AA36 PEG_MTX_GRX_C_P12 CFG[5:16] have internal pullup
CRT_VSYNC PEG_TX_12 PEG_MTX_GRX_C_P13 PEG_MTX_GRX_C_P8 C93
PEG_TX_13 AA39 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_P8
AD42 PEG_MTX_GRX_C_P14 PEG_MTX_GRX_C_N8 C94 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_N8
PEG_TX_14 PEG_MTX_GRX_C_P15
PEG_TX_15 AD46
PEG_MTX_GRX_C_P9 C95 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_P9
PEG_MTX_GRX_C_N9 C96 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_N9 +3.3V_RUN
CANTIGA ES_FCBGA1329~D
PEG_MTX_GRX_C_P10 C97 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_P10 @ R111 1 2 4.02K_0402_1%~D
<10> CFG19
PEG_MTX_GRX_C_N10 C98 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_N10
@ R112 1 2 4.02K_0402_1%~D
<10> CFG20
PEG_MTX_GRX_C_N11 C100 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_N11 @ R113 1 2 4.02K_0402_1%~D
<10> DDPC_CTRLDATA
PEG_MTX_GRX_C_N12 C102 1 2 0.1U_0402_10V7K~D PEG_MTX_GRX_N12 CFG[19:20] have internal pulldown


A A
401533
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
CRB 270uF U2H
U13 VTT_1
T13 +VCC_PEG
VTT_2
220U_D2_4VY_R15M~D
0.47U_0402_10V4Z~D
1 U12 VTT_3 VCCA_CRT_DAC_1 B27
1 T12 VTT_4 VCCA_CRT_DAC_2 A26 1 2 +1.05V_M
220U_D2_4VY_R15M~D
+ U11 R114
VTT_5
C109
C110
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
T11 0_1210_5%~D
VTT_6
U10 A25 1
CRT
2 2 VTT_7 VCCA_DAC_BG
T10 VTT_8 VSSA_DAC_BG B25 1 1 1 2 +1.05V_VCCP
U9 + @ R115
VTT_9
C111
C112
C113
T9 0_1210_5%~D
VTT_10
U8 VTT_11
D 2 2 2 Follow ERB,CRB option D
T8 VTT_12 VCCA_DPLLA F47
U7 to select +1.05V_M or
VTT
VTT_13 +1.05V_VCCP
T7 VTT_14 VCCA_DPLLB L48
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
2.2U_0603_10V7K~D
U6 VTT_15
1 1 1 T6 AD1
PLL
VTT_16 VCCA_HPLL +1.05V_M_HPLL
U5 VTT_17
C114
C115
C116
T5 VTT_18 VCCA_MPLL AE1 +1.05V_M_MPLL

V3 VTT_19
2 2 2
U3 VTT_20
V2 VTT_21 VCCA_LVDS J48
U2
A LVDS
VTT_22
T2 VTT_23 VSSA_LVDS J47
V1 VTT_24
U1 VTT_25
AD48 +VCCA_PEG_BG 1 2 +1.5V_RUN
VCCA_PEG_BG R778 1 2 0_0402_5%~D +3.3V_RUN
@R779
@ R779 0_0402_5%~D
1
A PEG
+1.05V_M L3 +1.05V_M_PEGPLL
AA48 +1.05V_M_PEGPLL C117 BLM21PG221SN1D_0805~D
VCCA_PEG_PLL 0.1U_0402_16V4Z~D +1.05V_M 1 2
2
0.1U_0402_16V4Z~D
100U_D2E_6.3VM_R15M~D
AR20 R116 C118
VCCA_SM_1 +1.05V_M_A_SM 1 10U_0805_4VAM~D
VCCA_SM_2 AP20 2 1
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
AN20 2 1
POWER VCCA_SM_3
C119
AR17 0_0805_5%~D 1 R117 1_0402_5%~D
VCCA_SM_4
VCCA_SM_5 AP17 1 1 1 1 2
@ C124
AN17 +
VCCA_SM_6
C121
C122
C123
C120
VCCA_SM_7 AT16
AR16
A SM
+1.05V_M VCCA_SM_8 2 2 2 2 2
VCCA_SM_9 AP16
C C
2 1 +VCC_AXF
+1.05V_M_SM_CK
10U_0805_4VAM~D
1U_0603_10V4Z~D
R118 +1.05V_M
0_1210_5%~D 1 1
@ C125
VCCA_SM_CK_1 AP28 1 2
C126
0.1U_0402_16V4Z~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
B22 AN28 R119 0_1210_5%~D
VCC_AXF_1 VCCA_SM_CK_2
B21 AP25
AXF
2 2 VCC_AXF_2 VCCA_SM_CK_3
A21 VCC_AXF_3 VCCA_SM_CK_4 AN25 1 1 1
@C129
@
VCCA_SM_CK_5 AN24
C127
C128
C129
VCCA_SM_CK_NCTF_1 AM28
AM26
A CK
+1.8V_SM_CK VCCA_SM_CK_NCTF_2 2 2 2
VCCA_SM_CK_NCTF_3 AM25
BF21 VCC_SM_CK_1 VCCA_SM_CK_NCTF_4 AL25
BH20 AM24 +1.05V_M_HPLL +1.05V_M +1.05V_M_MPLL +1.05V_M
SM CK
VCC_SM_CK_2 VCCA_SM_CK_NCTF_5 L4
BG20 VCC_SM_CK_3 VCCA_SM_CK_NCTF_6 AL24
BF20 VCC_SM_CK_4 VCCA_SM_CK_NCTF_7 AM23 24mA Max. 2 1 139.2mA Max. 2 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AL23 BLM18AG121SN1D_0603~D L5
VCCA_SM_CK_NCTF_8
2
4.7U_0603_6.3V6M~D
LQH32CNR15M33L_1210~D
1 1 1 R120
+3.3V_RUN K47 0_0603_5%~D
VCC_TX_LVDS
C130
C131
C132
VCCA_TV_DAC_1 B24
C35 A24
1
VCC_HV_1 VCCA_TV_DAC_2 2 2 2
TV
B35 VCC_HV_2 1
+1.5V_RUN
0.1U_0402_16V4Z~D
A35
HV
VCC_HV_3 C133
1
C136
A32 22U_0805_6.3VAM~D
VCC_HDA 2
HDA
+VCC_PEG V48 VCC_PEG_1 1

U48 VCC_PEG_2
2 C998
V47
PEG
VCC_PEG_3
U47 VCC_PEG_4 0.1U_0402_16V4Z~D
+VCC_DMI 2
D TV/CRT
B B
U46 VCC_PEG_5 VCCD_TVDAC M25
+1.5V_RUN
0.1U_0402_16V4Z~D
VCCD_QDAC L28
AH48 VCC_DMI_1
1 AF48 VCC_DMI_2 VCCD_HPLL AF1
AH47
DMI
VCC_DMI_3
C137
0.1U_0402_16V4Z~D
AG47 VCC_DMI_4 VCCD_PEG_PLL AA47
+1.05V_M
2
0.01U_0402_25V7K~D
2 1
VCCD_LVDS_1 M38
0.1U_0402_16V4Z~D
C138
C139
LVDS
GMCH_VTTLF1 A8 L37
GMCH_VTTLF2 L1 VTTLF1 VCCD_LVDS_2 +1.05V_M_PEGPLL +VCC_DMI
VTTLF2 1 2
VTTLF
GMCH_VTTLF3AB2 1
VTTLF3
0.1U_0402_16V4Z~D
2 1 +VCC_PEG
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C140
1 PJP21
1 1 1 PAD-OPEN1x1m
2
C142
C143
C144
C141
CANTIGA ES_FCBGA1329~D 2 1 +1.05V_M

1 @ L6
2 LBC2518T91NM_1210~D
2 2 2 +
@ C145
220U_D2_4VY_R15M~D
2
+1.8V_MEM +1.8V_SM_CK
2 1
0.1U_0402_16V4Z~D
A L7 A
1_0603_5%~D
LQM21FN1R0N00 _0805~D
1
Rdc=0.1~0.2,rated 1
R121
current=220mA(MAX)
C146
+1.05V_VCCP +3.3V_RUN
C147
2
10U_0805_4VAM~D 2 1 +1.05V_VCCP/+3.3V_RUN 1 2
2
D1
2 1
RB751V_SOD323-2~D R122 Compal Electronics, Inc.
10_0603_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Follow CRB to BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
VCC_HV(C35,B35,A35) NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
401533
5 4 3 2 1
5 4 3 2 1
U2G
+1.8V_MEM
AP33 VCC_SM_1 VCC_AXG_NCTF_1 W28
330U_D2_2.5VY_R15M
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28
+1.05V_M
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
U2F BH32 W26
VCC_SM_3 VCC_AXG_NCTF_3
1 BG32 VCC_SM_4 VCC_AXG_NCTF_4 V26
2 1 1 BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25
C148
D + BD32 V25 D
C149
C150
C151
AG34 VCC_1 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24
AC34 VCC_2 BB32 VCC_SM_8 VCC_AXG_NCTF_8 V24
1 2 2 2
AB34 VCC_3 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AA34 VCC_4 AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23
Y34 VCC_5 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
V34 VCC_6 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
CRB 270uF U34 VCC_7 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
AM33 VCC_8 Layout Note: AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AK33 VCC_9 Layout Note: Place on the edge AR32 VCC_SM_15 VCC_AXG_NCTF_15 V21
220U_D2_4VY_R15M~D
22U_0805_6.3VAM~D
0.22U_0402_10V4Z~D
POWER
AJ33 VCC_10 Place close to GMCH AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
1 AG33 VCC_11 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
1 1 AF33 VCC_12 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
C152
C153
+ BG31 W20
C154
AE33 VCC_13 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
VCC CORE
AC33 VCC_14 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19
2 2 2
AA33 VCC_15 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
Y33 VCC_16 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
W33 VCC_17 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
V33 VCC_18 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19
VCC SM
U33 VCC_19 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
AH28 VCC_20 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
AF28 VCC_21 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
Layout Note: AC28 VCC_22 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
Place close to GMCH AA28 VCC_23 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AJ26 VCC_24 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AG26 VCC_25 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AE26 VCC_26 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AC26 VCC_27 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
AH25 VCC_28 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17

AG25 VCC_29 VCC_AXG_NCTF_36 AK17
1 1 AF25 VCC_30 BA36 VCC_SM_36/NC VCC_AXG_NCTF_37 AH17
+1.05V_M
C155
C156
C C
AG24 VCC_31 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AJ23 VCC_32 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
AH23 VCC_33 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
2 2
POWER
AF23 VCC_34 AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17
VCC_NCTF_1 AM32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
T32 VCC_35 VCC_NCTF_2 AL32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17
VCC_NCTF_3 AK32 VCC_AXG_NCTF_44 W17
AJ32 V17
VCC GFX NCTF

VCC_NCTF_4 VCC_AXG_NCTF_45
VCC_NCTF_5 AH32 VCC_AXG_NCTF_46 AM16
Layout Note: 1 2 VCC_NCTF_6 AG32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
Inside GMCH cavity.R123
0_0402_5%~D VCC_NCTF_7 AE32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_8 AC32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_9 AA32 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
VCC_NCTF_10 Y32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
VCC_NCTF_11 W32 AC24 VCC_AXG_6 VCC_AXG_NCTF_52 AF16
VCC_NCTF_12 U32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_13 AM30 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_14 AL30 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
VCC_NCTF_15 AK30 AC23 VCC_AXG_10 VCC_AXG_NCTF_56 AA16
VCC_NCTF_16 AH30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
VCC_NCTF_17 AG30 AA23 VCC_AXG_12 VCC_AXG_NCTF_58 W16
VCC_NCTF_18 AF30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_19 AE30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
VCC_NCTF_20 AC30 AE21 VCC_AXG_15
VCC_NCTF_21 AB30 AC21 VCC_AXG_16
VCC_NCTF_22 AA30 AA21 VCC_AXG_17
VCC_NCTF_23 Y30 Y21 VCC_AXG_18
VCC_NCTF_24 W30 AH20 VCC_AXG_19
VCC NCTF
VCC_NCTF_25 V30 AF20 VCC_AXG_20

VCC_NCTF_26 U30 AE20 VCC_AXG_21
VCC_NCTF_27 AL29 AC20 VCC_AXG_22
VCC_NCTF_28 AK29 AB20 VCC_AXG_23
B B
VCC_NCTF_29 AJ29 AA20 VCC_AXG_24
VCC_NCTF_30 AH29 T17 VCC_AXG_25
VCC_NCTF_31 AG29 T16 VCC_AXG_26
VCC_NCTF_32 AE29 AM15 VCC_AXG_27
VCC_NCTF_33 AC29 AL15 VCC_AXG_28
VCC_NCTF_34 AA29 AE15 VCC_AXG_29
VCC_NCTF_35 Y29 AJ15 VCC_AXG_30
VCC_NCTF_36 W29 AH15 VCC_AXG_31
VCC_NCTF_37 V29 AG15 VCC_AXG_32
VCC_NCTF_38 AL28 AF15 VCC_AXG_33
VCC_NCTF_39 AK28 AB15 VCC_AXG_34
VCC_NCTF_40 AL26 AA15 VCC_AXG_35
VCC GFX
VCC_NCTF_41 AK26 Y15 VCC_AXG_36
VCC_NCTF_42 AK25 V15 VCC_AXG_37
VCC_NCTF_43 AK24 U15 VCC_AXG_38
VCC_NCTF_44 AK23 AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC_AXG_41 VCC_SM_LF1
VCC SM LF
T14 BA37 VCCSM_LF2
VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
VCC_SM_LF3 AM40
AV21 VCCSM_LF4
VCC_SM_LF4 VCCSM_LF5
VCC_SM_LF5 AY5
CANTIGA ES_FCBGA1329~D AM10 VCCSM_LF6
VCC_SM_LF6 VCCSM_LF7
VCC_SM_LF7 BB13
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.47U_0402_10V4Z~D
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
PAD~D T37 VCC_AXG_SENSE AJ14 1 1 1 1 1 1 1
VCC_AXG_SENSE
C157
C158
C159
C160
C161
C162
C163
PAD~D T38 VSS_AXG_SENSE AH14 VSS_AXG_SENSE
2 2 2 2 2 2 2
A A
401533
5 4 3 2 1
5 4 3 2 1
U2I
U2J
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8
AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
D D
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 H33 AT17 BC3
U44
T44
VSS_31
VSS_32
VSS_130
VSS_131 N32
K32
R17
M17
VSS_229
VSS_230 VSS VSS_327
VSS_328 AV3
AL3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
H17
C17
VSS_231
VSS_232
VSS_233
VSS_329
VSS_330
VSS_331
R3
P3
BC43 VSS_36 VSS_135 A31 VSS_332 F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
C C
BG42 VSS_42 VSS_141 F29 K16 VSS_240 VSS_338 AJ2
AY42 VSS_43 VSS_142 A29 G16 VSS_241 VSS_339 AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_1 AF32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_2 AB32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_3 V32
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_4 AJ30
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_5 AM29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_6 AF29
AT39 BD25 AA12 AB29
VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_7
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_8 U26
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_9 U23
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_10 AL20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_11 V20
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_12 AC19
B B
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_13 AL17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_14 AJ17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_15 AA17
BA38 VSS_77 VSS_176 J25 Y11 VSS_275 VSS_NCTF_16 U17
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277
AD38 BF24 C11 BH48
VSS SCB
VSS_80 VSS_179 VSS_278 VSS_SCB_1

AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_2 BH1
Y38 VSS_82 VSS_181 AY24 AV10 VSS_280 VSS_SCB_3 A48
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_4 C1
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282 VSS_SCB_5 A3
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284 NC_26 E1
C38 VSS_87 VSS_186 AB24 M10 VSS_285 NC_27 D2
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_28 C3
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_29 B4
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_30 A5
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_31 A6
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_32 A43
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_33 A44
H37 E24 B9 B45
NC
VSS_94 VSS_193 VSS_292 NC_34

C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_35 C46
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_36 D47
BD36 VSS_97 VSS_196 Y23 AV8 VSS_295 NC_37 B47
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_38 A46
AU36 VSS_99 VSS_198 A23 NC_39 F48
VSS_199 AJ6 NC_40 E48
NC_41 C48
NC_42 B48
A A
401533
5 4 3 2 1
5 4 3 2 1
+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

<11> DDR_A_DQS#[0..7]
+V_DDR_MCH_REF
<11> DDR_A_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIMMA
<11> DDR_A_DM[0..7] 1 VREF VSS 2
3 4 DDR_A_D4 1 1
DDR_A_D0 VSS DQ4 DDR_A_D5
<11> DDR_A_DQS[0..7] Layout Note: 5 DQ0 DQ5 6
C164
C165
DDR_A_D1 7 8
Place near JDIMMA 9
DQ1 VSS
10 DDR_A_DM0
<11> DDR_A_MA[0..14] VSS DM0 2 2
DDR_A_DQS#0 11 12
DDR_A_DQS0 DQS0# VSS DDR_A_D6
13 DQS0 DQ6 14
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D3 DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
+1.8V_MEM DDR_A_D9 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 <10>
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 <10>
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
33 VSS VSS 34
1 1 1 1 1 DDR_A_D10 35 36 DDR_A_D14
DQ10 DQ14
C166
C167
C168
C169
C170
DDR_A_D11 37 38 DDR_A_D15
DQ11 DQ15
39 VSS VSS 40
2 2 2 2 2
41 VSS VSS 42
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_A_DQS#2 49 50
DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
53 VSS VSS 54
1 1 1 1 DDR_A_D18 55 56 DDR_A_D22
DQ18 DQ22
C171
C172
C173
C174
DQ19 DQ23
59 VSS VSS 60
2 2 2 2 DDR_A_D25 DQ24 DQ28 DDR_A_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<10> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <10>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86 DDR_A_MA14
<11> DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: 91 A9 A7 92
Place one cap close to every 2 pullup 95
A8 A6
96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V_DDR_VTT 97 A5 A4 98
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 <11>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<11> DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# <11>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
<11> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <10>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<11> DDR_A_CAS# CAS# ODT0 M_ODT0 <10>
+0.9V_DDR_VTT DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<10> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
<10> M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
125 DQ33 DQ37 126
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
127 VSS VSS 128

DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
2 2 2 2 2 2 2 2 2 2 2 2 2 2 DQ35 VSS DDR_A_D44
139 VSS DQ44 140
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
DDR_A_D40 141 142 DDR_A_D45

B DDR_A_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 <10>
+0.9V_DDR_VTT 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <10>
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
RN1 RN2 169 170
DDR_A_MA3 DQS6 DM6
1 4 4 1 DDR_A_MA12 171 VSS VSS 172
DDR_A_MA1 2 3 3 2 DDR_A_MA8 DDR_A_D50 173 174 DDR_A_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
RN3 RN4 Layout Note: 177 VSS VSS 178
DDR_A_BS0 1 4 4 1 DDR_A_MA6 Place these resistor DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA10 DQ56 DQ60
2 3 3 2 DDR_A_MA7 closely JDIMMA,all DDR_A_D57 181 DQ57 DQ61 182 DDR_A_D61
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 183 184
RN5 RN6 trace length<750 mil DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_CS0_DIMMA# 1 4 4 1 DDR_A_MA5 187 188 DDR_A_DQS7
DDR_A_RAS# VSS DQS7
2 3 3 2 DDR_A_MA9 DDR_A_D58 189 DQ58 VSS 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D59 191 192 DDR_A_D62
RN8 DQ59 DQ62 DDR_A_D63
RN7 193 194
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA2 <17,24> MEM_SDATA
MEM_SDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_MA4 MEM_SCLK 197 198 R128 1 2 10K_0402_5%~D
<17,24> MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_M 199 200 R129 1 2 10K_0402_5%~D
RN10 VDDSPD SA1
RN9 201 202
G1 G2
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_CS1_DIMMA# 1 4 4 1 DDR_A_BS1
M_ODT1 2 3 3 2 DDR_A_MA0 1 1
C189
C190
A 56_0404_4P2R_5%~D 56_0404_4P2R_5%~D FOX_AS0A426-N4RN-7F~D A

RN11
DDR_CKE1_DIMMA 2 1 4 1 DDR_A_MA13
2 2
DIMMA
R130 3 2 M_ODT0
56_0402_5%~D 56_0404_4P2R_5%~D REVERSE
RN13
RN12 Layout Note:
DDR_CKE0_DIMMA 2 1 DDR_A_MA11
DDR_A_BS2 1
3
4
4
3 2 DDR_A_MA14
Place these resistor
closely JDIMMA,all
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
401533
5 4 3 2 1
5 4 3 2 1
+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

<11> DDR_B_DQS#[0..7]
+V_DDR_MCH_REF
<11> DDR_B_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
Layout Note: JDIMMB
<11> DDR_B_DM[0..7] 1 2
Place near JDIMMB 3
VREF VSS
4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D5
<11> DDR_B_DQS[0..7] 5 DQ0 DQ5 6
C191
C192
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
<11> DDR_B_MA[0..14] 9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
D +1.8V_MEM 21 22 DDR_B_D13 D
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 <10>
1 1 1 1 1 DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 <10>
C193
C194
C195
C196
C197
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
2 2 2 2 2
39 VSS VSS 40
41 VSS VSS 42
45 DQ17 DQ21 46
47 VSS VSS 48
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2
1 1 1 1 51 DQS2 DM2 52
C198
C199
C200
C201
53 VSS VSS 54
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
C <10> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <10> C
81 VDD VDD 82
83 NC NC/A15 84
Layout Note: DDR_B_BS2 85 86 DDR_B_MA14
<11> DDR_B_BS2 BA2 NC/A14
87 88
Place one cap close to every 2 pullup DDR_B_MA12 89
VDD VDD
90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
resistors terminated to +0.9V_DDR_VTT 91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 DDR_B_BS1 <11>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<11> DDR_B_BS0 107 BA0 RAS# 108 DDR_B_RAS# <11>
+0.9V_DDR_VTT DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<11> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <10>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<11> DDR_B_CAS# CAS# ODT0 M_ODT2 <10>
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
<10> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M_ODT3 119 120

<10> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D32 123 124 DDR_B_D36
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C212
C213
C214
133 134 DDR_B_D38

DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
B DDR_B_DQS#5 B
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 <10>
+0.9V_DDR_VTT 165 166 M_CLK_DDR#3
VSS CK1# M_CLK_DDR#3 <10>
DDR_B_DQS#6 167 168
RN15 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
RN14 169 170
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
1 4 4 1 171 VSS VSS 172
DDR_B_MA1 2 3 3 2 DDR_B_BS2 DDR_B_D50 173 174 DDR_B_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
RN16 RN17 177 178
DDR_B_BS0 DDR_B_MA14 DDR_B_D56 VSS VSS DDR_B_D60
1 4 4 1 179 DQ56 DQ60 180
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_D57 181 182 DDR_B_D61
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DQ57 DQ61
Layout Note: 183 VSS VSS 184
RN18 RN19 Place these resistor DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA5 DM7 DQS7# DDR_B_DQS7
1 4 4 1 closely JDIMMB,all 187 VSS DQS7 188
DDR_B_BS1 2 3 3 2 DDR_B_MA8 DDR_B_D58 189 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D trace length<750 mil DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
RN20 RN21 193 194 DDR_B_D63 +3.3V_M
DDR_B_RAS# DDR_B_MA7 MEM_SDATA VSS DQ63
1 4 4 1 <16,24> MEM_SDATA 195 SDA VSS 196
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 MEM_SCLK 197 198
<16,24> MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_M 199 200 2 1
VDDSPD SA1
10K_0402_5%~D
RN22 RN23 201 202
GND GND
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_B_WE# 1 4 4 1 DDR_B_MA4 R131
1
DDR_B_CAS# 2 3 3 2 DDR_B_MA2 FOX_AS0A426-N8RN-7F_RV 10K_0402_5%~D
R132
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 1 1
C215
C216
A RN24 A
DDR_CKE3_DIMMB 2 1 4 1 M_ODT2 DIMMB
R133 3 2 DDR_B_MA13
REVERSE
2
56_0402_5%~D 56_0404_4P2R_5%~D 2 2
RN26
RN25 Layout Note:
DDR_CS3_DIMMB# 2 DDR_B_MA9
M_ODT3 1
3
4
4
3
1
2 DDR_CKE2_DIMMB
Place these resistor
closely JDIMMB,all
56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
56_0404_4P2R_5%~D trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
401533
5 4 3 2 1
5 4 3 2 1
+3.3V_M
Discrete
1
R134
8.2K_0402_5%~D +3.3V_M VGA_THERMDP VGA_THERMDP <51>
2
+1.05V_VCCP THERMATRIP1#
1
R135 C217
1
2.2K_0402_5%~D C 1 470P_0402_50V7K~D
D R136 VGA_THERMDN 2 D
1 2 2 VGA_THERMDN <51>
B C218 10K_0402_5%~D
Q5 E 0.1U_0402_16V4Z~D Place Capacitor close to Guardian Chip
2
MMST3904-7-F_SOT323-3~D 2 JFAN1
<7> H_THERMTRIP# <22> FAN1_DET# 1 1
+FAN1_VOUT 2
FAN1_TACH_FB 2
3 3 G1 5
+3.3V_M
22U_0805_6.3VAM~D
4 6 PWR_MON_GFX T186PAD~D
4 G2
1
1
C219
D2 MOLEX_53398-0471~D
1
RB751S40T1_SOD523-2~D PWR_MON <47>
R137
8.2K_0402_5%~D 2 ISL88731_ICM_R 1 2 ISL88731_ICM <48>Diode circuit at DP4/DN4 is used for skin
2
R992
0_0402_5%~D temp sensor (placed optimally between CPU,
2
1
+1.05V_VCCP THERMATRIP2# Place C221 close to the MCH and MEM).
R138 @ R1005 Guardian pins as possible.
1
MMST3904-7-F_SOT323-3~D
MMST3904-7-F_SOT323-3~D
2.2K_0402_5%~D C 1
1 2 2 <38> BC_DAT_EMC4002 4.7K_0402_5%~D
3
E
B C220 1 C 1
Q7
0.1U_0402_16V4Z~D
B
Q6 E 2 2
3
Q9
MMST3904-7-F_SOT323-3~D 2 C221 B @C222
@C222
C
E 100P_0402_50V8K~D
<10> THERMTRIP_MCH# <38> BC_CLK_EMC4002
1
2 2200P_0402_50V7K~D 2
Place under CPU Place C222 close to Q7 as
possible.
1
2 C 2
@C223
@ C223 2 C224 THERMISTOR OPTION:
100P_0402_50V8K~D B 2200P_0402_50V7K~D
E Q8 Single-ended routing to thermistor is permissible
3
1 MMST3904-7-F_SOT323-3~D 1 U3 (ground return). Place R139 and C226 near EMC4002

C Place C223 close to the Q8 as possible EMC4002 C
Place C224,C225 close to the Guardian pins as possible 10 SMDATA/BC-LINK_DATA 1 2 1 2

<7> H_THERMDA 11 39 R139
SMBCLK/BC-LINK_CLK VIN1 1.2K_0402_1%~D R140
1 VCP1 48
45 10KB_0603_1%_TSM1A103F34D3R~D
C225 VCP2
Place C225 close to U3
470P_0402_50V7K~D REM_DIODE1_P 36 44 REM_DIODE4_P
2 REM_DIODE1_N DP1/VREF_T DP4/DN8 REM_DIODE4_N
<7> H_THERMDC 35 DN1/THERM DN4/DP8 43
<7> H_THERMDA1 38 47 VGA_THERMDP 1 2

DP2 DP5/DN9 VGA_THERMDN
37 DN2 DN5/DP9 46
1 C226
41 1 0.1U_0402_16V4Z~D
C228 DP3/DN7 DP6/VREF_T2
40 DN3/DP7 DN6/VIN2 2
Place C228 close to U3 470P_0402_50V7K~D
2
<7> H_THERMDC1 2 1 +3.3V_M
+3.3V_M 1 2 +3VSUS_THRM 4 R141 10K_0402_5%~D
R142 VCC
ATF_INT#/BC-LINK_IRQ# 12 BC_INT#_EMC4002 <38> 2 1 DOCK_PWR_SW# <38>
22_0603_1%~D 1 +RTC_CELL 21 26 R143 2 1 0_0402_5%~D POWER_SW_IN# <38>
RTC_PWR3V POWER_SW#
1U_0603_10V4Z~D
1 27 ACAV_IN_MB/DOCK <38> R144 0_0402_5%~D

ACAVAIL_CLR
C230
C229 20 2 1 +3.3V_M
0.1U_0402_16V4Z~D THERMTRIP_SIO/PWM1/GPIO5 R145 10K_0402_5%~D
SYS_SHDN# 25 THERM_STP# <44>
2
<38,41> 3.3V_M_PWRGD 1 2 18 VCC_PWRGD 1 2 +RTC_CELL
2 R146 1
<41> ICH_PWRGD# 2 1K_0402_5%~D 17 3V_PWROK#
@R147
@ R147 47K_0402_1%~D
R148 1K_0402_5%~D
THERMATRIP1# 22
THERMATRIP2# THERMTRIP1# R149
23 THERMTRIP2# At maximum load current of 600mA,the the
THERMATRIP3# 24 19 2 1 +3.3V_SUS
THERMTRIP3# LDO_SHDN# 10K_0402_5%~D voltage drop across the should be keep
VSET 42 VSET LDO_POK 34 2.5V_RUN_PWRGD <37,41> in the range of 0.5V to 1V
B B
1
1 +3VSUS_THRM 2 1 3 33 LDO_SET
R151 +5V_RUN R150 4.7K_0402_5%~D ADDR_MODE/XEN LDO_SET
C231 953_0402_1%~D +3.3V_RUN
0.1U_0402_16V4Z~D 6 32 +3V_LDOIN 2 1
2 VDD_5V VDDH/VDD_5V2
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
5 31 R152
2
+3.3V_RUN VDD_5V VDDH/VDD_5V2 0_1210_5%~D

1 1
9 28 +2.5V_RUN +2.5V_RUN
1 1 VDD_3V VDDL/VDD_3V2
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
C232
C233
C234
C235
Rset=953,Tp=88degree 1 1 +FAN1_VOUT 7 29
FAN_OUT LDO_OUT/FAN_OUT2 2 2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
8 FAN_OUT LDO_OUT/FAN_OUT2 30
1
2 2
C236
C237
0_0402_5%~D
1 1 @
R153
FAN1_TACH_FB 15 16
2 2 TACH1/GPIO3 TACH2/GPIO4
C238
C239
14 CLK_IN/GPIO2 PWM2/GPIO1 13 Ra
2 2
2
VSS
<38> EC_32KHZ_OUT EC_32KHZ_OUT 49 LDO_SET
1K_0402_1%~D
1
R154
+3.3V_M 2 1
+3.3V_RUN R985 0_0402_5%~D
PM_EXTTS# <10> Rb
2
1
Pull-up Resistor For Remote1 SMBUS

8.2K_0402_5%~D
2.2K_0402_5%~D
R155 Voltage margining circuit

on ADDR_MODE/XEN mode Address
1
8.2K_0402_5%~D
for LDO output. Adjustable
R156
R157
* <= 4.7K +/- 5% 2N3904 2F(r/w) from 1.2 to 2.5V.

2
A THERMATRIP3# 10K 2N3904 2E(r/w) Ra=((LDO_OUT/1.2)-1)*Rb. A

2
C 1 18K Thermistor 2F(r/w)

THERM_B3 2 Q11
B MMST3904-7-F_SOT323-3~D C240 >= 33K Thermistor 2E(r/w)
E 0.1U_0402_16V4Z~D DELL CONFIDENTIAL/PROPRIETARY
3
2
<51> THERMTRIP_VGA# Compal Electronics, Inc.
401533
5 4 3 2 1
5 4 3 2 1
JLVDS1
LCD Power
59 MGND1 Even_ClkIN+ 58 LCD_BCLK+_GPU <51>
60 57 +15V_ALW +LCDVDD +3.3V_RUN
D
MGND2 Even_ClkIN- LCD_BCLK-_GPU <51>
S
61 MGND3 VSS 56 6
62 55 +LCDVDD +15V_ALW 4 5
MGND4 Even_Rin2+ LCD_B2+_GPU <51>
1
63 MGND5 Even_Rin2- 54 LCD_B2-_GPU <51> 2
+3.3V_RUN
470_0402_5%~D
64 MGND6 VSS 53 1
100K_0402_5%~D
R158 Q12
G
65 MGND7 Even_Rin1+ 52 LCD_B1+_GPU <51> 1
1
R161
66 51 1 2 LDDC_CLK_GPU 100K_0402_5%~D SI3456DV-T1-E3_TSOP6~D
LCD_B1-_GPU <51>
3
MGND8 Even_Rin1-
R162
67 50 R159 2.2K_0402_5%~D C241
2
MGND9 VSS LDDC_DATA_GPU 0.1U_0402_16V4Z~D
68 MGND10 Even_Rin0+ 49 LCD_B0+_GPU <51> 1 2
2
2N7002DW-T/R7_SOT363-6~D
69 48 R160 2.2K_0402_5%~D
LCD_B0-_GPU <51>
6 2
MGND11 Even_Rin0-
100K_0402_5%~D
70 47
2
MGND12 VSS
@R163
@
0.1U_0603_25V7K~D
D D
Odd_ClkIN+ 46 LCD_ACLK+_GPU <51> Place near to JLVDS1 1
R163
Odd_ClkIN- 45 LCD_ACLK-_GPU <51>
Q13B
C242
44 Q13A
VSS 2N7002DW-T/R7_SOT363-6~D
Odd_Rin2+ 43 LCD_A2+_GPU <51> 2 5
2
42 LCD_A2-_GPU <51>
2
Odd_Rin2-
1
41 D3
4
VSS
40
O
Odd_Rin1+ LCD_A1+_GPU <51>
Odd_Rin1- 39 LCD_A1-_GPU <51> <37> LCD_VCC_TEST_EN 3
VSS 38
Odd_Rin0+ 37 LCD_A0+_GPU <51> 1 2 I
Odd_Rin0- 36 LCD_A0-_GPU <51>
35 2 Q15
VSS <51> ENVDD_GPU
G
34 LDDC_DATA_GPU DDTC124EUA-7-F_SOT323-3~D
DATA EEDID LDDC_CLK_GPU LDDC_DATA_GPU <51> BAT54CW_SOT323~D
33 LDDC_CLK_GPU <51>
3
CLK EEDID LVDS_CBL_DET#
VSS 32 LVDS_CBL_DET# <22> 1 2
31 +3.3V_RUN @ R164 0_0402_5%~D
VEEDID CAM_MIC_CBL_DET#
Diag_Loop_CAM 30 CAM_MIC_CBL_DET# <22>
29 DMIC_CLK
MIC_CLK DMIC_CLK <27>
3.3V 28 +3.3V_RUN
27 DMIC0
MIC_SIG DMIC0 <27>
26 +CMOS_VDD
5V USBP11_D-
USB- 25
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
24 USBP11_D+
USB+
1
GND 23
CONNTST 22
D47
D56
D48
21 LCD_SMBCLK
SMB_CLK LCD_SMBCLK <38> +3.3V_RUN
20 LCD_SMBDAT
SMB_DATA LCD_SMBDAT <38>
19 +INV_PWR_SRC @ @ @
2
INV_SRC
INV_SRC 18
INV_SRC 17 1 2
1
16 C246
INV_SRC 0.1U_0603_50V4Z~D R165
VBL- 15
C 10K_0402_5%~D C
VBL- 14
VBL- 13
12
2
VBL-
INV_PWM 11 1 2 BIA_PWM_GPU <51>
10 @ R166 0_0402_5%~D
+5V_ALW +5V_ALW
9 LCD_TST 1
TEST LCD_TST <37>
VDD 8 +LCDVDD
7 C245
VDD 0.1U_0402_16V4Z~D
VDD 6
2
CONNTST 5 PNL_BKLT_CBL_DET# <22>
4 BREATH_BLUE_LED_LCD @Q16
@ Q16
PWR_LED
3 BATT_YELLOW_LED_LCD
BREATH_BLUE_LED_LCD <42> Dual layout for Q17 +PWR_SRC FDS4435_NL_SO8~D
BATT2_LED
2 BATT_BLUE_LED_LCD
BATT_YELLOW_LED_LCD <42>
Overlap on Q16 for pop option 40mil
BATT1_LED
VSS 1
BATT_BLUE_LED_LCD <42> +3.3V_RUN +LCDVDD 40mil 8 +INV_PWR_SRC
1 7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 6
1000P_0402_50V7K~D
JAE_FI-DP58SB-VF100 3 5
1 1 1
1
C243 1
C244
+PWR_SRC R167 C247
4
C248
Q17 100K_0402_5%~D 0.1U_0603_50V4Z~D
2 2 SI3457DV-T1_TSOP6~D 2
2
2
D
PMV45EN_SOT23-3~D 6 +INV_PWR_SRC
S
+CMOS_VDD PWR_SRC_ON
Q132 Close to JLVD1.28 Close to JLVD1.6,7,8 4 5
2
1
S
3 1 +CMOS_VDD_R 2 @ 1 Q18
G
+3.3V_RUN
R170 2N7002W-7-F_SOT323-3~D
3
0.1U_0402_16V4Z~D
10U_1206_16V4Z~D
0_0603_5%~D
S
1 2 1 3
R168 100K_0402_5%~D
G
1 1
2
C249
C250
B B
2 1
G
+5V_RUN
2
R169 PWR_SRC_ON
2 2 0_0603_5%~D
0.1U_0402_16V4Z~D
@ U50
<28,37,40,41,50> RUN_ON
1 1 3 USBP11_D- SI3457DV : P CHANNAL FDS4435: P CHANNAL
GND IO2
C1026
USBP11_D+ 2 4 +CMOS_VDD
IO1 VIN
2 PRTR5V0U2X_SOT143-4~D
+15V_ALW
100K_0402_5%~D
1
R994
Webcam PWR CTRL

2
@ L59
2N7002W-7-F_SOT323-3~D
DLW21SN121SQ2L_4P~D
1
D
4700P_0402_25V7K~D
USBP11- 1 USBP11_D-
<24> USBP11- 1 2 2
Q133
<37> CCD_OFF 2 1
C1027
G
S USBP11+ 4 3 USBP11_D+
<24> USBP11+
3
4 3
2
1 2
R457 0_0402_5%~D
1 2
R513 0_0402_5%~D
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC, MB A4042
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A
5 4 3 2 1
2 1
+5V_RUN
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
1
SDM10U45-7_SOD523-2~D
@ @ @
2
D5
D6
D7
+3.3V_RUN
D8
2
+5V_RUN_CRT 1
RED_CRT 1 2 RED_CRT_L 1 2
L8 L61
BLM18BB470SN1D_0603~D BLM18BB470SN1D_0603~D
GREEN_CRT 1 2 GREEN_CRT_L 1 2 +CRT_VCC
L9 L62
5A_125V_R451005.MRL~D
0.01U_0402_16V7K~D
BLUE_CRT 1 2 BLUE_CRT_L 1 2
2
0_1206_5%~D
L10 L63 1
2
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
@F2
@
R171
C254
1 1 1 1 1 1
F2
1 1 1 2
C255
C256
C257
C390
C518
C996
R172
R173
R174
1
C251
C252
C253
1
2 2 2 2 2 2
2
2 2 2 JCRT1
6
11
R 1
+3.3V_RUN +5V_RUN_SYNC 7
12
B U4 G B
2
4 VCC 8 16
2.2K_0402_5%~D
2.2K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
10 JVGA_HS 13 17
VCC
1
18 48 DAT_DDC2_CRT B 3
VCC 0B1
R794
R793
@R175
@
@R176
@
27 47 CLK_DDC2_CRT +CRT_VCC 9
VCC 1B1
R175
R176
38 43 VSYNC_BUF JVGA_VS 14
VCC 2B1 HSYNC_BUF M_ID2#
50
56
VCC 3B1 42
37 RED_CRT
To MB CRT Conn. 4
10
2
VCC 4B1 GREEN_CRT
5B1 36 15
GPU_DAT_DDC 2 32 BLUE_CRT 5
<51> GPU_DAT_DDC GPU_CLK_DDC A0 6B1 DAT_DDC2_CRT
<51> GPU_CLK_DDC 3 A1 7B1 31
7 22 CLK_DDC2_CRT SUYIN_070546FR015S558ZR
<51> CRT_VSYNC_GPU A2 8B1
<51> CRT_HSYNC_GPU 8 A3 9B1 23
<51> CRT_RED_GPU 11 A4
<51> CRT_GRN_GPU 12 A5
<51> CRT_BLU_GPU 14 A6
<51> TV_CVBS_GPU 15 A7 1
19 46 DAT_DDC2_DOCK
<51> TV_Y_GPU A8 0B2 DAT_DDC2_DOCK <35>
20 45 CLK_DDC2_DOCK L11 C258
<51> TV_C_GPU A9 1B2 CLK_DDC2_DOCK <35>
41 VSYNC_DOCK BLM18AG121SN1D_0603~D
CRT_SWITCH 2B2 HSYNC_DOCK VSYNC_DOCK <35> HSYNC_CRT 2
<37> CRT_SWITCH 17 SEL 3B2 40 HSYNC_DOCK <35> To Dock Conn. 1 2 HSYNC_L2 1 2 0.1U_0402_16V4Z~D
35 RED_DOCK R177 0_0402_5%~D L12
4B2 GREEN_DOCK RED_DOCK <35> BLM18AG121SN1D_0603~D
1 GND 5B2 34 GREEN_DOCK <35>
6 30 BLUE_DOCK VSYNC_CRT 1 2 VSYNC_L2 1 2
GND 6B2 TV_CVBS_RSV BLUE_DOCK <35> R178 0_0402_5%~D
9 GND 7B2 29
13 25 TV_Y_RSV
GND 8B2 TV_C_RSV
16 GND 9B2 26
21 GND
24 GND +3.3V_RUN
SEL CRT TV 28
33
GND
GND NC 52
39 5
0 MB LIO 44
GND
GND
NC
NC 54
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
22P_0402_50V8J~D
49 51
1 APR/SPR NA 53
GND
GND
NC
1 1
55 GND 1 1 1 1 1 1 1 1
C267
C268
C259
C260
C261
C262
C263
C264
C265
C266
TS3DV520ERHUR_QFN56_11X5~D
2 2
2 2 2 2 2 2 2 2
1 2 TV_CVBS_RSV
@R669
@ R669 150_0402_1%~D
1 2 TV_Y_RSV
@R762
@ R762 150_0402_1%~D
1 2 TV_C_RSV +5V_RUN
@R763
@ R763 150_0402_1%~D
2
Prevent TV impedance D9
error when switch SDM10U45-7_SOD523-2~D
1
1 2 +5V_RUN_SYNC 1 2
R179 1K_0402_5%~D
C269
5
0.1U_0402_16V4Z~D
P
OE#
HSYNC_BUF 2 4 HSYNC_CRT
A Y
G
U5
SN74AHCT1G125GW_SC70-5~D
3
A A
1 2
5
C270
0.1U_0402_16V4Z~D
P
OE#
VSYNC_BUF 2 4 VSYNC_CRT
A Y
G
U6
SN74AHCT1G125GW_SC70-5~D
3
401533
2 1
2 1
Display port Connector

+3.3V_RUN
SW for MB side SW for eDOCK side
2
+3.3V_RUN +3.3V_RUN
D10
SDM10U45-7_SOD523-2~D
+3.3V_RUN_R 1
2
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
C272
2
100K_0402_5%~D
R964 C271 R965 0.1U_0402_10V7K~D
2
R180
0_0402_5%~D 0_0402_5%~D
R182
R183
<51> DPB_AUX 1 2 DPB_AUX_C 1 6 2 1 <51> DPC_DOCK_AUX 1 2DPC_DOCK_AUX_C 1 6 2 1
R181
1
Q19A 0.1U_0402_10V7K~D Q20A
1
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
1
1 2 DPB_AUX_SW 1 2
<51> DVI_B_CLK_DDC <51> DVI_C_CLK_DDC DPC_DOCK_AUX_SW <35>
R74 33_0402_5%~D R92 33_0402_5%~D
2
0_1206_5%~D
C274
R184
R966 Q19B C273 R967 Q20B 0.1U_0402_10V7K~D @ F1
0_0402_5%~D 2N7002DW-T/R7_SOT363-6 0_0402_5%~D 2N7002DW-T/R7_SOT363-6 5A_125V_R451005.MRL~D +VDISPLAY_VCC
<51> DPB_AUX# 1 2 DPB_AUX#C 4 3 2 1 DPB_AUX#SW
<51> DPC_DOCK_AUX# 1 2DPC_DOCK_AUX#C 4 3 2 1
1
DPC_DOCK_AUX#SW <35>
0.01U_0402_16V7K~D
C277 1 2 +3.3V_RUN
0.1U_0402_10V7K~D C276 0.1U_0402_16V4Z~D 1
5
5
1 2 0.1U_0402_16V4Z~D 1 2 1 2 +3.3V_RUN
<51> DVI_B_DAT_DDC <51> DVI_C_DAT_DDC
C275
B R89 33_0402_5%~D R764 33_0402_5%~D B
5
2
P
NC
5
4 2 DPB_CA_DET NC7SZ04P5X_NL_SC70-5~D
Y A U7
P
NC
G
U8 4 2 DPC_CA_DET
NC7SZ04P5X_NL_SC70-5~D Y A DPC_CA_DET <35,51>
G
JDP1
3
20 DP_PWR
1 2 DPC_CA_DET 19
R821 100K_0402_5%~D DPB_MB_HPD RTN
18 HP_DET
DPB_MB_AUX# 17 AUX_CH-
16 GND
DPB_MB_AUX 15
DPB_MB_CA_DET DPB_MB_P14 AUX_CH+
1 2 <51> DPB_MB_P14 14 GND
R185 1M_0402_5%~D DPB_MB_CA_DET 13 CA_DET
1 2 DPB_MB_HPD DPB_MB_LANE3#_C 12 LANE3- GND 21
R186 100K_0402_5%~D 11 22
LANE3_shield GND
1 2 DPB_DOCK_CA_DET DPB_MB_LANE3_C 10 LANE3+ GND 23
R187 1M_0402_5%~D DPB_MB_LANE2#_C 9 24
LANE2- GND
1 2 DPB_DOCK_HPD 8 LANE2_shield
R188 100K_0402_5%~D DPB_MB_LANE2_C 7
U9 DPB_MB_LANE1#_C LANE2+
6 LANE1-
5 LANE1_shield
DPB_MB_LANE1_C 4
DPB_MB_LANE0 C278 LANE1+
<51> DPB_LANE_P0_C 3 ML_IN 0(p) ML_A 0(p) 56 2 1 0.1U_0402_10V7K~D DPB_MB_LANE0_C DPB_MB_LANE0#_C 3 LANE0-
4 55 DPB_MB_LANE0# C279 2 1 0.1U_0402_10V7K~D DPB_MB_LANE0#_C 2
<51> DPB_LANE_N0_C ML_IN 0(n) ML_A 0(n) LANE0_shield
DPB_MB_LANE0_C 1
DPB_MB_LANE1 C280 LANE0+
<51> DPB_LANE_P1_C 6 ML_IN 1(p) ML_A 1(p) 53 2 1 0.1U_0402_10V7K~D DPB_MB_LANE1_C
7 52 DPB_MB_LANE1# C281 2 1 0.1U_0402_10V7K~D DPB_MB_LANE1#_C MOLEX_105019-0001
<51> DPB_LANE_N1_C ML_IN 1(n) ML_A 1(n)
9 50 DPB_MB_LANE2 C282 2 1 0.1U_0402_10V7K~D DPB_MB_LANE2_C
<51> DPB_LANE_P2_C ML_IN 2(p) ML_A 2(p)
10 49 DPB_MB_LANE2# C283 2 1 0.1U_0402_10V7K~D DPB_MB_LANE2#_C
<51> DPB_LANE_N2_C ML_IN 2(n) ML_A 2(n)
12 47 DPB_MB_LANE3 C284 2 1 0.1U_0402_10V7K~D DPB_MB_LANE3_C
<51> DPB_LANE_P3_C ML_IN 3(p) ML_A 3(p) D11 @
13 46 DPB_MB_LANE3# C285 2 1 0.1U_0402_10V7K~D DPB_MB_LANE3#_C
<51> DPB_LANE_N3_C ML_IN 3(n) ML_A 3(n) DPB_MB_LANE0_C 1 10 DPB_MB_LANE0_C
45 DPB_MB_AUX
DPB_AUX_SW AUX_A (p) DPB_MB_AUX# DPB_MB_LANE0#_C DPB_MB_LANE0#_C
36 AUX (p) AUX_A (n) 43 2 9
+3.3V_RUN DPB_AUX#SW 35 AUX (n) DPB_MB_LANE1_C DPB_MB_LANE1_C
4 7
DP_MB_HPD_EN 40 25 DPB_DOCK_LANE0 C286 2 1 0.1U_0402_10V7K~D DPB_MB_LANE1#_C 5 6 DPB_MB_LANE1#_C
HPD_A ML_B 0(p) DPB_DOCK_LANE0_C <35>
100K_0402_5%~D
DPB_DOCK_HPD 32 24 DPB_DOCK_LANE0# C287 2 1 0.1U_0402_10V7K~D

<35> DPB_DOCK_HPD HPD_B ML_B 0(n) DPB_DOCK_LANE0#_C <35>
2
3
22 DPB_DOCK_LANE1 C288 2 1 0.1U_0402_10V7K~D
ML_B 1(p) DPB_DOCK_LANE1_C <35>
R189
DPB_MB_CA_DET 41 21 DPB_DOCK_LANE1# C289 2 1 0.1U_0402_10V7K~D 8

DPB_DOCK_CA_DET CAD_A ML_B 1(n) DPB_DOCK_LANE1#_C <35>
<35> DPB_DOCK_CA_DET 33 CAD_B
19 DPB_DOCK_LANE2 C290 2 1 0.1U_0402_10V7K~D RCLAMP0524P.TCT~D
1
ML_B 2(p) DPB_DOCK_LANE2# C291 DPB_DOCK_LANE2_C <35> +3.3V_RUN

ML_B 2(n) 18 2 1 0.1U_0402_10V7K~D DPB_DOCK_LANE2#_C <35>
+3.3V_RUN_LP 30 LP DPB_DOCK_LANE3 C292 D12 @
ML_B 3(p) 16 2 1 0.1U_0402_10V7K~D DPB_DOCK_LANE3_C <35>
2
15 DPB_DOCK_LANE3# C293 2 1 0.1U_0402_10V7K~D DPB_MB_LANE2_C 1 10 DPB_MB_LANE2_C
DP_PRIORITY ML_B 3(n) DPB_DOCK_LANE3#_C <35> R798
<37> DP_PRIORITY 29 Priority
28 DPB_DOCK_AUX 10K_0402_5%~D DPB_MB_LANE2#_C 2 9 DPB_MB_LANE2#_C
AUX_B (p) DPB_DOCK_AUX <35>
2
100K_0402_5%~D
26 DPB_DOCK_AUX#
AUX_B (n) DPB_DOCK_AUX# <35> DPB_MB_LANE3_C DPB_MB_LANE3_C
4 7
1
R190
DPB_HPD_R DPB_HPD# <51> DPB_MB_LANE3#_C DPB_MB_LANE3#_C

HPD 37 5 6
1
D
1
BSS138_SOT23~D
Q10
DPB_HPD_R 2 3
39 DPB_CA_DET G
CAD DPB_CA_DET <51>
100K_0402_5%~D
1 S 8
3
DPVadj
2
1
5.11K_0402_1%~D
RCLAMP0524P.TCT~D
R191
+5V_RUN +3.3V_RUN D13 @
R193
+3.3V_RUN 38 5 +3.3V_RUN
VDD*1 GND DPB_MB_AUX#
11 1 10 DPB_MB_AUX#
1
GND DPB_MB_AUX
A +5V_RUN 2 20 2 1 2 1 A
2
VDD GND R875 100K_0402_5%~D @ R209 100K_0402_5%~D DPB_MB_AUX DPB_MB_AUX

8 VDD GND 27 2 9
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.01U_0402_16V7K~D
1000P_0402_50V7K~D
0.1U_0402_10V7K~D
14 31 2 1 DPB_MB_AUX# 2 1
VDD GND
1U_0603_10V4Z~D
17 42 R876 100K_0402_5%~D @ R278 100K_0402_5%~D DPB_MB_HPD 4 7 DPB_MB_HPD

VDD GND DPB_DOCK_AUX 2
1 1 1 1 1 1 23 VDD GND 44 2 1 1
34 51 R877 100K_0402_5%~D @ R336 100K_0402_5%~D DPB_MB_CA_DET 5 6 DPB_MB_CA_DET
VDD GND
C937
C938
C939
C940
C941
C950
48 2 1 DPB_DOCK_AUX# 2 1
VDD R878 100K_0402_5%~D @ R337 100K_0402_5%~D
54 VDD Thermal GND 57 3
2 2 2 2 2 2 DPC_DOCK_AUX 2
2 1 1
@R879
@ R879 100K_0402_5%~D @ R419 100K_0402_5%~D 8
2 1 DPC_DOCK_AUX# 2 1
TS2DP512_QFN56_8X8~D @R880
@ R880 100K_0402_5%~D @ R647 100K_0402_5%~D RCLAMP0524P.TCT~D
Pads for interoperability, +3.3V_RUN Place close to JDP1 connector

remove in X01 if not needed. 1 2
@ 1 R911 2 U66 C1018 0.1U_0402_16V4Z~D

<35,37> DOCK_DET#
5
0_0402_5%~D
1 R968
2 1
P
<37> DP_MB_EN A
0_0402_5%~D 4 DP_MB_HPD_EN
DPB_MB_HPD Y 74AHCT1G08GW SOT353~D
Pin30 Level State Description 2 B
G
Hi Normal Mode Standard operational mode for device
3
LP Low Low power Mode Device is forced into a low power mode
causing the output s to go to a high-Z Compal Electronics, Inc.
state, all other inputs are ignore PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
401533
2 1
5 4 3 2 1
+3.3V_RUN
R194 1 2 8.2K_0402_5%~D PCI_DEVSEL# <31> PCI_AD[0..31]

D U10B D
R195 1 2 8.2K_0402_5%~D PCI_STOP# PCI_AD0 D11 F1 PCI_REQ0#
PCI_AD1 AD0 REQ0# PCI_GNT0#
R196 1 2 8.2K_0402_5%~D PCI_TRDY# PCI_AD2
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1#
AD2 REQ1#/GPIO50 PCI_REQ1# <31>
PCI_AD3 E12 A7 PCI_GNT1#
AD3 GNT1#/GPIO51 PCI_GNT1# <31>
R197 1 2 8.2K_0402_5%~D PCI_FRAME# PCI_AD4 E9 AD4 REQ2#/GPIO52 F13 PCIE_MCARD2_DET# <34>
PCI_AD5 C9 F12 GNT2#/GPIO53 +3.3V_ALW_ICH
AD5 GNT2#/GPIO53 T183PAD~D
R198 1 2 8.2K_0402_5%~D PCI_PLOCK# PCI_AD6 E10 AD6 REQ3#/GPIO54 E6 PCIE_MCARD3_DET# <34>
C294
PCI_AD7 B7 F6 PCI_GNT3# 0.1U_0402_16V4Z~D
R199 1 AD7 GNT3#/GPIO55
2 8.2K_0402_5%~D PCI_IRDY# PCI_AD8 C7 AD8
PCI_AD9 C5 D8 PCI_C_BE0# PCI_C_BE0# <31>
R200 1 AD9 C/BE0#
2 8.2K_0402_5%~D PCI_SERR# PCI_AD10 G11 AD10 C/BE1# B4 PCI_C_BE1# PCI_C_BE1# <31>
PCI_AD11 F8 D6 PCI_C_BE2# PCI_C_BE2# <31>
R201 1 AD11 C/BE2#
2 8.2K_0402_5%~D PCI_PERR# PCI_AD12 PCI_C_BE3#
14
F11 AD12 C/BE3# A5 PCI_C_BE3# <31>
PCI_AD13 E7
PCI_AD14 AD13 PCI_IRDY# PCI_PCIRST#
A3 D3 1
P
AD14 IRDY# PCI_IRDY# <31> IN1
PCI_AD15 D2 E3 PCI_PAR 3 PCI_RST#
AD15 PAR PCI_PAR <31> OUT PCI_RST# <31,35>
PCI_AD16 F10 R1 PCI_PCIRST# 2
AD16 PCIRST# IN2
G
PCI_AD17 D5 C6 PCI_DEVSEL#
AD17 DEVSEL# PCI_DEVSEL# <31>
PCI_AD18 D10 E4 PCI_PERR# U11A
PCI_PERR# <31>
7
PCI_AD19 AD18 PERR# PCI_PLOCK# 74VHC08MTCX_NL_TSSOP14~D
B3 AD19 PLOCK# C2
PCI_AD20 F7 J4 PCI_SERR#
+3.3V_RUN AD20 SERR# PCI_SERR# <31>
PCI_AD21 C3 A4 PCI_STOP#
AD21 STOP# PCI_STOP# <31>
PCI_AD22 F3 F5 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <31> +3.3V_ALW_ICH
PCI_AD23 F4 D7 PCI_FRAME#
AD23 FRAME# PCI_FRAME# <31>
R202 1 2 8.2K_0402_5%~D PCI_PIRQA# PCI_AD24 C1 AD24
PCI_AD25 PCI_PLTRST#
14
G7 AD25 PLTRST# C14
R203 1 2 8.2K_0402_5%~D PCI_PIRQB# PCI_AD26 H7 AD26 PCICLK D4 CLK_PCI_ICH
CLK_PCI_ICH <6>
PCI_AD27 D1 R2 ICH_PME# PCI_PLTRST# 4
P
AD27 PME# ICH_PME# <37> IN1
R204 1 2 8.2K_0402_5%~D PCI_PIRQC# PCI_AD28 G5 6 PLTRST1#
AD28 OUT PLTRST1# <10,32,51>
PCI_AD29 H6 5
AD29 IN2
G
R205 1 2 8.2K_0402_5%~D PCI_PIRQD# PCI_AD30 G1
C PCI_AD31 AD30 U11B C
H3
7
R207 1 AD31
2 8.2K_0402_5%~D PCI_REQ0# 74VHC08MTCX_NL_TSSOP14~D
R208 1 2 8.2K_0402_5%~D PCI_REQ1# PCI_PIRQA# J5

Interrupt I/F H4 LVDS_CBL_DET#
PIRQA# PIRQE#/GPIO2 LVDS_CBL_DET# <19>
PCI_PIRQB# E1 K6 PNL_BKLT_CBL_DET#
<31> PCI_PIRQB# PIRQB# PIRQF#/GPIO3 PNL_BKLT_CBL_DET# <19> +3.3V_ALW_ICH
R702 1 2 100K_0402_5%~D FAN1_DET# <31> PCI_PIRQC#
PCI_PIRQC# J6 PIRQC# PIRQG#/GPIO4 F2 CAM_MIC_CBL_DET#
CAM_MIC_CBL_DET# <19>
PCI_PIRQD# C4 G2 FAN1_DET#
<31> PCI_PIRQD# PIRQD# PIRQH#/GPIO5 FAN1_DET# <18>
R755 1 2 100K_0402_5%~D LVDS_CBL_DET#
14
ICH9M REV 1.0
R212 1 2 100K_0402_5%~D CAM_MIC_CBL_DET# 10
P
IN1 PLTRST2#
OUT 8 PLTRST2# <37,38>
R817 1 2 100K_0402_5%~D PNL_BKLT_CBL_DET# 9 IN2
G
U11C
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
14
13
P
IN1
OUT 11 PLTRST3# PLTRST3# <34,36>
12 IN2
G
U11D
7
PCI_GNT0# ICH_SPI_CS1#
<24> ICH_SPI_CS1#
PCI_GNT3#
1
B B
1
@ R215 R213 @ R214

@R214
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D
2
2
2
Place closely pin U10.D4

CLK_PCI_ICH
2
A16 away override strap. Boot BIOS Strap
@ R216
@R216
10_0402_5%~D
Low = A16 swap override enabled.
PCI_GNT3#/(MDC_RST_DIS#) PCI_GNT0# SPI_CS1# Boot BIOS Location
CLK_ICH_TERM 1
High = Default. pull up internal
* 0 1 SPI
1 0 PCI 1
@ C295
@C295
8.2P_0402_50V8J~D
2
1 1 LPC
A A
401533
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
1
R217 R218
332K_0402_1%~D 332K_0402_1%~D
2
ICH_INTVRMEN LAN100_SLP
2
@ R219
@R219 @ R220
0_0402_5%~D 0_0402_5%~D
D +3.3V_ALW_ICH D
1
Package
2 1 GLAN_DOCK#
R221 10K_0402_5%~D 9.6X4.06 mm
ICH9M Internal VR Enable Strap ICH9M LAN100 SLP Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05)
CMOS_CLR1 CMOS setting 2 1 ICH_RTCX1

C296 ICH_INTVRMEN Low = Internal VR Disabled ICH_LAN100_SLP Low = Internal VR Disabled
Shunt Clear CMOS 15P_0402_50V8J~D
High = Internal VR Enabled(Default) High = Internal VR Enabled(Default)
1
4
3
Open Keep CMOS R222
Y1 10M_0402_5%~D
32.768K_12.5P_1TJS125DJ4A420P~D
ME_CLR1 TPM setting LPC_LAD[0..3] <36,37,38>
2
R223 U10A +3.3V_RUN
Shunt Clear ME RTC Registers 0_0402_5%~D C23 K5 LPC_LAD0
RTCX1 FWH0/LAD0 LPC_LAD0 <36,37,38>
2 1 1 2 ICH_RTCX2 C24 K4 LPC_LAD1
RTCX2 FWH1/LAD1 LPC_LAD1 <36,37,38>
Open Keep ME RTC Registers C297 15P_0402_50V8J~D L6 LPC_LAD2 +1.05V_VCCP SIO_A20GATE 2 1
FWH2/LAD2 LPC_LAD2 <36,37,38>
+RTC_CELL R224 1 2 20K_0402_5%~D ICH_RTCRST# A25 K2 LPC_LAD3 R230 10K_0402_5%~D
RTCRST# FWH3/LAD3 LPC_LAD3 <36,37,38>
SRTCRST#
RTC
LPC
R225 1 2 20K_0402_5%~D F20 SIO_RCIN# 2 1
R226 1 SRTCRST#
2 1M_0402_5%~D INTRUDER# C22 INTRUDER# FWH4/LFRAME# K3 LPC_LFRAME#
LPC_LFRAME# <36,37,38>
R231 10K_0402_5%~D
56_0402_1%~D
56_0402_1%~D
1
1
@R227
@
@R228
@
ICH_INTVRMEN B22 J3 LPC_LDRQ0#
INTVRMEN LDRQ0# LPC_LDRQ0# <37>
R227
R228
LAN100_SLP A22 J1 LPC_LDRQ1#
LAN100_SLP LDRQ1#/GPIO23 LPC_LDRQ1# <37> +1.05V_VCCP
1 2 1 2 E25 N7 SIO_A20GATE
1 2 1 2 <29> LAN_CLK GLAN_CLK A20GATE SIO_A20GATE <38>
AJ27 H_A20M# H_FERR# 2 1
H_A20M# <7>
2
A20M# R233 56_0402_5%~D
<29> LAN_RSTSYNC C13 LAN_RSTSYNC
AJ25 H_DPRSTP#
C DPRSTP# H_DPRSTP# <8,10,47> C
LAN_RX0 F14 AE23 H_DPSLP#
LAN / GLAN
<29> LAN_RX0 LAN_RXD0 DPSLP# H_DPSLP# <8>
ME_CLR1 @SHORT PADS~D CMOS_CLR1 @SHORT PADS~D LAN_RX1 G13 R229
<29> LAN_RX1 LAN_RXD1
1 2 1 2 LAN_RX2 D14 AJ26 2 1
<29> LAN_RX2 LAN_RXD2 FERR# H_FERR# <7>
C298 1U_0603_10V4Z~D C299 1U_0603_10V4Z~D 56_0402_5%~D
LAN_TX0 D13 AD22 H_PWRGOOD
<29> LAN_TX0 LAN_TXD0 CPUPWRGD H_PWRGOOD <8>
LAN_TX1 D12
<29> LAN_TX1 LAN_TXD1
LAN_TX2 E13 AF25 H_IGNNE#
<29> LAN_TX2 LAN_TXD2 IGNNE# H_IGNNE# <7>
CPU
GLAN_DOCK# B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# <7>
Close to U55 AG25 H_INTR +1.05V_VCCP
INTR H_INTR <7>
+1.5V_RUN_PCIE_ICH 1 2 B28 L3 SIO_RCIN#
GLAN_COMPI RCIN# SIO_RCIN# <38>
<27> ICH_AZ_CODEC_SDOUT 1 2 ICH_AZ_SDOUT 2 1 R232 B27 GLAN_COMPO
1
R234 33_0402_5%~D @ C300 R236 33_0402_5%~D 24.9_0402_1%~D AF23 H_NMI
NMI H_NMI <7>
<27> ICH_AZ_CODEC_SYNC 1 2 ICH_AZ_SYNC <33> ICH_AZ_MDC_BITCLK
27P_0402_50V8J~D 1 2 ICH_AZ_BITCLK AF6 HDA_BIT_CLK SMI# AF24 H_SMI#
H_SMI# <7>
R237
R235 33_0402_5%~D 1 2 ICH_AZ_SYNC AH4 56_0402_5%~D
<33> ICH_AZ_MDC_SYNC HDA_SYNC
<27> ICH_AZ_CODEC_RST# 1 2 ICH_AZ_RST# R238 33_0402_5%~D
STPCLK# AH27 H_STPCLK#
H_STPCLK# <7>
R239 33_0402_5%~D 1 2 ICH_AZ_RST# AE7
<33> ICH_AZ_MDC_RST#
2
HDA_RST#
<27> ICH_AZ_CODEC_BITCLK 1 2 ICH_AZ_BITCLK R240 33_0402_5%~D
THRMTRIP# AG26 THRMTRIP_ICH# 1 2
1 R241 33_0402_5%~D ICH_AZ_CODEC_SDIN0 AF4 C301
<27> ICH_AZ_CODEC_SDIN0 HDA_SDIN0
ICH_AZ_MDC_SDIN1 AG4 AG27 ICH_TP12 T41PAD~D 0.1U_0402_16V4Z~D
<33> ICH_AZ_MDC_SDIN1 HDA_SDIN1 TP12
@ C302 ICH_AZ_GPU_SDIN2
IHDA
<51> ICH_AZ_GPU_SDIN2 AH3 HDA_SDIN2
27P_0402_50V8J~D AE5
2 HDA_SDIN3
SATA4RXN AH11 ESATA_IRX_DTX_N4_C <33>
1 2 ICH_AZ_SDOUT AG5 AJ11
<33> ICH_AZ_MDC_SDOUT HDA_SDOUT SATA4RXP ESATA_IRX_DTX_P4_C <33>
R242 33_0402_5%~D AG12 ESATA_ITX_DRX_N4_C 2 1
SATA4TXN ESATA_ITX_DRX_N4 <33>
<37> ME_FWP ME_FWP AG7 AF12 ESATA_ITX_DRX_P4_C C303 2 1 0.01U_0402_16V7K~D
HDA_DOCK_EN#/GPIO33 SATA4TXP ESATA_ITX_DRX_P4 <33>
<51> ICH_AZ_GPU_SDOUT 1 2 ICH_AZ_SDOUT RTC_BAT_DET# AE8 HDA_DOCK_RST#/GPIO34
C304 0.01U_0402_16V7K~D
@ R243 33_0402_5%~D T46 PAD~D AH9
SATA5RXN SATA_SBRX_DTX_N3_C <35>
<51> ICH_AZ_GPU_SYNC 1 2 ICH_AZ_SYNC <42> SATA_ACT#_R
SATA_ACT#_R AG8 SATALED# SATA5RXP AJ9 SATA_SBRX_DTX_P3_C <35>
@ R244 33_0402_5%~D AE10 SATA_ITX_DRX_N3_C 2 1
SATA5TXN SATA_SBTX_C_DRX_N3 <35>
<51> ICH_AZ_GPU_RST# 1 2 ICH_AZ_RST# <26> PSATA_IRX_DTX_N0_C AJ16 SATA0RXN SATA5TXP AF10 SATA_ITX_DRX_P3_C C305 2 1 0.01U_0402_16V7K~D SATA_SBTX_C_DRX_P3 <35>
@ R245 33_0402_5%~D AH16 C306 0.01U_0402_16V7K~D
SATA
B <26> PSATA_IRX_DTX_P0_C SATA0RXP B
<51> ICH_AZ_GPU_BITCLK 1 2 ICH_AZ_BITCLK <26> PSATA_ITX_DRX_N0 2 1 PSATA_ITX_DRX_N0_C AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA#
CLK_PCIE_SATA# <6>
1 @ R246 33_0402_5%~D C307 2 1 0.01U_0402_16V7K~D PSATA_ITX_DRX_P0_C AG17 AJ18 CLK_PCIE_SATA
<26> PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA <6>
C308 0.01U_0402_16V7K~D
@ C309 AH13 AJ7
27P_0402_50V8J~D <26> SATA_ODD_IRX_DTX_N1_C SATA1RXN SATARBIAS#
<26> SATA_ODD_IRX_DTX_P1_C AJ13 SATA1RXP SATARBIAS AH7 2 1
2 SATA_ODD_ITX_DRX_N1_C AG14 R247 24.9_0402_1%~D
<26> SATA_ODD_ITX_DRX_N1 2 1 SATA1TXN
C310 2 1 0.01U_0402_16V7K~D SATA_ODD_ITX_DRX_P1_C AF14
<26> SATA_ODD_ITX_DRX_P1 SATA1TXP
C311 0.01U_0402_16V7K~D Within 500 mils
ICH9M REV 1.0
+3.3V_RUN
1
XOR Chain Entrance Strap

@ R248
1K_0402_5%~D
ICH RSVD_TP3 HDA SDOUT Description
2
0 0 RSVD ICH_AZ_SDOUT
ICH_RSVD_TP3 <24>
R375, R961, R960, R962 Q130 remove for RTC detect function
1
0 1 Enter XOR Chain

@ R249
1K_0402_5%~D
1 0 Normal Operation (Default)
2
1 1 Set PCIE port config bit 1

A A
401533
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_ICH
+3.3V_RUN +3.3V_RUN
1 2 ICH_SMBCLK
1 2 IMVP_PWRGD R252 2.2K_0402_5%~D 1 2
@ R251 2.2K_0402_5%~D 1 2 ICH_SMBDATA U10C R256 8.2K_0402_5%~D
1 2 MCH_ICH_SYNC# R255 2.2K_0402_5%~D ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23
@ R254 10K_0402_5%~D 1 2 ICH_CL_RST1# ICH_SMBDATA A13 AF19 SPEAKER_DET#
SMBDATA SATA1GP/GPIO19 SPEAKER_DET# <28> +3.3V_RUN
1 2 RSV_THRM# @R259
@ R259 10K_0402_5%~D ICH_GPIO60 E17 AE21 USB_MCARD3_DET#
SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 USB_MCARD3_DET# <34>
SMB
R258 8.2K_0402_5%~D 1 2 AMT_SMBCLK AMT_SMBCLK C17 AD20 1394_DET#
<38> AMT_SMBCLK SMLINK0 SATA5GP/GPIO37 1394_DET# <31>
2 1 IRQ_SERIRQ R262 10K_0402_5%~D
<38> AMT_SMBDAT
AMT_SMBDAT B18 SMLINK1
R261 10K_0402_5%~D 1 2 AMT_SMBDAT CLK14 H1 CLK_ICH_14M
CLK_ICH_14M <6>
1394_DET# 1 2
1 2 SPKR R265 10K_0402_5%~D ICH_RI# F19 AF3 CLK_ICH_48M R836 100K_0402_5%~D
Clocks
RI# CLK48 CLK_ICH_48M <6>
@ R264 1K_0402_5%~D 1 2 ICH_RI# ODD_DET# 2 1
R267 10K_0402_5%~D PAD~D T184 SUS_STAT#/LPCPD# R4 P1 ICH_SUSCLK T44 PAD~D R760 100K_0402_5%~D
SUS_STAT#/LPCPD# SUSCLK
1 2 ICH_PCIE_WAKE# <7,37> ITP_DBRESET#
ITP_DBRESET# G19 SYS_RESET#
HDD_DET# 1 2
D D
1 2 SPEAKER_DET# R268 10K_0402_5%~D
SLP_S3# C16 SIO_SLP_S3#
SIO_SLP_S3# <37>
R759 100K_0402_5%~D
R834 100K_0402_5%~D 2 1 ME_SUS_PWR_ACK PM_SYNC# M6 E16 SIO_SLP_S4#
<10> PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SIO_SLP_S4# <38>
R269 10K_0402_5%~D G17 SIO_SLP_S5#
SLP_S5# SIO_SLP_S5# <38>
1 2 SIO_EXT_SMI# SMB_ALERT# A17 SMBALERT#/GPIO11
1 2 SIO_EXT_SCI# R274 10K_0402_5%~D
S4_STATE#/GPIO26 C10 ICH_GPIO26 T130 PAD~D
R272 10K_0402_5%~D 1 2 ICH_GPIO60 <6> H_STP_PCI#
H_STP_PCI# A14 STP_PCI#
ICH_CL_PWROK 1 2
1 TPM_ID R787 10K_0402_5%~D H_STP_CPU# ICH_PWRGD R250 100K_0402_5%~D
SYS GPIO
2 <6> H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWRGD <10,41>
R273 100K_0402_5%~D 1 2 SMB_ALERT# DPRSLPVR 1 2
R192 10K_0402_5%~D <31,37,38> CLKRUN# CLKRUN# L4 M2 DPRSLPVR @ R253 100K_0402_5%~D
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR <10,47>
iTPM function 1 2 IO_LOOP ICH_PWRGD 1 2
R835 100K_0402_5%~D ICH_PCIE_WAKE# E20 B13 ICH_BATLOW# 2 1 R257 10K_0402_5%~D
Power MGT
<37> ICH_PCIE_WAKE# WAKE# BATLOW# +3.3V_ALW_ICH
No stuff = Disable 1 2 CONTACTLESS_DET# <31,36,37,38> IRQ_SERIRQ
IRQ_SERIRQ M5 SERIRQ
R275 8.2K_0402_5%~D ICH_RSMRST# 1 2
R270 R963 100K_0402_5%~D RSV_THRM# AJ23 R3 SIO_PWRBTN# R260 10K_0402_5%~D
THRM# PWRBTN# SIO_PWRBTN# <38>
Stuff = Enable 1 2 BIO_DET# ME_WOL_EN 1 2
R823 100K_0402_5%~D IMVP_PWRGD D21 D20 ICH_LAN_RST# R263 100K_0402_5%~D
<37,41,47> IMVP_PWRGD VRMPWRGD LAN_RST# ICH_LAN_RST# <38>
+3.3V_LAN ICH_TP11 A20 D22 ICH_RSMRST#
PAD~D T45 TP11 RSMRST# ICH_RSMRST# <38>
1 2 ICH_EC_SPI_DO <38> SIO_EXT_SCI#
SIO_EXT_SCI# AG19 GPIO1 CK_PWRGD R5 CLK_PWRGD
CLK_PWRGD <6>
@ R270 1K_0402_5%~D TPM_ID AH21 Place closely pin U10.H1
GPIO6 ICH_CL_PWROK +3.3V_ALW_ICH
<37> SIO_EXT_WAKE# 1 2 AG21 GPIO7 CLPWROK R6 ICH_CL_PWROK <10,38>
No Reboot Strap R277 0_0402_5%~D SIO_EXT_SMI# A21 CLK_ICH_14M
<38> SIO_EXT_SMI# GPIO8
10K_0402_5%~D
C12 B16 SIO_SLP_M#
<29,37> LAN_PHY_PWR_CNTRL GPIO12 SLP_M# SIO_SLP_M# <38>
1
Low = Default CONTACTLESS_DET# C21
<36> CONTACTLESS_DET# GPIO13
R271
SPKR AE18 F24 @
GPIO17 CL_CLK0 CL_CLK0 <10>
High = No Reboot 1 2 PAD~D T39 K1 B19 @ R279
<34> USB_MCARD1_DET# GPIO18 CL_CLK1 ICH_CL_CLK1 <34>
R280 0_0402_5%~D ICH_GPIO20 AF8 10_0402_5%~D
PAD~D T132 GPIO20
<34> USB_MCARD2_DET# 1 2 AJ22 F22 CL_DATA0 <10>
2
+3.3V_RUN R281 0_0402_5%~D SD_DET# SCLOCK/GPIO22 CL_DATA0 ICH_LAN_RST#
<31> SD_DET# A9 C19 ICH_CL_DATA1 <34>
GPIO
Controller Link
GPIO27 CL_DATA1
47P_0402_50V8J~D
47P_0402_50V8J~D
4700P_0402_25V7K~D
IO_LOOP D19 1
<33> IO_LOOP GPIO28
2
10K_0402_5%~D
1 1 1 SATA_CLKREQ# L1 C25 +CL_VREF0_ICH
<6> SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
1
@ C313
@ C315
@ ODD_DET# AE19 A19 +CL_VREF1_ICH @ C312

<26> ODD_DET# SLOAD/GPIO38 CL_VREF1
C316
R276
C R282 WPAN_RADIO_DIS_MINI# AG22 4.7P_0402_50V8C~D C
PAD~D T48 SDATAOUT0/GPIO39 2
8.2K_0402_5%~D HDD_DET# AF21 F21 CL_RST0#
2 2 2 <26> HDD_DET# SDATAOUT1/GPIO48 CL_RST0# CL_RST0# <10>
PAD~D T185 ICH_GPIO49 AH24 D18 ICH_CL_RST1#
1
BIO_DET# GPIO49 CL_RST1# ICH_CL_RST1# <34>
<33> BIO_DET# A8
2
GPIO57/CLGPIO5
MEM_LED/GPIO24 A16 PCIE_MCARD1_DET# <34>
CLKRUN# SPKR M7 C18 ME_SUS_PWR_ACK
<27> SPKR SPKR GPIO10/SUS_PWR_ACK ME_SUS_PWR_ACK <38>
MCH_ICH_SYNC# AJ24 C11 AC_PRESENT Place closely pin U10.AF3
<10> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT <38>
ICH_RSVD_TP3 B21 C20 ME_WOL_EN
<23> ICH_RSVD_TP3 TP3 WOL_EN/GPIO9 ME_WOL_EN <38>
1
ICH_TP8 CLK_ICH_48M
MISC
Option to " Disable " PAD~D T50 AH20 TP8
@ R283 1 2 ITP_DBRESET# PAD~D T51 ICH_TP9 AJ20 1 2 +3.3V_ALW_ICH
clkrun. Pulling it TP9
1
10_0402_5%~D @R811
@ R811 100K_0402_5%~D PAD~D T52 ICH_TP10 AJ21 @ R284
TP10 10K_0402_5%~D
down
ICH9M REV 1.0 @ R285
will keep the clks
2
10_0402_5%~D
running.
2
U10D
PCIE_IRX_WANTX_N1 N29 V27 DMI_MTX_IRX_N0 1
<34> PCIE_IRX_WANTX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <10>
PCIE_IRX_WANTX_P1 N28 V26 DMI_MTX_IRX_P0
<34> PCIE_IRX_WANTX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 <10>
Direct Media Interface

MiniWWAN (Mini Card 1)---> C317 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_N1 P27 U29 DMI_MRX_ITX_N0 @ C318
<34> PCIE_ITX_WANRX_N1_C PETN1 DMI0TXN DMI_MRX_ITX_N0 <10>
C319 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_P1 P26 U28 DMI_MRX_ITX_P0 4.7P_0402_50V8C~D
<34> PCIE_ITX_WANRX_P1_C PETP1 DMI0TXP DMI_MRX_ITX_P0 <10> 2
PCIE_IRX_WLANTX_N2 L29 Y27 DMI_MTX_IRX_N1
<34> PCIE_IRX_WLANTX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <10>
PCIE_IRX_WLANTX_P2 L28 Y26 DMI_MTX_IRX_P1
+3.3V_ALW_ICH <34> PCIE_IRX_WLANTX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <10>
MiniWLAN (Mini Card 2)---> C320 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_N2 M27 W29 DMI_MRX_ITX_N1
<34> PCIE_ITX_WLANRX_N2_C PETN2 DMI1TXN DMI_MRX_ITX_N1 <10>
RP1 C321 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_P2 M26 W28 DMI_MRX_ITX_P1
<34> PCIE_ITX_WLANRX_P2_C PETP2 DMI1TXP DMI_MRX_ITX_P1 <10>
5 4 USB_OC0_1#
6 3 USB_OC2# PCIE_IRX_MCARDTX_N3 J29 AB27 DMI_MTX_IRX_N2 +3.3V_WLAN +3.3V_M
<34> PCIE_IRX_MCARDTX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 <10>
3.24K_0402_1%~D
3.24K_0402_1%~D
7 2 ESATA_USB_OC# PCIE_IRX_MCARDTX_P3 J28 AB26 DMI_MTX_IRX_P2
<34> PCIE_IRX_MCARDTX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <10>
PCI-Express
8 1 USB_OC4# BT/UWB---> C322 1 2 0.1U_0402_10V7K~D PCIE_ITX_MCARDRX_N3 K27 AA29 DMI_MRX_ITX_N2
<34> PCIE_ITX_MCARDRX_N3_C PETN3 DMI2TXN DMI_MRX_ITX_N2 <10>
1
C323 1 2 0.1U_0402_10V7K~D PCIE_ITX_MCARDRX_P3 K26 AA28 DMI_MRX_ITX_P2
<34> PCIE_ITX_MCARDRX_P3_C PETP3 DMI2TXP DMI_MRX_ITX_P2 <10>
R286
R287
10K_1206_8P4R_5%~D
RP2 PCIE_IRX_EXPTX_N4 G29 AD27 DMI_MTX_IRX_N3
B <32> PCIE_IRX_EXPTX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 <10> B
5 4 USB_OC6# PCIE_IRX_EXPTX_P4 G28 AD26 DMI_MTX_IRX_P3
<32> PCIE_IRX_EXPTX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 <10>
6 3 USB_OC5# C803 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_N4 H27 AC29 DMI_MRX_ITX_N3
DMI_MRX_ITX_N3 <10>
2
USB_OC7# <32> PCIE_ITX_EXPRX_N4_C C804 1 PETN4 DMI3TXN
7 2 <32> PCIE_ITX_EXPRX_P4_C 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_P4 H26 PETP4 DMI3TXP AC28 DMI_MRX_ITX_P3
DMI_MRX_ITX_P3 <10>
+CL_VREF1_ICH +CL_VREF0_ICH
8 1 USB_OC11#
453_0402_1%~D
453_0402_1%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Express card---> E29 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH# <6>
1
10K_1206_8P4R_5%~D E28 T25 CLK_PCIE_ICH 1 1
PERP5 DMI_CLKP CLK_PCIE_ICH <6>
R289
R290
1 2 USB_OC9# F27 Within 500 mils
PETN5
C324
C325
R288 10K_0402_5%~D F26 AF29
USB_OC10# PETP5 DMI_ZCOMP DMI_IRCOMP
1 2 DMI_IRCOMP AF28 1 2 +1.5V_RUN_PCIE_ICH
R291 10K_0402_5%~D PCIE_IRX_GLANTX_N6 R292 24.9_0402_1%~D 2 2
<29> PCIE_IRX_GLANTX_N6 C29
2
USB_OC8# PCIE_IRX_GLANTX_P6 PERN6/GLAN_RXN USBP0-
1
R293
2
10K_0402_5%~D
<29> PCIE_IRX_GLANTX_P6
C326 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_N6
C28
D27
PERP6/GLAN_RXP USBP0N AC5
AC4 USBP0+
USBP0- <33> ----->Right Side Top
<29> PCIE_ITX_GLANRX_N6_C PETN6/GLAN_TXN USBP0P USBP0+ <33>
10/100/1G LAN ---> C327 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_P6 USBP1-
<29> PCIE_ITX_GLANRX_P6_C R294
D26 PETP6/GLAN_TXP USBP1N AD3
AD2 USBP1+
USBP1- <33> ----->Right Side Bottom
USBP1P USBP1+ <33>
33_0402_5%~D ICH_EC_SPI_CLK USBP2-
D23 SPI_CLK USBP2N AC1 USBP2- <33> ----->Left Side Top +3.3V_M
2.2K_0402_5%~D
2.2K_0402_5%~D
ICH_SPI_CS0# 1 2 ICH_SPI_CS0#_R D24 AC2 USBP2+
200 MIL SO8 <22> ICH_SPI_CS1# SPI_CS0# USBP2P USBP2+ <33>
1
ICH_SPI_CS1# ICH_SPI_CS1#_R USBP3-
+3.3V_LAN R295
1 2 F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AA5
USBP3+
USBP3- <33> ----->Left Side Bottom
Flash ROM USBP3P AA4 USBP3+ <33>
R296
R297
C328 33_0402_5%~D ICH_EC_SPI_DO USBP4-
D25 SPI_MOSI USBP4N AB2 USBP4- <34> ----->WLAN
SPI
1 2 ICH_EC_SPI_DIN E23 AB3 USBP4+

SPI_MISO USBP4P USBP4+ <34>
1
USBP5-
AA1 USBP5- <34> ----->WWAN
2
USBP5N
1
R298 0.1U_0402_16V4Z~D USB_OC0_1# N4 AA2 USBP5+

<33> USB_OC0_1# OC0#/GPIO59 USBP5P USBP5+ <34>
For iAMT 3.3K_0402_5%~D R299 USBP6- ICH_SMBDATA 6 MEM_SDATA
3.3K_0402_5%~D USB_OC2#
N5 OC1#/GPIO40 USBP6N W5
USBP6+
USBP6- <34> ----->WPAN 1 MEM_SDATA <16,17>
U12
<33> USB_OC2#
ESATA_USB_OC#
N6 OC2#/GPIO41 USB USBP6P W4
USBP7-
USBP6+ <34>
Q27A
<33> ESATA_USB_OC# P6 Y3 USBP7- <32> ----->EXP Card
2
ICH_SPI_CS0# R301 USB_OC4# OC3#/GPIO42 USBP7N USBP7+ 2N7002DW-T/R7_SOT363-6~D

1 8 M1 Y2 USBP7+ <32>
2
2
ICH_EC_SPI_DIN 1 CS# VCC OC4#/GPIO43 USBP7P
2SPI_DIN_R1 2 SO HOLD# 7 33_0402_5%~D USB_OC5# N2 OC5#/GPIO29 USBP8N W1 USBP8-
USBP8- <35> ----->DOCK +3.3V_M
R300 3 6 SPI_CLK_R1 1 2 ICH_EC_SPI_CLK USB_OC6# M4 W2 USBP8+
WP# SCLK OC6#/GPIO30 USBP8P USBP8+ <35>
5
33_0402_5%~D SPI_DO_R1 1 2 ICH_EC_SPI_DO USB_OC7# USBP9-
4 GND SI 5
R302 33_0402_5%~D USB_OC8#
M3
N3
OC7#/GPIO31 USBP9N V2
V3 USBP9+
USBP9- <35> ----->DOCK
OC8#/GPIO44 USBP9P USBP9+ <35>
W25X32VSSIG_SO8~D USB_OC9# USBP10- ICH_SMBCLK 3 MEM_SCLK
USB_OC10#
N1
P5
OC9#/GPIO45 USBP10N U5
U4 USBP10+
USBP10- <36> ----->BIO 4
Q27B
MEM_SCLK <16,17>
A OC10#/GPIO46 USBP10P USBP10+ <36> A
+3.3V_LAN USB_OC11# USBP11- 2N7002DW-T/R7_SOT363-6~D
@ C329
P3 OC11#/GPIO47 USBP11N U1
U2 USBP11+
USBP11- <19> ----->Camera
USBP11P USBP11+ <19>
1 2 2 1 USBRBIAS AG2
R303 USBRBIAS
AG1 USBRBIAS#
1
0.1U_0402_16V4Z~D 22.6_0402_1%~D
R304 @
3.3K_0402_5%~D
R305
3.3K_0402_5%~D
Within 500 mils ICH9M REV 1.0 DELL CONFIDENTIAL/PROPRIETARY
@
U13 @ Compal Electronics, Inc.
2
ICH_SPI_CS1# 1 8 R308 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
ICH_SPI_DIN_R 1 CS# VCC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2SPI_DIN_R2 2 SO HOLD# 7 33_0402_5%~D ICH_EC_SPI_DIN 1 2 ICH_SPI_DIN_R SCHEMATIC, MB A4042
R306 3 6 SPI_CLK_R2 1 2 @ ICH_EC_SPI_CLK R307 0_0402_5%~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
33_0402_5%~D WP# SCLK SPI_DO_R2 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
4 GND SI 5 1 2 @ ICH_EC_SPI_DO Follow Daisy Chain and Star
R309 33_0402_5%~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
@ W25X32VSSIG_SO8~D
Topology. Place close to U10
pinE23 within 500mils
401533
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
U10E
+1.05V_VCCP AA26 H5
D14 VSS[1] VSS[107]
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AA27 VSS[2] VSS[108] J23
1 1 1 AA3 VSS[3] VSS[109] J26
+5V_RUN +3.3V_RUN +1.5V_RUN
2 AA6 VSS[4] VSS[110] J27
C330
C331
C332
+1.05V_VCCP R310 AB1 AC22
+1.05V_VCCP_D 1 VSS[5] VSS[111]
1 2 AA23 VSS[6] VSS[112] K28
1
2
2 2 2 U10F AB28 VSS[7] VSS[113] K29
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R311 D15 A23 A15 3 10_0805_5%~D AB29 L13
100_0402_5%~D VCCRTC VCC1_05[1] VSS[8] VSS[114]
RB751S40T1_SOD523-2~D VCC1_05[2] B15 AB4 VSS[9] VSS[115] L15
ICH_V5REF_RUN A6 C15 AB5 L2
V5REF VCC1_05[3] VSS[10] VSS[116]
D15 1 1 AC17 L26
2
1 VCC1_05[4] MMBD4148-7-F_SOT23-3~D VSS[11] VSS[117]

ICH_V5REF_RUN +1.5V_RUN +1.5V_RUN_PCIE_ICH ICH_V5REF_SUS AE1 V5REF_SUS VCC1_05[5] E15 AC26 VSS[12] VSS[118] L27
C333
C334
1 L13 F15 AC27 L5
+1.5V_RUN_PCIE_ICH VCC1_05[6] VSS[13] VSS[119]
D 1 2 AA24 VCC1_5_B[1] VCC1_05[7] L11 AC3 VSS[14] VSS[120] L7 D
C335 BLM21PG600SN1D_0805~D AA25 L12 2 2 AD1 M12
VCC1_5_B[2] VCC1_05[8] VSS[15] VSS[121]
220U_D2_4VY_R15M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
1U_0603_10V6K~D AB24 L14 AD10 M13
2 VCC1_5_B[3] VCC1_05[9] VSS[16] VSS[122]
1 AB25 VCC1_5_B[4] VCC1_05[10] L16 AD12 VSS[17] VSS[123] M14
AC24 L17 L14 +1.5V_RUN AD13 M15
1 1 1 VCC1_5_B[5] VCC1_05[11] VSS[18] VSS[124]
+ AC25 L18 BLM18PG181SN1_0603~D AD14 M16
VCC1_5_B[6] VCC1_05[12] VSS[19] VSS[125]
C336
C337
C338
C339
AD24 VCC1_5_B[7] VCC1_05[13] M11 1 2 2 1 AD17 VSS[20] VSS[126] M17
0.01U_0402_16V7K~D
10U_0805_4VAM~D
AD25 M18 R312 AD18 M23
2 2 2 2 VCC1_5_B[8] VCC1_05[14] 1_0603_1%~D VSS[21] VSS[127]
AE25 VCC1_5_B[9] VCC1_05[15] P11 1 1 AD21 VSS[22] VSS[128] M28
AE26 VCC1_5_B[10] VCC1_05[16] P18 AD28 VSS[23] VSS[129] M29
+5V_ALW +3.3V_ALW_ICH
C340
C341
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD29 VSS[24] VSS[130] N11
AE28 VCC1_5_B[12] VCC1_05[18] T18 AD4 VSS[25] VSS[131] N12
2 2
AE29 VCC1_5_B[13] U11 AD5 N13
CORE
VCC1_05[19] VSS[26] VSS[132]
1
F25 VCC1_5_B[14] VCC1_05[20] U18 AD6 VSS[27] VSS[133] N14

R313 D16 G25 V11 AD7 N15
100_0402_5%~D VCC1_5_B[15] VCC1_05[21] 5ohm@100MHz VSS[28] VSS[134]
RB751S40T1_SOD523-2~D H24 VCC1_5_B[16] VCC1_05[22] V12 AD9 VSS[29] VSS[135] N16
H25 VCC1_5_B[17] VCC1_05[23] V14 1 2 +1.05V_VCCP AE12 VSS[30] VSS[136] N17
+1.05V_VCCP
4.7U_0603_6.3V6M~D
J24 V16 L15 AE13 N18
2
ICH_V5REF_SUS VCC1_5_B[18] VCC1_05[24] BLM18PG181SN1_0603~D VSS[31] VSS[137]

J25 VCC1_5_B[19] VCC1_05[25] V17 AE14 VSS[32] VSS[138] N26
1 K24 VCC1_5_B[20] VCC1_05[26] V18 1 AE16 VSS[33] VSS[139] N27
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
K25 VCC1_5_B[21] AE17 VSS[34] VSS[140] P12
C343
C342 L23 R29 +VCCDMIPLL AE2 P13
1U_0603_10V6K~D VCC1_5_B[22] VCCDMIPLL VSS[35] VSS[141]
L24 VCC1_5_B[23] 1 1 1 AE20 VSS[36] VSS[142] P14
2 +VCC_DMI_ICH 2
L25 VCC1_5_B[24] VCC_DMI[1] W23 AE24 VSS[37] VSS[143] P15
C344
C345
C346
M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE3 VSS[38] VSS[144] P16
M25 VCC1_5_B[26] AE4 VSS[39] VSS[145] P17
N23 AB23 2 2 2 AE6 P2
VCC1_5_B[27] V_CPU_IO[1] +3.3V_RUN VSS[40] VSS[146]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE9 VSS[41] VSS[147] P23
N25 VCC1_5_B[29] AF13 VSS[42] VSS[148] P28
P24 VCC1_5_B[30] VCC3_3[1] AG29 AF16 VSS[43] VSS[149] P29
0.1U_0402_16V4Z~D
P25 VCC1_5_B[31] AF18 VSS[44] VSS[150] P4
+1.5V_RUN
VCCA3GP
R24 VCC1_5_B[32] VCC3_3[2] AJ6 +3.3V_RUN AF22 VSS[45] VSS[151] P7
+1.5V_RUN_SATAPLL +3.3V/1.5V_RUN_HDA
0.1U_0402_16V4Z~D
L16 R25 1 AH26 R11
10UH_LB2012T100MR_20%_0805~D VCC1_5_B[33] VSS[46] VSS[152]
R26 VCC1_5_B[34] VCC3_3[7] AC10 +3.3V_RUN 1 AF26 VSS[47] VSS[153] R12
C347
+VCCSATAPLLR 1 2 R27 2 1 +3.3V_RUN AF27 R13
C VCC1_5_B[35] VSS[48] VSS[154] C
C348
T24 AD19 R314 AF5 R14
VCC1_5_B[36] VCC3_3[3] 2 VSS[49] VSS[155]
10U_0805_4VAM~D
1U_0603_10V4Z~D
T27 AF20 C349 0_0603_5%~D AF7 R15
VCCP_CORE
VCC1_5_B[37] VCC3_3[4] 0.1U_0402_16V4Z~D 2 VSS[50] VSS[156]
1 1 T28 VCC1_5_B[38] VCC3_3[5] AG24 2 1 +1.5V_RUN AF9 VSS[51] VSS[157] R16
T29 AC20 1 2 @ R315 AG13 R17
VCC1_5_B[39] VCC3_3[6] VSS[52] VSS[158]
C350
C351
U24 1 0_0603_5%~D AG16 R18

VCC1_5_B[40] Choice to support GMCH VSS[53] VSS[159]
U25 VCC1_5_B[41] VCC3_3[8] B9 +3.3V_RUN AG18 VSS[54] VSS[160] R28
2 2 V24 F9 C352 AG20 T12
VCC1_5_B[42] VCC3_3[9] VSS[55] VSS[161]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V25 G3 0.1U_0402_16V4Z~D AG23 T13
VCC1_5_B[43] VCC3_3[10] 2 VSS[56] VSS[162]
U23 VCC1_5_B[44] VCC3_3[11] G6 1 1 1 AG3 VSS[57] VSS[163] T14
W24 VCC1_5_B[45] VCC3_3[12] J2 AG6 VSS[58] VSS[164] T15
C353
C354
C355
PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG9 VSS[59] VSS[165] T16
K23 VCC1_5_B[47] VCC3_3[14] K7 AH12 VSS[60] VSS[166] T17
2 2 2
Y24 VCC1_5_B[48] AH14 VSS[61] VSS[167] T23
Y25 AJ4 +3.3V_ALW_ICH AH17 B26
VCC1_5_B[49] VCCHDA +3.3V/1.5V_RUN_HDA VSS[62] VSS[168]
AH19 VSS[63] VSS[169] U12
AJ19 VCCSATAPLL VCCSUSHDA AJ3 AH2 VSS[64] VSS[170] U13
AH22 VSS[65] VSS[171] U14
AC16 AC8 TP_VCCSUS1.05_INT_ICH1 T53 PAD~D AH25 U15
VCC1_5_A[1] VCCSUS1_05[1] VSS[66] VSS[172]
1U_0603_10V4Z~D
AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 2 AH28 VSS[67] VSS[173] U16

1 AD16 TP_VCCSUS1.05_INT_ICH2 T122 PAD~D AH5 U17
VCC1_5_A[3] VSS[68] VSS[174]
ARX
AE15 AD8 VCCSUS1_5_ICH_1 C357 AH8 AD23
VCC1_5_A[4] VCCSUS1_5[1] T91 VSS[69] VSS[175]
C358
AF15 VCC1_5_A[5] 0.1U_0402_16V4Z~D AJ12 VSS[70] VSS[176] U26

VCCSUS1_5_ICH_2 1
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AJ14 VSS[71] VSS[177] U27
2
AH15 VCC1_5_A[7] AJ17 VSS[72] VSS[178] U3
AJ15 VCC1_5_A[8] AJ8 VSS[73] VSS[179] V1
A18 B11 V13
VCCPSUS
VCCSUS3_3[1] +3.3V_ALW_ICH VSS[74] VSS[180]
AC11 D16 VCCSUS1_5_ICH_2 B14 V15
VCC1_5_A[9] VCCSUS3_3[2] VSS[75] VSS[181]
1U_0603_10V4Z~D
AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 B17 VSS[76] VSS[182] V23

1 AE11 VCC1_5_A[11] VCCSUS3_3[4] E22 1 B2 VSS[77] VSS[183] V28
ATX
AF11 VCC1_5_A[12] B20 VSS[78] VSS[184] V29

C359
AG10 C360 B23 V4

VCC1_5_A[13] +3.3V_ALW_ICH VSS[79] VSS[185]
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 0.1U_0402_16V4Z~D B5 VSS[80] VSS[186] V5
2 2
AH10 VCC1_5_A[15] B8 VSS[81] VSS[187] W26
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 C26 VSS[82] VSS[188] W27
B
VCCSUS3_3[7] T2 C27 VSS[83] VSS[189] W3 B
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.1U_0402_16V4Z~D
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 E11 VSS[84] VSS[190] Y1
VCCSUS3_3[9] T4 E14 VSS[85] VSS[191] Y28
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 1 1 1 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z~D
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 E2 VSS[87] VSS[193] Y4
C361
C362
C363
U6 E21 Y5
VCCPUSB
VCCSUS3_3[12] VSS[88] VSS[194]

1 AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 E24 VSS[89] VSS[195] AG28
V6 2 2 2 E5 AH6
VCCSUS3_3[14] VSS[90] VSS[196]
C364
G10 VCC1_5_A[21] VCCSUS3_3[15] V7 E8 VSS[91] VSS[197] AF2

G9 VCC1_5_A[22] VCCSUS3_3[16] W6 F16 VSS[92] VSS[198] B25
2
0.1U_0402_16V4Z~D
VCCSUS3_3[17] W7 F28 VSS[93]

AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 F29 VSS[94] VSS_NCTF[1] A1
1 AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 G12 VSS[95] VSS_NCTF[2] A2
AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 G14 VSS[96] VSS_NCTF[3] A28
C365
G18 VSS[97] VSS_NCTF[4] A29

AJ5 G22 VCCCL1_05_ICH 1 2 G21 AH1
2 VCCUSBPLL VCCCL1_05 C366 0.1U_0402_16V4Z~D VSS[98] VSS_NCTF[5]
+3.3V_LAN G24 VSS[99] VSS_NCTF[6] AH29
0.1U_0402_16V4Z~D
AA7 G23 VCCCL1_5 G26 AJ1

VCC1_5_A[26] VCCCL1_5 VSS[100] VSS_NCTF[7]
USB CORE
AB6 VCC1_5_A[27] G27 VSS[101] VSS_NCTF[8] AJ2
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1 AB7 VCC1_5_A[28] VCCCL3_3[1] A24 +3.3V_LAN G8 VSS[102] VSS_NCTF[9] AJ28
AC6 VCC1_5_A[29] VCCCL3_3[2] B24 1 1 H2 VSS[103] VSS_NCTF[10] AJ29
C367
AC7 VCC1_5_A[30] H23 VSS[104] VSS_NCTF[11] B1
C368
C369
H28 VSS[105] VSS_NCTF[12] B29
2 VCCLAN1.05_INT_ICH
1 2 A10 VCCLAN1_05[1] H29 VSS[106]
C370 2 2
A11 VCCLAN1_05[2]
0.1U_0402_16V4Z~D ICH9M REV 1.0
A12 VCCLAN3_3[1]
B12 VCCLAN3_3[2]
A27 VCCGLANPLL
+1.5V_RUN +VCCGLANPLL
+1.5V_RUN
GLAN POWER
D28 VCCGLAN1_5[1]
+VCCGLANPLL_L 1 2 D29 VCCGLAN1_5[2]
2.2U_0603_6.3V6K~D
L17 E26 VCCGLAN1_5[3]

10U_0805_4VAM~D
4.7U_0603_6.3V6M~D
1UH_20%_0805~D E27
A VCCGLAN1_5[4] A
1 1
1 +3.3V_RUN A26 VCCGLAN3_3
C371
C372
C373
ICH9M REV 1.0

2 2
2
401533
5 4 3 2 1
5 4 3 2 1
D D
+5VMOD Source
+15V_ALW +5V_ALW
For ODD
1
+3.3V_ALW2
JSATA1 R316
1 100K_0402_5%~D
GND
1
2
5
6
+5V_MOD SATA_ODD_ITX_DRX_P1 2
<23> SATA_ODD_ITX_DRX_P1 RX+ D Q29
SATA_ODD_ITX_DRX_N1 3 R317
<23> SATA_ODD_ITX_DRX_N1
2
RX- 100K_0402_5%~D G SI3456BDV-T1-E3_TSOP6~D
4 GND
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
2 1 SATA_ODD_IRX_DTX_N1 5 2 MOD_EN 3
<23> SATA_ODD_IRX_DTX_N1_C C374 0.01U_0402_16V7K~D TX- S
1 1 6
2
TX+
3
2N7002DW-T/R7_SOT363-6
2 1 SATA_ODD_IRX_DTX_P1 7 +5V_MOD +5V_RUN
4
<23> SATA_ODD_IRX_DTX_P1_C GND
C376
C377
0.1U_0603_50V4Z~D
C375 0.01U_0402_16V7K~D PJP23
Q31B
ODD_DET# 8 1 2
2 2 <24> ODD_DET# DP
10U_0805_10V4Z~D
100K_0402_5%~D
close SATA connector +5V_MOD 9 +5V 5 1
1
10 1 @ PAD-OPEN 4x4m
+5V
6
2N7002DW-T/R7_SOT363-6
C378
11
4
MD
C379
R318
12 GND GND1 14
2
Q31A
13 GND GND2 15
2
<37> MODC_EN 2
2
TYCO_1759920-3
1
Pleace near ODD CONN R319
100K_0402_5%~D
C Main SATA +5V Default C
2
HDD PWR
For HDD +5V_ALW
JSATA2 +15V_ALW
1 GND
PSATA_ITX_DRX_P0 2
<23> PSATA_ITX_DRX_P0 RX+
PSATA_ITX_DRX_N0 3 +3.3V_ALW2
<23> PSATA_ITX_DRX_N0 RX-
1
4 GND
C380 2 1 0.01U_0402_16V7K~D PSATA_IRX_DTX_N0 5 R320
<23> PSATA_IRX_DTX_N0_C TX-
1
2
5
6
C381 2 1 0.01U_0402_16V7K~D PSATA_IRX_DTX_P0 6 100K_0402_5%~D
<23> PSATA_IRX_DTX_P0_C TX+
1
7 D Q32
GND G SI3456BDV-T1-E3_TSOP6~D
2
+3.3V_HDD 8 R321 HDD_EN_5V 3
3.3V 100K_0402_5%~D S
close SATA connector 9 3.3V
10 +5V_HDD +5V_RUN
4
3.3V
3
2N7002DW-T/R7_SOT363-6
11 PJP25
GND
0.1U_0603_50V4Z~D
+5V_HDD +3.3V_HDD HDD_DET# 12 1 2
<24> HDD_DET# GND
Q34B
10U_0805_10V4Z~D
13 GND
100K_0402_5%~D
+5V_HDD 14 5 1 1 @ PAD-OPEN 4x4m
5V
1
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_10V7K~D
15 5V Open
6
2N7002DW-T/R7_SOT363-6
C382
C383
R322
B 16 B
4
5V
1 1 1 1 1 17 GND 2 2
@ C386
@ C387
@ C388
Q34A
18 Reserved GND1 23
C384
C385
19 24 <37> HDDC_EN 2
2
GND GND2
20 12V
2 2 2 2 2
21
1
12V
1
22 12V R323
FOX_LD2122H-S4SL6_RV 100K_0402_5%~D +5V_HDD Source
2
Main SATA +5V Default +3.3V_ALW
Pleace near HDD CONN
1
2
5
6
D @ Q131
G SI3456BDV-T1-E3_TSOP6~D
3
S
+3.3V_HDD +3.3V_RUN
4
PJP42
1 2
10U_0805_10V4Z~D
@ C1020
100K_0402_5%~D
@ R974
1 @ PAD-OPEN 4x4m
1
Short
2
2
A
+3.3V_HDD Source A
Title
5 4 3 2 1
2 1
1 2 XTALO_12MHZ
R786 0_0402_5%~D
+3.3V_RUN L18
Y5 BK1608LM182-T_0603~D
1 2 XTALI_12MHZ 2 1 +3.3V_RUN_I2S_VDD
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
+3.3V_RUN +3.3V_RUN
27P_0402_50V8J~D
27P_0402_50V8J~D
2 12MHZ_18PF_X5H012000FI1H~D 2 1 2 2
C994
C995
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
C391
C392
C393
<24> SPKR 1 2 1 2 1 2
C389 0.1U_0402_16V4Z~D R327 20K_0402_5%~D 1 1 2 1 1
1 2
C395
C396
1 2 1 2 AUD_PC_BEEP
<38> BEEP
C397
C398
C394 0.1U_0402_16V4Z~D R828 20K_0402_5%~D TRACE>15 mil U15
1
2 1
R328 2 1 SSM2602
10K_0402_5%~D 3 4
+3.3V_RUN_I2S_AVDD DCVDD DVSS
18 AVDD AVSS 19
+3.3V_RUN_I2S_HPVDD 12 15
2
HPVDD HPVSS
5 DBVDD
+VDDA
AUD_DOCK_HP_L_R 24 16 AUD_DOCK_MIC_IN_L_C
+3.3V_RUN LLINEIN LOUT AUD_DOCK_MIC_IN_R_C
ROUT 17
AUD_DOCK_HP_R_R 23 RLINEIN
0.1U_0402_10V7K~D
10U_0805_10V6K~D
1U_0603_10V6K~D
1000P_0402_50V7K~D
1 1 1 DAI_SMBCLK 28 13 NC_LHPOUT T56 PAD~D

SCLK LHPOUT
10U_0805_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
@ C400
+3.3V_RUN DAI_SMBDATA 27 14 NC_RHPOUT T57 PAD~D
SDIN RHPOUT
C399
C401
1 1 1 1 +3.3V_RUN
@ C403
U16 XTALI_12MHZ 1 6 I2S_12MHZ

MCLK/XTI CLKOUT
1
2 2 2
C402
C404
C405
XTALO_12MHZ 2
@ R329 XTO/ POR I2S_BCLK
1 DVDD_CORE AVDD 25 BCLK 7
2 2 2 2 9 38 10K_0402_5%~D NC_MICIN 22
DVDD_CORE AVDD PAD~D T59 MICIN
B 40 PAD~D T60 NC_MICBIAS 21 8 I2S_DI# B
NC/OTP MICBIAS DACDAT I2S_DO
3 10
2
DVDD_IO AUD_SENSE_A ADCDAT
SENSE_A 13 25 MODE
34 AUD_SENSE_B 9 I2S_LRCLK
SENSE_B @ DACLRC NC_ADCLRC
Close to U16 pin1 & pin9 +3.3V_RUN 1 2 26 CSB ADCLRC 11 T61PAD~D
1
R330
10K_0402_5%~D
ICH_AZ_CODEC_BITCLK 6 39 R331 10K_0402_5%~D 20 29
<23> ICH_AZ_CODEC_BITCLK HDA_BITCLK PORT_A_L AUD_HP_OUT_L <28> VMID Thermal Pad
1
41 10K_0402_5%~D
PORT_A_R AUD_HP_OUT_R <28>
R333
1 2 ICH_AC_SDIN0_R 8 37 1 SSM2602_LFCSP28_5X5~D
<23> ICH_AZ_CODEC_SDIN0 HDA_SDI_CODEC NC
R332 33_0402_5%~D
2
ICH_AZ_CODEC_SDOUT 5 C406
<23> ICH_AZ_CODEC_SDOUT HDA_SDO
+3.3V_RUN 21 1U_0402_6.3V6K~D
AUD_EXT_MIC_L <33>
2
PORT_B_L 2
<23> ICH_AZ_CODEC_SYNC 10 HDA_SYNC PORT_B_R 22 AUD_EXT_MIC_R <33> Select I2C & SPI
28 +VREFOUT
VREFOUT_B interface
0.1U_0402_10V7K~D
<23> ICH_AZ_CODEC_RST# 11 HDA_RST# +3.3V_RUN +3.3V_RUN

1 PORT_C_L 23
PORT_C_R 24
C407
2.2K_0402_5%~D
2.2K_0402_5%~D
VREFOUT_C 29
1
2 92HD71B
R334
R335
PORT_D_L 35 AUD_LINE_OUT_L <28>
PORT_D_R 36 AUD_LINE_OUT_R <28>
2
<19> DMIC_CLK 1 2 DMIC_CLK_R 46
2
R338 0_0402_5%~D DMIC_CLK
Close to U16 pin3 2 14 AUD_DOCK_MIC_IN_L 2 1 AUD_DOCK_MIC_IN_L_C DAI_SMBCLK 1 6
<19> DMIC0 DMIC0/VOL_UP/GPIO1 PORT_E_L CKG_SMBCLK <6,38,48>
15 AUD_DOCK_MIC_IN_R C408 2 1 1U_0805_10V7K~D AUD_DOCK_MIC_IN_R_C
PORT_E_R C409 1U_0805_10V7K~D Q36A
4 DMIC1/VOL_DN/GPIO2 GPIO4/VREFOUT_E 31
5
R340 2N7002DW-T/R7_SOT363-6~D
Close to U16 pin6 C410 1U_0805_10V7K~D 0_0603_5%~D
16 AUD_DOCK_HP_OUT_L 2 1 AUD_DOCK_HP_L_C 1 2 AUD_DOCK_HP_L_R DAI_SMBDATA 4 3
PORT_F_L CKG_SMBDAT <6,38,48>
17 AUD_DOCK_HP_OUT_R 2 1 AUD_DOCK_HP_R_C 1 2 AUD_DOCK_HP_R_R
ICH_AZ_CODEC_BITCLK PORT_F_R C411 1U_0805_10V7K~D R342 For next version I2S. Q36B
GPIO3 30
0_0603_5%~D will disconnect SMBUS 2N7002DW-T/R7_SOT363-6~D
1
<28> AUD_EAPD 47 SPDIF_OUT_0_1/EAPD/GPIO0 Place close to U16 and PU.

@ R343 18
10_0402_5%~D NC Need check the PU
<51> SPDIF_OUT 48 SPDIF_OUT_0 NC 19 value.
NC 20
2
1
12 AUD_PC_BEEP +3.3V_RUN +3.3V_RUN
@C412
@C412 PC_BEEP
10P_0402_50V8J~D
2
0.1U_0402_16V7K~D
43 GPIO5 MONO_OUT 32
44 GPIO6
45 SPDIF_OUT_1/GPIO7
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
33 CAP2 2
CAP2
C413
@ D17
@ D18
@ D19
@ D55
27 VREFFILT
VREFFILT
10U_0805_10V6K~D
1U_0603_10V6K~D
Close to U16 pin5 7 DVSS 1 1 1
C414
C415
26 U17
AVSS
49 42 16
1
ICH_AZ_CODEC_SDOUT Thermal PAD GND AVSS VCC
2 2 I2S_BCLK 2 3
1A 1Y# DAI_BCLK# <35>
1
92HD71B8X5NLGXA1X8_QFN48_7x7~D
@ R344 I2S_LRCLK 4 5
47_0402_5%~D 2A 2Y# DAI_LRCK# <35>
I2S_DO 6 7
3A 3Y# DAI_DO# <35>
2
1 I2S_12MHZ 10 9
4A 4Y# DAI_12MHZ# <35>
@C416
@C416 12 11
0.1U_0402_10V7K~D 5A 5Y#
2 14 13 I2S_DI#
6A 6Y#
<37> EN_I2S_NB_CODEC 1 OE1#

2 1 15 OE2# GND 8
R345 +3.3V_RUN
1K_0402_5%~D
A +VDDA CD74HC366M96_SO16~D A
Place closely to Pin 34
2
Place closely to Pin 13. R346 +VDDA +3.3V_RUN +3.3V_RUN
5.11K_0402_1%~D R347 D20
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
@
AUD_SENSE_A 2 1 5.11K_0402_1%~D DA204U_SOT323-3~D
AUD_SENSE_B 2 1
+3.3V_RUN
1000P_0402_50V7K~D
1000P_0402_50V7K~D
+3.3V_RUN +3.3V_RUN +3.3V_RUN

39.2K_0402_1%~D
20K_0402_1%~D
39.2K_0402_1%~D
1 1 2 2
1
1
20K_0402_1%~D
1
1
R348
R349
C417
C420
C418
C419
1
1
100K_0402_5%~D
R352
R350
1
1
5
1
5
2 2 1 1
R351
100K_0402_5%~D R354
R353
R355 100K_0402_5%~D
P
NC
NC
2
100K_0402_5%~D 4 2 4 2
2
Y A Y A DAI_DI <35>
2
2
6
G
2
U18 U19
3
6
74LVC1G14GV_SOT753-5 74LVC1G14GV_SOT753-5
<28,33,37> AUD_HP_NB_SENSE 2 5 AUD_MIC_SWITCH <33>
Q38A Q38B 2 5
<37> DOCK_HP_DET DOCK_MIC_DET <37>
1
2N7002DW-T/R7_SOT363-6~D 2N7002DW-T/R7_SOT363-6~D
Q40A Q40B
1

SCHEMATIC, MB A4042
401533
2 1
5 4 3 2 1
+5V_SPK_AMP
C421
1 2
5
0.1U_0402_10V7K~D
AUD_HP_NB_SENSE 1 @ R357
P
<27,33,37> AUD_HP_NB_SENSE IN1
O 4 1 2
AUD_NB_MUTE 2 IN2 Speaker Connector
G
0_0402_5%~D
U20 15 mils trace JSPK1
3
1 1
INT_SPK_R1 2
INT_SPK_R2 2
3 3
D 74AHC1G08GW_SOT353-5~D INT_SPK_L1 D
4 4
INT_SPK_L2 5 5
<24> SPEAKER_DET# 6 6
+5V_SPK_AMP 7
C422 GND
8 GND
1 2 L19
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
BLM21PG600SN1D_0805~D MOLEX_53780-0670~D
5
0.1U_0402_10V7K~D 1 2 +5V_SPK_AMP
+5V_RUN
1
P
IN1 AUD_HP_EN
O 4 Place Close to Audio Chip Place Close to Audio Chip 1 1 1 1
@ C423
@ C424
@ C425
@ C426
AUD_EAPD 2 W=40mils
<27> AUD_EAPD IN2
G
+5V_SPK_AMP
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
U21
3
74AHC1G08GW_SOT353-5~D 2 2 2 2
2 2 1 2 1 2 1
C427
C428
C429
C430
C431
C432
C433
1 1 2 1 2 1 2
30
18
8
U22
VDD
SPVDD
SPVDD
C434
0 .033U_0805_50V7K~D
1 2 SPKR_INL_C 3 6 INT_SPK_L1
<27> AUD_LINE_OUT_L SPKR_LIN+ LOUT+
C435
0 .033U_0805_50V7K~D
1 2 SPKR_INR_C 2 7 INT_SPK_L2
<27> AUD_LINE_OUT_R SPKR_RIN+ LOUT-
Gain Setting
1 2 1 2 HP_INL_C 27 20 INT_SPK_R1 +5V_SPK_AMP
<27> AUD_HP_OUT_L HP_INL ROUT+
C436 R818 0_0402_5%~D
C 2.2U_1206_25V7M~D C
1 2 1 2 HP_INR_C 26 19 INT_SPK_R2
<27> AUD_HP_OUT_R HP_INR ROUT-
100K_0402_5%~D
100K_0402_5%~D
R827 0_0402_5%~D
1
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
C437
@ R359
2.2U_1206_25V7M~D 1 1 1 1 1 2 24 16 HP_SPK_L1
BYPASS HP_OUTL HP_SPK_L1 <33>
@C439
@
@C440
@
@C441
@
@C442
@
R358
C438 1U_0603_10V6K~D
C439
C440
C441
C442
AUD_SPK_ENABLE# 23 15 HP_SPK_R1 See Note 1
2
2 2 2 2 /SPKR_EN HP_OUTR HP_SPK_R1 <33>
to 2.2uF
2
AUD_HP_EN 22 AUD_GAIN1
HP_EN
AUD_AMP_MUTE# 25 31 AUD_GAIN1 AUD_GAIN2
REG_EN GAIN0
100K_0402_5%~D
100K_0402_5%~D
32 AUD_GAIN2
GAIN1
1
@ R360
+5V_SPK_AMP 17 HPVDD See Note 2
10U_0805_10V6K~D
1U_0603_10V6K~D
R361
@ R362 0_0402_5%~D
1 2 9 CPVDD SPKR_LIN- 4 1 2 RUN_ON <19,37,40,41,50>
1 2
2
C444
C445
C443
C1P 10 0.033U_0402_16V7K~D
2 1 1U_0603_10V6K~D C1P
REG_OUT 29 +VDDA
1
1M_0402_1%~D
1U_0603_10V6K~D
1U_0603_10V6K~D
C1N 12 C1N
R363
2 2 2 MINIMAM 150 mA
11 CPGND
C446
C447
C448
+5V_SPK_AMP SET
SPGND
SPGND
1
HPVSS
CPVSS
SPKR_RIN-
SGND
+5V_SPK_AMP
0.033U_0402_16V7K~D
See Note 1
2
1
1 1 1
0_0402_5%~D
TP
2
2
R366
C449
GAIN1 GAIN2 AV(inv) INPUT
14
13
28
5
21
33
R364 R367 TPA6040A4RHBR_QFN32_5X5~D IMPEDANCE
100K_0402_5%~D R365 1
100K_0402_5%~D
2
B 100K_0402_5%~D @ B
@
2 1 +CPVSS 0 0 6dB 82K ohm
1
AUD_SPK_ENABLE# 8mil
RUN_ON 1 2 AUD_AMP_MUTE# C450
R368 0_0402_5%~D 1U_0603_10V6K~D 0 1 10dB 66K ohm
6
See Note 2
1 0 15.6dB 45K ohm
<27> AUD_EAPD 2
See Note 2 *
Q42A 1 1 21.6dB 26K ohm
1
2N7002DW-T/R7_SOT363-6~D
3
R362 R366 C443 C449 R367 R368

5
<37> AUD_NB_MUTE
Q42B
* TPA6040 @ @ @
4
2N7002DW-T/R7_SOT363-6~D
9789A @ @ @
A A
401533
5 4 3 2 1
5 4 3 2 1
D D
Layout Notice : Place as close

chip as possible.
<24> PCIE_IRX_GLANTX_P6 2 1 PCIE_IRX_GLANTX_P6_C
C451 0.1U_0402_10V7K~D U23
52 26 LAN_TX0- +3.3V_ALW
GLAN_TXP MDI_N_0 LAN_TX0- <30>
<24> PCIE_IRX_GLANTX_N6 2 1 PCIE_IRX_GLANTX_N6_C 53 GLAN_TXN MDI_P_0 27 LAN_TX0+
LAN_TX0+ <30>
C452 0.1U_0402_10V7K~D
55 22 LAN_TX1-
<24> PCIE_ITX_GLANRX_P6_C GLAN_RXP MDI_N_1 LAN_TX1- <30>
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
56 23 LAN_TX1+
<24> PCIE_ITX_GLANRX_N6_C GLAN_RXN MDI_P_1 LAN_TX1+ <30> +3.3V_LAN
2 2 Q44
20 LAN_TX2- STS11NF30L_SO8~D
MDI_N_2 LAN_TX2- <30>
C453
C454
<23> LAN_CLK 1 2 LAN_CLK_R 45 JKCLK MDI_P_2 21 LAN_TX2+
LAN_TX2+ <30> 8 1
R369 33_0402_5%~D 50 7 2
<23> LAN_RSTSYNC JRSTSYNC 1 1
10U_0805_10V4Z~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
16 LAN_TX3- 6 3
MDI_N_3 LAN_TX3- <30> +3.3V_LAN
42 17 LAN_TX3+ 5 1 2 2 2 2
<23> LAN_TX0 JTXD_0 MDI_P_3 LAN_TX3+ <30>
<23> LAN_TX1 43 JTXD_1
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
C455
C456
C457
C458
C459
<23> LAN_TX2 44 3
4
JTXD_2 VDDO_33_3
VDDO_33_46 46 <40> ENAB_3VLAN 2 1 1 1 1
<23> LAN_RX0 47 JRXD_0 AVDD_33_28 28 2 2
<23> LAN_RX1 48 JRXD_1 +3.3V_LAN
C463
C464
<23> LAN_RX2 49 JRXD_2 DVDD_10_5 5 +1V_LAN_M
DVDD_10_8 8
1 1
DVDD_10_33 33
2_1210_5%~D
2_1210_5%~D
C C
DVDD_10_38 38
1
<30> LOM_ACTLED_YEL# 4 LED_0
R370
R371
<30> LOM_SPD100LED_ORG# 2 LED_1 AVDD_18_11 11 +1.8V_LAN_M
<30> LOM_SPD10LED_GRN# 1 LED_2 AVDD_18_14 14
AVDD_18_19 19
18 Trace=12mil +1.8V_LAN_M
2
AVDD_18_18
2 1 15 RSET AVDD_18_24 24
R372 4.99K_0402_1%~D 25 +3.3V_LAN_R
AVDD_18_25
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
AVDD_18_41 41
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
470P_0402_50V7K~D
470P_0402_50V7K~D
1 2 LAN_TEST_P 12 54 2 1
@ R373 0_0402_5%~D LAN_TEST_N IEEE_TEST_P AVDD_18_54 R374
13 IEEE_TEST_N AVDD_18_32 32 1 1 1 2 2 2 2 1 1
C466
30 5.1K_0402_5%~D
AVDD_18_30
C465
C467
C468
C469
C470
C471
C472
C473
2 1 34 DIS_REG10
R376 1K_0402_5%~D 29 REGCTL_PNP18
CTRL18
3
2 2 2 1 1 1 1 2 2
<24,37> LAN_PHY_PWR_CNTRL 1 2 37 LAN_DISABLE_N CTRL10 31
R1004 0_0402_5%~D Trace=12mil
1 2 36 51 REGCTL_PNP18 1
R378 10K_0402_5%~D TEST_EN RESERVED_NC
JTAG_TRST
JTAG_TMS
JTAG_TDO
JTAG_TCK
XTALO Q45
JTAG_TDI
9 XTAL2
XTALI 10 57 BCP69_SOT223~D
2
4
XTAL1 GND_PAD
+1.8V_LAN_M
1 2 XTALO
R379 0_0402_5%~D 82567LM_QFN56~D
35
40
39
7
6
10U_0805_10V4Z~D
JTAG_TDO_LAN T155 PAD~D 1
C474
1 2 XTALI JTAG_TDI_LAN T156 PAD~D
27P_0402_50V8J~D
JTAG_TMS_LAN T157 PAD~D

27P_0402_50V8J~D
Y2 JTAG_TCK_LAN T158 PAD~D

25MHZ_18PF_1BX25000CK1D~D JTAG_TRST_LAN 2
2 2 T159 PAD~D +1V_LAN_M
C475
C476
B B
1 1
4.7U_0805_10V4Z~D
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
MA use internal 1V,NOT external solutions. 1 1 2 2 2
Need to ensure
82567LM:
C477
C478
crystal at least
C479
C1024
C1025
B0 version: 1.05V 2 2 1 1 1
300uW max power
A1 version: 1V
drive-level
Follow 82567 schematic

chiplist that VCC_1.0 for
external use 10uF XR5 *2 and
0.1uF *2
for internal use 4.7uF X5R *2
and 0.1uF *3
A A
Title
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_LAN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2 2
C460
C461
C462
LAN ANALOG
1 1 1
SWITCH
56
50
38
27
18
10
4
U25
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
48 SW_LAN_TX0-
0B1 SW_LAN_TX0- <33>
47 SW_LAN_TX0+
1B1 SW_LAN_TX0+ <33>
LAN_TX0- 1 2 LAN_TX0-R 2
<29> LAN_TX0- A0
L20 36NH_0603CS-360EJTS_5%_0603~D 43 SW_LAN_TX1-
2B1 SW_LAN_TX1- <33>
LAN_TX0+ 1 2 LAN_TX0+R 3 42 SW_LAN_TX1+
<29> LAN_TX0+ A1 3B1 SW_LAN_TX1+ <33>
L21 36NH_0603CS-360EJTS_5%_0603~D
37 SW_LAN_TX2-
LAN_TX1- LAN_TX1-R 4B1 SW_LAN_TX2+ SW_LAN_TX2- <33>
<29> LAN_TX1- 1 2 7 A2 5B1 36 SW_LAN_TX2+ <33>
L22 36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ 1 2 LAN_TX1+R 8 32 SW_LAN_TX3-
<29> LAN_TX1+ A3 6B1 SW_LAN_TX3- <33>
L23 36NH_0603CS-360EJTS_5%_0603~D 31 SW_LAN_TX3+
7B1 SW_LAN_TX3+ <33>
LAN_TX2- 1 2 LAN_TX2-R 11 22 LAN_LEDACT#
<29> LAN_TX2- A4 0LED1
L24 36NH_0603CS-360EJTS_5%_0603~D 23 LINK_LED10#
LAN_TX2+ 1 LAN_TX2+R 1LED1 LINK_LED100#
<29> LAN_TX2+ 2 12 A5 2LED1 52
C L25 36NH_0603CS-360EJTS_5%_0603~D C
46 DOCK_LOM_TRD0-
0B2 DOCK_LOM_TRD0- <35>
LAN_TX3- 1 2 LAN_TX3-R 14 45 DOCK_LOM_TRD0+
<29> LAN_TX3- A6 1B2 DOCK_LOM_TRD0+ <35>
L26 36NH_0603CS-360EJTS_5%_0603~D
LAN_TX3+ 1 2 LAN_TX3+R 15 41 DOCK_LOM_TRD1-
<29> LAN_TX3+ A7 2B2 DOCK_LOM_TRD1- <35>
L27 36NH_0603CS-360EJTS_5%_0603~D 40 DOCK_LOM_TRD1+
3B2 DOCK_LOM_TRD1+ <35>
DOCKED 17 35 DOCK_LOM_TRD2-
<37> DOCKED SEL 4B2 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <35>
5B2 34 DOCK_LOM_TRD2+ <35>
19 30 DOCK_LOM_TRD3-
<29> LOM_ACTLED_YEL# LED0 6B2 DOCK_LOM_TRD3- <35>
20 29 DOCK_LOM_TRD3+
<29> LOM_SPD10LED_GRN# LED1 7B2 DOCK_LOM_TRD3+ <35>
Layout Notice : Place bead as <29> LOM_SPD100LED_ORG# 54 LED2
25 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible 0LED2 DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_ACTLED_YEL# <35>
5 NC 1LED2 26 DOCK_LOM_SPD10LED_GRN# <35>
51 DOCK_LOM_SPD100LED_ORG#
2LED2 DOCK_LOM_SPD100LED_ORG# <35>
57 PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
PI3L500-AZFEX_TQFN56~D TO
1
6
9
13
16
21
24
28
33
39
44
49
53
55
1: TO DOCK DOCK
FROM NIC DOCKED
0: TO RJ45
+3.3V_LAN
B B
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
1
@R392
@
@R393
@
@R394
@
R392
R393
R394
2
2
@C488
@ C488 1 2 0.1U_0402_16V4Z~D R384 1 2 @ 49.9_0402_1%~D LAN_TX0-
R385 1 2 @ 49.9_0402_1%~D LAN_TX0+ LOM_ACTLED_YEL#
@C489
@ C489 1 2 0.1U_0402_16V4Z~D R386 1 2 @ 49.9_0402_1%~D LAN_TX1- LOM_SPD10LED_GRN#
R387 1 2 @ 49.9_0402_1%~D LAN_TX1+ LOM_SPD100LED_ORG#
@C490
@ C490 1 2 0.1U_0402_16V4Z~D R388 1 2 @ 49.9_0402_1%~D LAN_TX2-
R389 1 2 @ 49.9_0402_1%~D LAN_TX2+
@C491
@ C491 1 2 0.1U_0402_16V4Z~D R390 1 2 @ 49.9_0402_1%~D LAN_TX3-
R391 1 2 @ 49.9_0402_1%~D LAN_TX3+
LAN_LEDACT# 1 2 LAN_ACTLED_YEL_R#
LAN_ACTLED_YEL_R# <33>
R395 150_0402_5%~D
Layout Notice : Place LINK_LED10# 1 2 LED_10_GRN_R#
LED_10_GRN_R# <33>
R396 110_0402_5%~D
termination as close as LINK_LED100# LED_100_ORG_R#
1 2 LED_100_ORG_R# <33>
ASIC as possible R397 200_0402_5%~D
The resistors need at

least 1/16W
A A
Title
5 4 3 2 1
5 4 3 2 1
0.01U_0402_16V7K~D
0.33U_0603_10V7K~D
TPBIAS0
56.2_0402_1%~D
56.2_0402_1%~D
1 1
1
U26A
R398
R399
C492
C493
R5C847-CSP208Q 2 2
<22> PCI_AD[0..31]
PCI_AD0 W12 B19 JS1394
CBS_CAD31 <32>
2
PCI_AD1 AD0 CDATA10/CAD31
V12 AD1 CDATA9/CAD30 C18 CBS_CAD30 <32> 1 1
PCI_AD2 T12 D19 TPAP0 2
AD2 CDATA1/CAD29 CBS_CAD29 <32> 2
PCI_AD3 W11 D18 TPAN0 3
PCI_AD4 V11 E19 4
PCI_AD5 T11 E16 TPBP0 5
AD5 CADR0/CAD26 CBS_CAD26 <32> 5
PCI_AD6 W9 F18 TPBN0 6
+3.3V_RUN AD6 CADR1/CAD25 CBS_CAD25 <32> 6
PCI_AD7 V9 F15 7
AD7 CADR2/CAD24 CBS_CAD24 <32> 7
1
PCI_AD8 R9 G18 8
AD8 CADR3/CAD23 CBS_CAD23 <32> <24> 1394_DET# 8
1
1 2 CB_HWSPND# PCI_AD9 W8 G15 9
D AD9 CADR4/CAD22 CBS_CAD22 <32> <37> PWR_BTN_BD_DET# 9 D
R400 10K_0402_5%~D PCI_AD10 V8 H18 R403 R401 SNIFFER_BLUE 10
AD10 CADR5/CAD21 CBS_CAD21 <32> <42> SNIFFER_BLUE 10
1 2 CBS_SPK PCI_AD11 T8 H15 56.2_0402_1%~D 56.2_0402_1%~D SNIFFER_YELLOW 11
AD11 CADR6/CAD20 CBS_CAD20 <32> <42> SNIFFER_YELLOW 11
R402 100K_0402_5%~D PCI_AD12 R8 J18 SNIFFER_PWR_SW# 12
CBS_CAD19 <32> <38> SNIFFER_PWR_SW#
2
UDIO3 PCI_AD13 AD12 CADR25/CAD19 WIRELESS_ON/OFF# 12
1 2 W7 J16 CBS_CAD18 <32> <37> WIRELESS_ON/OFF# 13
2
R405 10K_0402_5%~D PCI_AD14 AD13 CADR7/CAD18 Z3008 13
V7 AD14 CADR24/CAD17 J15 CBS_CAD17 <32> <37,38> INSTANT_ON_SW# 14 14
PCI_AD15 T7 P16 15
AD15 CADR17/CAD16 CBS_CAD16 <32> <38,39> POWER_SW#_MB 15
2
PCI_AD16 V1 P19 CBS_CAD15 2 BREATH_BLUE_LED_IO 16
AD16 IOWR#/CAD15 CBS_CAD15 <32> <42> BREATH_BLUE_LED_IO 16
PCI_AD17 U1 R19 R407 17
AD17 CADR9/CAD14 CBS_CAD14 <32> <37,42> LID_CL# 17
PCI_AD18 U2 P18 CBS_CAD13 C494 5.1K_0402_1%~D +3.3V_ALW 18
AD18 IORD#/CAD13 CBS_CAD13 <32> 18
0.1U_0402_16V4Z~D
+3.3V_RUN_PHY PCI_AD19 T1 R18 270P_0402_50V7K~D 19
AD19 CADR11/CAD12 CBS_CAD12 <32> 1 19
PCI_AD20 T2 T19 2 20
CBS_CAD11 <32>
1
AD20 OE#/CAD11 20
PCI I/F
1 2 CPS PCI_AD21 R1 T18
AD21 CE2#/CAD10 CBS_CAD10 <32>
C685
R404 0_0402_5%~D PCI_AD22 R2 U19 21
AD22 CADR10/CAD9 CBS_CAD9 <32> GND1
1 2 UDIO4 PCI_AD23 R4 U18 22
AD23 CDATA15/CAD8 CBS_CAD8 <32> 1 GND2
R406 10K_0402_5%~D PCI_AD24 P4 W17
AD24 CDATA7/CAD7 CBS_CAD7 <32>
PCI_AD25 P5 V17 Close to U26
PCI_AD26 N1 W16 HRS_FH28E-20S-0.5SH(11)
16 bit PC card I/F

PCI_AD27 N2 V16
PCI_AD28 N4 W15
PCI_AD29 N5 V15
PCI_AD30 M1 T15
PCI_AD31 M2 R14
PCI_PAR V6 F16 CBS_CC/BE3#
<22> PCI_PAR PAR REG#/CCBE3# CBS_CC/BE3# <32>
<22> PCI_C_BE0# PCI_C_BE0# T9 K18 CBS_CC/BE2#
C/BE0# CADR12/CCBE2# CBS_CC/BE2# <32>
<22> PCI_C_BE1# PCI_C_BE1# W6 P15 CBS_CC/BE1#
C/BE1# CADR8/CCBE1# CBS_CC/BE1# <32>
<22> PCI_C_BE2# PCI_C_BE2# W2 V19 CBS_CC/BE0#
C/BE2# CE1#/CCBE0# CBS_CC/BE0# <32>
<22> PCI_C_BE3# PCI_C_BE3# P2 N15 CBS_CPAR
C/BE3# CADR13/CPAR CBS_CPAR <32>
PCI_AD17 1 2 CBS_IDSEL P1 K16 CBS_CFRAME#
IDSEL CADR23/CFRAME# CBS_CFRAME# <32>
R409 100_0402_5%~D L16 CBS_CTRDY#
CADR22/CTRDY# CBS_CTRDY# <32>
PCI_REQ1# M4 K15 CBS_CIRDY#
<22> PCI_REQ1# REQ# CADR15/CIRDY# CBS_CIRDY# <32>
PCI_GNT1# M5 M16 CBS_CSTOP#
C <22> PCI_GNT1# GNT# CADR20/CSTOP# CBS_CSTOP# <32> C
PCI_FRAME# V3 L18 CBS_CDEVSEL#
<22> PCI_FRAME# FRAME# CADR21/CDEVSEL# CBS_CDEVSEL# <32>
PCI_IRDY# V4 N19 CBS_CBLOCK#
<22> PCI_IRDY# IRDY# CADR19 CBS_CBLOCK# <32>
PCI_TRDY# W4 N18 CBS_CPERR#
<22> PCI_TRDY# TRDY# CADR14/CPERR# CBS_CPERR# <32>
PCI_DEVSEL# T5 G16 CBS_CSERR#
<22> PCI_DEVSEL# DEVSEL# WAIT#/CSERR# CBS_CSERR# <32>
PCI_STOP# V5 G19 CBS_CREQ# must have clean layout
<22> PCI_STOP# STOP# INPACK#/CREQ# CBS_CREQ# <32> +3.3V_RUN +CBS_VCC
PCI_PERR# W5 M15 CBS_CGNT# U27
<22> PCI_PERR# PERR# WE#/CGNT# CBS_CGNT# <32>
PCI_SERR# T6 E18 CBS_CSTSCHNG
<22> PCI_SERR# SERR# BVD1/CSTSCHG CBS_CSTSCHNG <32>
A18 CBS_CCLKRUN# 11 9
WP/CCLKRUN# CBS_CCLKRUN# <32> VCC3IN VCCOUT
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
CBUS_GRST# G2 L19 CBS_CCLK_R 2 1 14
GBRST# CADR16/CCLK CBS_CCLK <32> +5V_RUN VCCOUT
CLK
RST&
1U_0402_6.3V6K~D
@ C497
PCI_RST# L4 M18 CBS_CINT# R410 12 1 1
<22,35> PCI_RST# PCIRST# READY/CINT# CBS_CINT# <32> VCCOUT
CLK_PCI_PCM K1 H19 CBS_CRST# 22_0402_5%~D 1
<6> CLK_PCI_PCM PCICLK RESET/CRST# CBS_CRST# <32>
C496
CLKRUN# L5 F19 CBS_CAUDIO 13
<24,37,38> CLKRUN# CLKRUN# BVD2/CAUDIO CBS_CAUDIO <32> VCC5IN
C495
1U_0402_6.3V6K~D
CB_HWSPND# F2 1 2 15
<37> CB_HWSPND# HWSPND# VCC5IN +CBS_VPP 2 2
T14 CBS_CCD1# @ C501 1
CD1#/CCD1# CBS_CCD1# <32> 2
J2 D15 CBS_CCD2# 0.01U_0402_16V7K~D
<22> PCI_PIRQD# INTA# CD2#/CCD2# CBS_CCD2# <32>
C498
K4 R16 CBS_CVS1 VPPEN0 3 8
<22> PCI_PIRQB# INTB# VS1#/CVS1 CBS_CVS1 <32> EN0 VPPOUT
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
K2 H16 CBS_CVS2 VPPEN1 4
<22> PCI_PIRQC# INTC# VS2#/CVS2 CBS_CVS2 <32> 2 EN1
AUDIO
INT &
@ C500
<24,36,37,38> IRQ_SERIRQ J4 UDIO0/SRIRQ# 1 2
H1 W18 CBS_DATA14
UDIO1 CDATA14 CBS_DATA14 <32>
C499
H2 C19 CBS_DATA2 VCC3EN# 2
UDIO2 CDATA2 CBS_DATA2 <32> VCC3_EN
UDIO3 H4 N16 CBS_DATA18 VCC5EN# 1
UDIO3 CADR18 CBS_DATA18 <32> VCC5_EN 2 1
UDIO4 H5 V13 VPPEN0
UDIO4 VPPEN0 VPPEN1
G1 UDIO5 VPPEN1 W13
G4 R13 VCC5EN# 5 7
CBS_SPK RI_OUT#/PME# VCC5EN# VCC3EN# FLG NC
F1 SPKROUT# VCC3EN# T13 16 GND NC 6
NC 10
TPAP0 B12 B1 SDCD#/MMCCD#
TPAP0 MDIO00
1394 I/F
TPAN0 A12 A2
TPBP0 TPAN0 MDIO01 R5531V002-E2-FA_SSOP16~D
B13 TPBP0 MDIO02 A3
TPBN0 A13 B3 SDWP#
TPBIAS0 TPBN0 MDIO03 CARD_PWR
D12 TPBIAS0 MDIO04 B4
+3.3V_ALW_ICH
Media Card I/F
CPS D11 A5 must have clean layout

B CBVREF CPS MDIO05 B
D13 VREF MDIO06 B5
0.01U_0402_16V7K~D
CBREXT B14 D5 MDIO07 2 1

REXT MDIO07
10K_0402_1%~D
R5C847XI A16 A6 SDCMD/MMCCMD R414 0_0402_5%~D

XI MDIO08
2
2
2 R5C847XO B16 B6 SDCLK/MMCCLK 1 2 SDCLK/MMC_CLK_R
XO MDIO09
C513
R417
A14 D6 SDDAT0/MMCDAT0 R416 0_0402_5%~D R784

FIL0 MDIO10 SDDAT1/MMCDAT1
MDIO11 E6 close to R5C847 100K_0402_5%~D
A7 SDDAT2/MMCDAT2
1 MDIO12
USB TEST
W14 B7 SDDAT3/MMCDAT3 JSD1

1
1
USBDM MDIO13 MMCDAT4 SD_DET#
V14 USBDP MDIO14 D7 <24> SD_DET# 1 1
E7 MMCDAT5 SDWP# 2
MDIO15 MMCDAT6 2
MDIO16 A8 For MMC PLUS 3 3
B8 MMCDAT7 SDCD#/MMCCD# 4
MDIO17 4
close to U26 F4 TEST1 MDIO18 D8 5 5
R7 TEST2 MDIO19 E8 6 6
SDDAT1/MMCDAT1 7
SDDAT0/MMCDAT0 7
8 8
R5C847-CSP208Q_CSP208~D MMCDAT7 9 9
10 10
MMCDAT6 11
SDCLK/MMC_CLK_R 11
12 12
+3.3V_RUN_CARD 13 13
+3.3V_RUN +3.3V_RUN_CARD 14
U28 MMCDAT5 14
15 15
CLK_PCI_PCM VPPEN0 1 2 5 1 SDCMD/MMCCMD 16
+3.3V_RUN SDCLK/MMCCLK R411 1 IN OUT 16
2 100K_0402_5%~D GND 2 MMCDAT4 17 17
@ 0.01U_0402_16V7K~D
1U_0603_10V4Z~D
150K_0402_5%~D
@R412
@ R412 100K_0402_5%~D CARD_PWR 4 3 SDDAT3/MMCDAT3 18
ON/OFF# N.C 18
1
2
10_0402_5%~D
100K_0402_5%~D
0.1U_0402_16V4Z~D
2 1 SDDAT2/MMCDAT2 19 19
1
R418
AAT4250IGV-T1_SOT23-5~D 20 20
C505
C506
R413
1
R420
21 GND1
1 2
C509
22
PCI_CBS_TERM 2
1
GND2
2
A 2 A
CBUS_GRST# HRS_FH28E-20S-0.5SH(11)
@ Close to JP5 pin5 Close to JP5 pin5 Some SD Caps move to SD board.
4.7P_0402_50V8C~D
1U_0603_10V4Z~D
2 1 R5C847XI
C514
1
2
18P_0402_50V8J~D
C516
2 X3
24.576MHz_16P_1BG24576CKIA~D
2 Compal Electronics, Inc.
C517
2 1 2 1 R5C847XO PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1 C515 R421 0_0402_5%~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
18P_0402_50V8J~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
Close to Pin A16,B16 401533
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN L28 +3.3V_RUN_PHY
BLM21AG601SN1D_0805~D
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1 1 1 1 1 1 1 1 1 1 1
C519
C520
C521
C522
C523
C776
C524
C525
C526
C527
C528
2 2 2 2 2 2 2 2 2 2 2
+1.5V_CARD
D D
+1.5V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_RUN +3.3V_SUS
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
+3.3V_RUN
0.1U_0402_16V4Z~D
1 1 1 +3.3V_CARD
1 1 1 1 U26B
C531
C532
C997
C999
C314
R5C847-CSP208Q
C529
C530
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 2 2 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
F5 J1 U52
2 2 2 2 VCC_3V GND
C134
C135
G5 VCC_3V GND J5 12 1.5Vin 1.5Vout 11
J19 VCC_3V GND K5 14 1.5Vin 1.5Vout 13 1 1 1
2 2
DIGITAL
POWER
DIGITAL
K19 VCC_3V GND E9
C356
C781
C788
W3 VCC_PCI3V GND R10
+3.3V_RUN R11 T10 2 3
VCC_PCI3V GND 3.3Vin 3.3Vout 2 2 2
R12 VCC_PCI3V GND V10 4 3.3Vin 3.3Vout 5
GND
R6 VCC_RIN GND W10
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
E13 VCC_RIN GND L15 17 AUX_IN AUX_OUT 15 +3.3V_CARDAUX

L1 VCC_ROUT GND M19
+3.3V_SUS
0.1U_0402_16V4Z~D
E14 <10,22,51> PLTRST1# PLTRST1# 6 19
VCC_ROUT SYSRST# OC#
0.47U_0402_16V4Z~D
0.01U_0402_16V7K~D
0.47U_0402_16V4Z~D
0.01U_0402_16V7K~D
1 1 1 1 A4 VCC_MD3V
1 1 1 1 +3.3V_RUN_PHY A9 1 2 20 8 1
ANALOG
AGND SHDN# PERST#
C533
C534
C535
C536
POWER
ANALOG
C801
B9 R657 100K_0402_5%~D
AGND
C537
C538
C539
C540
E10 D9 1 2 EXPRCRD_STBY_R# 1 16
2 2 2 2 AVCC_PHY3V AGND <37> EXPRCRD_STDBY# STBY# NC
E11 D14 R683 0_0402_5%~D
AVCC_PHY3V AGND
GND
2 2 2 2 EXPRCRD_PWREN# 2
A17 AVCC_PHY3V AGND A15 1 2 10 CPPE# GND 7
B17 B15 R684 100K_0402_5%~D
AVCC_PHY3V AGND CPUSB#
1 2 9 CPUSB#
R790 100K_0402_5%~D
D10 NC NC A10 <37> EXPRCRD_PWREN# 18 RCLKEN
E1 NC NC A11
R5538_QFN20~D CARD_RESET#
C
C2
D2
NC NC NC B10
B11 C
NC NC
E2 NC NC C1
L2 NC NC D1
E4 E12
NC
R5C847-CSP208Q_CSP208~D
NC
Express Card
+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_ALW
<31> CBS_CAD[0..31] +3.3V_CARD: Max. 1300mA, Average 1000mA
JCBUS1
1 GND1 GND3 35
2
CBS_CAD0 2 36 CBS_CCD1#
CBS_CAD1 CAD0 CCD1# CBS_CAD2 CBS_CCD1# <31> +1.5V_CARD R947
3 CAD1 CAD2 37
0.1U_0402_16V4Z~D
CBS_CAD3 4 38 CBS_CAD4 100K_0402_5%~D
CBS_CAD5 CAD3 CAD4 CBS_CAD6
5 CAD5 CAD6 39
CBS_CAD7 6 40 CBS_DATA14 CBS_DATA14 <31> 1
1
CBS_CC/BE0# CAD7 CB_D14 CBS_CAD8
<31> CBS_CC/BE0# 7 CCBE0# CAD8 41 1 2
C802
CBS_CAD9 8 42 CBS_CAD10 R791 0_0402_5%~D JEXP1
CBS_CAD11 CAD9 CAD10 CBS_CVS1
9 CAD11 CVS1 43 CBS_CVS1 <31> <37> EXPRCRD_DET# 1 GND1
CBS_CAD12 CBS_CAD13 2
10 CAD12 CAD13 44 2 GND2
CBS_CAD14 11 45 CBS_CAD15 1 2 3
CBS_CC/BE1# CAD14 CAD15 CBS_CAD16 R792 0_0402_5%~D GND3
<31> CBS_CC/BE1# 12 CCBE1# CAD16 46 4 GND4
CBS_CPAR 13 47 CBS_DATA18 1 USBP7_D-
<31> CBS_CPAR
CBS_CPERR# CPAR CB_D18 CBS_CBLOCK#
CBS_DATA18 <31> <24> USBP7- 1 2 2 USBP7_D+
5 USBD-
<31> CBS_CPERR# 14 CPERR# CBLOCK# 48 CBS_CBLOCK# <31> 6 USBD+
<31> CBS_CGNT# CBS_CGNT# 15 49 CBS_CSTOP# CBS_CSTOP# <31> CPUSB# 7
CBS_CINT# CGNT# CSTOP# CBS_CDEVSEL# CPUSB#
<31> CBS_CINT# 16 CINT# CDEVSEL# 50 CBS_CDEVSEL# <31> <24> USBP7+ 4 4 3 3 8 RESERVE1
+CBS_VCC 17 51 +CBS_VCC L64 @ 9
B VCC VCC EXP_SMBCLK RESERVE2 B
+CBS_VPP 18 VPP1 VPP2 52 +CBS_VPP 10 SMBCLK
<31> CBS_CCLK CBS_CCLK 19 53 CBS_CTRDY# DLW21SN900SQ2_0805~D EXP_SMBDATA 11
CCLK CTRDY# CBS_CTRDY# <31> SMBDATA
<31> CBS_CIRDY# CBS_CIRDY# 20 54 CBS_CFRAME# 12
CIRDY# CFRAME# CBS_CFRAME# <31> +1.5V_1
<31> CBS_CC/BE2# CBS_CC/BE2# 21 55 CBS_CAD17 13
CBS_CAD18 CCBE2# CAD17 CBS_CAD19 PCIE_WAKE# +1.5V_2
22 CAD18 CAD19 56 <34,37> PCIE_WAKE# 14 WAKE#
CBS_CAD20 23 57 CBS_CVS2 +3.3V_CARDAUX 15
CAD20 CVS2 CBS_CVS2 <31> +3.3VAUX
0.1U_0402_16V4Z~D
CBS_CAD21 24 58 CBS_CRST# CARD_RESET# 16
CAD21 CRST# CBS_CRST# <31> PERST#
CBS_CAD22 25 59 CBS_CSERR# +3.3V_CARD 17
CAD22 CSERR# CBS_CSERR# <31> +3.3V_1
CBS_CAD23 26 60 CBS_CREQ# 1 18
CAD23 CREQ# CBS_CREQ# <31> +3.3V_2
CBS_CAD24 27 61 CBS_CC/BE3# 19
CAD24 CCBE3# CBS_CC/BE3# <31> +3.3V_3
C789
CBS_CAD25 28 62 CBS_CAUDIO 20
CAD25 CAUDIO CBS_CAUDIO <31> <6> EXPCLK_REQ# EXPRCRD_PWREN# CLKREQ#
CBS_CAD26 29 63 CBS_CSTSCHNG 21
CAD26 CSTSCHG CBS_CSTSCHNG <31> 2 CPPE#
0.1U_0402_16V4Z~D
CBS_CAD27 30 64 CBS_CAD28 22
CBS_CAD29 CAD27 CAD28 CBS_CAD30 NC
31 CAD29 CAD30 65 <6> CLK_PCIE_EXP# 23 REFCLK-
<31> CBS_DATA2 CBS_DATA2 32 66 CBS_CAD31 1 24
CB_D2 CAD31 <6> CLK_PCIE_EXP REFCLK+
<31> CBS_CCLKRUN# CBS_CCLKRUN# 33 67 CBS_CCD2# 25
CCLKRUN# CCD2# CBS_CCD2# <31> GND5
C790
34 GND2 GND4 68 26 GND6
+3.3V_SUS 27
2 GND7
28 GND8
69 GND5 GND7 71 <24> PCIE_IRX_EXPTX_N4 29 PERN0
70 GND6 GND8 72 <24> PCIE_IRX_EXPTX_P4 30 PERP0
2.2K_0402_5%~D
2.2K_0402_5%~D
31 GND9
1
32 GND10
MOLEX_48315-0013_RT 33 GND11
R126
R127
34 GND12
<24> PCIE_ITX_EXPRX_N4_C 35 PETN0
<24> PCIE_ITX_EXPRX_P4_C 36
2
PETP0
37 GND13
6 1 EXP_SMBDATA 38
+CBS_VPP <34,38> CARD_SMBDAT GND14
+CBS_VCC 39 GND15
0.1U_0402_10V7K~D
Q112A 40
2N7002DW-T/R7_SOT363-6 GND16
2
A A
1 +3.3V_SUS 41 GND17
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
42 GND18
5
C769
Q112B
2N7002DW-T/R7_SOT363-6 HRS_FH28-40S-0.5SH(05)
2 1 1 1
C541
C542
C543
3 4 EXP_SMBCLK
<34,38> CARD_SMBCLK
2 2 2
Close to JCBUS1 Pin18/52 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Close to JCBUS1 pin51,17 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
401533
5 4 3 2 1
5 4 3 2 1
+5V_ESATA
@FUSE1
@ FUSE1
USB PORT# DESTINATION
150U_D_6.3VM_R15M~D
L0603
0.1U_0402_16V4Z~D
1 2
+5V_ESATA
1 0 JUSB1 (Ext Right Side Top)
1
+5V_ALW @ PJP26 U29 +
C544
C545
PAD-OPEN 4x4m 1 8 ESATA_USB_OC#
2 1 +5V_ALW_FUSE 2
GND
IN
OC1#
OUT1 7
ESATA_USB_OC# <24>
2 2
1 JUSB1 (Ext Right Side Bottom)
3 EN1# OUT2 6
0.1U_0402_16V4Z~D
10U_1206_16V4Z~D
<37> ESATA_USB_PWR_EN# 4 EN2# OC2# 5
1 1 TPS2062DR_SO8~D JESA1 2 JESA1 (Ext Left Side Bottom)

C546
C547
D D
1 A_VCC
USBP3_D- 2
USBP3_D+ A_D-
3
2 2 +5V_CHGUSB 4
A_D+
A_GND
3 JESA1 (Ext Left Side TOP)
5 USB
B_VCC
150U_D_6.3VM_R15M~D
0.1U_0402_16V4Z~D
USBP2_D-_SW 6
1 USBP2_D+_SW 7
B_D-
B_D+
4 WLAN
1 8 B_GND
+
C588
C548
9
2 2 <23> ESATA_ITX_DRX_P4 10
GND
A+ ESATA
5 WWAN
<23> ESATA_ITX_DRX_N4 11 A-
+5V_CHGUSB 12 GND
2 1ESATA_IRX_DTX_N4 13
U53
USB_OC2#
<23> ESATA_IRX_DTX_N4_C C549 0.01U_0402_16V7K~D 14
B-
B+
6 WPAN
1 GND OC1# 8 USB_OC2# <24> <23> ESATA_IRX_DTX_P4_C 2 1ESATA_IRX_DTX_P4 15 GND
+5V_ALW_FUSE 2 7 C550 0.01U_0402_16V7K~D
IN OUT1
3 6 2 1 1 2 16
<37> USB_POWERSHARE_PWR_EN# 4
EN1#
EN2#
OUT2
OC2# 5
<38> EN_CELL_CHARGER_DET# R986 0_0402_5%~D C1021 0.1U_0402_16V4Z~D 17
DET1
DET2
7 Express card
<37> CELL_CHARGER_DET# 2 1
TPS2062DR_SO8~D R987 0_0402_5%~D 18 G1
19
20
G2
G3
8 DOCKING
21 G4
TYCO_1759562-1
9 DOCKING
+3.3V_SUS
C
@ L30
@L30
DLW21SN121SQ2L_4P~D
U54 10 USH->BIO C
8 VCC NC 1
USBP2- 1 USBP2_D-
<24> USBP2- 1 2 2 USBP2_D+ USBP2_D+_SW
2 3
USBP2+ USBP2_D+ USBP2_D-

HSD+ D+
USBP2_D-_SW
11 Camera
<24> USBP2+ 4 4 3 3 6 HSD- D- 5
7 OE# GND 4
1 2
R425 0_0402_5%~D TS3USB31RSER @ L29
DLW21SN121SQ2L_4P~D
1 2 1 FP_USB_D+
R424 0_0402_5%~D
<36> FP_USBD+ 1 2 2
4 3 FP_USB_D-
<36> FP_USBD- 4 3
@ L31 @ U30 1 2
DLW21SN121SQ2L_4P~D 1 3 USBP2_D-_SW R422 0_0402_5%~D
USBP3- USBP3_D- GND IO2
<24> USBP3- 1 1 2 2 1 2
USBP2_D+_SW 2 4 +5V_CHGUSB R423 0_0402_5%~D
IO1 VIN
USBP3+ 4 3 USBP3_D+ PRTR5V0U2X_SOT143-4~D
<24> USBP3+ 4 3 +5V_RUN Fingerprint CONN. +3.3V_RUN
@ U55
0.1U_0402_16V4Z~D
1 2 1 3 USBP3_D- JBIO1
GND IO2
0.1U_0402_16V4Z~D
R426 0_0402_5%~D 1
1 +3.3V_RUN
USBP3_D+ 2 4 +5V_ESATA 2
IO1 VIN 2 FP_USB_D-
1 2 1 3 3 1
R427 0_0402_5%~D PRTR5V0U2X_SOT143-4~D @ 4 FP_USB_D+
4
C1015
C770
Left side USB Port Place ESD diodes as close as USB connector. 5 5 BIO_DET# <24>
6 6 1 2 +5V_RUN
2 R910 2
7 0_0603_5%~D
B JIO1 GND @ B
1 2 GND 8
1 26 DETECT_GND @ R324 0_0402_5%~D Place close to
<30> SW_LAN_TX3+ 1 26
2 27 TYCO_1734820-6
<30> SW_LAN_TX3-
3
2 27
28
AUD_EXT_MIC_L <27> JBIO1.1
3 28 AUD_EXT_MIC_R <27> ICH_AZ_MDC_RST1#
S
<30> SW_LAN_TX2- 4 4 29 29 <23> ICH_AZ_MDC_RST# 1 3
5 30 +VREFOUT Q35
<30> SW_LAN_TX2+ 5 30
6 31 2N7002W-7-F_SOT323-3~D
6 31 AUD_MIC_SWITCH <27>
1
7 32 +5V_RUN
G
<30> SW_LAN_TX1+ LAN_ACTLED_YEL_R# <30>
2
7 32 R325 @ U51
<30> SW_LAN_TX1- 8 8 33 33 LED_10_GRN_R# <30>
9 34 100K_0402_5%~D 1 3 FP_USB_D+
9 34 LED_100_ORG_R# <30> GND IO2
2
<30> SW_LAN_TX0- 10 10 35 35 +3.3V_SUS
11 36 +1.8V_LAN_M R326 FP_USB_D- 2 4
<30> SW_LAN_TX0+ +3.3V_RUN
2
11 36 IO1 VIN
12 12 37 37 USB_SIDE_EN# <37> 10K_0402_5%~D
+3.3V_LAN 13 38 PRTR5V0U2X_SOT143-4~D
13 38 USB_OC0_1# <24>
14 39
1
14 39
<24> USBP0+ 15 15 40 40 <37> MDC_RST_DIS#
<24> USBP0- 16 16 41 41 ICH_AZ_MDC_BITCLK <23>
17 42 ICH_AZ_MDC_RST1#
17 42
<24> USBP1+ 18 18 43 43 ICH_AZ_MDC_SDOUT <23>
<24> USBP1- 19 19 44 44 ICH_AZ_MDC_SYNC <23>
20 20 45 45 ICH_AZ_MDC_SDIN1 <23>
21 21 46 46 AUD_HP_NB_SENSE <27,28,37>
22 22 47 47
23 23 48 48 HP_SPK_L1 <28>
+5V_ALW 24 24 49 49 HP_SPK_R1 <28>
<24> IO_LOOP 25 25 50 50
0.1U_0402_16V4Z~D
1
TYCO_1759898-1
C623
A A
+3.3V_LAN +VREFOUT +3.3V_SUS +1.8V_LAN_M
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 1
C768
C634
C711
C712
2 2 2 2
Title
Place close Place close Place close Place close NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A
to JIO1.13 to JIO1.30 to JIO1.35 to JIO1.36 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401533
5 4 3 2 1
5 4 3 2 1
+3.3V_WLAN
+3.3V_RUN 1 2 +15V_ALW +3.3V_ALW +3.3V_WLAN
@R428
@R428 0_0402_5%~D
100K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
1
1
D
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2 WLAN_RADIO_DIS#_R 6
S
<37> WLAN_RADIO_DIS#
1
100K_0402_5%~D
R433
R434
5 4
1
R429
R430
R432
D21 2
RB751S40T1_SOD523-2~D 1 Q47
2
R431
SI3456BDV-T1-E3_TSOP6~D
2
2
2
3
WLAN_SMBCLK 1 6 CARD_SMBCLK
CARD_SMBCLK <32,38>
2
MINI_SMBCLK 1 6 CARD_SMBCLK
3
2N7002DW-T/R7_SOT363-6~D
4700P_0402_25V7K~D
Q49A
5
470K_0402_5%~D
Q48A 1 2N7002DW-T/R7_SOT363-6~D
1
Q53B
2N7002DW-T/R7_SOT363-6~D @
R435
C551
D WLAN_SMBDATA CARD_SMBDAT D
5 4 3 CARD_SMBDAT <32,38>
200K_0402_5%~D
MINI_SMBDATA 4 3 CARD_SMBDAT
6
Q53A 2 Q49B
4
1
Q48B 2N7002DW-T/R7_SOT363-6~D @ 2N7002DW-T/R7_SOT363-6~D
2
+3.3V_ALW_ICH
R436
2N7002DW-T/R7_SOT363-6~D
Mini WWAN
@
USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET#
<38> AUX_EN_WOWL 2 Mini WLAN
1
R740 0_0402_5%~D
2
+3.3V_RUN +3.3V_RUN R437 +3.3V_WLAN +3.3V_WLAN PCIE_MCARD1_DET# 1 2
JMINI1 100K_0402_5%~D R439 100K_0402_5%~D
PCIE_WAKE# 1 2 JMINI2 +1.5V_RUN
<32,37> PCIE_WAKE# 1 2 +3.3V_RUN
3 4 PCIE_WAKE# 1 2
2
3 4 COEX2_WLAN_ACTIVE R440 1 2
5 5 6 6 +1.5V_RUN 1 2 0_0402_5%~D 3 3 4 4
MINI1CLK_REQ# 7 8 +SIM_PWR COEX1_BT_ACTIVE R441 1 2 0_0402_5%~D 5 6
<6> MINI1CLK_REQ# 7 8 UIM_DATA 5 6 USB_MCARD1_DET#
9 9 10 10 <6> MINI2CLK_REQ# 7 7 8 8 1 2
CLK_PCIE_MINI1# 11 12 UIM_CLK 9 10 R438 100K_0402_5%~D
<6> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET 9 10
<6> CLK_PCIE_MINI1 13 13 14 14 <6> CLK_PCIE_MINI2# 11 11 12 12
15 16 UIM_VPP 13 14 USB_MCARD1_DET# 1 @ 2PCIE_MCARD1_DET#
15 16 <6> CLK_PCIE_MINI2 13 14 R741 0_0402_5%~D
17 17 18 18 15 15 16 16
19 20 WWAN_RADIO_DIS# 17 18
19 20 WWAN_RADIO_DIS# <37> 17 18
21 21 22 22 1 2 PLTRST3# PLTRST3# <22,36> 19 19 20 20 WLAN_RADIO_DIS#_R
PCIE_IRX_WANTX_N1 23 24 R442 0_0402_5%~D 21 22 2 1 PLTRST3#
<24> PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 23 24 PCIE_IRX_WLANTX_N2 21 22 R444 0_0402_5%~D
<24> PCIE_IRX_WANTX_P1 25 25 26 26 <24> PCIE_IRX_WLANTX_N2 23 23 24 24
27 28 PCIE_IRX_WLANTX_P2 25 26
27 28 MINI_SMBCLK <24> PCIE_IRX_WLANTX_P2 25 26
29 29 30 30 27 27 28 28
PCIE_ITX_WANRX_N1_C 31 32 MINI_SMBDATA 29 30 WLAN_SMBCLK
<24> PCIE_ITX_WANRX_N1_C 31 32 29 30
PCIE_ITX_WANRX_P1_C 33 34 PCIE_ITX_WLANRX_N2_C 31 32 WLAN_SMBDATA
<24> PCIE_ITX_WANRX_P1_C 33 34 <24> PCIE_ITX_WLANRX_N2_C 31 32
35 36 USBP5_D- COEX2_WLAN_ACTIVE PCIE_ITX_WLANRX_P2_C 33 34
35 36 <24> PCIE_ITX_WLANRX_P2_C 33 34
PCIE_MCARD2_DET# 37 38 USBP5_D+ 35 36 USBP4_D-
<22> PCIE_MCARD2_DET# 37 38 USB_MCARD2_DET# PCIE_MCARD1_DET# 35 36 USBP4_D+
39 39 40 40 USB_MCARD2_DET# <24> 1 <24> PCIE_MCARD1_DET# 37 37 38 38
41 42 LED_WWAN_OUT# 39 40 USB_MCARD1_DET#
41 42 LED_WWAN_OUT# <42> 39 40 USB_MCARD1_DET# <24>
43 44 @ C552 41 42 WIMAX LED
C 43 44 WIMAX LED 33P_0402_50V8J~D 41 42 LED_WLAN_OUT# C
45 45 46 46 1 2 43 43 44 44 LED_WLAN_OUT# <42>
@ R840 0_0402_5%~D 2
47 47 48 48 <24> ICH_CL_CLK1 45 45 46 46 1 2 LED_WPAN_OUT# LED_WPAN_OUT# <42>
49 50 For WIMAX LED debug 47 48 @ R446 0_0402_5%~D
49 50 +3.3V_RUN <24> ICH_CL_DATA1 47 48
51 51 52 52 <24> ICH_CL_RST1# 1 2 49 49 50 50
R448 0_0402_5%~D 51 52 WLAN Noise
USB_MCARD2_DET# 2 51 52
53 GND1 GND2 54 1
R447 100K_0402_5%~D 53 54 USB_MCARD1_DET#
PCIE_MCARD2_DET# 1 +1.5V_RUN +3.3V_WLAN GND1 GND2
2 1
TYCO_1775861-1~D R449 8.2K_0402_5%~D
+1.5V_RUN
330U_D2E_6.3VM_R25~D
+3.3V_RUN TYCO_1775861-1~D C553
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
@ L32
@L32 4700P_0402_25V7K~D
DLW21SN121SQ2L_4P~D 2
1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3VAM~D
33P_0402_50V8J~D
330U_D2E_6.3VM_R25~D
1 1 USBP5_D-
<24> USBP5- 2 2 1 1 1 1 1 1 1 1
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
@C557
@
C554
+ @ L33
1
C555
C556
C557
C558
C559
C560
C561
C562
1 1 1 1 1 DLW21SN121SQ2L_4P~D
+ USBP5_D+ USBP4_D+
1 1 <24> USBP5+ 4 4 3 3
2 2 2 2 2 2 2 2 2 Mini-Card Latch Remove <24> USBP4+ 1 1 2 2
C564
C565
C566
C567
C568
C563
1 2
For ME 2007/10/29
C569
C570
R450 0_0402_5%~D
2 2 2 2 2 2 USBP4_D-
2 2
1 2 Drawing <24> USBP4- 4 4 3 3
R451 0_0402_5%~D
1 2
R452 0_0402_5%~D
U31 1 2
R453 0_0402_5%~D
UIM_RESET 1 6 UIM_VPP
@
USB_MCARD3_DET# 1 2 PCIE_MCARD3_DET#
+SIM_PWR
JSIM1
2 5 +SIM_PWR WPAN Card R742 0_0402_5%~D WPAN Noise
1 5 +3.3V_RUN +3.3V_RUN USB_MCARD3_DET#
UIM_RESET VCC GND UIM_VPP UIM_CLK UIM_DATA
2 RST VPP 6 3 4
B UIM_CLK UIM_DATA JMINI3 B
3 CLK I/O 7 1
1U_0603_10V4Z~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
4 8 PCIE_WAKE# 1 2
NC NC COEX2_WLAN_ACTIVE R454 1 1 2
1 GND 9 1 1 1 1 2 0_0402_5%~D 3 3 4 4 C572
10 SRV05-4.TCT_SOT23-6~D COEX1_BT_ACTIVE R455 1 2 0_0402_5%~D 5 6 +1.5V_RUN 4700P_0402_25V7K~D
GND 5 6 2
C573
C574
C575
C576
C577
MINI3CLK_REQ# 7 8
MOLEX_475531001 <6> MINI3CLK_REQ# 7 8
9 9 10 10 1 2
2 2 2 2 2 CLK_PCIE_MINI3#
<6> CLK_PCIE_MINI3# 11 11 12 12
CLK_PCIE_MINI3 13 14 C571 4700P_0402_25V7K~D
<6> CLK_PCIE_MINI3 13 14
15 16 HOST_DEBUG_TX
15 16 HOST_DEBUG_TX <38>
HOST_DEBUG_RX 17 18
<38> HOST_DEBUG_RX MSCLK 17 18 JLAT3
<38> MSCLK 19 19 20 20 WPAN_RADIO_DIS# <37>
21 21 22 22 2 1 PLTRST3# 1 GND1
PCIE_IRX_MCARDTX_N3 23 24 R456 0_0402_5%~D 2
<24> PCIE_IRX_MCARDTX_N3 PCIE_IRX_MCARDTX_P3 23 24 +3.3V_RUN GND2
Primary Power Aux Power <24> PCIE_IRX_MCARDTX_P3 25 25 26 26 3 GND3
PWR Voltage 27 27 28 28 4 GND4
1
29 30 MINI_SMBCLK
Rail Tolerance Peak Normal Normal PCIE_ITX_MCARDRX_N3_C 31
29 30
32 MINI_SMBDATA R266 TYCO_1775868-1~D
<24> PCIE_ITX_MCARDRX_N3_C 31 32
PCIE_ITX_MCARDRX_P3_C 33 34 100K_0402_5%~D
<24> PCIE_ITX_MCARDRX_P3_C 33 34
35 36 USBP6_D-
+3.3V +-9% 1000 750 PCIE_MCARD3_DET# 37
35 36
38 USBP6_D+ Mini-Card Latch
2
<22> PCIE_MCARD3_DET# 37 38 USB_MCARD3_DET#
39 39 40 40 USB_MCARD3_DET# <24>
250 (Wake enable) +3.3V_RUN 1 2 41 42 MSDATA
41 42 MSDATA <38>
+3.3Vaux +-9% 330 250 5 (Not wake enable) R458 100K_0402_5%~D 43 44
43 44 LED_WPAN_OUT#
45 45 46 46 1 2
47 48 R459 0_0402_5%~D
+1.5V_RUN +3.3V_RUN 47 48 @ L34
+1.5V +-5% 500 375 NA 49 49 50 50
51 52 DLW21SN121SQ2L_4P~D
51 52 USBP6_D-
<24> USBP6- 1 1 2 2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
53 GND1 GND2 54
1 1 1 1 1 1 1 1 4 3 USBP6_D+
<24> USBP6+ 4 3
@C580
@
TYCO_1775861-1~D
C578
C579
C580
C581
C582
C583
C584
C585
A A
1 2
R460 0_0402_5%~D
2 2 2 2 2 2 2 2
1 2
R461 0_0402_5%~D
401533
5 4 3 2 1
2 1
JP1
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <37>
<30> DOCK_LOM_SPD10LED_GRN# 3 3 4 4 DOCK_LOM_SPD100LED_ORG# <30>
DPB_DOCK_CA_DET 5 6 DPC_CA_DET D22 @
D23 @ <21> DPB_DOCK_CA_DET 5 6 DPC_CA_DET <21,51> DPC_LANE_P0_C
7 7 8 8 1 10 DPC_LANE_P0_C
DPB_DOCK_LANE0_C 1 10 DPB_DOCK_LANE0_C DPB_DOCK_LANE0_C 9 10 DPC_LANE_P0_C
<21> DPB_DOCK_LANE0_C DPB_DOCK_LANE0#_C 9 10 DPC_LANE_N0_C DPC_LANE_P0_C <51> DPC_LANE_N0_C DPC_LANE_N0_C
<21> DPB_DOCK_LANE0#_C 11 11 12 12 DPC_LANE_N0_C <51> 2 9
DPB_DOCK_LANE0#_C 2 9 DPB_DOCK_LANE0#_C 13 14
DPB_DOCK_LANE1_C 13 14 DPC_LANE_P1_C DPC_LANE_P1_C DPC_LANE_P1_C
<21> DPB_DOCK_LANE1_C 15 15 16 16 DPC_LANE_P1_C <51> 4 7
DPB_DOCK_LANE1_C 4 7 DPB_DOCK_LANE1_C DPB_DOCK_LANE1#_C 17 18 DPC_LANE_N1_C
<21> DPB_DOCK_LANE1#_C 17 18 DPC_LANE_N1_C <51> DPC_LANE_N1_C DPC_LANE_N1_C
19 19 20 20 5 6
DPB_DOCK_LANE1#_C 5 6 DPB_DOCK_LANE1#_C DPB_DOCK_LANE2_C 21 22 DPC_LANE_P2_C
<21> DPB_DOCK_LANE2_C DPB_DOCK_LANE2#_C 21 22 DPC_LANE_N2_C DPC_LANE_P2_C <51>
<21> DPB_DOCK_LANE2#_C 23 23 24 24 DPC_LANE_N2_C <51> 3
3 25 25 26 26
DPB_DOCK_LANE3_C 27 28 DPC_LANE_P3_C 8
8 <21> DPB_DOCK_LANE3_C DPB_DOCK_LANE3#_C 27 28 DPC_LANE_N3_C DPC_LANE_P3_C <51>
<21> DPB_DOCK_LANE3#_C 29 29 30 30 DPC_LANE_N3_C <51>
31 32 RCLAMP0524P.TCT~D
RCLAMP0524P.TCT~D DPB_DOCK_AUX 31 32 DPC_DOCK_AUX_SW
<21> DPB_DOCK_AUX 33 33 34 34 DPC_DOCK_AUX_SW <21>
DPB_DOCK_AUX# 35 36 DPC_DOCK_AUX#SW
<21> DPB_DOCK_AUX# 35 36 DPC_DOCK_AUX#SW <21> D24 @
37 37 38 38
D25 @ DPB_DOCK_HPD 39 40 DPC_DOCK_HP_R DPC_LANE_P2_C 1 10 DPC_LANE_P2_C
DPB_DOCK_LANE2_C <21> DPB_DOCK_HPD 39 40
1 10 DPB_DOCK_LANE2_C 41 41 42 42 ACAV_IN_DOCK# <38,49>
43 44 DPC_LANE_N2_C 2 9 DPC_LANE_N2_C
DPB_DOCK_LANE2#_C 2 DPB_DOCK_LANE2#_C BLUE_DOCK 43 44
9 <20> BLUE_DOCK 45 45 46 46 DAT_DDC2_DOCK <20>
47 48 DPC_LANE_P3_C 4 7 DPC_LANE_P3_C
B 47 48 CLK_DDC2_DOCK <20> B
DPB_DOCK_LANE3_C 4 7 DPB_DOCK_LANE3_C 49 50
49 50 DPC_LANE_N3_C DPC_LANE_N3_C
51 51 52 52 5 6
DPB_DOCK_LANE3#_C 5 6 DPB_DOCK_LANE3#_C RED_DOCK 53 54 SATA_SBRX_DTX_P3 2 1
<20> RED_DOCK 53 54 SATA_SBRX_DTX_P3_C <23>
55 56 SATA_SBRX_DTX_N3 C586 2 1 0.01U_0402_16V7K~D 3
55 56 SATA_SBRX_DTX_N3_C <23>
3 57 58 C587 0.01U_0402_16V7K~D
GREEN_DOCK 57 58 8
<20> GREEN_DOCK 59 59 60 60 SATA_SBTX_C_DRX_P3 <23>
8 61 62
61 62 SATA_SBTX_C_DRX_N3 <23> RCLAMP0524P.TCT~D
63 63 64 64
RCLAMP0524P.TCT~D 65 66
<20> HSYNC_DOCK 65 66 USBP8+ <24>
<20> VSYNC_DOCK 67 67 68 68 USBP8- <24>
69 70 D26 @
D27 @ 69 70 DPC_DOCK_AUX_SW
<38> CLK_MSE 71 71 72 72 USBP9+ <24> 1 10 DPC_DOCK_AUX_SW
DPB_DOCK_AUX# 1 10 DPB_DOCK_AUX# 73 74
<38> DAT_MSE 73 74 USBP9- <24>
75 76 DPC_DOCK_AUX#SW 2 9 DPC_DOCK_AUX#SW
DPB_DOCK_AUX DPB_DOCK_AUX 75 76
2 9 <27> DAI_BCLK# 77 77 78 78 CLK_KBD <38>
79 80 DPC_DOCK_HP_R 4 7 DPC_DOCK_HP_R
<27> DAI_LRCK# 79 80 DAT_KBD <38>
DPB_DOCK_HPD 4 7 DPB_DOCK_HPD 81 82
81 82 DPC_CA_DET DPC_CA_DET
<27> DAI_DI 83 83 84 84 5 6
DPB_DOCK_CA_DET 5 6 DPB_DOCK_CA_DET 85 86
<27> DAI_DO# 85 86
87 87 88 88 3
3 <27> DAI_12MHZ# 89 89 90 90
91 92 8
8 91 92
93 93 94 94
95 96 RCLAMP0524P.TCT~D
RCLAMP0524P.TCT~D 95 96
<37> D_LAD0 97 97 98 98 BREATH_LED# <38,42>
<37> D_LAD1 99
101
99 100 100
102
DOCK_LOM_ACTLED_YEL# <30> Place close to JP1 connector
101 102
Place close to JP1 connector <37> D_LAD2 103
105
103 104 104
106
DOCK_LOM_TRD0+ <30>
<37> D_LAD3 105 106 DOCK_LOM_TRD0- <30>
107 107 108 108
<37> D_LFRAME# 109 109 110 110 DOCK_LOM_TRD1+ <30>
<37> D_CLKRUN# 111 111 112 112 DOCK_LOM_TRD1- <30>
113 113 114 114
<37> D_SERIRQ 115 115 116 116 TR0/1CT
<37> D_DLDRQ1# 117 117 118 118 TR2/3CT +1.8V_LAN_M
119 119 120 120
<6> CLK_PCI_DOCK 121 121 122 122 DOCK_LOM_TRD2+ <30>
123 123 124 124 DOCK_LOM_TRD2- <30>
125 125 126 126
<38> DOCK_SMB_CLK 127 127 128 128 DOCK_LOM_TRD3+ <30>
<38> DOCK_SMB_DAT 129 129 130 130 DOCK_LOM_TRD3- <30>
131 131 132 132
<38> DOCK_SMB_ALERT# 133 133 134 134 DOCK_DCIN_IS+ <48>
<43> DOCK_PSID 135 135 136 136 DOCK_DCIN_IS- <48>
137 138 +RTC_CELL
137 138
<38> DOCK_PWR_BTN# 139 139 140 140 PCI_RST# <22,31>
141 141 142 142
143 144 DOCK_DET# DOCK_DET# 2 1
<37> SLICE_BAT_PRES# 143 144 DOCK_DET# <21,37>
R124 100K_0402_5%~D
145 149 +DOCK_PWR_BAR CLK_PCI_DOCK
GND1 PWR2
+DOCK_PWR_BAR 146 PWR1 PWR2 150
1
SD05.TCT_SOD323-2~D
147 PWR1 PWR2 151
0.1U_0603_50V4Z~D
SD05.TCT_SOD323-2~D
148 152 @ R462

PWR1 GND2
1
0.1U_0603_50V4Z~D
C1016
1 10_0402_5%~D
1
C1017
D66
1 153 Shield_G Shield_G 161
D65
154 162
2
Shield_G Shield_G +3.3V_RUN
155 Shield_G Shield_G 163 1
2
156 164
2
2 Shield_G Shield_G @C590
@C590
157 165
2
Shield_G Shield_G
2
158 166 4.7P_0402_50V8C~D
Shield_G Shield_G R795 2
159 Shield_G Shield_G 167
160 Shield_G Shield_G 168 20K_0402_5%~D
1
A JAE_SP06-16082-R144-2 A
DPC_DOCK_HPD# <51>
1
D
BSS138_SOT23~D
Q114
DPC_DOCK_HP_R 2
G
S
3
100K_0402_5%~D
2
R796
1

Title
2 1
2 1
U32C
U32A +1.2V_VDDC_5880
R464
<6> CLK_PCI_TPM
BCM5880
U32B
C13
BCM5880 R4 C591
1 2
680P_0402_50V7-K~D
1
0_0402_5%~D
2
CLK_PCI_TPM
LPC_EN_R
M7
R6
LCLK SMC_ADD_0 H1
J4 F12
BCM5880 A7 +RFID_AVDD2P5
E5
F5
VDDC
VDDC
CORE_CINRUSH
CORE_PWRDN M5
D10 R463 1
1 2
2 2.2K_0402_5%~D
<37> SP_TPM_LPC_EN LPCEN SMC_ADD_1 +1.2V_PLL_5880 POR_AVSS HF_RFIDTAG_AVDD2P5 VDDC ALDO_PWRDN
PLTRST3# N5 H2 POR_EXTR G13 F7 J11 A14 R465 4.7K_0402_5%~D
<22,34> PLTRST3# GPIO_17/LRESET_N SMC_ADD_2 POR_EXTR HF_RFIDTAG_AVDD2P5 VDDC AVDD33_LDO25
LPC_LFRAME# P5 H3 G15 C6 +RFID_AVDD1P2 K11 G12 +2.5V_AVDD_5880
<23,37,38> LPC_LFRAME# GPIO_18/LFRAME_N SMC_ADD_3 POR_INT12 HF_RFIDTAG_DVDD1P2 VDDC AVDD_2P5I
4.7U_0603_6.3V6M~D
1 2 IRQ_SERIRQ_R M6 G1 G14 E10 K6 B13
<24,31,37,38> IRQ_SERIRQ GPIO_19/LSERIRQ SMC_ADD_4 POR_MONITOR HF_RX_ADC_AVDD1P2 VDDC AVDD_2P5O
1U_0603_10V4Z~D
1U_0603_10V4Z~D
R842 0_0402_5%~D LPC_LAD0 R5 H4 F9 C595 close to Pin A6 K7 A13 +3.3V_RUN 1 Place
<23,37,38> LPC_LAD0 GPIO_20/LAD[0] SMC_ADD_5 HF_RX_AVDD1P2 VDDC AVDD25_ldo12
LPC_LAD1 N6 F2 1 1 B14 G9 K9 B12 close
<23,37,38> LPC_LAD1 GPIO_21/LAD[1] SMC_ADD_6 PLL_VDD_1P2I HF_RX_AVDD2P5 VDDC AVDD25_ldo12
C932
LPC_LAD2 N7 G4 B15 D8 N4 E11 +1.2V_AVDD_5880 to
<23,37,38> LPC_LAD2
UART LPC
GPIO_22/LAD[2] SMC_ADD_7 PLL_AVDD_1P2O HF_TX_AVDD1P2 +3.3V_RUN VDDC AVDD_1P2O
C592
C593
LPC_LAD3 P6 G2 D12 A8 P4 E13
<23,37,38> LPC_LAD3 GPIO_23/LAD[3] SMC_ADD_8 PLL_VSS HF_TX_AVDD2P5 VDDC AVDD_1P2I_AUX 2 pinA14
1 2 LPD# P7 G3 D13 D9 +RFID_AVDD3P3 F13 +1.2V_PLL_5880
<37> SP_TPM_LPC_EN GPIO_24/LPCPD_N SMC_ADD_9 2 2 PLL_VDD_1P2I HF_TX_AVDD3P3 AVDD_1P2I_REF
@ R466 0_0402_5%~D E2 E12 E6 D14
UART_RX/GPIO0 SMC_ADD_10 PLL_VSS VDDO_VAR AVDD25_PLL
B5 GPIO_0/UART_RX SMC_ADD_11 F4 A15 NC 1 2 F6 VDDO_VAR OTP_PWR P15 +OTP_PWR 2 1 +3.3V_RUN
UART_TX/GPIO1 B4 F1 B6 C595 R467 0_0603_5%~D
UART_CTS GPIO_1/UART_TX SMC_ADD_12 OVSTB HF_RFIDTAG_AVSS 0.01U_0402_25V7K~D
PAD~D T171 D6 GPIO_2/UART_CTS SMC_ADD_13 F3 N9 OVSTB/ZEROB HF_RFIDTAG_VREF A6 G5 VDDO_SMC AVSS_LDO12 F11 2 1 +SC_PWR
@
SC_DET 2 1 SC_DET_R A4 D2 PAD~D T66 SCANMOD M8 C7 RFTAG_VRXN H5 C12 R829 0_0603_5%~D
R849 10K_0402_5%~D GPIO_3/UART_RTS SMC_ADD_14 SMC_ADD15 SBOOT SCANACCMODE HF_RFIDTAG_VRX_N RFTAG_VRXP VDDO_SMC AVSS_ldo25
SMC_ADD_15/REFCLK_FREQ_0 E3 P9 SECURE_BOOT HF_RFIDTAG_VRX_P B7 J5 VDDO_SMC AVSS_ldo25 D11
SPI_CLK C5 D1 SMC_ADD16 SWV M12 E7 C15
UART_RX/GPIO0 SPI_CS GPIO_6/SSP_CLK SMC_ADD_16/REFCLK_FREQ_1 SMC_ADD17 TSTMOD SWV/ERROR,OSC1,OSC2,SPL HF_RFIDTAG_VTX AVSS_AUX +1.2V_VDDC_5880
B3 GPIO_7/SSP_FSS SMC_ADD_17/BOOT_SRC_0 E1 PAD~D T68 R9 TESTMODE/TST_SEC_BOOT HF_RX_TEST0 B10 K8 VDDO_LPC AVSS_REF E15
@ R58 SPI_RXD D5 C2 SMC_ADD18 PAD~D T69 IDQ_EN R10 C10 L7 C14
GPIO_8/SSP_RXD SMC_ADD_18/BOOT_SR_1 IDDQ_EN/CM3_MODE HF_RX_TEST1 VDDO_LPC AVSS_PLL
RDIF
0_0402_5%~D SPI_TXD
SPI
A3 GPIO_9/SSP_TXD SMC_ADD_19 D3 HF_RX_TEST2 A11
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2 C1 REF_XIN F15 A12 K5 G11
SMC_ADD_20 REF_XOUT F14 REFCLK_XTALIN HF_RX_TEST3 RFREADER_RXN VDDO_33CORE VSS
SMC_ADD_21 E4 REFCLK_XTALOUT HF_RX_N C11 L5 VDDO_33CORE VSS G6
UART_TX/GPIO1 GPIO14_TER_ON/OFF C4 B1 B11 RFREADER_RXP L6 G7 2 2 2 2
BCM5880_GPIO15 GPIO_14 SMC_ADD_22 AUX_XIN HF_RX_P RFREADER_TXN1 VDDO_33CORE VSS
A2 GPIO_15 SMC_ADD_23 C3 PAD~D T70 D15 AUXCLK_XTALIN HF_TX_N C9 VSS G8
C596
C597
C598
C599
GPIO16_TER_TRIS D4 PAD~D T71 AUX_XOUT E14 B9 RFREADER_TXP1 L13 H10
GPIO_16 AUXCLK_XTALOUT HF_TX_P VDDO_33SC VSS
SMC_DATA_0 R2 M14 VDDO_33SC VSS H11
1 1 1 1
CLK
SMC_DATA_1 P3 A1 CLKOUT K13 VDDO_SC VSS H6
BootStrap
R468 1 2 22_0402_5%~D USBP10-_R R13 R1 B2 H7
B <24> USBP10- USBD_DN SMC_DATA_2 CLKOUT_EN VSS B
<24> USBP10+
R469 1 2 22_0402_5%~D USBP10+_R R14 USBD_UP SMC_DATA_3 P2 R991
HF_RFIDTAG_AVSS C8 BBCLK H14 V3P3_BBLCLK VSS H8
R470 1 2 1.5K_0402_5%~D P14 R3 0_0402_5%~D RST_N N8 D7 H9
GPIO_27/USBD_ATATCH SMC_DATA_4 SPI_RST 1 RST_N HF_RFIDTAG_AVSS VSS
SMC_DATA_5 M4 2 SPI_RST_R R8 RSTOUT_N HF_RFIDTAG_DVSS A5 2 1 H15 V3P3_PWRGOOD VSS J10
N2 E9 R471 0_0402_5%~D J12
SMC_DATA_6 HF_RX_ADC_AVSS1 +3.3V_RUN VSS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6M~D
FP_USBD- N11 N3 PAD~D T72 JTAG_CLK_USH P10 G10 TAMPER_N H13 J6
<33> FP_USBD- USBH_DN0 SMC_DATA_7 JTAG_TCK HF_RX_ADC_AVSS2 V3P3_TAMPER_N VSS
FP_USBD+ N12 P1 PAD~D T73 JTAG_TDI_USH R11 F10 J7
<33> FP_USBD+ USBH_UP0 SMC_DATA_8 JTAG_TDI HF_RX_AVSS VSS
JTAG
USBH_OC0# M11 M3 PAD~D T74 JTAG_TDO_USH N10 A10 +VDD_BBL H12 J8 2 2 1
USBH_OC_0 SMC_DATA_9 JTAG_TMS_USH JTAG_TDO HF_RX_AVSS VDD_BB VSS @
SMC_DATA_10 M2 PAD~D T75 R12 JTAG_TMS HF_TX_AVSS A9 J13 VDD_BB VSS J9
C873
C877
C933
L4 JTAG_RST#_USH P11 B8 K10
SPI
SMC_DATA_11 PAD~D T76 JTAG_TRSTN HF_TX_AVSS VSS
TER_USBH_N1 R768 1 2 22_0402_5%~D USBH_N1 N13 N1 PAD~D T77 JTCE_USH M9 E8 +3.3V_RUN L8 K12
TER_USBH_P1 USBH_DN1 SMC_DATA_12 JTCE HF_TX_AVSS VESD VSS 1 1 2
R769 1 2 22_0402_5%~D USBH_P1 P13 USBH_UP1 SMC_DATA_13 L3 VSS L12
USBH_OC1# R15 L2 L9 M13
C600 USBH_OC_1 SMC_DATA_14 SWV BCM5880KFBG_FBGA225~D VDDO_33 VSS
SMC_DATA_15 K4 1 2 L10 VDDO_33 VSS F8
680P_0402_50V7-K~D C594 680P_0402_50V7-K~D L11
@ 5880_GPIO25 VDDO_33
P8 GPIO_25/SC_SEL5V SMC_ADV_N K2
+3.3V_RUN
Smard Card
1 2 5880_GPIO26 R7 J1
GPIO_26/SC_SEL18V SMC_BLS_N_0 +3.3V_RUN +3.3V_RUN BCM5880KFBG_FBGA225~D
N15 SC_CINRUSH SMC_BLS_N_1 K1
BCM5880_SCCLK 1 2 BCM5880_SCCLK_R L14 J3
BCM5880_SCVCC SC_CLK SMC_CRE
R472 10_0402_5%~D L15 SC_VCC SMC_CS_N_0 M1 1 2 LPD# 1 2 BBCLK
+3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
PAD~DT142 BCM5880_SCRST K15 SC_RST SMC_CS_N_1 K3 R474 4.7K_0402_5%~D R473 10K_0402_5%~D
2
+1.2V_AVDD_5880 +2.5V_AVDD_5880
@R475
@
@R844
@
@R845
@
BCM5880_IO K14 P12 1 2 1 2 OVSTB 1 2 LPC_EN_R
SC_IO SMC_IO_3V
R475
R819
R844
R845
AUX1UC J14 J2 R339 R484 4.7K_0402_5%~D @ R483 4.7K_0402_5%~D
SC_FCB SMC_OE_N
2
AUX2UC J15 L1 4.7K_0402_5%~D 1 2 TAMPER_N 1 2 JTAG_RST#_USH
SC_FCB_ENB SMC_WE_N
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6M~D
BCM5880_SCDET M10 R476 R736 4.7K_0402_5%~D R737 1K_0402_5%~D
SC_DET
+SC_PWR M15 510K_0402_5%~D 1 2 RST_N 1 2 SMC_ADD15
1
SC_PWR R810 4.7K_0402_5%~D R479 4.7K_0402_5%~D SMC_ADD18
N14 SC_PWR 2 2 2 2 2 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2 SMC_ADD16 SMC_ADD17 @
C601
C602
C605
C606
C607
C934
1 2 REF_XOUT 2 2 POR_EXTR R478 4.7K_0402_5%~D USBH_OC0#
330K_0402_5%~D
R481 0_0402_5%~D BCM5880KFBG_FBGA225~D 2 1 SC_USB# USBH_OC1#
2
1 1 1 1 1 2
C935
C936
R850 10K_0402_5%~D
+3.3V_RUN
R488
1 2 1 2 REF_XIN
1 1
@
R486 10M_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
R487
2
Y3 0_0402_5%~D
R820
@ R482
R846
R847
4 3 XO R485 Function SSMC 00 01 10 11
GND OUT +3.3V_RUN
XI 1 2 +SC_VCC +3.3V_RUN 4.7K_0402_5%~D Boot SRC AD[18:17] SMC SPI USB RVD
IN GND
1 1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
27.12MHZ_18PF_9C27100001~D SBOOT REF CLK AD[16:15] RVD 24MHZ 27.12MHz 48MHz
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
C608 C609 2 2
22P_0402_50V8J~D 22P_0402_50V8J~D 2 1 2 2 2 2 2 2 2 2
2
2 2 +2.5V_AVDD_5880
C920
C1019
Pull-downs for 5880

C620
C706
C612
C613
C614
C615
C616
C617
C618
C619
@ R972 BLM18BB100SN1D_0603~D
1 1
4.7K_0402_5%~D 2 1 +RFID_AVDD2P5 Rev A0, and pull-ups
1 2 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z~D
L36
for Rev B0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
Default setting is CN part
1
+1.2V_AVDD_5880 +3.3V_RUN
2 2 1
C626
C624
C625
U33 2 1 +RFID_AVDD1P2 2 1 +RFID_AVDD3P3
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
19 L37 L38
VCC C621 1 1 2
1U_0603_10V4Z~D
3.3U_0603_10V4Z~D
GPIO14_TER_ON/OFF 24 26 4.7U_0603_6.3V6M~D
ON/OFF VPC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
BCM5880_SCCLK 2 1 7 29 8009_VDDMON 1 2 1 1 2 1
R771 10K_0402_5%~D CLKIN VDD
8 RDY VP 15 1 2
PAD~D T139
C627
C628
C629
C630
C631
C632
9 27 +LIN 2 1 2 2 2 2 2 1 1
PAD~D T63 OFF_ACK LIN L69 10UH_LQH32CN100K53L_10%~D
11 OFF_REQ
PAD~D T64 2 1 2 2 1 2
C635
C636
C637
C638
C875
C930
C931
8009_VDDMON 12 23 TER_USBH_N1 +3.3V_RUN
GPIO16_TER_TRIS CS DM
1 2 SC_USB# 13 SC_USB# DP 25 TER_USBH_P1
5880_GPIO26 R490 1 SC_DET 1 1 1 1 1 2 2
2 47K_0402_1%~D 4 CMDVCC5# PRES 14 2 1
3
5880_GPIO25 R766 1 2 47K_0402_1%~D 5 22 R773 1 2 100K_0402_5%~D SC_IO
BCM5880_SCRST R767 2 CMDVCC3# I/O
1 47K_0402_1%~D 6 RSTIN AUX1 21 R491 1 2 0_0402_5%~D SC_C4 SC_C4 & SC_C8 is for 90 ohm
BCM5880_SCDET R770 10K_0402_5%~D 32 20 R493 1 2 0_0402_5%~D SC_C8 C639 1U_0603_10V4Z~D
OFF# AUX2 R492 1 0_0402_5%~D SC_CLK RFREADER_RXN
10 TEST1 CLK 16 2 1 2 1 2
30 18 R772 0_0402_5%~D SC_RST 1 R494 3K_0402_1%~D
TEST2 RST
27P_0402_50V8J~D
27P_0402_50V8J~D
BCM5880_IO 1 I/OUC
150P_0402_50V8J~D
A AUX1UC 2 17 RFREADER_TXN1 1 2 A
AUX1UC GND 2 2
AUX2UC 3 28 1 R495 1_0402_5%~D JCS1
AUX2UC GND
C633
C898
D28 RFTAG_VRXN ANT_RFTAG_VRXN_R
@ C641
GND 31 1 2 1 2 1 1
33 2 BAS40-04_SOT23-3~D R496 4.12K_0402_1%~D C640 1U_1206_100V4Z~D 2
Therm_GND 1 1 CLK_PCI_TPM RFTAG_VRXP ANT_RFTAG_VRXP_R 2
1 2 1 2 3 3
+SC_VCC 73S8009CN 2 R497 4.12K_0402_1%~D C642 1U_1206_100V4Z~D 4 4
1
10_0402_5%~D
@ RFREADER_RXP 1 2 1 2 ANTENNA_P_C 5 5
R744
+3.3V_RUN R498 3K_0402_1%~D C643 1U_0603_10V4Z~D 6 6

10U_0805_10V4Z~D
0.47U_0402_6.3V4Z~D
When using the 73S8009C,no-stuff R768,R769,R490 RFREADER_TXP1 1 2

1 2 +3.3V_RUN R499 1_0402_5%~D 7
When using the 73S8009CN,stuff R768,R769,R490 GND
3
@
1U_0603_10V4Z~D
150P_0402_50V8J~D
CONTACTLESS_DET# 8
PCI_TPM_TERM 2
<24> CONTACTLESS_DET# GND

C958
C611
@ C647
1 MOLEX_53780-0670~D
2 1 JSC1
C644
12 GND 1
2
11 GND 2
4.7P_0402_50V8C~D
10 10
SC_RST 9 U34 D29
SC_CLK 9 SPI_TXD SPI_RXD BAS40-04_SOT23-3~D
8 1 8
2
SC_C4 8 SPI_CLK D Q
7 7 2 C VSS 7 2
6 SPI_RST 3 6 @
6 RESET# VCC
C589
5 SPI_CS 4 5 BCM5880_GPIO15
SC_IO 5 S# W#
SC_C8
4
3
4 M45PE16-VMP6TP_SO8~D 1 Compal Electronics, Inc.
SC_DET 3 Title
2 2
1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1 R210 2
1 BCM5880_GPIO15 1 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC, MB A4042
TYCO_1-1734821-0_10P~D @R341
@ R341 4.7K_0402_5%~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
+3.3V_RUN NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4.7K_0402_5%~D A
2 1
5 4 3 2 1
+3.3V_ALW
1 2 PCIE_WAKE# 1 2 SP_TPM_LPC_EN
R501 10K_0402_5%~D @R969
@ R969 10K_0402_5%~D +3.3V_ALW
1 2 USB_SIDE_EN# 1 2 LCD_TST
R502 10K_0402_5%~D R816 100K_0402_5%~D
1 2 SLICE_BAT_PRES# 2 1 PANEL_BKEN_GPU
R503 100K_0402_5%~D R505 100K_0402_5%~D 1 1 1 1
1 2 USB_POWERSHARE_PWR_EN# 1
R504 100K_0402_5%~D C648 C649 C650 C651
1 2 DCIN_CBL_DET# 0.1U_0402_16V4Z~D C652 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
R909 100K_0402_5%~D +3.3V_RUN 2 0.1U_0402_16V4Z~D 2 2 2
ESATA_USB_PWR_EN# 2
1 2
D R988 100K_0402_5%~D WIRELESS_ON/OFF# D
1 2
1 2 CELL_CHARGER_DET# R913 100K_0402_5%~D
108
R951 100K_0402_5%~D @ 2 SP_TPM_LPC_EN
34
57
85
1
1 2 PWR_BTN_BD_DET# R788 10K_0402_5%~D U35
R704 100K_0402_5%~D
VCC1
VCC1
VCC1
VCC1
PBAT_PRES# 97 +3.3V_ALW
<43> PBAT_PRES# GPIOA[0]
remove the circuit, No need for BIOS <42> SCRL_LED# 98 GPIOA[1]
+3.3V_ALW
<42> NUM_LED# 99 GPIOA[2] VCC1(VDDA33) 8
0.1U_0402_16V4Z~D
DCIN_CBL_DET# 100 14 DOCK_MIC_DET
<43> DCIN_CBL_DET# GPIOA[3] GPIOJ[7](VDDA33) DOCK_MIC_DET <27>
<49> PBATT_OFF PBATT_OFF 101 20
GPIOA[4] GPIOK[4](VDDA33) MCH_TSATN_EC <10>
PNL_LED_MASK# 102 1 VGA_IDENTIFY 1 2
PAD~D T42
<32,34> PCIE_WAKE#
PCIE_WAKE# 103
GPIOA[5]
GPIOA[6]
ECE5028-NU GPIOI[1](VCC1) 119 1.8V_RUN_ON T81 PAD~D R522 100K_0402_5%~D
C653
USB_POWERSHARE_PWR_EN# 104 SNIFFER_BLUE# 2 1
<33> USB_POWERSHARE_PWR_EN# GPIOA[7]
9 SNIFFER_BLUE# @ R507 100K_0402_5%~D
<31> WIRELESS_ON/OFF#
WIRELESS_ON/OFF#
WPAN_RADIO_DIS#
24
25
GPIOH[0]
(ECE5018) GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0) 10
13
SNIFFER_YELLOW#
DOCK_HP_DET
SNIFFER_BLUE# <42>
SNIFFER_YELLOW# <42>
2 SNIFFER_YELLOW# 2
@R508
@ R508
1
100K_0402_5%~D
<34> WPAN_RADIO_DIS# GPIOH[1] GPIOJ[6](USBDP1) DOCK_HP_DET <27>
EXPRCRD_PWREN# 26 12 CRT_SWITCH CRT_SWITCH <20> TP_DET# 2 1
<32> EXPRCRD_PWREN# GPIOH[4] GPIOJ[5](USBDN1)
EXPRCRD_STDBY# 27 15 ME_FWP ME_FWP <23> R756 100K_0402_5%~D
<32> EXPRCRD_STDBY# GPIOH[5] GPIOK[0](USBDP2)
BC_INT#_ECE5028 58 16 NB_AC_OFF
<38> BC_INT#_ECE5028
<38> BC_DAT_ECE5028
BC_DAT_ECE5028 59
BC_INT#
BC_DAT
USB GPIOK[1](USBDN2)
GPIOK[3](USBDP3) 19
NB_AC_OFF <43,49>
DP_PRIORITY <21>
+3.3V_RUN
BC_CLK_ECE5028 60 18
<38> BC_CLK_ECE5028 BC_CLK GPIOK[2](USBDN3) 2.5V_RUN_PWRGD <18,41>
21 RUN_ON D_CLKRUN# 2 1
GPIOK[5](USBDP4) RUN_ON <19,28,40,41,50>
1 22 1.5V_RUN_ON R510 100K_0402_5%~D
GPIOE[0]/RXD GPIOK[6](USBDN4) 1.5V_RUN_ON <45>
2 D_SERIRQ 2 1
QUAD_DET GPIOE[1]/TXD R511 100K_0402_5%~D
<7> QUAD_DET 3 GPIOE[2]/RTS# GPIOI[6](VDDA33PLL) 125 1 2 IMVP_VR_ON <47>
QUAD_REF_EN 4 124 R509 0_0402_5%~D D_DLDRQ1# 2 1
<7> QUAD_REF_EN GPIOE[3]/DSR# GPIOI[5](VDDA18PLL) IMVP_PWRGD <24,41,47>
EXPRCRD_DET# 5 120 0.9V_DDR_VTT_ON R512 100K_0402_5%~D
<32> EXPRCRD_DET# GPIOE[4]/CTS# GPIOI[2](VDD18) 8mil 0.9V_DDR_VTT_ON <46>
MDC_RST_DIS# 84 86 +CAP_LDO
<33> MDC_RST_DIS# GPIOE[5]/DTR# CAP_LDO
PAD~D T161 BIOS_RECOVERY 83 127 DP_MB_EN RUN_ON 2 1
GPIOE[6]/RI# GPIOJ[0](RBIAS) DP_MB_EN <21>
6 R515 100K_0402_5%~D
GPIOE[7]/DCD# 1.5V_RUN_ON 2 1
C USB_SIDE_EN# R516 100K_0402_5%~D C
<33> USB_SIDE_EN# 65 GPIOB[0]/INIT#
EN_I2S_NB_CODEC 66 1.05V_RUN_ON 2 1
<27> EN_I2S_NB_CODEC GPIOB[1]/SLCTIN#
CB_HWSPND# 67 35 2 1 R518 100K_0402_5%~D
<31> CB_HWSPND# GPIOC[2]/SCLT TEST_PIN
EN_DOCK_PWR_BAR 68 R514 3.3V_RUN_ON 2 1
<49> EN_DOCK_PWR_BAR
<48> ADAPT_OC
ADAPT_OC 69
GPIOC[3]/PE
GPIOC[4]/BUSY GPIO TEST 1K_0402_5%~D R519 100K_0402_5%~D
70 0.9V_DDR_VTT_ON 2 1
LCD_TST GPIOC[5]/ACK# R520 100K_0402_5%~D
<7,24> ITP_DBRESET# 1 2 71 GPIOC[6]/ERROR# GPIOI[7](ATEST) 126 DOCK_AC_OFF <35>
@ R517 0_0402_5%~D PSID_DISABLE# 73 PBATT_OFF 2 1
<43> PSID_DISABLE# PANEL_BKEN_GPU GPIOC[7]/ALF# R521 100K_0402_5%~D
<19> LCD_TST <51> PANEL_BKEN_GPU 74 GPIOD[0]/STROBE# GPIOI[4](XTAL1/CLKIN) 123 SIO_SLP_S3# <24>
DOCKED 75 122 3.3V_RUN_ON
<30> DOCKED
<21,35> DOCK_DET#
DOCK_DET# 76
GPIOC[1]/PD7
GPIOC[0]/PD6
CLK GPIOI[3](XTAL2) 3.3V_RUN_ON <40>
AUD_NB_MUTE 77 GFX_CORE_ON 1 2
<28> AUD_NB_MUTE CELL_CHARGER_DET# GPIOB[7]/PD5 R523 100K_0402_5%~D
<33> CELL_CHARGER_DET# 78 GPIOB[6]/PD4 LPC_LAD[0..3] <23,36,38>
LCD_VCC_TEST_EN 79 54 LPC_LAD0
<19> LCD_VCC_TEST_EN GPIOB[5]/PD3 LAD0
CCD_OFF 80 52 LPC_LAD1
<19> CCD_OFF GPIOB[4]/PD2 LAD1
AUD_HP_NB_SENSE 81 49 LPC_LAD2 +3.3V_RUN
<27,28,33> AUD_HP_NB_SENSE GPIOB[3]/PD1 LAD2
ESATA_USB_PWR_EN# 82 47 LPC_LAD3
<33> ESATA_USB_PWR_EN# GPIOB[2]/PD0 LAD3 LPC_LFRAME#
LFRAME# 42 LPC_LFRAME# <23,36,38>
2
LID_CL_SIO# 61 41 PLTRST2# CLK_PCI_5028 CLK_SIO_14M
<40> 1.05V_RUN_ON
1.05V_RUN_ON 62
GPIOD[1]
GPIOD[2]
LPC LRESET#
PCICLK 56 CLK_PCI_5028
PLTRST2# <22,38>
CLK_PCI_5028 <6>
R648
37 CLKRUN# 10K_0402_5%~D
CLKRUN# CLKRUN# <24,31,38>
1
GFX_CORE_ON 63 46 LPC_LDRQ0#
<50> GFX_CORE_ON GPIOD[3]/VBUS_DET LDRQ0# LPC_LDRQ0# <23>
INSTANT_ON_SW# 28 44 LPC_LDRQ1# @ R527 @R506
@ R506
<31,38> INSTANT_ON_SW# LPC_LDRQ1# <23>
1
GPIOD[4]/OCS1_N LDRQ1# IRQ_SERIRQ ME_FWP 10_0402_5%~D
29 GPIOD[5]/OCS2_N SER_IRQ 39 IRQ_SERIRQ <24,31,36,38> 10_0402_5%~D
HDDC_EN 30
<26> HDDC_EN GPIOD[6]/OCS3_N
2
MODC_EN 31 64 CLK_SIO_14M
<26> MODC_EN CLK_SIO_14M <6>
2
GPIOD[7]/OCS4_N CLKI (14.318 MHz) @ R649
SLICE_BAT_PRES# 32 96 10K_0402_5%~D 1 1
<35> SLICE_BAT_PRES# GPIOH[6] VSS
PWR_BTN_BD_DET# 33
<31> PWR_BTN_BD_DET# GPIOH[7]
55 D_LAD0 @ C656 @C654
@ C654
1
DLAD0 D_LAD1 D_LAD0 <35> 4.7P_0402_50V8C~D
<24,29> LAN_PHY_PWR_CNTRL 88 GPIOG[0] DLAD1 53 D_LAD1 <35> 4.7P_0402_50V8C~D
D_LAD2 2 2
<42> CAP_LED# 89 GPIOG[1] DLAD2 50 D_LAD2 <35>
B SYS_LED_MASK# D_LAD3 B
<42> SYS_LED_MASK# 90 GPIOG[2] DLPC DLAD3 48 D_LAD3 <35>
<51> GFX_OPEN_GL_EN GFX_OPEN_GL_EN 91 43 D_LFRAME# +3.3V_ALW
GPIOG[3] DLFRAME# D_LFRAME# <35>
<24> SIO_EXT_WAKE# R526 1 2 0_0402_5%~D 92 38 D_CLKRUN#
GPIOG[4] DCLK_RUN# D_CLKRUN# <35>
ICH_PME# 93 45 D_DLDRQ1#
<22> ICH_PME# GPIOG[5] DLDRQ1# D_DLDRQ1# <35>
ICH_PCIE_WAKE# 94 40 D_SERIRQ
<24> ICH_PCIE_WAKE# GPIOG[6] DSER_IRQ D_SERIRQ <35>
1
WLAN_RADIO_DIS# 95
<34> WLAN_RADIO_DIS# GPIOG[7] R524
WWAN_RADIO_DIS# 106 1M_0402_5%~D
<34> WWAN_RADIO_DIS# SYSOPT1/GPIOH[2]
107 SYSOPT0/GPIOH[3]
BID2 BID1 BID0 REV 7 RUNPWROK R525
RUNPWROK <38,41,47>
2
PWRGD 10_0402_5%~D
109 GPIOF[7]
110 105 LID_CL_SIO# 2 1 LID_CL#
0 0 0 X00 VGA_IDENTIFY 111
GPIOF[6]
GPIOF[5]
OUT65 SP_TPM_LPC_EN <36> LID_CL# <31,42>
CHIPSET_ID1 112
0 0 0 X01 R528 GPIOF[4]
GPIOJ[4](VSS) 11 GPIO_PSID_SELECT <43>
1
10K_0402_5%~D 113 17 C655
0 0 1 X02 2 1 114
IRTX
IRRX
VSS
GPIOK[7](VSS) 23
1
2
0.047U_0402_16V4Z~D
36 C657
0 1 0 X03 CHIPSET_ID0 115 GPIOF[3]/IRMODE/IRRX3B
VSS
VSS 51
2
4.7U_0603_6.3V4Z~D
BID2 116 72
0 1 1 A00 BID1 117
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
VSS
VSS 87
BID0 118 121
1 0 0 GPIOF[0]/IRMODE/IRRX3A VSS
GPIOJ[1](VSS) 128
TP_DET#
+3.3V_ALW TP_DET# <39>
ECE5028-NU_VTQFP128_14X14~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
2
2
@ R529
@R530
@
@R531
@
@ R532
@ R533
R530
R531
CHIPSET_ID1 CHIPSET_ID0
1
A A
0 0 Roush-I Foose-I
BID0 1 2
R534 10K_0402_5%~D
BID1 1
R535
2
10K_0402_5%~D
0 1 Roush-A DELL CONFIDENTIAL/PROPRIETARY
BID2 1 2
R536 10K_0402_5%~D
CHIPSET_ID0 1 2
1 0 SmFF Compal Electronics, Inc.
R537 10K_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
CHIPSET_ID1 Nike TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1
R538
2
10K_0402_5%~D
1 1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
401533
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
1
R539
100K_0402_5%~D 1 2
@ C658
2
+3.3V_ALW 1U_0402_6.3V6K~D
POWER_SW_IN# 1 2
<18> POWER_SW_IN# POWER_SW#_MB <31,39>
1 2 CKG_SMBDAT 1 R541 1K_0402_5%~D
R540 2.2K_0402_5%~D
1 2 CKG_SMBCLK +RTC_CELL +3.3V_ALW C659
R542 2.2K_0402_5%~D 1U_0603_10V4Z~D
2
1 2 BC_DAT_ECE5028 1 2 +RTC_CELL_VBAT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R543 100K_0402_5%~D R544 1
D 2 1 BC_DAT_EMC4002 0_0402_5%~D D
R545 100K_0402_5%~D C660
1 1 1 1 1 1 1 1
C661
2 1 BC_DAT_ECE1077 0.1U_0402_16V4Z~D
2
C662
C663
C664
C665
C666
C667
C668
R546 100K_0402_5%~D +RTC_CELL
2 1 DOCK_SMB_ALERT#
R547 10K_0402_5%~D 2 2 2 2 2 2 2 2
1
1 2 LCD_SMBCLK
121
116
104
R548 8.2K_0402_5%~D R550
21
44
65
83
52
4
1 2 LCD_SMBDAT U36 100K_0402_5%~D 1 2
R549 8.2K_0402_5%~D
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
1 2 PBAT_SMBDAT @ C669
2
R551 2.2K_0402_5%~D 1U_0402_6.3V6K~D
1 2 PBAT_SMBCLK <18> DOCK_PWR_SW#
DOCK_PWR_SW# 1 2 DOCK_PWR_BTN# <35>
R552 2.2K_0402_5%~D PS/2 INTERFACE MISC INTERFACE 1 R554 1K_0402_5%~D
2 1 HOST_DEBUG_RX 9 GPIO007/I2C1D_DATA/PS2_CLK0B GPIO021/RC_ID 19 RC_ID
R553 10K_0402_5%~D 10 27 DDR_ON C670
GPIO010/I2C1D_CLK/PS2_DAT0B GPIO025/UART_CLK DDR_ON <46>
2 1 BC_DAT_ECE1088 <39> CLK_TP_SIO
CLK_TP_SIO 75 GPIO110/PS2_CLK2/GPTP-IN6 VCC_PRWGD 49 RUNPWROK
RUNPWROK <37,41,47>
1U_0603_10V4Z~D
R557 100K_0402_5%~D DAT_TP_SIO 2 +RTC_CELL
<39> DAT_TP_SIO 76 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO060/KBRST 50 ICH_LAN_RST# <24>
2 1 EC_SPI_CS# <35> CLK_KBD
CLK_KBD 77 GPIO112/PS2_CLK1A GPIO101/ECGP_SCLK 67 +3.3V_ALW
R558 100K_0402_5%~D DAT_KBD 78 68 SPI Rom Remove 2007/10/29 EN_CELL_CHARGER_DET# 1 2
<35> DAT_KBD GPIO113/PS2_DAT1A GPIO102/ECGP_SOUT
2 1 LPC_LDRQ#_MEC5035 <35> CLK_MSE
CLK_MSE 79 GPIO114/PS2_CLK0A GPIO103/ECGP_SIN 69 R975 100K_0402_5%~D
2
@ R837 100K_0402_5%~D DAT_MSE 80 70 HOST_DEBUG_TX INSTANT_ON_SW# 2 1
<35> DAT_MSE GPIO115/PS2_DAT0A GPIO104/UART_TX HOST_DEBUG_TX <34>
1 2 CARD_SMBDAT PBAT_SMBDAT 111 71 HOST_DEBUG_RX R211 R560 100K_0402_5%~D
<43> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO105/UART_RX HOST_DEBUG_RX <34>
R838 2.2K_0402_5%~D PBAT_SMBCLK 112 72 RESET_OUT# 1K_0402_5%~D SNIFFER_PWR_SW# 1 2
<43> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO106/nRESET_OUT RESET_OUT# <41>
1 2 CARD_SMBCLK 81 MSDATA R562 100K_0402_5%~D
GPIO116/MSDATA MSDATA <34>
R839 2.2K_0402_5%~D 82 MSCLK SNIFFER/INSTANT_SW# 1 2
MSCLK <34>
1
HOST_DEBUG_TX GPIO117/MSCLK SIO_A20GATE RC_ID R971 100K_0402_5%~D
2 1 GPIO127/A20M 92 SIO_A20GATE <23>
4700P_0402_25V7K~D
R959 10K_0402_5%~D JTAG INTERFACE 110 PS_ID +3.3V_ALW
GPIO153/LED3 PS_ID <43>
JTAG_TDI 102 114 BAT1_LED# Bat2 = Amber LED
GPIO145/I2C1K_DATA/JTAG_TDI GPIO156/LED1 BAT1_LED# <42>
JTAG_TDO 103 115 BAT2_LED# Bat1 = Blue LED 1 DOCK_SMB_DAT 2 1
GPIO146/I2C1K_CLK/JTAG_TDO GPIO157/LED2 BAT2_LED# <42>
JTAG_CLK 105 123 FWP# R565 8.2K_0402_5%~D
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK nFWP
C480
JTAG_TMS 106 20mA drive pins DOCK_SMB_CLK 2 1
JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS R567 8.2K_0402_5%~D
107 JTAG_RST# 2 +5V_RUN
2 1 M_ON GENERAL PURPOSE I/O
R561 1M_0402_5%~D 2 SIO_SLP_M# CLK_KBD 2 1
GPIO001 SIO_SLP_M# <24>
1 2 AUX_ON FAN PWM & TACH 3 DOCK_SMB_ALERT# R569 4.7K_0402_5%~D
R563 2.7K_0402_5%~D ACAV_IN_DOCK# GPIO002 ME_WOL_EN DOCK_SMB_ALERT# <35> DAT_KBD
C <35,49> ACAV_IN_DOCK# 41 GPIO050/FAN_TACH1 GPIO014/GPTP-IN7 14 ME_WOL_EN <24> 2 1 C
1 2 DDR_ON SUS_ON 42 15 ME_SUS_PWR_ACK R570 4.7K_0402_5%~D
<40,41> SUS_ON GPIO051/FAN_TACH2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <24>
R564 100K_0402_5%~D 43 16 1.8V_SUS_PWRGD CLK_MSE 2 1
GPIO052/FAN_TACH3 GPIO016/GPTP-IN8 1.8V_SUS_PWRGD <46>
1 2 SUS_ON BREATH_LED# 45 17 ICH_CL_PWROK R571 4.7K_0402_5%~D
<35,42> BREATH_LED# GPIO053/PWM0 GPIO017/GPTP-OUT8 ICH_CL_PWROK <10,24>
R566 100K_0402_5%~D ICH_ALW_ON 46 18 3.3V_LAN_PWRGD DAT_MSE 2 1
<40> ICH_ALW_ON GPIO054/PWM1 GPIO020 3.3V_LAN_PWRGD <41>
1 2 ICH_ALW_ON 47 28 1.05V_M_PWRGD R572 4.7K_0402_5%~D
<39> KYBRD_BKLT_PWM GPIO055/PWM2 GPIO26/GPTP-IN1 1.05V_M_PWRGD <45>
R568 100K_0402_5%~D EC_SPI_CS# 48 29 ALW_PWRGD_3V_5V AC_PRESENT 1 2
GPIO056/PWM3 GPIO27/GPTP-OUT1 ALW_PWRGD_3V_5V <44>
30 SUSPWROK R573 10K_0402_5%~D
GPIO30/GPTP-IN2 SUSPWROK <41>
31 SIO_SLP_S5# +3.3V_ALW
GPIO31/GPTP-OUT2 SIO_SLP_S5# <24>
32 BEEP
GPIO032/GPTP-IN3 BEEP <27>
BC-LINK 33 AUX_ON
GPIO040/GPTP-OUT3 AUX_ON <40>
BC_CLK_EMC4002 23 34 +3.3V_ALW
<18> BC_CLK_EMC4002 GPIO022/BCM_B_CLK/V_CLK GPIO041
2
<18> BC_DAT_EMC4002 BC_DAT_EMC4002 24 73
GPIO023/BCM_B_DAT/V_DATA GPIO107 3.3V_M_PWRGD <18,41>
<18> BC_INT#_EMC4002 BC_INT#_EMC4002 25 84 R578
GPIO024/BCM_B_INT#/V_FRAME GPIO120 AUX_EN_WOWL <34>
2
+3.3V_ALW 35 89 10K_0402_5%~D
GPIO042/BCM_C_INT# GPIO124/GPTP-OUT5 SIO_SLP_S4# <24>
Remove ECE1088 (2007/10/29) BC_DAT_ECE1088 36 90 M_ON R579
GPIO043/BCM_C_DAT GPIO125/GPTP-IN5 M_ON <40,45>
37 91 ICH_RSMRST# 10K_0402_5%~D
ICH_RSMRST# <24>
1
GPIO044/BCM_C_CLK GPIO126
100K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
<39> BC_INT#_ECE1077 BC_INT#_ECE1077 38 108 AC_PRESENT FWP#

GPIO045/LSBCM_D_INT# GPIO151/GPTP-IN4 AC_PRESENT <24>
1
<39> BC_DAT_ECE1077 BC_DAT_ECE1077 39 109 SIO_PWRBTN#

SIO_PWRBTN# <24>
1
GPIO046/LSBCM_D_DAT GPIO152/GPTP-OUT4
R574
BC_CLK_ECE1077 40
<39> BC_CLK_ECE1077 GPIO047/LSBCM_D_CLK
R575
R576
BC_INT#_ECE5028 85 JTAG_RST#
<37> BC_INT#_ECE5028 GPIO121/BCM_A_INT#
2
BC_DAT_ECE5028 86
<37> BC_DAT_ECE5028 GPIO122/BCM_A_DAT
100_0402_1%~D
BC_CLK_ECE5028 @ R586
0.1U_0402_16V7K~D
<37> BC_CLK_ECE5028 87 SMBUS INTERFACE 1
2
GPIO123/BCM_A_CLK
1
JDEG1 5 DOCK_SMB_DAT 10K_0402_5%~D
GPIO003/I2C1A_DATA DOCK_SMB_DAT <35>
C978
DOCK_SMB_CLK
5 5 GPIO004/I2C1A_CLK 6 DOCK_SMB_CLK <35>
1
R585
MSDATA LCD_SMBDAT
4 4 7 LCD_SMBDAT <19>
1
MSCLK GPIO005/I2C1B_DATA LCD_SMBCLK @ 2
3 3 HOST INTERFACE 8
1
GPIO006/I2C1B_CLK LCD_SMBCLK <19>
HOST_DEBUG_RX SIO_EXT_SMI# CKG_SMBDAT
2 2 1 2 <24> SIO_EXT_SMI# 11 12 CKG_SMBDAT <6,27,48>
2
R577 0_0402_5%~D SIO_RCIN# GPIO011/nSMI GPIO012/I2C1H_DATA/I2C2D_DATA CKG_SMBCLK
1 1 <23> SIO_RCIN# LPC_LDRQ#_MEC5035
54 GPIO061/LPCPD# GPIO013/I2C1H_CLK/I2C2D_CLK 13 CKG_SMBCLK <6,27,48>
55 LDRQ# GPIO130/I2C2A_DATA 93 AMT_SMBDAT <24>
Molex_53261 IRQ_SERIRQ 56 94
<24,31,36,37> IRQ_SERIRQ SER_IRQ GPIO131/I2C2A_CLK AMT_SMBCLK <24>
PLTRST2# 57 95 ACAV_IN_NB
+3.3V_ALW <22,37> PLTRST2# LRESET# GPIO132/I2C1G_DATA
CLK_PCI_5035 58 96
<6> CLK_PCI_5035 PCI_CLK GPIO140/I2C1G_CLK
2
LPC_LFRAME# 59 97 CARD_SMBDAT
<23,36,37> LPC_LFRAME# LFRAME# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <32,34>
LPC_LAD0 60 98 CARD_SMBCLK
<23,36,37> LPC_LAD0 CARD_SMBCLK <32,34>
2
LPC_LAD1 LAD0 GPIO142/I2C1F_CLK/I2C2B_CLK +RTC_CELL EC_JTAG_RST_PAD1
<23,36,37> LPC_LAD1 61 LAD1 GPIO143/I2C1E_DATA 99
10K_0402_5%~D
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
LPC_LAD2 62 100
<23,36,37> LPC_LAD2 LAD2 GPIO144/I2C1E_CLK
1
B LPC_LAD3 63 1 2 @SHORT PADS~D B

<23,36,37> LPC_LAD3 LAD3
R580
R581
R582
R583
CLKRUN#
R584
<24,31,37> CLKRUN# 64 CLKRUN#

SIO_EXT_SCI# 66 C827 0.1U_0402_16V4Z~D
<24> SIO_EXT_SCI# GPIO100/nEC_SCI
5
DELL PWR SW INF
118 2 INSTANT_ON_SW#
P
INSTANT_ON_SW# <31,37>
2
@ JP2 BGPO0 SNIFFER/INSTANT_SW# A

VCI_IN2# 119 4 Y
1 MASTER CLOCK 120 ALWON 1 SNIFFER_PWR_SW# 1=JTAG interface Reset disabled
1 VCI_OUT ALWON <44> B SNIFFER_PWR_SW# <31>
G
2 JTAG_TDI MEC5035_XTAL1 122 126 EN_CELL_CHARGER_DET# 0=Reset JTAG interface
2 XTAL1 VCI_IN1# EN_CELL_CHARGER_DET# <33>
7 3 JTAG_TMS MEC5035_XTAL2 2 1 124 127 POWER_SW_IN# 74AHCT1G08GW_SOT353-5~D
3
G1 3 JTAG_CLK R587 0_0402_5%~D XTAL2 VCI_IN0# ACAV_IN_MB/DOCK
8 G2 4 4 117 GPIO160/32KHZ_OUT VCI_OVRD_IN 128 U62
JTAG_TDO DOCK_PWR_SW#
thermal GND
5 5 <18> EC_32KHZ_OUT VCI_IN3# 1

VR_CAP[1]
6 6
VSS_RO
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
AGND
ACES_85204-06001~D
+RTC_CELL
MEC5035_XVTQFP128_14X14~D
1+5035_AGND 125
26
51
74
88
113
20
53
22
+5035_VSS 101
129
1 2
15mil
Place closely pin 58 C846 0.1U_0402_16V4Z~D

32 KHz Clock
15mil
5
U64
Same as Laguna CLK_PCI_5035 1 ACAV_IN_NB
P
ACAV_IN_NB <48>
8mil +VR_CAP
INA
<18> ACAV_IN_MB/DOCK 4 O
1
MEC5035_XTAL1 2 ACAV_IN_DOCK
INB ACAV_IN_DOCK <48,49>
G
@ R588
10_0402_5%~D 1 2 SN74AHC1G32DCKR_SC70-5~D
3
L39 L40
4.7U_0603_6.3V4Z~D
Y4 BLM18AG121SN1D_0603~D 1 BLM18AG121SN1D_0603~D
2
C671
32.768K_12.5P_1TJS125DJ4A420P~D 1
MEC5035_XTAL2 4 1
@ C673
2
2
3 2 4.7P_0402_50V8C~D
2
22P_0402_50V8J~D
22P_0402_50V8J~D
1 1
C674
C675
2 2
A A
Remove EC SPI rom (2007/10/29)

401533
5 4 3 2 1
5 4 3 2 1
+5V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
1
1
R594
R595
2
2
L41
D TP_DATA DAT_TP_SIO D
1 2 DAT_TP_SIO <38>
TP_CLK 1 2 CLK_TP_SIO
CLK_TP_SIO <38>
L42
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1
C680
C681
C682
C683
2 2 2 2
C C
Power Switch for debug
POWER_SW#_MB 1 2
<31,38> POWER_SW#_MB 1 2
1
JTP1
1 @ C684
1 +5V_RUN +3.3V_RUN 100P_0402_50V8J~D PWR_SW1
<38> BC_DAT_ECE1077 2 2 2 @SHORT PADS~D
<38> BC_CLK_ECE1077 3 3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
<38> BC_INT#_ECE1077 4 4 Place on Top
+3.3V_ALW 5 5 1 1
6 6
C678
C679
7 7
TP_CLK 8
TP_DATA 8 2 2
9 9
10 10 Close to JTP1
+5V_RUN 11 11 1 1 2 2
B +5V_ALW 12 12 B
+3.3V_RUN 13 13
TP_DET# 14
<37> TP_DET# 14 +3.3V_ALW
15 15
16 PWR_SW2
16
0.1U_0402_16V4Z~D
17 @SHORT PADS~D
<38> KYBRD_BKLT_PWM 17
18 18 Place on Bottom
19 19 1
20
For new ALPS KB 20
C771
21
Backlight only, need 22
G1
G2
2
modify at next gerber

JST_SM20B-SURS-TF(LF)(SN)
TP_CLK
TP_DATA
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
1
A
@ @ A
D53
D54

2
Place close to JTP1 connector NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
401533
5 4 3 2 1
5 4 3 2 1
+5VRUN Source
+3.3V_ALW2 +15V_ALW +5V_ALW Q55
DC/DC Interface +3.3V_ALW_ICH Source STS11NF30L_SO8~D +5V_RUN
8 1
1
+15V_ALW +3.3V_ALW Q54 +3.3V_ALW_ICH 7 2
10U_0805_10V4Z~D
SI3456BDV-T1-E3_TSOP6~D R597 6 3
1
100K_0402_5%~D 5 1
D
+3.3V_ALW2 6 R599 R600
S
1
C686
5 4 100K_0402_5%~D 20K_0402_5%~D
4
R598 2 RUN_ENABLE
1
100K_0402_5%~D 2
1 1
2
1
3
10U_0805_10V4Z~D
D D
C687
2200P_0402_50V7K~D
R602 R601 Q56B
3
100K_0402_5%~D ALW_ENABLE 20K_0402_5%~D 2N7002DW-T/R7_SOT363-6~D
2 RUN_ON_5V# 5 1
2
3
2
C689
Q57B
4
2N7002DW-T/R7_SOT363-6~D 1
6
ALW_ON_3.3V# 2
5
C688 Q56A
6
4700P_0402_25V7K~D 2N7002DW-T/R7_SOT363-6~D
4
Q57A 2
<19,28,37,41,50> RUN_ON 2
2N7002DW-T/R7_SOT363-6~D
<38> ICH_ALW_ON 2
1
+3.3V_RUN Source
1
+15V_ALW +3.3V_SUS Source Q61 +3.3V_RUN

+3.3V_ALW +3.3V_ALW2 +15V_ALW +3.3V_ALW SI4336DY-T1-E3_SO8~D
1 Q60 +3.3V_SUS 8 1
STS11NF30L_SO8~D 7 2
20K_0402_5%~D
R603 8 1 6 3 1
R607
10U_0805_10V4Z~D
+3.3V_ALW2 100K_0402_5%~D 7 2 5
C691
6 3 R606
1
20K_0402_5%~D
5 1 100K_0402_5%~D
2
4
1
2
10U_0805_10V4Z~D
R605
2
1
C690
R608
4
R604 SUS_ENABLE 100K_0402_5%~D 1 2
100K_0402_5%~D 2 @ D30
2
3
3
RB751V_SOD323-2~D
2
Q62B 1 2 1
2
2N7002DW-T/R7_SOT363-6~D R609
SUS_ON_3.3V# 5 1 RUN_ON_3V# 5 0_0402_5%~D C693
C Q64B 470P_0402_50V7K~D C
6
6
C692 2N7002DW-T/R7_SOT363-6~D 2
4
4
Q62A 4700P_0402_25V7K~D Q64A
2
<38,41> SUS_ON 2 <37> 3.3V_RUN_ON 2
1
1
+3.3VM Source +1.05V_VCCP Source
+3.3V_ALW2 +15V_ALW +3.3V_ALW Q66 Q67 +1.05V_VCCP
100K_0402_5%~D
SI3456BDV-T1-E3_TSOP6~D +3.3V_M +3.3V_ALW2 +15V_ALW +1.05V_M SI4336DY-T1-E3_SO8~D

8 1
Discharge Circuit
D
6 7 2
S
1
1
R610
20K_0402_5%~D
5 4 6 3 1
10U_0805_10V4Z~D
R614
10U_0805_10V4Z~D
2 +1.05V_M +3.3V_M 5
1
1
20K_0402_5%~D
C695
1 1 R613
R612
1K_0402_5%~D
R611 100K_0402_5%~D
G
4
1
1
2
C694
75_0603_5%~D
@R616
@
100K_0402_5%~D
2
2
1
R616
M_ENABLE
@R615
@
2
R615
R617 1 2
2
2
3
100K_0402_5%~D @ D31
3
Q68B RB751V_SOD323-2~D
2
2N7002DW-T/R7_SOT363-6~D 1 2 1
2
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
M_ON_3.3V# 5 1 R618
1
D D RUN_ON_1.05V# 0_0402_5%~D C697
5
6
@ Q71
@ Q72
C696 M_ON_3.3V# 2 2 Q70B 470P_0402_50V7K~D
4
6
Q68A 4700P_0402_25V7K~D G G 2N7002DW-T/R7_SOT363-6~D 2
4
2 S S Q70A
2N7002DW-T/R7_SOT363-6~D
3
<38,45> M_ON 2 2N7002DW-T/R7_SOT363-6~D
B B
<37> 1.05V_RUN_ON 2
1
1
+15V_ALW
Discharge Circuit
+3.3V_ALW2
1
+5V_RUN +1.5V_RUN +0.9V_DDR_VTT +3.3V_RUN +1.05V_VCCP

R619 +3.3V_SUS +3.3V_ALW_ICH
100K_0402_5%~D
1
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1
@ R622
@ R623
@ R624
@ R625
@ R626
2
@R627
@
@R628
@
R620
ENAB_3VLAN <29>
R627
R628
100K_0402_5%~D
3
1
2N7002DW-T/R7_SOT363-6~D
2
@ R621
2
2
Q74B
C698 470K_0402_5%~D
1
D D D D D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
N21917830 5 4700P_0402_25V7K~D
1
2 D D
200K_0402_5%~D
@ Q81
@ Q82
@ Q76
@ Q77
@ Q78
@ Q79
@ Q80
RUN_ON_5V# 2 2 2 RUN_ON_3V# 2 RUN_ON_1.05V# 2
2
6
2N7002DW-T/R7_SOT363-6~D
@ R629
SUS_ON_3.3V# 2 ALW_ON_3.3V# 2 G G G G G
4
G G S S S S S
3
Q74A
S S
3
<38> AUX_ON 2
2
1
A A
401533
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS +3.3V_ALW C699

<18,37> 2.5V_RUN_PWRGD 2 @ 1 0.1U_0402_16V4Z~D
100K_0402_5%~D 0.1U_0402_16V4Z~D
R630 0_0402_5%~D 1 2
1
<45> 1.5V_RUN_PWRGD 2 1
R631 0_0402_5%~D +3.3V_ALW
R632
<50,53> GFX_CORE_PWRGD 2 1
R808 0_0402_5%~D
8
+5V_ALW <50> 1.1V_GFX_PWRGD 2 @ 1
2
R809 0_0402_5%~D
P
+5V_RUN 1 7 6 2 +3.3V_ALW C700
R633 A Y A Y 0.1U_0402_16V4Z~D
G
E
10K_0402_5%~D Q83 1 U39A U39B 1 2
B
2 1 1 2 2 MMBT3906WT1G_SC70-3~D 74LVC3G14DC_VSSOP8~D 74LVC3G14DC_VSSOP8~D
4
C701
D D
1
200K_0402_5%~D
C
D32
14
1 1
1
RB751V_SOD323-2~D R635 2 U40A
1
R634
C702 C703 4.7K_0402_5%~D C 1 74VHC08MTCX_NL_TSSOP14~D
P
0.1U_0402_16V4Z~D 2200P_0402_50V7K~D Q84 IN1
1 2 2 OUT 3
2 2 B MMST3904-7-F_SOT323-3~D <19,28,37,40,50> RUN_ON 1 2 2
2
IN2
G
E R636 +3.3V_ALW
3
0_0402_5%~D
14
U40B
4 74VHC08MTCX_NL_TSSOP14~D
P
IN1 RUNPWROK
OUT 6 RUNPWROK <37,38,47>
+3.3V_ALW 5 IN2
G
+3.3V_RUN
7
3
E
Q85
2 1 1 2
B
2 MMBT3906WT1G_SC70-3~D
R637
1
200K_0402_5%~D
C
1 D33 1 10K_0402_5%~D
1
RB751V_SOD323-2~D R639
1
R638
C704 C705 4.7K_0402_5%~D C +3.3V_ALW

0.1U_0402_16V4Z~D 2200P_0402_50V7K~D 1 2 2 Q86
2 2 B MMST3904-7-F_SOT323-3~D
14
2
3
10
P
<38,40> SUS_ON IN1
OUT 8 SUSPWROK <38>
3.3V_5V_SUS_PWRGD 9
IN2
G
U40C
7
+3.3V_ALW +3.3V_ALW
+3.3V_SUS
D34 R641
3
C
E C
RB751V_SOD323-2~D 10K_0402_5%~D B
2 1 1 2 2 Q88
200K_0402_5%~D
2200P_0402_50V7K~D
MMBT3906WT1G_SC70-3~D
1
8
C
1 1 D35 +3.3V_M
1
R642
C708
RB751V_SOD323-2~D
P
C707 2 1 3 5
A Y
1
200K_0402_5%~D
0.1U_0402_16V4Z~D
1
G
2 2 U39C R640
2
R643
74LVC3G14DC_VSSOP8~D 100K_0402_5%~D
4
+3.3V_ALW
2
ICH_PWRGD# ICH_PWRGD# <18>
2
14
1
IMVP_PWRGD D
13
P
<24,37,47> IMVP_PWRGD IN1
11 ICH_PWRGD 2 Q87
RESET_OUT# OUT G 2N7002W-7-F_SOT323-3~D
<38> RESET_OUT# 12 IN2
G
U40D S
3
7
IO board ICH_PWRGD <10,24>
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H22 H12
@H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_2P2 @H_3P0
1
+3.3V_ALW +3.3V_ALW
+3.3V_M
B D36 R644 B
3
E
RB751V_SOD323-2~D 10K_0402_5%~D B
H16 H17 H23 H18 H19 H20 H21 H15 H14 2 1 1 2 2 Q89
200K_0402_5%~D
2200P_0402_50V7K~D
@H_4P0 @H_3P8 @H_4P0 @H_4P0 @H_4P0 @H_3P9 @H_3P3 @H_5P3 @H_5P3 MMBT3906WT1G_SC70-3~D
8
C
1 1
P
R645
C710
C709 2 1 1 7 3.3V_M_PWRGD <18,38>
1
A Y
200K_0402_5%~D
0.1U_0402_16V4Z~D
G
2 2 D37 U41A
2
RB751V_SOD323-2~D 74LVC3G14DC_VSSOP8~D
4
R646
CPU x 4 GPU x 3 eDOCK x 2
2
+3.3V_ALW +3.3V_ALW
+3.3V_LAN C713
D40 R651 0.1U_0402_16V4Z~D
3
E
RB751V_SOD323-2~D 10K_0402_5%~D 1 2
B
2 1 1 2 2 Q91
200K_0402_5%~D
2200P_0402_50V7K~D
MMBT3906WT1G_SC70-3~D
8
C
EMI CLIP Fiducial Mark 1 1
P
R652
C715
C714 2 1 6 2 3.3V_LAN_PWRGD <38>
A Y
200K_0402_5%~D
CLIP1 FD1 FD2 0.1U_0402_16V4Z~D
G
EMI_CLIP 2 2 D41 U41B
1 1 2
RB751V_SOD323-2~D 74LVC3G14DC_VSSOP8~D
4
R653
1 FIDUCIAL MARK~D FIDUCIAL MARK~D
GND
FD3 FD4
2
CLIP2 1 1
A EMI_CLIP A
FIDUCIAL MARK~D FIDUCIAL MARK~D
GND 1
401533
5 4 3 2 1
5 4 3 2 1
+5V_ALW
DDTA114EUA-7-F_SOT323-3~D
R995 +5V_ALW
+3.3V_ALW 1 2 BATTERY LED
Q143
2N7002DW-T/R7_SOT363-6~D
100K_0402_5%~D Q145B
2
2N7002DW-T/R7_SOT363-6~D
4 3 2 R996 +5V_ALW
100K_0402_5%~D
6
Q145A
3
+3.3V_ALW
2 MARK_BASE_LEDS# Q146
1
1 2BREATH_BLUE_LED_IO BREATH_BLUE_LED_IO <31> 2N7002DW-7-F_SOT363-6~D DDTA114EUA-7-F_SOT323-3~D
R997 150_0402_5%~D 2
1
5
6
+3.3V_ALW
Q140A +5V_ALW
NC
+5V_ALW
<35,38> BREATH_LED# 2 A Y 4
BAT2_LED
ON MB
R998 2
G
2
D NC7SZ04P5X_NL_SC70-5~D U42 D46 D
1
R999 BLUE D64
BREATH_LED
1 2
NC
+3.3V_ALW
3
1
3
Q147
Q144B <38> BAT2_LED# 2 A Y 4 100K_0402_5%~D 1 2 BATT_BLUE_LED 2 1
100K_0402_5%~D R665 150_0402_5%~D 2N7002W-7-F_SOT323-3~D
G
2N7002DW-T/R7_SOT363-6~D U68
1
NC7SZ04P5X_NL_SC70-5~D
S
4 3 2 4 3 1 3
6
YEL
2N7002DW-T/R7_SOT363-6~D
Q141A +5V_ALW LTST-C155TBJSKT_Blue/YEL~D
G
5
2
Q144A
MARK_BASE_LEDS#
SYS_LED_MASK# 2
1
2 1 2BREATH_BLUE_LED_LCD BREATH_BLUE_LED_LCD <19>
3
R1000 150_0402_5%~D 2N7002DW-7-F_SOT363-6~D Q142A
1
2N7002DW-7-F_SOT363-6~D
1
Q148
1 6 2
2
SYS_LED_MASK#
BREATH LED
1
+3.3V_ALW
+3.3V_ALW
2
R906
3
100K_0402_5%~D
+3.3V_WLAN +5V_RUN Q149
2N7002DW-7-F_SOT363-6~D
1
2
WLAN LED solution for Blue LED
3
100K_0402_5%~D
+3.3V_ALW
3
Q140B +3.3V_ALW
1
BAT1_LED 5 DDTA114EUA-7-F_SOT323-3~D
2
R662
1
Q151A Q97 R905
NC
4
2N7002DW-7-F_SOT363-6~D PDTA114EU_SC70-3~D 2 4 100K_0402_5%~D 1 2 BATT_YELLOW_LED
<38> BAT1_LED# A Y R1003 150_0402_5%~D
2
G
1 6 U69
<34> LED_WLAN_OUT#
1
NC7SZ04P5X_NL_SC70-5~D
1
3
C C
1 2 WLAN_LED 2 1 +3.3V_ALW
2
R663 150_0402_5%~D Q141B
MARK_BASE_LEDS# D45
LTST-C191TBKT-5A BLU_0603~D 5 ON LCD
3
Q142B
4
+5V_RUN 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D
Q150
4 3 2
WWAN LED solution for Blue LED
3
+3.3V_RUN
1 2 BATT_BLUE_LED_LCD <19>
5
100K_0402_5%~D
SYS_LED_MASK# R903 150_0402_5%~D

2
1
1
Q115
Q151B PDTA114EU_SC70-3~D 1 2 BATT_YELLOW_LED_LCD <19>
R206
R904 150_0402_5%~D
2N7002DW-7-F_SOT363-6~D
2
<34> LED_WWAN_OUT# 4 3 1 2 WWAN_LED 2 1

R125 150_0402_5%~D
D61
LTST-C191TBKT-5A BLU_0603~D
5
+5V_RUN
MARK_BASE_LEDS#
KEYBOARD STATUS LED

3
+3.3V_RUN
Q94
100K_0402_5%~D
1
2 +5V_ALW
R660
Q152A
WPAN LED solution for Blue LED
3
2
2N7002DW-7-F_SOT363-6~D
1
<34> LED_WPAN_OUT# 1 6
D43 2
<37> CAP_LED#
1 2 WPAN_LED 2 1
R661 150_0402_5%~D Q120
2
3
MARK_BASE_LEDS# LTST-C191TBKT-5A BLU_0603~D DDTA114EUA-7-F_SOT323-3~D
B B
1
2 1 2 R_CAP_LED# 2 1
<37> NUM_LED#
R556 150_0402_5%~D
+3.3V_ALW Q121 D57
3
DDTA114EUA-7-F_SOT323-3~D LTST-C191TBKT-5A BLU_0603~D
SNIFFER LED
3
1
2 1 2 R_NUM_LED# 2 1
<37> SCRL_LED#
R596 150_0402_5%~D
2 Q122 D58
<37> SNIFFER_YELLOW#
DDTA114EUA-7-F_SOT323-3~D LTST-C191TBKT-5A BLU_0603~D
1
Q100 1 2 R_SCRL_LED# 2 1
DDTA114EUA-7-F_SOT323-3~D R655 150_0402_5%~D
1
D59
1 2 SNIFFER_YELLOW SNIFFER_YELLOW <31> LTST-C191TBKT-5A BLU_0603~D
R667 220_0402_5%~D
+5V_ALW
3
Q102 +3.3V_ALW
<37> SNIFFER_BLUE# 2
5
SYS_LED_MASK# 2
P
<37> SYS_LED_MASK# A
4 MARK_BASE_LEDS#
LID_CL# Y
<31,37> LID_CL# 1 B
G
1
74AHCT1G08GW_SOT353-5~D
3
SNIFFER_BLUE
1
R668
2
150_0402_5%~D
SNIFFER_BLUE <31> U14
BIOS GPIO Table for LED Control
SYS_LED_MARK# LID_CL#
+5V_RUN
+3.3V_RUN
A HDD LED solution for Blue LED MARK ALL LED (SNIFFER FUNCTION) Low X A
1
100K_0402_5%~D
MARK BASE MB LEDs (Lid Closed) High Low

3
R654
Q92
Do Not Mark LEDs (Lid Opened) High High
2
Q152B 2
2N7002DW-7-F_SOT363-6~D
<23> SATA_ACT#_R 4 3
1
Title
5
1 2 SATA_LED 2 1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
R659 150_0402_5%~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC, MB A4042
MARK_BASE_LEDS# D42 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LTST-C191TBKT-5A BLU_0603~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D JRTC1
PAD~D@ +COINCELL 1
+3.3V_RTC_LDO RTC_BAT_DET_R# 1
T47 2 4
2
2 G1
3 3 G2 5
Z4012
MOLEX_53398-0371~D
D D
+3.3V_ALW
3
+RTC_CELL
ESD Diodes
PD1
1
3
2
BAT54CW_SOT323~D
1
PL1 +3.3V_ALW
FBMA-L18-453215-900LMA90T_1812~D PC1
1 2 1U_0603_10V6K~D
2
Primary Battery Connector PD2 PD3 PD4 PD5
1
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D Move to power schematic
1
10K_0402_1%~D
PJP1
1 2 PBATT+
PR2
0.1U_0603_25V7K~D
1
FOX_BP02093-P5652-7F~D PAD-OPEN 4x4m
PC2
11 9 PR3
2
GND 9 100_0402_5%~D PR4
10 8
2
GND 8 Z4304 100_0402_5%~D PR5
2200P_0402_50V7K~D
7 7 1 2 PBAT_SMBCLK <38>
6 Z4305 1 2 100_0402_5%~D
6 PBAT_SMBDAT <38>
5 Z4306 1 2 PR6 @
5 PBAT_PRES# <37>
1
PC3
4 100_0402_5%~D
4 PBAT_ALARM#
3 3 1 2
2
2
2
1 1
PBATT1
C C
+5V_ALW +3.3V_ALW
DA204U_SOT323~D
2
PD6
@ PR7 PU1
2.2K_0402_5%~D
2
1 2 <35> DOCK_PSID 1 NO IN 6 GPIO_PSID_SELECT <37>
0_0402_5%~D
PR8
2 GND V+ 5 +5V_ALW
PL2 PR9
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
S
2 1 1 3 1 2 3 NC COM 4 PS_ID <38>
100K_0402_1%~D PQ1 TS5A63157DCKR_SC70-6~D
2
2 FDV301N_SOT23~D +5V_ALW
G
2
PR10
+5V_ALW
DA204U_SOT323~D
2
PD8
10K_0402_1%~D
1
1
@ C
1
PR11
PD7 2 PQ2
SM24_SOT23 B MMST3904-7-F_SOT323~D @
B E B
15K_0402_1%~D
3
2
1
PR12
PR13
1 2
PSID_DISABLE# <37>
1
@ 10K_0402_5%~D
PQ3
DCIN_CBL_DET# <37> +DC_IN FDS6679AZ_SO8~D DC_IN+ Source +DC_IN_SS
1 8
2 7
PL3 3 6
FBMJ4516HS720NT_1806~D 5
1 2 +DC_IN
240K_0402_5%~D
1
VZ0603M260APT_0603
0.47U_0805_25V7K~D
2
10U_1206_25V6M~D
4.7K_0805_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
4
1
PC4
PR14
PQ4B
1
PD9
1
1
IMD2AT-108_SC74-6~D
PC6
PC7
PC8
PC9
PR15
0.1U_0603_25V7K~D
2
1
@
0.1U_0603_25V7K~D
3 4
2
1
PC5
47K_0402_1%~D
PJPDC1
1
2
PC10
0_0402_5%~D
47K_0402_1%~D
1
2
1
1
PR17
2 2
PR18
3 -DCIN_JACK
2
3
PR16
4 @
4
5
2
5 +DCIN_JACK PL4
A 6 A
2
6 FBMJ4516HS720NT_1806~D
MOLEX_87437-0663 1 2 @
1
PQ4A
0.1U_0603_25V7K~D
RHU002N06_SOT323
1
IMD2AT-108_SC74-6~D PR172
1
D 0_0402_5%~D
PQ5
PC11
5 2 NB_AC_OFF_R 1 2
2
<49> NB_AC_OFF_BJT G NB_AC_OFF <37,49>

S
3
PC12
0.1U_0603_25V7K~D Title
6
SCHEMATIC, MB A4042
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401533
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D D
PJP2
+PWR_SRC 1 2
PAD-OPEN 4x4m
VOUT1=5V
2
0_0805_5%
0_0805_5%
PJP3 +5V_VCC1
L=4.7uF
2200P_0402_50V7K~D
0.1U_0805_50V7K
+5V_ALW2 1 2
PR19
PR20
Fsw=400KHz
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
@ PR21
0.1U_0805_50V7K
D=0.265
1
PAD-OPEN1x1m 10_0603_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
1
1
Output Ripple Current=1.97A
PC18
PC19
PC20
PC21
PC22
4.7U_0805_6.3V6K
2 1
PC13
PC14
PC15
PC16
PC17
Output Ripple Voltage=1.97A*25mOhm=49.37mV)
2
2
1
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
PC23
+3.3V_ALW2
2
Component select
1U_0603_25V7K~D
Input CAP 10uF_1206_25V *2
1U_0603_10V6K~D
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
1
PC24
PR22
1U_0603_10V6K~D
1
PC25
H_MOSFET FDS8880 @ 0_0402_5%~D
1
PC26
1 2
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
2
Inductor 4.7U_HMU1356-4R7-R_10A(DELTA) PR23
2
0_0402_5%~D
1 2
EN_3V_5V
PC27
0.1U_0603_25V7K~D
1
GNDA_3V5V 1 2 GNDA_3V5V 0_0402_5%~D
5 Volt +/-5% 1 2 PR25 3.3 Volt +/-5%
Thermal Design Current:6.62A Thermal Design Current: 7.39A
0.1U_0402_10V7K~D
@ PR24
0.1U_0402_10V7K~D
2
8
7
6
5
PC29
Peck current: 9.46A 0_0603_5%~D @ PR26 Peak current: 10.56A
8
7
6
5
4
3
2
1
5
6
7
8
PQ6 GNDA_3V5V PU2 2 1
D
D
D
D
1
+5V_ALWP
OCP min: 11.3A FDS8880_NL_SO8~D OCP min: 13A
PC28
@ PQ7
V5FILT
LDO
VREF3
EN_LDO
TONSEL
VREF2
LDOREFIN
VIN
D
D
D
D
C 0_0402_5%~D FDS8880_NL_SO8~D C
2
2
4 @ PR27
G 187K_0402_1%~D
9 VSW REFIN2 32 4 G
+5V_ALWP PR28 10 31 1 2 GNDA_3V5V
VOUT1 TRIP2
S
S
S
150K_0402_1%~D 11 30
VFB1 VOUT2
S
S
S
GNDA_3V5V 1 2 12 29 2 PR29 0_0402_5%~D
1 +3.3V_ALWP
1
2
3
ALW_PWRGD_3V_5V TRIP1 SKIPSEL POK2

13 28
3
2
1
PL5 PR168 1 PGOOD1 PGOOD2 EN_3V_5V PL6
2 14 EN1 EN2 27 1 2
3.0UH_HMP1362-3R0-R_17A_20%~D 0_0402_5%~D +5V_ALW_UGATE 15 26 +3.3V_ALW_UGATE PR169 0_0402_5%~D 3.0UH_HMP1362-3R0-R_17A_20%~D
+5V_ALW_PHASE DRVH1 DRVH2 +3.3V_ALW_PHASE
2 1 16 LL1 LL2 25 2 1
0_0603_5%~D
1500P_0603_25V7K~D
1500P_0603_25V7K~D
0.1U_0603_25V7K~D
V5DRV
SECFB
DRVL1
DRVL2
VBST1
VBST2
2
8
7
6
5
PGND
0_0402_5%~D
GNDA_3V5V
0.1U_0603_25V7K~D
EN_3V_5V
GND
PAD
NC
NC
5
6
7
8
1
PR30
220U_V_6.3VM_R25M~D
220U_V_6.3VM_R25M~D
330U_D3L_6.3VM_R25~D
1
PC218
PC219
PR31
PQ8 PQ9
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
PC30
PC31
1 SN0608098_QFN32_5X5~D 1 1
33
17
18
19
20
21
22
23
24
@ FDS6676AS_NL_SO8~D FDS6676AS_NL_SO8~D
1
2
1
1
+ + +
PC32
PC33
PC34
PC35
PC169
@ 4 GNDA_3V5V @
2
4.7_1206_5%~D
4.7_1206_5%~D
4
2
2
PR32 PR33
2
2
2 2 2
PR231
PR232
0_0402_5%~D 0_0402_5%~D
0_0603_5%~D
0_0402_5%~D
1 2 +5V_ALW_BOOT +3.3V_ALW_BOOT1 2
1
2
3
2
1
3
2
1
PR35
@ +5V_ALW_LGATE +3.3V_ALW_LGATE @
1
1
PR34
@
1
2
GNDA_3V5V
GNDA_3V5V
GNDA_3V5V PC36 PJP4
4.7U_0603_6.3V6K~D
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2 VOUT2=3.3V
+3.3V_ALW +3.3V_ALW
PC37
1 1 2
L=3.0uF
+5V_ALW2
0.1U_0603_25V7K~D
2
PAD-OPEN1x1m Fsw=500KHz
D=0.176
1
B B
PD10 GNDA_3V5V
200K_0402_1%~D
200K_0402_1%~D
PC38
BAT54SW-7-F_SOT323-3~D Output Ripple Current=1.84A
2
Output Ripple Voltage=1.84A*25mOhm=46.05mV
2
PR36
PR37
PC39
2 0.1U_0603_25V7K~D PD12 Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
1
1 1 2 BAT54CW_SOT323~D
3 @
1
Component select
PR38 PD11 POK2 Input CAP 10uF_1206_25V *2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
<38> ALWON
3
H_MOSFET FDS8880
0_0402_5%~D
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
1
200K_0402_5%
2
PR41
PR39 Inductor 3.0U_HMP1362-3R0-R_17A(DELTA)
PR40
0_0402_5%~D
<18> THERM_STP# 2 1
2
1
ALW_PWRGD_3V_5V
ALW_PWRGD_3V_5V <38>
PR42
PJP5 200K_0402_1%~D
+15V_ALW 2 1 +15V_ALWP 2 1
0.1U_0603_25V7K~D
PAD-OPEN1x1m
39.2K_0402_1%~D
2
PJP34 (100mA,20mils ,Via NO.=1)

1
1 2
PC40
PR43
PAD-OPEN 4x4m
2
PJP6
+5V_ALWP 1 2 +5V_ALW
A PAD-OPEN 4x4m A
GNDA_3V5V
PJP7
+3.3V_ALWP 1 2 +3.3V_ALW
PAD-OPEN 4x4m
PJP35
1 2 Compal Electronics, Inc.
PAD-OPEN 4x4m Title
SCHEMATIC, MB A4042
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401533
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN / +1.05V_M/ +3.3V_RTC_LDO

+DC2_PWR_SRC
PJP8
+PWR_SRC 1 2
D D
2
10U_1206_25V6M~D
2200P_0402_50V7K~D
0_0805_5%~D
1U_0603_25V7K~D 0_0805_5%~D
0.1U_0603_25V7K~D
PAD-OPEN 4x4m
10U_1206_25V6M~D
2200P_0402_50V7K~D
PR44
PR45
0.1U_0603_25V7K~D
1
10U_1206_25V6M~D
PC41
PC42
PC43
1
PC44
PC45
2
PC46
PC47
2
2
2
PC48
+5V_VCC2
1
+3.3V_RTC_LDO
2
PR46
0_0402_5%~D
PC49
0_0402_5%~D
0.1U_0603_25V7K~D
1.5 Volt +/-5% 1.05 Volt +/-5%
5
6
7
8
1U_0402_6.3V6K~D
REF 1 2
PR47
Thermal Design Current: 2.63A Thermal Design Current: 7.89A
D
D
D
D
PR49 2 1
1
0_0402_5%~D
Peak current: 3.76A GNDA_1P5V_1P05V @ 0_0402_5%~D Peack current: 11.27A
PC50
1 2 PR51 PQ10
1
PR48
OCP min: 4.3A OCP min: 13.8A
0.1U_0402_10V7K~D
0_0402_5%~D 4 FDS6298_SO8~D
2
G
1U_0603_10V6K~D
0.1U_0402_10V7K~D
SI4800BDY-T1_SO8~D
2 1
8
7
6
5
1
PR50 GNDA_1P5V_1P05V
S
S
S
PC63
@ 0_0603_5%~D
1
PC51
3
2
1
8
7
6
5
4
3
2
1
+1.05V_MP
PQ11
PC52
C PU3 C
PL7
1
GNDA_1P5V_1P05V
LDOREFIN
VIN
LDO
VREF3
EN_LDO
TONSEL
VREF2
V5FILT
1
4 GNDA_1P5V_1P05V 1.4UH_HMU1350-1R4PF_15A_20%~D
+1.5V_RUN_P 2 1
2
GNDA_1P5V_1P05V @
1500P_0603_25V7K~D
PL8 9 VSW 32 REFIN2_1_05 @
3.3UH_MPLC0730L3R3_6.5A_20%~D REFIN2
10 VOUT1 31 1 2
1
2
3
3
TRIP2
0.1U_0402_10V7K~D
2 1 PR53 11 VFB1 30 PR52 130K_0402_1%~D GNDA_1P5V_1P05V
VOUT2
5
6
7
8
1
PC221
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1 2 12 TRIP1 29 PR54 2 0_0402_5%~D
1 GNDA_1P5V_1P05V
SKIPSEL
8
7
6
5
1500P_0603_25V7K~D
10U_1206_6.3V7K
SI4810BDY-T1-E3_SO8~D
130K_0402_1%~D 1.5V_RUN_PWRGD
13 PGOOD1 28 1.05V_M_PWRGD 1 1
PGOOD2
0.1U_0402_10V7K~D
FDS6299S_SO8~D
EN1 14 27 EN2
D
D
D
D
GNDA_1P5V_1P05V
2
1.5V_UGATE 15 EN1 EN2
2
2
0_0603_5%~D
PC53
+
PC54
+
PC56
PC57
10U_1206_6.3V7K
330U_D2E_2.5VM_R9
26 1.05V_UGATE @
1.5V_PHASE 16 DRVH1 DRVH2
1
PQ13
4.7_1206_5%~D
PC220
1 25 1.05V_PHASE
LL1 SN0608098_QFN32_5X5~D LL2
2
PR55
1
1
2 2
PQ12
PC55
+
PC58
PC59
PR234
0.1U_0603_25V7K~D
4 @
V5DRV
SECFB
DRVL1
DRVL2
VBST1
VBST2
2
PGND
0.1U_0603_25V7K~D
@
GND
PAD
1
4.7_1206_5%~D
@
2
2
S
S
S
@ @
3
2
1
1
2
2
PR233
PC60
PC61
1
2
3
33
17
18
19
20
21
22
23
24
0_0603_5%~D
2
1
@
1
PR56
GNDA_1P5V_1P05V
PR57 PR58
1
@ 0_0402_5%~D 0_0402_5%~D
1 2 1 2
1.5V_LGATE GNDA_1P5V_1P05V
GNDA_1P5V_1P05V 1.05V_LGATE
B B
+5V_ALW +5V_VCC2
VOUT2=1.05V
@ PR59
10_0603_5%~D L=0.88uF
VOUT1=1.5V 2 1 Fsw=300KHz
L=3.3uF D=0.057
+3.3V_SUS +3.3V_ALW Output Ripple Current=3.88A
4.7U_0603_6.3V6K~D
Fsw=200KHz
1
D=0.081 Output Ripple Voltage=3.88A*4.5mOhm=17.44mV

100K_0402_1%~D
100K_0402_1%~D
PC62
Output Ripple Current=2.15A Input Ripple Current=TDC*(D*(1-D))^0.5=2.53A

2
1
Output Ripple Voltage=2.15A*15mOhm=32.27mV

PR61
PR60
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A Component select

@
Input CAP 10uF_1206_25V*2
2
Component select Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9)

Input CAP 10uF_1206_25V 1.05V_M_PWRGD
H_MOSFET SI4682DY
1.05V_M_PWRGD <38>
Output Cap 220U_D2_4VM_R15(NEC_PSLV0G227M) L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
H_MOSFET SI4800BDY Inductor 0.88U_MPC1040LR88_17A(NEC_TOKIN)
L_MOSFET SI4810BDY(16/20mOhm@4.5V, 6A)
Inductor 3.3U_MPL73-3R3_6A(DELTA) 1.5V_RUN_PWRGD 1.5V_RUN_PWRGD <41>
PJP9
PR171 1 2
0_0402_5%~D
EN1 1 2 PAD-OPEN 4x4m
1.5V_RUN_ON <37> PJP10
@PR62
@ PR62 2 1 PJP12
PJP11 100K_0402_1%~D +1.05V_MP 1 2 +1.05V_M
+1.5V_RUN_P 1 2 +1.5V_RUN +3.3V_ALW 2 1
A PR170 PR63 PAD-OPEN1x1m PAD-OPEN 4x4m A
PAD-OPEN 4x4m 0_0402_5%~D 0_0402_5%~D
EN2 1 2 1 2 GNDA_1P5V_1P05V
M_ON <38,40>
OK to Short if CAD
System can Support
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, MB A4042
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
401533
5 4 3 2 1
5 4 3 2 1
+1.8VSUSP/ +0.9V_DDR_VTT
DDR2 Termination
+DDR_PWR_SRC
PJP13
PAD-OPEN 4x4m
+PWR_SRC 1 2
D D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1 1
1
PC64
PC65
PC66
PC67
2
2
2 2
+5V_ALW
RB751V-40_SOD323~D
+1.8V_SUSP
PD13
2
1.8 Volt +/-5%
1
PC216
Thermal Design Current: 6.24A
8
7
6
5
1U_0402_6.3V6K~D
12
1
2
7
Peck current: 8.91A PQ14 @ PU4
D
D
D
D
FDS6298_SO8~D PC68
NC
NC
PR64
OCP min: 9.85A 0.22U_0603_10V7K~D
1 2 2 1 22 23
VBST VLDOIN
G 4
0_0603_5%~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
TPS51116_DRVH 21 24 1 1 1 +0.9V_DDR_VTTP
DRVH VTT
S
S
S
+1.8V_SUSP
PC69
PC70
PC171
PL9
3
1.4UH_HMU1350-1R4PF_15A_20%~D 1
2
3
20 LL VTTGND 1
2 2 2 +1.8V_SUSP
1 2+1.8VSUSP_L
2
TPS51116_DRVL
1500P_0603_25V7K~D
19 DRVL VTTSNS 2
5
PR65
C PQ15 0_0402_5%~D
Design current 0.7A for +0.9V_DDR_VTTP C
1
FDMS8670AS_POWER56-8_5P~D
PC222
18 PGND_D GND 3 GNDA_DDR Peak current 1A for +0.9V_DDR_VTTP

0.1U_0402_10V7K~D
330U_D2E_2.5VM_R15~D
330U_D2E_2.5VM_R15~D
PR67
1
1 1 +3.3V_ALW PR66 @
2
@ 4 2 1 16 4 2 1 GNDA_DDR
CS MODE
1
+ +
PC71
PC72
PC73
4.7_1206_5%~D
2
2
5.9K_0402_1%~D +V_DDR_MCH_REF 0_0402_5%~D
PR235
PR68 14 5 PR69 @
2
V5FILT VTTREF
1
2 2 200K_0402_1%~D 0_0402_5%~D
1
2
3
PC74
@ 13 6 0.033U_0603_16V6K~D
1
1
PGOOD COMP
11 S5 VDDQSNS 8
<38> 1.8V_SUS_PWRGD +5V_ALW
PR70
0.1U_0402_10V7K~D
CS_GND
1 2 10 S3 VDDQSET 9
<38> DDR_ON
V5IN
PC170
TP
0_0402_5%~D
TPS51116RGE_QFN24_4X4~D
15
25
17
2
<37> 0.9V_DDR_VTT_ON PR71 @
5.1_0402_1%~D
1U_0603_10V6K~D
2 1
1
1
PC75
PC76
1U_0603_10V6K~D
2
2
GNDA_DDR
+5V_ALW
GNDA_DDR GNDA_DDR
B B
@ PR225 @ PR226
PJP14
27.4K_0402_1%~D 17.4K_0603_1%~D
1 2 1 2 GNDA_DDR 2 1
2
PR174 PAD-OPEN1x1m
0_0402_5%~D GNDA_DDR
1
PJP15
+5V_ALW PAD-OPEN 4x4m
1 2
PJP16
PAD-OPEN 4x4m
+1.8V_SUSP 1 2 +1.8V_MEM
PJP17
+0.9V_DDR_VTTP 2 1 +0.9V_DDR_VTT
A PAD-OPEN 2x2m~D A
401533
5 4 3 2 1
8 7 6 5 4 3 2 1
+CPU_PWR_SRC @ PL10
FBMJ4516HS720NT_1806~D
1 2 +PWR_SRC
PJP18
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
H H
1 1 1 1 2
PC82
PC83
PC84
1
1
+ + +
PC77
PC78
PC80
PC81
PAD-OPEN 4x4m
PC79
2
2
2 2 2
2.4_0805_1%~D
5
6
7
8
+CPU_PWR_SRC
PR72
D
D
D
D
+5V_ALW
PQ16 @ Iccmax=44A
1
SI4686DY-T1-E3_SO8~D
I_TDC=35A
1000P_0603_25V7K~D
1U_0603_10V6K~D
4 G
PR73 OCP=65A, Intel spec=50A
1
PC85
10_0603_5%~D
1
S
S
S
PC87
@
PR74 PC86
@ 0.01U_0402_25V7K~D
3
2
1
PU5 0_0603_5%~D 0.22U_0603_10V7K~D
2
G 5 1 2 1 1 2 @ G
VDD BST PL11
6 8 UGATE1 0.45UH_ETQP4LR45XFC_25A_20%~D
SKIP DH
1
PC88
2 7 PHASE1 4 1 +VCC_CORE
PWM LX
1500P_0603_25V7K~D
3 4 3 2
2
GND DL
9
D
EP
2
+5V_ALW
PC91
PQ17
MAX8791GTA+_TQFN8_3X3~D PR76
+3.3V_RUN
1U_0603_10V6K~D 10_0603_5%~D
GNDA_VCORE 0_0402_5%~D
2
2
LGATE1 2 @ PR78 PC89

G 2K_0402_1%~D 0.22U_0603_10V7K~D
1
PR77
2.4_0805_1%~D
1 2 2 1
2
S
2
PR75
1
1
PR80 @
2
7.68K_0805_1%~D PR81
1
F PR79 @ F
0_0402_5%~D
1
PC90
1.91K_0603_1%~D
1
PR82 VSUM
2
2
147K_0402_1%~D
1
2 1 IMVP_PWRGD <24,37,41>
0_0603_5%~D
VO
1
+CPU_PWR_SRC
PR83
@ PR84
1
13K_0402_1%
0_0402_5%~D GNDA_VCORE +5V_ALW

PR85
2 1
19
20
18
39
40
2
2
PU7
2200P_0402_50V7K~D
2.4_0805_1%~D
0.1U_0603_25V7K~D
PR90
10U_1206_25V6M~D
10U_1206_25V6M~D
N.C.
IMVPOK
V3P3
GND
VCC
2
5
6
7
8
@ PC92
1
PC93
2200P_0402_50V7K~D PAD~D
1U_0603_10V6K~D
D
D
D
D
PC94
PC96
PC97
2 1 T1 IMVP6_PROCHOT# 4 @
1
VRHOT
PC95
@ PQ18
2
SI4686DY-T1-E3_SO8~D
1500P_0603_25V7K~D 1000P_0603_25V7K~D
3 OSC PWM1 27
4
2
E G E
PC98 2 PH11@ 5 THRM
1
PC100
470p_0402_50V7K~D PR91 PC99
S
S
S
2 1 100K_0603_5%_ERTJ1VV104J~D 6 23 PU6 0_0603_5%~D 0.22U_0603_10V7K~D
CCV CSP1
5 1 2 1 1 2
3
2
1
2
GNDA_VCORE VDD BST @ PL12
2 PR87 1 28 6 8 UGATE2 0.45UH_ETQP4LR45XFC_25A_20%~D
<8> VID0 D0 SKIP DH
<8> VID1 2 PR86 1 0_0402_5%~D 29 D1
0_0402_5%~D 2 PR89 1 30 26 2 7 PHASE2 4 1 +VCC_CORE
<8> VID2 D2 PWM2 PWM LX
<8> VID3 2 PR88 1 0_0402_5%~D 31 D3
0_0402_5%~D 2 PR93 1 32 3 4 3 2
<8> VID4 D4 GND DL
<8> VID5 2 PR92 1 0_0402_5%~D 33 D5
1
PC102
0_0402_5%~D 2 PR94 1 34 22 9
<8> VID6 D6 CSP2 EP
0_0402_5%~D
2
37 MAX8791GTA+_TQFN8_3X3~D
PQ19
<8,10,23> H_DPRSTP#
2
PR96 DPRSTP PR97
<10,24> DPRSLPVR 2 1 36 DPRSLPVR 0_0402_5%~D
PR98 499_0402_1%~D LGATE2 2 @ PR100 PC103
G 2K_0402_1%~D 0.22U_0603_10V7K~D
2.4_0805_1%~D
<8> H_PSI# 2 1 1
1
PSI
2
D @ PR99 0_0402_5%~D 1 2 2 1 D
PR95
2 1 2 PGD_IN DRSKP 24
2
<18> PWR_MON 10K_0402_5%~D @
1
2
1
0_0402_5%~D
PR102 PAD~D T2 CLK_ENABLE# 38 PR101 @
CLKEN
PR275
@ PC101 0_0402_5%~D @ 7.68K_0805_1%~D PR103 @
1
1U_0603_10V6K~D 2 1 35 10_0402_1%~D
1
PR104 10_0402_1%~D SHDN
1
GNDA_VCORE @ PR105 0_0402_5%~D 2 1 12 25 VSUM
CSN2 2
2
FBS PWM3
<37,38,41> RUNPWROK 2 1 <8> VCCSENSE
13 GNDS VO
21 PR106 +CPU_PWR_SRC
CSP3 226K_0402_1%~D
<37> IMVP_VR_ON 11 VPS
2 1 GNDA_VCORE +5V_ALW
@ PR107
0.1U_0603_25V7K~D
2 1 10 TIME
2
11.5K_0402_1%~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
2.4_0805_1%~D
PR108
PH2 PC104 1000P_0402_50V7K~D
10U_1206_25V6M~D
ILIMPK 7 2 1
5
6
7
8
1
PC107
10KB_0603_1%_ERTJ1VG103FA~D 2 1 9 REF
1
PC108
PC106
PQ20
1U_0603_10V6K~D
C C
D
D
D
D
PC110
PR109 PC105 1000P_0402_50V7K~D 17 VSUM SI4686DY-T1-E3_SO8~D @
2
PWR
1
PC109
1000P_0603_25V7K~D
2 1 2 1 8
2
4.99K_0402_1% TRC
2.43K_0402_1%~D
0.033U_0402_16V7K~D
41 MAX8786GTL+_TQFN40_6X6~D PR114 PC113 4

2
TP G
CSN3
CSN2
CSN1
@ PR111
GNDA_VCORE PR110 PU8 0_0603_5%~D 0.22U_0603_10V7K~D

4.53K_0402_1%~D
1
1
PC114
<8> VSSSENSE 2 1 5 VDD BST 1 2 1 1 2
2
S
S
S
@ PC112
0_0402_5%~D PL13
@ PR112
6 8 UGATE3 0.45UH_ETQP4LR45XFC_25A_20%~D
14
15
16
3
2
1
2
@ PR113 PR115 SKIP DH @
1
PHASE3
17.8K_0402_1%~D
0.33U_0603_10V7K
2 1 1 2 2 1 2 2 7 1 4 +VCC_CORE
2
PWM LX
1
PR117
332_0402_1%~D
@ PC115
@ PC111 @ PR116 6.49K_0603_1%~D 3 4 2 3

CSN3
CSN2
6.8KB_0603_5%_ERTJ1VR682J~D
VO GND DL
1500P_0603_25V7K~D
680P_0402_50V7K~D 2 1
1
1
PC118
1.69K_0402_1%~D
0.01U_0402_16V7K~D
EP
D
2
2
2 1 1 MAX8791GTA+_TQFN8_3X3~D
PQ21
2
PR118 GNDA_VCORE @ PR120
@ PC116
71.5K_0402_1%~D 0_0402_5%~D
1
B LGATE3 PC119 B
15K_0402_1%~D
@ PR122 @ PR123 PR125
2.4_0805_1%~D
2 G
2
0_0402_5%~D 0_0402_5%~D 2 2K_0402_1%~D 0.22U_0603_10V7K~D
1 2 2 1
1
@ PH3
@ PR124
PR119
@ PC117 @ PR121 2 1 2 1 1 2 2 1
S
1500P_0402_50V7K~D 82.5K_0402_1%~D
2
PWR_MON <18>
2
1
0_0402_5%~D
PC120 @ PR126 @
PR276
0.01U_0402_25V7K~D @ PC121 @ PC122 7.68K_0805_1%~D PR127 @
1 2 2 1 2 1 10_0402_1%~D
1K_0402_1%~D
1
0_0402_5%~D
1000P_0402_50V7K~D 330P_0402_50V7K~D VSUM

22.1K_0402_1%~D
CSN3 2
2
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
1
PR130
1000P_0402_50V7K~D
2 1
PR128
PR131
PC124 VO
1
0.1U_0402_10V7K~D
PC123
PC125
PR129
2
PC126
909_0402_1%~D @
2
2
2
0.01U_0402_16V7K~D
A 1 A
GNDA_VCORE
@ PC127
GNDA_VCORE Title
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D SCHEMATIC, MB A4042
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
GNDA_VCORE 401533
8 7 6 5 4 3 2 1
5 4 3 2 1
PQ22
+SDC_IN PR132 +PWR_SRC CHAGER_SRC
SI4835BDY-T1-E3_SO8~D 0.01_1206_1%~D
8 1 PJP19
+DC_IN_SS 7 2 1 4 1 2
TBD_0603_25V7K~D
33K_0402_5%~D
6 3
0.1U_0603_25V7K~D
5 2 3 PAD-OPEN 4x4m
NTR4502PT1G_SOT23-3~D
+DC_IN
2200P_0402_50V7K~D
@
1
PR133
PC128
PC130
4
PC129
PR134 PR135
10K_0402_5%~D
10K_0402_5%~D 100K_0402_5%~D
2
1
1
1
NTR4502PT1G_SOT23-3~D
2 1 2 1 @ @
PQ23
PR136
D D
2
1
D 2
10K_0402_5%~D
2 PQ24 3
3
1
1
G RHU002N06_SOT323 1
PQ25
PR137
S 2
3
RHU002N06_SOT323
2
3
3
1
D
2
PQ66
RHU002N06_SOT323
2
<38,49> ACAV_IN_DOCK G
1
D
S DOCK_DCIN_IS+ <35>
PQ26
2
+DC_IN_SS
TBD_0603_25V7K~D
33K_0402_5%~D
G 2 1 DOCK_DCIN_IS- <35>
S
3
1
0_0402_5%~D
@ PR138 @
1
PR139
10K_0402_5%~D
PC131
PR140
ISL88731_VDDP ISL88731_VREF PC132 PC133
2
10K_0402_1%~D
10K_0402_5%~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
2
2
1 2 1 2
1
PR141
@ PR142
PR143
@ PC134
309K_0402_1% Throttle_ICREF 1U_0603_10V6K~D
Throttle_ICOUT
28
27
1 2 GNDA_CHG
1
1
PC135 GNDA_CHG PU9
2
1U_0805_25V6K~D
CSSP
CSSN
ICREF
2
PR145 2 1 22 26
49.9K_0402_1%~D DCIN ICOUT PR144 @ PR148
RB751V_SOD323~D
2 1 2 0_0603_5%~D 33_0603_1%~D
PR146 ACIN
BOOT 25 1 2
15.8K_0402_1%~D
PC136 1 2 13
1
<38> ACAV_IN_NB ACOK
1
PC137
0.1U_0603_25V7K~D
0_0402_5%~D
1
PD14
C C
SI4800BDY-T1_SO8~D
SI4800BDY-T1_SO8~D
2 1 11 VDDSMB
5
6
7
8
5
6
7
8
@ PR147
0.01U_0402_25V7K~D 10 PC138
2
SCL
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1U_0603_10V6K~D
PQ27
PQ28
GNDA_CHG +3.3V_ALW 9 21 ISL88731_VDDP 1 2
2
SDA VDDP
1
PC142
PC139
PC140
PC141
GNDA_CHG 14 NC 4 4
24 CHG_UGATE
ISL88731_ICM UGATE
8
2
VICM
1
23 2 PR149
1
PC143 PHASE 0_0603_5%~D
6
3
2
1
3
2
1
FBO
3300PF_0402_50V7K~D
0.1U_0402_10V7K~D
2
1 2 5 @ PC144
PR150 EAI 220P_0402_50V7K~D
2
4.7K_0402_5%~D
GNDA_CHG 200K_0402_5%~D 1 2 1 2 4 20 CHG_LGATE

EAO LGATE
1
PBATT+
0.01U_0402_25V7K~D56P_0402_50VNPO~D
<6,27,38> CKG_SMBCLK PC145 PR151 PR153

PL14
1
PC146
2200P_0402_50V7K~D 7.5K_0402_5%~D 0.01_1206_1%~D
5.6U_HMU1356-5R6_8.8A_20%~D
PR152
<6,27,38> CKG_SMBDAT
2
2
PC147
ISL88731_VREF 3 19 +VCHGR_B 2 1+VCHGR_L 1 4

VREF PGND
D 5
D 6
D 7
D 8
1.8K_1206_5%~D
18 @
CSOP
1500P_0603_25V7K~D
2200P_0402_50V7K~D
PC148 PR154 2 3
2
<18> ISL88731_ICM
PR156 @
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0_0402_5%~D
0.1U_0603_25V7K~D
120P_0402_50VNPO~D
SI4810BDY-T1-E3_SO8~D
1 2 7 CE CSON 17
220P_0402_25V8K~D
16.2K_0402_1%~D
1 2 10K_0402_5%~D
1
1
PC217
0.1U_0402_10V7K~D
VFB 15 1 PR157 2 PBATT+

1
1
PQ29
PR155
PC149
PC159
1U_0603_10V6K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12 GND 4 G
1
PR158
PC155
PC156
PC157
PC158
16 0_0402_5%~D
2
NC
1
1
@ PC150
PC151
@ PC152
PC153
PC154
29 @
2
2
TP
S
S
S
4.7_1206_5%~D
@ PC160 PC161 @
2
2
2
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
2
3
2
1
PR227
RHU002N06_SOT323
@ @ BQ24745RHDR_QFN28_5X5~D 1 2 1 2
1
D
PQ30
B @ B
2
1
G
GNDA_CHG S
3
@
GNDA_CHG
ACAV_IN_NB
GNDA_CHG Maximum charging current is 6.24A

PJP20
Throttle_ICREF
ISL88731_VREF 1 2
1 Throttle_ICOUT
+5V_ALW +3.3V_ALW
2
PR229 PAD-OPEN1x1m
100K_0402_5%~D
0_0402_5%~D PR159
1M_0402_1%~D GNDA_CHG
1
51.1K_0402_1%~D
1 2
1
1
200K_0402_1%~D
200K_0402_1%~D
PR162
PR160
PR161
1
100K_0402_1%~D
PR230
ISL88731_ICM 1 2
1
PR228
8.45K_0402_5%~D
2
2
PR163
@
2
@ GNDA_CHG ADAPT_OC <37>

2
PU10A
2
@ PR164 LM393DR_SO8~D D
2
G
IN-
1K_0402_5%~D
33.2K_0402_1%~D
O 1 2
G
1 2 3 IN+ 1
P
17.8K_0402_1%
10P_0402_50V8J~D
PAD~D T43 S +5V_ALW

3
1
100P_0402_50V8J
PC163
PR166
0.1U_0402_10V7K~D
PQ31
8
1
100P_0402_50V8J
PR165
0.01U_0402_25V7K~D
RHU002N06_SOT323
1
8
100P_0402_50V8J
0.01U_0402_25V7K~D
1
PC162
PC166
@ 5
P
2
IN+
1
1
PC164
PC165
A A
7
2
O
1
1
PC167
PC168
6
2
IN-
G
PU10B
2
2
348_0402_1%~D
LM393DR_SO8~D
2
4
1
+5V_ALW GNDA_CHG GNDA_CHG GNDA_CHG DELL CONFIDENTIAL/PROPRIETARY

PR167
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG

GNDA_CHG Compal Electronics, Inc.
2
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, MB A4042
GNDA_CHG GNDA_CHG AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401533
5 4 3 2 1
5 4 3 2 1
PD16
B540C~D
2 1
FDS6679AZ_SO8~D
PQ34
+DOCK_PWR_BAR 8 1
7 2
6 3 PQ35B
3
240K_0402_5%~D
0.47U_0805_25V7K~D
5 IMD2AT-108_SC74-6~D
+3.3V_ALW +3.3V_ALW
22K_0402_5%~D
1
D D
1
PC192
PR197
2
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
PR198
4
2
1
1
PR199
PR271
PR272
2
4
2
47K_0402_1%~D
5
PQ36
NB_AC_OFF <37,43>
1
+3.3V_ALW2 PQ35A RHU002N06_SOT323
1
D D
PR200
2 PQ50 IMD2AT-108_SC74-6~D 2
6
EN_DOCK_PWR_BAR <37>
100K_0402_5%~D
G RHU002N06_SOT323 G
S S
3
1
1
D
PR299
2 PQ51 1 2
G RHU002N06_SOT323
22K_0402_5%~D
S PR201
3
1
22K_0402_5%~D
2
1
D
PR273
2 +5V_ALW
<35,38> ACAV_IN_DOCK# G
PQ37 S
22K_0402_5%~D
1
RHU002N06_SOT323
PR274
2
+3.3V_ALW2
C C
NB_AC_OFF_BJT <43>
100K_0402_5%~D
1
D FDS6679AZ_SO8~D FDS6679AZ_SO8~D
1
2 PQ52 PQ38 PQ39

PR300
G RHU002N06_SOT323
S
3
1 8 8 1
PBATT+ 2 7 +PBATT_PSRC 7 2 +PWR_SRC
2
240K_0402_5%~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
3 6 6 3
ACAV_IN_DOCK <38,48> 5 5
1
PC193
PC194
PR202
2
2
1
D PQ67
RHU002N06_SOT323 +DC_IN_SS
2
1
1
G PQ40B
S
3
IMD2AT-108_SC74-6~D
33K_0402_5%~D
2
<37> PBATT_OFF 5
PR203
2
PQ40A PR204
1
47K_0402_5%~D
IMD2AT-108_SC74-6~D
1
B B
A A
Title
5 4 3 2 1
5 4 3 2 1
PL16
FBMJ4516HS720NT_1806~D
+GPU_PWR_SRC 1 2 +PWR_SRC
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0603_50V4Z~D
1 1 1 1 2
PC225
PC195
PC196
PC197
PC198
@PJP24
@ PJP24
D D
1 2
PR205 +5V_RUN 2 2 2 2 1 PAD-OPEN 43X118

10_0805_5%~D
GFX_+5V_RUN 1 2
1U_0603_10V4Z~D
2.2U_0603_6.3V6K~D
1 1 GPU_CORE
PC199
PC200
5
6
7
8
Thermal Design Current:7.7A
RB751V_SOD323~D
PQ41
D
D
D
D
2
2 2 SI4386DY_T1_SO8~D
Peak current: 11A
PD17
4
OCP min: 12A
G
1
1
S
S
S
GNDA_GPU_CORE
@ PR206
26
28
22
3
2
1
2
61.9K_0402_1%~D PU12
PR209 PC201 PL17
OVP/ UVP
AVDD
VDD
TP0
4.7_1206_5%~D 1500P_0603_25V7K~D
2 17 0_0603_5%~D 0.22U_0603_10V7K~D 0.88UH_MPC1040LR88_17A_20%~D
VIN
BST 20 1 2 1 2 1 2 +VCC_GFX_CORE
0.1U_0402_10V7K~D
330U_D2E_2.5VM~D
330U_D2E_2.5VM~D
GFX_CORE_PWRGD 5
<41,53> GFX_CORE_PWRGD POK1
10_0402_5%~D
2200P_0402_50V7K~D
330U_D2E_2.5VM~D
1
PC227
1.1V_GFX_PWRGD 6 18 1 1 1
<41> 1.1V_GFX_PWRGD POK2 DH
5
6
7
8
5
6
7
8
PR207
PC202
FDS6676AS_NL_SO8~D
FDS6676AS_NL_SO8~D
1
1
+
PC203
PC204
+
PC226
2 1 27 +
<19,28,37,40,41> RUN_ON SHDN
PC205
@ PR208 0_0402_5%~D 19 @
GFX_REF
LX
PQ42
PQ58
<37> GFX_CORE_ON 2 1
2
PR210 0_0402_5%~D 2 2 2 2
7 STBY
1000P_0402_50V7K~D
DL 21 4 4
2
C C
PR241
+FBVDDQ 13 VTTI 1
PC206
PGND1 23
1
MAX8632ETI+_TQFN28~D
GPU_VDD_SENSE <53>
3
2
1
3
2
1
1 14 @ PR211
1
REFIN @ 2 24.9K_0402_1%~D
VOUT 16
PC207
10U_0805_10V4Z~D 11
2
2 PGND2
FB 15
1
+1.1VRUNP 12 VTT
1 2 1 PR213
TON
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
9 @ PR212
@PR212 88.7K_0402_1%
VTTS
0.22U_0402_10V4Z~D
0_0402_5%~D
1 1 10 3 GFX_REF
2
VTTR REF
PC208
PC209
SKIP
1
GND
GND
ILIM
PC210
SS
1
2 2
PR214
29
24
25
4
100K_0402_1%~D 2
1U_0603_10V4Z~D
0.047U_0402_16V4Z~D
1 GNDA_GPU_CORE
1
PC211
1 PR215
2
PC212
GNDA_GPU_CORE 90.9K_0402_1%~D
2
2 1
@ PR216 0_0402_5%~D
2
1
2
+3.3V_RUN
100P_0402_50V8J~D
PR217
PC213
100K_0402_1%~D
1
1
1
GNDA_GPU_CORE PR236
301_0402_1%~D
221K_0402_1%
PR219
B PR218 B
100K_0402_5%~D GNDA_GPU_CORE 2
2
PR220 GNDA_GPU_CORE
2
487_0402_1%
1
+3.3V_RUN
301_0402_1%~D
1 2
PR238
0.01U_0402_16V7K~D
GNDA_GPU_CORE 1
1
1 PC223
2
PC214
PR221 100P_0402_50V8J~D
2
4.87K_0402_1% PR222 +3.3V_RUN 2
10K_0402_5%~D
PJP27 2
2
2 1
1
2
D GNDA_GPU_CORE
GPU_VID_0 2 1 2 PQ43 PR240
PAD-OPEN1x1m <51> GPU_VID_0
0.01U_0402_16V7K~D
G BSS138W-7-F_SOT323~D 10K_0402_5%~D
100K_0402_5%~D
GNDA_GPU_CORE GNDA_GPU_CORE PR223 S
3
10K_0402_5%~D
1
1
1
GNDA_GPU_CORE D
1
PR224
PC215
GPU_VID_1 2 1 2 PQ44
<51> GPU_VID_1
0.01U_0402_16V7K~D
G BSS138W-7-F_SOT323~D
100K_0402_5%~D
PR237 S
3
2 10K_0402_5%~D
2
1
@PJP36
@ PJP36 1
PR239
PC224
1 2
PAD-OPEN 43X118
0.9V 1.09V 1.17V 2
2
@PJP37
@ PJP37
+VCC_GFX_CORE 1 2 +GPU_CORE
default GNDA_GPU_CORE
PAD-OPEN 43X118
A A
GPU_VID_0 0 1 1
GNDA_GPU_CORE
@PJP28
@ PJP28
output voltage adjustable network
1 2
GPU_VID_1 0 0 1
+1.1VRUNP
PAD-OPEN 43X79
+1.1V_GFX_PCIE
401533
5 4 3 2 1
5 4 3 2 1
PEG_MTX_GRX_P[0..15]
<12> PEG_MTX_GRX_P[0..15]
U44A U44C
PEG_MTX_GRX_N[0..15] LCD_ACLK+_GPU AC4 G4
<12> PEG_MTX_GRX_N[0..15] <19> LCD_ACLK+_GPU IFPA_TXC IFPC_AUX DPB_AUX <21>
PEG_MTX_GRX_P0 AE12 Part 1 of 5 N1 LCD_ACLK-_GPU AD4 Part 3 of 5 G5
PEG_MRX_GTX_P[0..15] PEX_RX0 GPIO0 <19> LCD_ACLK-_GPU IFPA_TXC_N IFPC_AUX_N DPB_AUX# <21>
PEG_MTX_GRX_N0 AF12 G1 DPB_HPD# LCD_A0+_GPU V5 P4 DPB_LANE_P0
<12> PEG_MRX_GTX_P[0..15] PEX_RX0_N GPIO1 DPB_HPD# <21> <19> LCD_A0+_GPU IFPA_TXD0 IFPC_L0
PEG_MTX_GRX_P1 AG12 C1 BIA_PWM_GPU LCD_A0-_GPU V4 N4 DPB_LANE_N0
PEG_MRX_GTX_N[0..15] PEX_RX1 GPIO2 BIA_PWM_GPU <19> <19> LCD_A0-_GPU IFPA_TXD0_N IFPC_L0_N
PEG_MTX_GRX_N1 AG13 M2 ENVDD_GPU LCD_A1+_GPU AA5 M5 DPB_LANE_P1
<12> PEG_MRX_GTX_N[0..15] PEX_RX1_N GPIO3 ENVDD_GPU <19> <19> LCD_A1+_GPU IFPA_TXD1 IFPC_L1
PEG_MTX_GRX_P2 AF13 M3 PANEL_BKEN_GPU LCD_A1-_GPU AA4 M4 DPB_LANE_N1
PEX_RX2 GPIO4 PANEL_BKEN_GPU <37> <19> LCD_A1-_GPU IFPA_TXD1_N IFPC_L1_N
PEG_MRX_GTX_P0 0.1U_0402_10V7K~D 2 1 C716 PEG_MRX_GTX_C_P0 PEG_MTX_GRX_N2 AE13 K3 GPU_VID_0 LCD_A2+_GPU W4 L4 DPB_LANE_P2
PEX_RX2_N GPIO5 GPU_VID_0 <50> <19> LCD_A2+_GPU IFPA_TXD2 IFPC_L2
PEG_MRX_GTX_N0 0.1U_0402_10V7K~D 2 1 C717 PEG_MRX_GTX_C_N0 PEG_MTX_GRX_P3 AE15 K2 GPU_VID_1 LCD_A2-_GPU Y4 K4 DPB_LANE_N2
PEX_RX3 GPIO6 GPU_VID_1 <50> <19> LCD_A2-_GPU IFPA_TXD2_N IFPC_L2_N
PEG_MTX_GRX_N3 AF15 J2 AB4 H4 DPB_LANE_P3
PEX_RX3_N GPIO7 IFPA_TXD3 IFPC_L3
DVO / GPIO
MXM/DVI/DP
PEG_MRX_GTX_P1 0.1U_0402_10V7K~D 2 1 C718 PEG_MRX_GTX_C_P1 PEG_MTX_GRX_P4 AG15 C2 1 2 AB5 J4 DPB_LANE_N3
PEX_RX4 GPIO8 THERMTRIP_VGA# <18> IFPA_TXD3_N IFPC_L3_N
PEG_MRX_GTX_N1 0.1U_0402_10V7K~D 2 1 C719 PEG_MRX_GTX_C_N1 PEG_MTX_GRX_N4 AG16 M1 R670 0_0402_5%~D LCD_BCLK+_GPU AB3
PEX_RX4_N GPIO9 <19> LCD_BCLK+_GPU IFPB_TXC
PEG_MTX_GRX_P5 AF16 D2 1 R889 2 0_0402_5%~D LCD_BCLK-_GPU AB2 R5 1 2
PEX_RX5 GPIO10 GPIO10_REF_SW <55> <19> LCD_BCLK-_GPU IFPB_TXC_N IFPC_RSET
LVDS
D PEG_MRX_GTX_P2 0.1U_0402_10V7K~D 2 1 C720 PEG_MRX_GTX_C_P2 PEG_MTX_GRX_N5 AE16 D1 2 1 LCD_B0+_GPU W1 @ R720 1K_0402_1%~D D
PEX_RX5_N GPIO11 <19> LCD_B0+_GPU IFPB_TXD4
PEG_MRX_GTX_N2 0.1U_0402_10V7K~D 2 1 C721 PEG_MRX_GTX_C_N2 PEG_MTX_GRX_P6 AE18 J3 C982 0.1U_0402_10V7K~D LCD_B0-_GPU V1 D3
PEX_RX6 GPIO12 <19> LCD_B0-_GPU IFPB_TXD4_N IFPE_AUX DPC_DOCK_AUX <21>
PEG_MTX_GRX_N6 AF18 J1 1 2 LCD_B1+_GPU W3 D4
PEX_RX6_N GPIO13 <19> LCD_B1+_GPU IFPB_TXD5 IFPE_AUX_N DPC_DOCK_AUX# <21>
PEG_MRX_GTX_P3 0.1U_0402_10V7K~D 2 1 C722 PEG_MRX_GTX_C_P3 PEG_MTX_GRX_P7 AG18 K1 R890 10K_0402_5%~D LCD_B1-_GPU W2 F5 DPC_LANE_P0
PEX_RX7 GPIO14 <19> LCD_B1-_GPU IFPB_TXD5_N IFPE_L0
PEG_MRX_GTX_N3 0.1U_0402_10V7K~D 2 1 C723 PEG_MRX_GTX_C_N3 PEG_MTX_GRX_N7 AG19 F3 DPC_DOCK_HPD# LCD_B2+_GPU AA2 F4 DPC_LANE_N0
PEX_RX7_N GPIO15 DPC_DOCK_HPD# <35> <19> LCD_B2+_GPU IFPB_TXD6 IFPE_L0_N
PEG_MTX_GRX_P8 AF19 G3 GPU_GPIO16 LCD_B2-_GPU AA3 E4 DPC_LANE_P1
PEX_RX8 GPIO16 <19> LCD_B2-_GPU IFPB_TXD6_N IFPE_L1
PEG_MRX_GTX_P4 0.1U_0402_10V7K~D 2 1 C724 PEG_MRX_GTX_C_P4 PEG_MTX_GRX_N8 AE19 G2 DPB_GPU_P14 AB1 D5 DPC_LANE_N1
PEG_MRX_GTX_N4 0.1U_0402_10V7K~D C725 PEG_MRX_GTX_C_N4 PEG_MTX_GRX_P9 PEX_RX8_N GPIO17 GPU_GPIO18 IFPB_TXD7 IFPE_L1_N DPC_LANE_P2
2 1 AE21 PEX_RX9 GPIO18 F1 AA1 IFPB_TXD7_N IFPE_L2 C3
PEG_MTX_GRX_N9 AF21 F2 HDMI_DET1 T119PAD~D C4 DPC_LANE_N2
PEG_MRX_GTX_P5 0.1U_0402_10V7K~D PEX_RX9_N GPIO19 IFPE_L2_N
2 1 C726 PEG_MRX_GTX_C_P5 PEG_MTX_GRX_P10 AG21 PEX_RX10
@ 2 1 AB6 IFPAB_RSET IFPE_L3 B3 DPC_LANE_P3
PEG_MRX_GTX_N5 0.1U_0402_10V7K~D 2 1 C727 PEG_MRX_GTX_C_N5 PEG_MTX_GRX_N10 AG22 AD2 CRT_HSYNC_GPU @R672
@ R672 1K_0402_5%~D B4 DPC_LANE_N3
PEX_RX10_N DACA_HSYNC CRT_HSYNC_GPU <20> IFPE_L3_N
PEG_MTX_GRX_P11 AF22 AD1 CRT_VSYNC_GPU 1 2 A7
PEX_RX11 DACA_VSYNC CRT_VSYNC_GPU <20> <23> ICH_AZ_GPU_BITCLK HDA_BCLK
PEG_MRX_GTX_P6 0.1U_0402_10V7K~D 2 1 C728 PEG_MRX_GTX_C_P6 PEG_MTX_GRX_N11 AE22 AE2 CRT_RED_GPU @ R673 1 2 33_0402_5%~D B7 M6 1 2
HDA
PEX_RX11_N DACA_RED CRT_RED_GPU <20> <23> ICH_AZ_GPU_SYNC HDA_SYNC IFPE_RSET
PEG_MRX_GTX_N6 0.1U_0402_10V7K~D 2 1 C729 PEG_MRX_GTX_C_N6 PEG_MTX_GRX_P12 AE24 AD3 CRT_BLU_GPU @ R674 1 2 33_0402_5%~D A6 @ R721 1K_0402_1%~D
PEX_RX12 DACA_BLUE CRT_BLU_GPU <20> <23> ICH_AZ_GPU_SDIN2 HDA_SDI
PEG_MTX_GRX_N12 AF24 AE3 CRT_GRN_GPU @ R675 1 2 33_0402_5%~D B6 C9 ROM_SCLK_GPU
PEX_RX12_N DACA_GREEN CRT_GRN_GPU <20> <23> ICH_AZ_GPU_SDOUT HDA_SDO ROM_SCLK
PEG_MRX_GTX_P7 0.1U_0402_10V7K~D 2 1 C730 PEG_MRX_GTX_C_P7 PEG_MTX_GRX_P13 AG24 AE1 DACA_RSET 1 2 @ R676 1 2 33_0402_5%~D C6 A10 ROM_SI_GPU
PEX_RX13 DACA_RSET <23> ICH_AZ_GPU_RST# HDA_RST_N ROM_SI
PEG_MRX_GTX_N7 0.1U_0402_10V7K~D 2 1 C731 PEG_MRX_GTX_C_N7 PEG_MTX_GRX_N13 AF25 AF1 DACA_VREF R677 124_0402_1%~D1 2 @ R678 33_0402_5%~D C10 ROM_SO_GPU
PEG_MTX_GRX_P14 PEX_RX13_N DACA_VREF C732 ROM_SO
AG25 PEX_RX14 C15 RFU0(NC) ROMCS_N B10
PEG_MRX_GTX_P8 0.1U_0402_10V7K~D 2 1 C733 PEG_MRX_GTX_C_P8 PEG_MTX_GRX_N14 AG26 F7 TV_C_GPU 0.1U_0402_10V7K~D D15
PEX_RX14_N DACB_RED TV_C_GPU <20> RFU1(NC)
PEG_MRX_GTX_N8 0.1U_0402_10V7K~D 2 1 C734 PEG_MRX_GTX_C_N8 PEG_MTX_GRX_P15 AF27 E6 TV_CVBS_GPU J5 C7 STRAP0
PEX_RX15 DACB_BLUE TV_CVBS_GPU <20> RFU2(NC) STRAP0
PEG_MTX_GRX_N15 TV_Y_GPU STRAP1
PEG_MRX_GTX_P9 0.1U_0402_10V7K~D 2 1 C735 PEG_MRX_GTX_C_P9
AE27 PEX_RX15_N DACB_GREEN E7
F8 DACB_RSET 1
TV_Y_GPU <20>
2 DP Conn.
F6
J22
RFU3(NC) GENERAL STRAP1 B9
A9 STRAP2
DACB_RSET RFU4(NC) STRAP2
DACs
PEG_MRX_GTX_N9 0.1U_0402_10V7K~D 2 1 C736 PEG_MRX_GTX_C_N9 PEG_MRX_GTX_C_P0 AD10 D6 R679 124_0402_1%~D GPIO16 GPIO17 L22 F10 STRAP_CAL_PU_GND0
PEX_TX0 DACB_CSYNC function RFU5(NC) STRAP_CAL_PD_3V3(NC)
PCI EXPRESS
PEG_MRX_GTX_C_N0 AD11 G6 DACB_VREF 1 2 AG9 F11 STRAP_CAL_PU_GND1
PEG_MRX_GTX_P10 0.1U_0402_10V7K~D PEX_TX0_N DACB_VREF RFU6(NC) STRAP_CAL_PD_MIOB(NC)
2 1 C738 PEG_MRX_GTX_C_P10 PEG_MRX_GTX_C_P1 AD12 PEX_TX1
C737 0.1U_0402_10V7K~D 1 X DP AE9 RFU7(NC)
PEG_MRX_GTX_N100.1U_0402_10V7K~D 2 1 C739 PEG_MRX_GTX_C_N10 PEG_MRX_GTX_C_N1 AC12 U6 F9 SPDIF_OUT_GPU
PEG_MRX_GTX_C_P2 PEX_TX1_N DACC_HSYNC SPDIF
AB11 PEX_TX2 DACC_VSYNC U4 0 0 DVI AA6 NC0 BUFRST_N N5
PEG_MRX_GTX_P11 0.1U_0402_10V7K~D 2 1 C740 PEG_MRX_GTX_C_P11 PEG_MRX_GTX_C_N2 AB12 T5 AC19
PEG_MRX_GTX_N110.1U_0402_10V7K~D C741 PEG_MRX_GTX_C_N11 PEG_MRX_GTX_C_P3 PEX_TX2_N DACC_RED NC1
2 1 AD13 PEX_TX3 DACC_BLUE R4 0 1 HDMI E15 NC2 THERMDP D9 VGA_THERMDP <18>
PEG_MRX_GTX_C_N3 AD14 T4 T6 D8 1
PEG_MRX_GTX_P12 0.1U_0402_10V7K~D PEX_TX3_N DACC_GREEN NC3 THERMDN
2 1 C742 PEG_MRX_GTX_C_P12 PEG_MRX_GTX_C_P4 AD15 PEX_TX4 DACC_RSET V6
PEG_MRX_GTX_N120.1U_0402_10V7K~D 2 1 C743 PEG_MRX_GTX_C_N12 PEG_MRX_GTX_C_N4 AC15 R6 @ C744
C PEG_MRX_GTX_C_P5 PEX_TX4_N DACC_VREF 100P_0402_50V8K~D C
AB14 PEX_TX5
PEG_MRX_GTX_P13 0.1U_0402_10V7K~D 2
2 1 C745 PEG_MRX_GTX_C_P13 PEG_MRX_GTX_C_N5 AB15 PEX_TX5_N VGA_THERMDN <18>
PEG_MRX_GTX_N130.1U_0402_10V7K~D 2 1 C746 PEG_MRX_GTX_C_N13 PEG_MRX_GTX_C_P6 AC16 R1 CRT_CLK_DDC <---CRT NB9M-NS_BGA533~D
PEG_MRX_GTX_C_N6 PEX_TX6 I2CA_SCL CRT_DAT_DDC
AD16 PEX_TX6_N I2CA_SDA T3
PEG_MRX_GTX_P14 0.1U_0402_10V7K~D 2 1 C747 PEG_MRX_GTX_C_P14 PEG_MRX_GTX_C_P7 AD17 R2 DVI_C_CLK_DDC DVI_C_CLK_DDC <21> <---DVI C
PEG_MRX_GTX_N140.1U_0402_10V7K~D C749 PEG_MRX_GTX_C_N14 PEG_MRX_GTX_C_N7 PEX_TX7 I2CB_SCL DVI_C_DAT_DDC +3.3V_RUN
2 1 AD18 PEX_TX7_N I2CB_SDA R3 DVI_C_DAT_DDC <21> check GDDR3 and nonOpenGL
PEG_MRX_GTX_C_P8 AC18 A2 LDDC_CLK_GPU LDDC_CLK_GPU <19> <---LVDS Strap pin define
PEG_MRX_GTX_P15 0.1U_0402_10V7K~D PEX_TX8 I2CC_SCL
2 1 C752 PEG_MRX_GTX_C_P15 PEG_MRX_GTX_C_N8 AB18 B1 LDDC_DATA_GPU LDDC_DATA_GPU <19>
I2C
PEX_TX8_N I2CC_SDA
15K_0402_1%
20K_0402_1%~D
45.3K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
PEG_MRX_GTX_N150.1U_0402_10V7K~D 2 1 C754 PEG_MRX_GTX_C_N15 PEG_MRX_GTX_C_P9 AB19 N2 DVI_B_CLK_DDC DVI_B_CLK_DDC <21> <---DVI B
PEX_TX9 I2CD_SCL
1
PEG_MRX_GTX_C_N9 AB20 N3 DVI_B_DAT_DDC DVI_B_DAT_DDC <21>
PEG_MRX_GTX_C_P10 PEX_TX9_N I2CD_SDA I2CE_SCL
AD19 PEX_TX10 I2CE_SCL Y6
R713
R714
R715
R716
R717
R718
PEG_MRX_GTX_C_N10 AD20 W6 I2CE_SDA @ R858 0_0402_5%~D
PEG_MRX_GTX_C_P11 PEX_TX10_N I2CE_SDA HDCP_CLK GPU_GPIO16 1
AD21 PEX_TX11 I2CH_SCL A3 2 DPB_CA_DET <21>
PEG_MRX_GTX_C_N11 AC21 A4 HDCP_DAT
2
PEG_MRX_GTX_C_P12 PEX_TX11_N I2CH_SDA @ R859 0_0402_5%~D @ @ @
AB21 PEX_TX12 I2CS_SCL T1
PEG_MRX_GTX_C_N12 AB22 T2 GPU_GPIO18 1 2 STRAP0
PEX_TX12_N I2CS_SDA DPC_CA_DET <21,35>
PEG_MRX_GTX_C_P13 AC22 STRAP1
PEG_MRX_GTX_C_N13 PEX_TX13 JTAG_TCK_GPU
AD22 PEX_TX13_N JTAG_TCK AF3 T83 PAD~D @ STRAP2
PEG_MRX_GTX_C_P14 AD23 AG4 JTAG_TDI_GPU T84 PAD~D @ ROM_SCLK_GPU
PEG_MRX_GTX_C_N14 PEX_TX14 JTAG_TDI JTAG_TDO_GPU ROM_SI_GPU
AD24 PEX_TX14_N JTAG_TDO AE4 T85 PAD~D @
PEG_MRX_GTX_C_P15 AE25 AF4 JTAG_TMS_GPU T86 PAD~D @ ROM_SO_GPU
PEX_TX15 JTAG_TMS
TEST
15K_0402_1%
10K_0402_1%~D
10K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
PEG_MRX_GTX_C_N15 AE26 AG3 JTAG_RST#_GPU T87 PAD~D @ DPB_LANE_P0 2 1
PEX_TX15_N JTAG_TRST_N DPB_LANE_P0_C <21>
1
AD25 2 1 DPB_LANE_N0 C748 2 1 0.1U_0402_10V7K~D
TESTMODE DPB_LANE_N0_C <21>
<6> CLK_PCIE_VGA CLK_PCIE_VGA AB10 R680 10K_0402_5%~D DPB_LANE_P1 C750 2 1 0.1U_0402_10V7K~D
PEX_REFCLK DPB_LANE_P1_C <21>
R728
R729
R730
R719
R725
R726
<6> CLK_PCIE_VGA# CLK_PCIE_VGA# AC10 AF10 DPB_LANE_N1 C751 2 1 0.1U_0402_10V7K~D
PEX_REFCLK_N PEX_TSTCLK_OUT DPB_LANE_N1_C <21>
AE10 1 2 DPB_LANE_P2 C753 2 1 0.1U_0402_10V7K~D
PEX_TSTCLK_OUT_N DPB_LANE_P2_C <21>
<10,22,32> PLTRST1# R681 1 2 0_0402_5%~D AD9 R696 200_0402_1%~D DPB_LANE_N2 C755 2 1 0.1U_0402_10V7K~D @ @
DPB_LANE_N2_C <21>
2
PEX_TERMP PEX_RST_N DPB_LANE_P3 C756 0.1U_0402_10V7K~D @
AG10 PEX_TERMP 2 1 DPB_LANE_P3_C <21>
@ R872 10K_0402_5%~D DPB_LANE_N3 C757 2 1 0.1U_0402_10V7K~D
DPB_LANE_N3_C <21>
1 2 E9 D10 CLK_NV_27M <6> C758 0.1U_0402_10V7K~D Each strap pin represents a 4 bit value
XTALOUTBUFF XTALIN
<6> CLK_NVSS_27M 1 2 XTALSSIN_R D11 XTALSSIN
CLK XTALOUT E10 DPC_LANE_P0 2 1 DPC_LANE_P0_C <35>
B R686 0_0402_5%~D DPC_LANE_N0 C759 2 1 0.1U_0402_10V7K~D Pullup or Pulldown configures the MSB B
DPC_LANE_N0_C <35>
1
DPC_LANE_P1 C760 2 1 0.1U_0402_10V7K~D Resistor Value determines the 3 LSBs

DPC_LANE_P1_C <35>
@ R871 NB9M-NS_BGA533~D DPC_LANE_N1 C761 2 1 0.1U_0402_10V7K~D Resistor range is R*n
DPC_LANE_N1_C <35>
10K_0402_5%~D DPC_LANE_P2 C762 2 1 0.1U_0402_10V7K~D where n is 0-9 and R is 5K ohm.
DPC_LANE_P2_C <35>
DPC_LANE_N2 C763 2 1 0.1U_0402_10V7K~D For NVG98 NS part stuff R719, no-stuff R716
DPC_LANE_N2_C <35>
DPC_LANE_P3 C764 2 1 0.1U_0402_10V7K~D For NVG98 GLM part stuff R716, no-stuff R719
DPC_LANE_P3_C <35>
2
1 2 PEX_TERMP DPC_LANE_N3 C765 2 1 0.1U_0402_10V7K~D For Samsung 32Mx16 DDR2 part stuff R725=30K
+3.3V_RUN +3.3V_RUN DPC_LANE_N3_C <35>
R687 2.49K_0402_1%~D C766 0.1U_0402_10V7K~D For Qimonda 32Mx16 DDR2 part stuff R725=35K
For Hynix 32Mx16 DDR2 part stuff R725=45K
1 2
1
C610
R694 R695 0.1U_0402_10V7K~D U56 ROM_SCLK_GPU 1 2
2.2K_0402_5%~D 2.2K_0402_5%~D @ R841 10K_0402_5%~D @R825
@ R825 15K_0402_1%~D GFX_OPEN_GL_EN <37>
8 VCC A0 1 1 2
1 2 HDCP_WP 7 R752 2 0_0402_5%~D I2CE_SDA 1 2
@ R860 HDCP_CLK WP A1
6 1 3 2
2
0_0402_5%~D HDCP_DAT SCL A2 R753 +3.3V_RUN

5 SDA GND 4
0_0402_5%~D @ R843 10K_0402_5%~D
CRT_CLK_DDC 1 6 GPU_CLK_DDC GPU_CLK_DDC <20> 190-00001-0001-T03 AT88SC0808C_SO8~D I2CE_SCL 1 2
4.99K_0402_1%~D 4.99K_0402_1%~D
2
Q123A
1
2N7002DW-T/R7_SOT363-6~D +3.3V_RUN D63
2
R856
+3.3V_RUN DA204U_SOT323-3~D
HDCP_DAT 2 1 +3.3V_RUN
5
Q123B R758 10K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D HDCP_WP 1 2
1
1
CRT_DAT_DDC 4 3 GPU_DAT_DDC GPU_DAT_DDC <20> R96 10K_0402_5%~D <27> SPDIF_OUT 1 2 SPDIF_OUT_GPU

TV_C_GPU 1 2 R929
1
R688 150_0402_5%~D 10K_0402_5%~D C1032
R857
1 2 TV_CVBS_GPU 1 2 0.01U_0402_16V7K~D
@ R861 R689 150_0402_5%~D
2
0_0402_5%~D TV_Y_GPU 1 2 HDCP_CLK

A R690 150_0402_5%~D A
2
1
DPB_GPU_P14 1 2 CRT_RED_GPU 1 2
R855 10K_0402_5%~D DPB_MB_P14 <21> R691 150_0402_5%~D @ R801
CRT_GRN_GPU 1 2 10K_0402_5%~D
1
R692 150_0402_5%~D
R797 CRT_BLU_GPU 1 2
2
100K_0402_5%~D R693 150_0402_5%~D

STRAP_CAL_PU_GND0 1
R727
2
40.2K_0402_1% Stuff R824 for
2
STRAP_CAL_PU_GND1 1 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
R731 40.2K_0402_1% standard I2C ROM. TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
JTAG_RST#_GPU 1 2 Stuff R801 for BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, MB A4042
@ R853 1K_0402_5%~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
crypto ROM PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
401533
5 4 3 2 1
5 4 3 2 1
0..31 32..63
FBA_CMD0 A4
FBA_CMD1 RAS# RAS#

FBAD[0:63]
FBAD[0:63] <55,56>
DQMA#[0:7]
FBA_CMD2 A5
D
DQMA#[0:7] <55,56> D
DQSA_WP[0:7] FBA_CMD3 BA1 BA1
DQSA_WP[0:7] <55,56>
DQSA_RN[0:7]
DQSA_RN[0:7] <55,56>
FBA_CMD[0..27]
FBA_CMD4 A2
FBA_CMD[0..27] <55,56>
FBA_CMD5 A4
FBA_CMD6 A3
U44B
FBA_CMD7 CS1# CS1#
FBAD0 D21 F26 FBA_CMD0
FBAD1 FBAD0 FBA_CMD0 FBA_CMD1
C22 FBAD1 FBA_CMD1 J24
FBAD2 B22 F25 FBA_CMD2 FBA_CMD8 CS0# CS0#
FBAD3 FBAD2 Part 2 of 5 FBA_CMD2 FBA_CMD3
A22 FBAD3 FBA_CMD3 M23
FBAD4 C24 N27 FBA_CMD4
B25 FBAD5 FBA_CMD5 M27 FBA_CMD9 A11 A11
FBAD6 A25 K26 FBA_CMD6
A26 FBAD7 FBA_CMD7 J25
FBAD8 D22 J27 FBA_CMD8 FBA_CMD10 CAS# CAS#
E22 FBAD9 FBA_CMD9 G23
FBAD10 E24 G26 FBA_CMD10
D24 FBAD11 FBA_CMD11 J23 FBA_CMD11 WE# WE#
FBAD12 D26 M25 FBA_CMD12
D27 FBAD13 FBA_CMD13 K27
FBAD14 C27 G25 FBA_CMD14 FBA_CMD12 BA0 BA0
B27 FBAD15 FBA_CMD15 L24
FBAD16 D16 K23 FBA_CMD16
C
E16 FBAD17 FBA_CMD17 K24 FBA_CMD13 A5 C
FBAD18 D17 G22 FBA_CMD18
F18 FBAD19 FBA_CMD19 K25
FBAD20 D20 H22 FBA_CMD20 FBA_CMD14 A12 A12
F20 FBAD21 FBA_CMD21 M26
FBAD22 E21 H24 FBA_CMD22
F21 F27 FBA_CMD15 RST/ODT RST/ODT
INTERFACE
C16 FBAD24 FBA_CMD24 J26
FBAD25 B18 G24 FBA_CMD25
MEMORY
C18 FBAD26 FBA_CMD26 G27 T114PAD~D @ FBA_CMD16 A7 A7
FBAD27 D18 M24 FBA_CMD27
FBAD28 FBAD27 FBA_CMD27 SNN_FBA_CMD28
C19 FBAD28 FBA_CMD28 K22 T115PAD~D @
FBAD29 C21 FBA_CMD17 A10 A10
FBAD30 FBAD29 DQMA#0
B21 FBAD30 FBADQM0 D23
FBAD31 A21 C26 DQMA#1
FBAD32 FBAD31 FBADQM1 DQMA#2
P22 FBAD32 FBADQM2 D19 FBA_CMD18 CKE CKE
FBAD33 P24 B19 DQMA#3
FBAD34 FBAD33 FBADQM3 DQMA#4
R23 FBAD34 FBADQM4 T24
FBAD35 R24 T26 DQMA#5 FBA_CMD19 A0 A0
FBAD36 FBAD35 FBADQM5 DQMA#6 FBA_CMD15
T23 FBAD36 FBADQM6 AA23 1 2
FBAD37 U24 AB27 DQMA#7 R697 10K_0402_5%~D
FBAD38 FBAD37 FBADQM7 FBA_CMD18
V23 FBAD38 1 2 FBA_CMD20 A9 A9
FBAD39 V24 B24 DQSA_RN0 R698 10K_0402_5%~D
FBAD40 FBAD39 FBADQS_RN0 DQSA_RN1
N25 FBAD40 FBADQS_RN1 D25
FBAD41 N26 E18 DQSA_RN2 FBA_CMD21 A6 A6
R25 FBAD42 FBADQS_RN3 A18
FBAD43 R26 R22 DQSA_RN4 Pull-down for initialization
T25 FBAD44 FBADQS_RN5 R27
CKE & RESET/ODT FBA_CMD22 A2
FBAD45 V26 Y24 DQSA_RN6
V25 FBAD46 FBADQS_RN7 AA27
FBAD47 V27 FBA_CMD23 A8 A8
FBAD48 FBAD47 DQSA_WP0 +FBVDDQ
V22 FBAD48 FBADQS_WP0 A24
FBAD49 W22 C25 DQSA_WP1
B FBAD50 FBAD49 FBADQS_WP1 DQSA_WP2 B
W23 FBAD50 FBADQS_WP2 E19 FBA_CMD24 A3
1
1K_0402_1%~D
FBAD51 W24 A19 DQSA_WP3
FBAD52 FBAD51 FBADQS_WP3 DQSA_WP4
AA22 FBAD52 FBADQS_WP4 T22
R699
FBAD53 AB23 T27 DQSA_WP5 FBA_CMD25 A1 A1
FBAD54 FBAD53 FBADQS_WP5 DQSA_WP6
AB24 FBAD54 FBADQS_WP6 AA24
FBAD55 AC24 AA26 DQSA_WP7
2
FBAD56 FBAD55 FBADQS_WP7
W25 FBAD56 FBA_CMD26 A13 A13
FBAD57 W26 A16 FBA_VREF
FBAD58 FBAD57 FB_VREF 10mil
W27 FBAD58
FBAD59 AA25 F24 CLKA0 FBA_CMD27 BA2 BA2
FBAD59 FBA_CLK0 CLKA0 <55,56>
0.1U_0402_10V7K~D
FBAD60 AB25 F23 CLKA0#
FBAD60 FBA_CLK0_N CLKA0# <55,56>
1
1K_0402_1%~D
FBAD61 AB26 N24 CLKA1 1
FBAD62 FBAD61 FBA_CLK1 CLKA1# CLKA1 <55,56>
AD26 FBAD62 FBA_CLK1_N N23 CLKA1# <55,56> FBA_CMD28 RFU0 RFU0
C775
R700
FBAD63 AD27 M22 T88 PAD~D @
FBAD63 FBA_DEBUG
2 1 +FBVDDQ
R701 2
FBA_CMD29 RFU1 RFU1
2
10K_0402_5%~D
NB9M-NS_BGA533~D
FBA_CMD30 RFU2 RFU2
A A
401533
5 4 3 2 1
5 4 3 2 1
+15V_ALW +1.8V_MEM +1.8V_RUN Source

+FBVDDQ
100K_0402_5%~D
Q116 +FBVDDQ
1K_0402_5%~D
STS11NF30L_SO8~D
1
R813
8 1
@R500
@
+3.3V_ALW2 7 2
R500
6 3
1
20K_0402_5%~D
5 1
10U_0805_10V4Z~D
R814
2
1
C889
4
4700P_0402_25V7K~D
2N7002W-7-F_SOT323-3~D
R815 1.8V_RUN_ENABLE
1
2 D
@ Q2
100K_0402_5%~D
2
3
GFX_CORE_PWRGD_1.8V# 2 +1.1V_GFX_PCIE
1
Q117B G PEX_IOVDD = 500mA PEX_PLLVDD = 100mA +1.1V_GFX_PCIE
C897
2N7002DW-T/R7_SOT363-6 S 10 mil
3
D GFX_CORE_PWRGD_1.8V# 5 +PEX_PLLVDD D
2 1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V4Z~D
22U_0805_6.3VAM~D
0.1U_0402_10V7K~D
0.01U_0402_16V7K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V4Z~D
L65
6
10UH_LB2012T100MR_20%_0805~D
4
1 1 1 1 1 1 1 1 1 1
C778
C779
C780
C774
C782
C604
C784
C785
C786
C787
<41,50> GFX_CORE_PWRGD 2
Q117A
2N7002DW-T/R7_SOT363-6 +GPU_CORE U44D 2 2 2 2 2 2 2 2 2 2
Place near Balls
1
J10 VDD_0 PEX_IOVDD_0 AC9

J12 Part 4 of 5 AD7
VDD_1 PEX_IOVDD_1
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
10U_0805_10V4Z~D
J13 VDD_2 PEX_IOVDD_2 AD8 Place near Balls
J9 VDD_3 PEX_IOVDD_3 AE7 Place near GPU
1 1 1 1 L9 VDD_4 PEX_IOVDD_4 AF7 Place near Balls Place near GPU
M11 VDD_5 PEX_IOVDD_5 AG7
+1.1V_GFX_PCIE
C791
C792
C793
C645
M17 VDD_6 PEX_IOVDDQ_0 AB13 PEX_IOVDDQ = 1600mA
M9 VDD_7 PEX_IOVDDQ_1 AB16
2 2 2 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
22U_0805_6.3VAM~D
N11 VDD_8 PEX_IOVDDQ_2 AB17
N13 VDD_10 PEX_IOVDDQ_4 AB8 1 1 1 1 1 1
C795
C796
C797
C798
C799
C800
N15 VDD_12 PEX_IOVDDQ_6 AC13
N16 VDD_13 PEX_IOVDDQ_7 AC7
2 2 2 2 2 2
N17 VDD_14 PEX_IOVDDQ_8 AD6
N19 VDD_15 PEX_IOVDDQ_9 AE6
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
0.47U_0402_6.3V4Z~D
N9 VDD_16 PEX_IOVDDQ_10 AF6
P11 VDD_17 PEX_IOVDDQ_11 AG6 Place near Balls
1 1 1 1 1 1 1 P12 VDD_18
P13 VDD_19 PEX_PLLVDD AF9 +PEX_PLLVDD
C805
C806
C807
C808
C809
C810
C811
P14 VDD_20
P15 W15 G_VDD_S 1 2 +FBVDDQ
2 2 2 2 2 2 2 VDD_21 VDD_SENSE GPU_VDD_SENSE <50>
P16 R852 0_0402_5%~D
C VDD_22 C
+1.1V_GFX_PCIE
FB_PLLVDD = 20 mA P17 VDD_23 FBVDDQ_0 A13
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
R11 VDD_24 FBVDDQ_1 B13
+FB_PLLVDD
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
L44 R12 C13
BLM18AG121SN1D_0603~D VDD_25 FBVDDQ_2
R13 VDD_26 FBVDDQ_3 D13
1 2 +FB_PLLVDD R14 D14 1 1 1 1 1 1 1 1
VDD_27 FBVDDQ_4
R15 E13
POWER
VDD_28 FBVDDQ_5
C813
C814
C815
C816
C817
C818
C819
C820
R16 VDD_29 FBVDDQ_6 F13
4.7U_0603_6.3V6M~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 T11 VDD_32 FBVDDQ_9 F16
T17 VDD_33 FBVDDQ_10 F17
+FBVDDQ
C646
C828
C829
C812
C821
C822
C823
C824
C825
C826
T9 VDD_34 FBVDDQ_11 F19
U19 VDD_35 FBVDDQ_12 F22
2 2 2 2 2 2 2 2 2 2
U9 VDD_36 FBVDDQ_13 H23
4700P_0402_25V7K~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
W10 VDD_37 FBVDDQ_14 H26
W12 VDD_38 FBVDDQ_15 J15
W13 VDD_39 FBVDDQ_16 J16 1 1 1 1 1 1 1 1 1 1 1 1 1
C830
C831
C832
C833
C834
C835
C836
C837
C838
C839
C840
C841
C842
+3.3V_RUN W9 L19
VDD_42 FBVDDQ_19 2 2 2 2 2 2 2 2 2 2 2 2 2
FBVDDQ_20 L23
A12 VDD33_0 FBVDDQ_21 L26
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
B12 VDD33_1 FBVDDQ_22 M19

C12 VDD33_2 FBVDDQ_23 N22
1 1 1 D12 VDD33_3 FBVDDQ_24 U22
E12 VDD33_4 FBVDDQ_25 Y22
C844
C845
C773
F12 VDD33_5
V3 +IFPAB_IOVDD
2 2 2 IFPA_IOVDD +1.1V_GFX_PCIE
+DACA_VDD AG2 DACA_VDD IFPB_IOVDD V2 +IFPX_IOVDD= 385mA GPU_PLLVDD = 140 mA
+DACB_VDD D7 J6 +IFPC_IOVDD
+DACC_VDD DACB_VDD IFPC_IOVDD +IFPE_IOVDD +GPU_PLLVDD
W5 DACC_VDD IFPE_IOVDD H6 1 2
4700P_0402_25V7K~D
L45
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
B +IFPAB_PLLVDD BLM18AG121SN1D_0603~D B
+FB_PLLVDD R19 FB_PLLAVDD IFPAB_PLLVDD AD5
T19 P6 +IFPC_PLLVDD +IFPX_PLLVDD= 160mA
FB_DLLAVDD IFPC_PLLVDD +IFPE_PLLVDD
DACA VDD= 120mA IFPE_PLLVDD N6 1 1 1 1
+3.3V_RUN L46 1 2 FB_CAL_PD_VDDQ B15
+FBVDDQ FBCAL_PD_VDDQ
C847
C848
C849
C850
BLM18AG121SN1D_0603~D R706 44.2_0402_1%~D K5 +GPU_PLLVDD
+DACA_VDD PLLVDD
1 2 VID_PLLVDD K6
2 2 2 2
0.1U_0402_10V7K~D
SP_PLLVDD L6
4.7U_0603_6.3V6M~D
4700P_0402_25V7K~D
470P_0402_50V7K~D
2 1 +DACC_VDD
R722 10K_0402_5%~D
1 1 1 1
C852
C853
C854
C871
NB9M-NS_BGA533~D
L66 +FBVDDQ L67 +1.1V_GFX_PCIE
2 2 2 2 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D
+IFPC_PLLVDD 1 2 +IFPC_IOVDD 1 2
+FBVDDQ L47 +FBVDDQ
470P_0402_50V7K~D
4700P_0402_25V7K~D
4.7U_0603_6.3V6M~D
470P_0402_50V7K~D
4700P_0402_25V7K~D
4.7U_0603_6.3V6M~D
IFPAB_PLLVDD = 100 mA
IFPAB_IOVDD = 100mA L48 BLM18AG121SN1D_0603~D
1 1 1 1 1 1 BLM18AG121SN1D_0603~D +IFPAB_PLLVDD 1 2
220P_0402_50V8K~D
4700P_0402_25V7K~D
+IFPAB_IOVDD 1 2
C865
C863
C862
C880
C879
C866
470P_0402_50V7K~D
4700P_0402_25V7K~D
470P_0402_50V7K~D
4700P_0402_25V7K~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
C843
C858
C860
C861
C864
C855
C856
C857
C859
DACB VDD= 150mA
+3.3V_RUN L49 L75 L76 2 2 2 2 2 2 2 2 2
BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D
1 2 +DACB_VDD +IFPE_PLLVDD 1 2 +IFPE_IOVDD 1 2
0.1U_0402_10V7K~D
470P_0402_50V7K~D
4700P_0402_25V7K~D
4.7U_0603_6.3V6M~D
470P_0402_50V7K~D
4700P_0402_25V7K~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4700P_0402_25V7K~D
470P_0402_50V7K~D
1 1 1 1 1 1
1 1 1 1
C878
C783
C767
C888
C777
C794
A A
C867
C868
C869
C870
2 2 2 2 2 2
2 2 2 2
401533
5 4 3 2 1
5 4 3 2 1
D D
U44E
AC11 GND_0
AC14 Part 5 of 5 L16
GND_1 GND_48
AC17 GND_2 GND_49 L17
C AC2 GND_3 GND_50 L2 C
AC20 GND_4 GND_51 L5
AC23 GND_5 GND_52 M12
AF11 GND_9 GND_56 M16
AF14 GND_10 GND_57 P19
AF5 GND_16 GND_63 T12
AF8 GND_17 GND_64 T13
B11 GND_18 GND_65 T14
B14 GND_19 GND_66 T15
B17 GND_20 GND_67 T16
B2 GND_21 GND_68 U11
B20 GND_22 GND_69 U12
B23 GND_23 GND_70 U13
B26 GND_24 GND_71 U14
GND
B E11 GND_27 GND_74 U17 B

E14 GND_28 GND_75 U2
E17 GND_29 GND_76 U23
E23 GND_32 GND_79 V19
E26 GND_33 GND_80 V9
E5 GND_34 GND_81 W11
E8 GND_35 GND_82 W14
H2 GND_36 GND_83 W17
H5 GND_37 GND_84 Y2
J11 GND_38 GND_85 Y23
J14 GND_39 GND_86 Y26
J17 GND_40 GND_87 Y5
K19 GND_41
K9 GND_42 RFU_GND AC6
L11 GND_43
L12 W16 GND_SENSE 1 2
GND_44 GND_SENSE R707 0_0402_5%~D
L13 GND_45
L14 A15 FB_CAL_PU_GND 1 2
GND_46 FBCAL_PU_GND FBCAL_TERM_GND R703 1
L15 GND_47 FBCAL_TERM_GND B16 2 30.9_0402_1%
R84 40.2_0402_1%~D
A A
NB9M-NS_BGA533~D DELL CONFIDENTIAL/PROPRIETARY
Title
SCHEMATIC, MB A4042
5 4 3 2 1
5 4 3 2 1
32Mx32 GDDR3 32Mx32 GDDR3

FBAD[0..63]
FBAD[0..63] <52,56>
DQSA_WP[0..7]
DQSA_WP[0..7] <52,56>
G11
D12
B12
P12
T12
L11
DQSA_RN[0..7]
G2
D1
D4
D9
B1
B4
B9
P1
P4
P9
T1
T4
T9
L2
G11
D12
DQSA_RN[0..7] <52,56>
B12
P12
T12
L11
G2
U57
D1
D4
D9
B1
B4
B9
P1
P4
P9
T1
T4
T9
L2
U58 DQMA#[0..7]
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQMA#[0..7] <52,56>
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBA_CMD[0..27]
FBA_CMD[0..27] <52,56>
FBA_CMD19 K4
FBA_CMD25 A0 FBAD25 FBA_CMD5
H2 A1 DQ0 B2 K4 A0
FBA_CMD22 K3 B3 FBAD26 FBA_CMD13 H2 B2 FBAD62
D FBA_CMD24 A2 DQ1 FBAD27 FBA_CMD21 A1 DQ0 FBAD61 D
M4 A3 DQ2 C2 K3 A2 DQ1 B3
FBA_CMD0 K9 C3 FBAD24 FBA_CMD20 M4 C2 FBAD60
FBA_CMD2 A4 DQ3 FBAD29 FBA_CMD19 A3 DQ2 FBAD63
H11 A5 DQ4 E2 K9 A4 DQ3 C3
FBA_CMD21 K10 F3 FBAD28 FBA_CMD25 H11 E2 FBAD58
L9 A7 DQ6 F2 K10 A6 DQ5 F3
FBA_CMD23 K11 G3 FBAD30 FBA_CMD9 L9 F2 FBAD56
FBA_CMD20 A8/AP DQ7 FBAD17 FBA_CMD17 A7 DQ6 FBAD59
M9 A9 DQ8 B11 Mirror U58 K11 A8/AP DQ7 G3
FBA_CMD17 K2 B10 FBAD16 FBA_CMD6 M9 B11 FBAD55
T143 A10 DQ9 A9 DQ8
FBA_CMD9 L4 C11 FBAD18 RAS# --> BA2 FBA_CMD23 K2 B10 FBAD52
A11 DQ10 T144 A10 DQ9
J2 C10 FBAD21 CAS# --> CS0# FBA_CMD16 L4 C11 FBAD54
FBA_CMD12 A12 DQ11 FBAD20 A11 DQ10 FBAD53
G4 BA0 DQ12 E11 WE --> CKE J2 A12 DQ11 C10
FBA_CMD3 G9 F10 FBAD22 CS0# --> CAS# FBA_CMD3 G4 E11 FBAD48
CLKA0 DQMA#3 BA1 DQ13 FBAD23 FBA_CMD12 BA0 DQ12 FBAD49
E3 DM0 DQ14 F11 A0 --> A4 G9 BA1 DQ13 F10
DQMA#2 E10 G10 FBAD19 A1 --> A5 DQMA#7 E3 F11 FBAD50 CLKA1
DM1 DQ15 DM0 DQ14
2
DQMA#1 N10 M11 FBAD9 A2 --> A6 DQMA#6 E10 G10 FBAD51

DM2 DQ16 DM1 DQ15
2
DQMA#0 N3 L10 FBAD8 A3 --> A9 DQMA#4 N10 M11 FBAD37
R750 DM3 DQ17 FBAD15 DQMA#5 DM2 DQ16 FBAD38
DQ18 N11 A4 --> A0 N3 DM3 DQ17 L10
475_0402_1%~D DQSA_WP3 D2 M10 FBAD14 A5 --> A1 N11 FBAD36 R824
DQSA_WP2 WDQS0 DQ19 FBAD12 DQSA_WP7 DQ18 FBAD39 475_0402_1%~D
D11 R11 A6 --> A2 D2 M10
1
CLKA0# DQSA_WP1 WDQS1 DQ20 FBAD11 DQSA_WP6 WDQS0 DQ19 FBAD35

P11 R10 A7 --> A11 D11 R11
1
DQSA_WP0 WDQS2 DQ21 FBAD10 DQSA_WP4 WDQS1 DQ20 FBAD32 CLKA1#
P2 WDQS3 DQ22 T11 A8 --> A10 P11 WDQS2 DQ21 R10
243 ohm for NB8P T10 FBAD13 A9 --> A3 DQSA_WP5 P2 T11 FBAD34
FBA_VREF_1 DQ23 FBAD5 WDQS3 DQ22 FBAD33
475 ohm for NB9X H1 VREF DQ24 M2 A10 --> A8 DQ23 T10 243 ohm for NB8P
FBA_VREF_2 H12 L3 FBAD7 A11 --> A7 FBA_VREF_3 H1 M2 FBAD44
Place close to U57 VREF DQ25
N2 FBAD4 CKE --> WE# FBA_VREF_4 H12
VREF DQ24
L3 FBAD45 475 ohm for NB9X
DQ26 FBAD6 VREF DQ25 FBAD47
DQ27 M3 BA0 --> BA1 DQ26 N2 Place close to U58
R2 FBAD3 BA1 --> BA0 M3 FBAD46
FBA_CMD1 H3 RAS#
DQ28
DQ29 R3 FBAD1 BA2 --> RAS# U58 is Mirror DQ27
DQ28 R2 FBAD42
FBA_CMD10 F4 T2 FBAD2 NC/CS1# --> NV/CS1# FBA_CMD27 H3 R3 FBAD43
FBA_CMD11 CAS# DQ30 FBAD0 FBA_CMD8 RAS# DQ29 FBAD41
H9 WE# DQ31 T3 F4 CAS# DQ30 T2
FBA_CMD8 F9 FBA_CMD18 H9 T3 FBAD40
FBA_CMD14 CS0# FBA_CMD10 WE# DQ31
J3 A12/CS1# F9 CS0#
C FBA_CMD18 FBA_CMD14 C
H4 CKE VDDQ A1 +FBVDDQ J3 A12/CS1#
CLKA0 J11 A12 FBA_CMD11 H4 A1 +FBVDDQ
<52,56> CLKA0 CK VDDQ CKE VDDQ
CLKA0# J10 C1 CLKA1 J11 A12
<52,56> CLKA0# CK# VDDQ <52,56> CLKA1 CK VDDQ
C4 CLKA1# J10 C1
VDDQ <52,56> CLKA1# CK# VDDQ
1 2 ZQ1 A4 C9 C4
ZQ VDDQ ZQ2 VDDQ
A9 MF VDDQ C12 1 2 A4 ZQ VDDQ C9
R862 E1 +FBVDDQ A9 C12
243_0402_1%~D DQSA_RN3 VDDQ R863 MF VDDQ
D3 RDQS0 VDDQ E4 VDDQ E1
DQSA_RN2 D10 E9 243_0402_1%~D DQSA_RN7 D3 E4
DQSA_RN1 RDQS1 VDDQ DQSA_RN6 RDQS0 VDDQ
P10 RDQS2 VDDQ E12 D10 RDQS1 VDDQ E9
DQSA_RN0 P3 J4 DQSA_RN4 P10 E12
RDQS3 VDDQ DQSA_RN5 RDQS2 VDDQ
VDDQ J9 P3 RDQS3 VDDQ J4
+FBVDDQ A2 VDD VDDQ N1 VDDQ J9
A11 VDD VDDQ N4 +FBVDDQ A2 VDD VDDQ N1
FBA_VREF_1 FBA_VREF_1 <56> F1 N9 A11 N4
FBA_VREF_2 VDD VDDQ FBA_VREF_3 VDD VDDQ
FBA_VREF_2 <56> F12 VDD VDDQ N12 FBA_VREF_3 <56> F1 VDD VDDQ N9
M1 R1 FBA_VREF_4 FBA_VREF_4 <56> F12 N12
VDD VDDQ VDD VDDQ
M12 VDD VDDQ R4 M1 VDD VDDQ R1
V2 VDD VDDQ R9 M12 VDD VDDQ R4
V11 VDD VDDQ R12 V2 VDD VDDQ R9
V1 V11 R12 +FBVDDQ
VDDQ VDD VDDQ
V4 SEN VDDQ V12 VDDQ V1
FBA_CMD15 V9 V4 V12
RESET SEN VDDQ
1
FBA_CMD27 H10 K1 FBA_CMD15 V9
BA2 VDDA FBA_CMD1 RESET R864
VDDA K12 H10 BA2 VDDA K1
K12 511_0402_1%~D
VDDA
J1 VSSA
J12 J1 R831 12 mil
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA VSSA
J12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+FBVDDQ VSSA
0.01U_0402_16V7K~D
1 2 FBA_VREF_3
K4J10324QD-BC12_FBGA136~D
A3
A10
G1
G12
L1
L12
V3
V10
1
K4J10324QD-BC12_FBGA136~D 909_0402_1%~D
FBA_VREF_6
Avia 1
A3
A10
G1
G12
L1
L12
V3
V10
1
B B
C917
R734 R832
511_0402_1%~D 1.18K_0402_1%~D
2
2
R866 12 mil
2
2N7002W-7-F_SOT323-3~D
0.01U_0402_16V7K~D
1 2 FBA_VREF_1
1
1
909_0402_1%~D +FBVDDQ D +FBVDDQ
1
+FBVDDQ Place below decoupling caps close U58
Q118
FBA_VREF_5
Place below decoupling caps close U57 2

C872
R887 G
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1.18K_0402_1%~D S
1
2
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1 1 1 1 1 1 1 1 1 R865
2N7002W-7-F_SOT323-3~D
1 1 1 1 1 1 1 1 1 511_0402_1%~D
C890
C891
C892
C893
C899
C900
C881
C882
C883
C884
C901
C902
C903
R867 12 mil
C908
C909
C910
C911
C912
2
1
D +FBVDDQ 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K~D
1 2 FBA_VREF_4
2 2 2 2 2 2 2 2 2
Q119
1
G 909_0402_1%~D 1
S
3
C918
R868
R738 1.18K_0402_1%~D
511_0402_1%~D 2
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
R869 12 mil
2
0.01U_0402_16V7K~D
1 2 FBA_VREF_2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO10_REF_SW <51>

C894
C895
C896
1
C913
C914
C915
C916
C885
C886
C887
C904
C905
C906
C907
909_0402_1%~D 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2
C919
R870
1.18K_0402_1%~D
A 2 need check new value for NB9M A
2
GPIO10_REF_SW <51>
need check new value for NB9M Compal Electronics, Inc.
401533
5 4 3 2 1
5 4 3 2 1
32Mx32 GDDR3 32Mx32 GDDR3
G11
D12
B12
P12
T12
L11
FBAD[0..63]
G2
D1
D4
D9
B1
B4
B9
P1
P4
P9
T1
T4
T9
L2
G11
D12
FBAD[0..63] <52,55>
B12
P12
T12
U60
L11
G2
D1
D4
D9
U59
B1
B4
B9
P1
P4
P9
T1
T4
T9
L2
K4J10324QD-BC12_FBGA136~D DQSA_WP[0..7]
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQSA_WP[0..7] <52,55>
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQSA_RN[0..7]
DQSA_RN[0..7] <52,55>
FBA_CMD0 K4
FBA_CMD2 A0 FBAD17 FBA_CMD19 DQMA#[0..7]
Mirror U59 H2 A1 DQ0 B2 K4 A0 DQMA#[0..7] <52,55>
FBA_CMD21 K3 B3 FBAD16 FBA_CMD25 H2 B2 FBAD55
FBA_CMD20 A2 DQ1 FBAD18 FBA_CMD4 A1 DQ0 FBAD52 FBA_CMD[0..27]
RAS# --> BA2 M4 A3 DQ2 C2 K3 A2 DQ1 B3 FBA_CMD[0..27] <52,55>
CAS# --> CS0# FBA_CMD19 K9 C3 FBAD21 FBA_CMD6 M4 C2 FBAD54
D FBA_CMD25 A4 DQ3 FBAD20 FBA_CMD5 A3 DQ2 FBAD53 D
WE --> CKE H11 A5 DQ4 E2 K9 A4 DQ3 C3
CS0# --> CAS# FBA_CMD22 K10 F3 FBAD22 FBA_CMD13 H11 E2 FBAD48
A0 --> A4 L9 A7 DQ6 F2 K10 A6 DQ5 F3
A1 --> A5 FBA_CMD17 K11 G3 FBAD19 FBA_CMD16 L9 F2 FBAD50
FBA_CMD24 A8/AP DQ7 FBAD25 FBA_CMD23 A7 DQ6 FBAD51
A2 --> A6 M9 A9 DQ8 B11 K11 A8/AP DQ7 G3
A3 --> A9 FBA_CMD23 K2 B10 FBAD26 FBA_CMD20 M9 B11 FBAD62
T40 A10 DQ9 A9 DQ8
A4 --> A0 FBA_CMD16 L4 C11 FBAD27 FBA_CMD17 K2 B10 FBAD61
A11 DQ10 T146 A10 DQ9
A5 --> A1 J2 C10 FBAD24 FBA_CMD9 L4 C11 FBAD60
FBA_CMD3 A12 DQ11 FBAD29 A11 DQ10 FBAD63
A6 --> A2 G4 BA0 DQ12 E11 J2 A12 DQ11 C10
A7 --> A11 FBA_CMD12 G9 F10 FBAD28 FBA_CMD12 G4 E11 FBAD58
DQMA#2 BA1 DQ13 FBAD31 FBA_CMD3 BA0 DQ12 FBAD57
A8 --> A10 E3 DM0 DQ14 F11 G9 BA1 DQ13 F10
A9 --> A3 DQMA#3 E10 G10 FBAD30 DQMA#6 E3 F11 FBAD56
DQMA#0 DM1 DQ15 FBAD5 DQMA#7 DM0 DQ14 FBAD59
A10 --> A8 N10 DM2 DQ16 M11 E10 DM1 DQ15 G10
A11 --> A7 DQMA#1 N3 L10 FBAD7 DQMA#5 N10 M11 FBAD44
DM3 DQ17 FBAD4 DQMA#4 DM2 DQ16 FBAD45
CKE --> WE# DQ18 N11 N3 DM3 DQ17 L10
BA0 --> BA1 DQSA_WP2 D2 M10 FBAD6 N11 FBAD47
DQSA_WP3 WDQS0 DQ19 FBAD3 DQSA_WP6 DQ18 FBAD46
BA1 --> BA0 D11 WDQS1 DQ20 R11 D2 WDQS0 DQ19 M10
BA2 --> RAS# DQSA_WP0 P11 R10 FBAD1 DQSA_WP7 D11 R11 FBAD42
DQSA_WP1 WDQS2 DQ21 FBAD2 DQSA_WP5 WDQS1 DQ20 FBAD43
NC/CS1# --> NV/CS1# P2 WDQS3 DQ22 T11 P11 WDQS2 DQ21 R10
T10 FBAD0 DQSA_WP4 P2 T11 FBAD41
FBA_VREF_1 DQ23 FBAD9 FBAD9 WDQS3 DQ22 FBAD40
H1 VREF DQ24 M2 DQ23 T10
FBA_VREF_2 H12 L3 FBAD8 FBAD8 FBA_VREF_3 H1 M2 FBAD37
VREF DQ25 FBAD15 FBAD14 FBA_VREF_4 VREF DQ24 FBAD38
DQ26 N2 H12 VREF DQ25 L3
M3 FBAD14 FBAD15 N2 FBAD36
U59 is Mirror DQ27
DQ28 R2 FBAD12 FBAD12 DQ26
DQ27 M3 FBAD39
FBA_CMD27 H3 R3 FBAD11 FBAD11 R2 FBAD35
FBA_CMD7 RAS# DQ29 FBAD10 FBAD10 FBA_CMD1 DQ28 FBAD32
F4 CAS# DQ30 T2 H3 RAS# DQ29 R3
FBA_CMD18 H9 T3 FBAD13 FBAD13 FBA_CMD10 F4 T2 FBAD34
FBA_CMD10 WE# DQ31 FBA_CMD11 CAS# DQ30 FBAD33
F9 CS0# H9 WE# DQ31 T3
FBA_CMD14 J3 FBA_CMD7 F9
FBA_CMD11 A12/CS1# FBA_CMD14 CS0#
H4 CKE VDDQ A1 +FBVDDQ J3 A12/CS1#
CLKA0 J11 A12 FBA_CMD18 H4 A1 +FBVDDQ
C <52,55> CLKA0 CK VDDQ CKE VDDQ C
CLKA0# J10 C1 CLKA1 J11 A12
<52,55> CLKA0# CK# VDDQ <52,55> CLKA1 CK VDDQ
C4 CLKA1# J10 C1
VDDQ <52,55> CLKA1# CK# VDDQ
1 2 ZQ3 A4 C9 C4
ZQ VDDQ ZQ4 VDDQ
+FBVDDQ A9 MF VDDQ C12 1 2 A4 ZQ VDDQ C9
R873 E1 A9 C12
243_0402_1%~D DQSA_RN2 VDDQ R874 MF VDDQ
D3 RDQS0 VDDQ E4 VDDQ E1
DQSA_RN3 D10 E9 243_0402_1%~D DQSA_RN6 D3 E4
DQSA_RN0 RDQS1 VDDQ DQSA_RN7 RDQS0 VDDQ
P10 RDQS2 VDDQ E12 D10 RDQS1 VDDQ E9
DQSA_RN1 P3 J4 DQSA_RN5 P10 E12
RDQS3 VDDQ DQSA_RN4 RDQS2 VDDQ
VDDQ J9 P3 RDQS3 VDDQ J4
+FBVDDQ A2 VDD VDDQ N1 VDDQ J9
A11 VDD VDDQ N4 +FBVDDQ A2 VDD VDDQ N1
F1 VDD VDDQ N9 A11 VDD VDDQ N4
F12 VDD VDDQ N12 F1 VDD VDDQ N9
M1 VDD VDDQ R1 F12 VDD VDDQ N12
M12 VDD VDDQ R4 M1 VDD VDDQ R1
V2 VDD VDDQ R9 M12 VDD VDDQ R4
V11 VDD VDDQ R12 V2 VDD VDDQ R9
VDDQ V1 V11 VDD VDDQ R12
V4 SEN VDDQ V12 VDDQ V1
FBA_CMD15 V9 V4 V12
FBA_CMD1 RESET FBA_CMD15 SEN VDDQ
H10 BA2 VDDA K1 V9 RESET
K12 FBA_CMD27 H10 K1
VDDA BA2 VDDA
VDDA K12
J1 VSSA
J12 J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA VSSA
J12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
K4J10324QD-BC12_FBGA136~D
A3
A10
G1
G12
L1
L12
V3
V10
A3
A10
G1
G12
L1
L12
V3
V10
FBA_VREF_1 FBA_VREF_1 <55>
FBA_VREF_2 FBA_VREF_2 <55> FBA_VREF_3 FBA_VREF_3 <55>
B FBA_VREF_4 B
FBA_VREF_4 <55>
+FBVDDQ
+FBVDDQ
Place below decoupling caps close U48
Place below decoupling caps close U49
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
C960
C961
C942
C943
C944
C945
C962
C963
C964
C969
C970
C951
C952
C953
C971
C972
C954
C973
2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 1 1 1 1 1 1
1 1 1 1 1 1 1
C946
C947
C948
C965
C966
C967
C968
C955
C956
C957
C974
C975
C976
C977
2 2 2 2 2 2 2
2 2 2 2 2 2 2
A A
401533
5 4 3 2 1

HP Dv4 Intel Series Compal La4042p Laptop Schematics

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HP Dv4 Intel Series Compal La4042p Laptop Schematics

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A B C D E

PCB NO : LA-4042P (DAA00000T0L)

M09 Maybach DIS

Intel Cantiga PM + ICH9M

Compal confidential FAN Thermal Pentium-M Clock Generator

page 48 page 47 Int.KBD & +3.3V_ALW SCHEMATIC, MB A4042

POWER STATES USB PORT# DESTINATION

S5 (SOFT OFF) / M1 LOW HIGH LOW LOW HIGH ON ON ON OFF ON 4 WLAN

+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M 10 USH->BIO

S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 6 10/100/1G LAN

PCI DEVICE IDSEL REQ#/GNT# PIRQ

R5C847 AD17 REQ#1 / GNT#1 PIRQ[B..D]

+5V_HDD +5V_MOD +VDDA

SMBUS Address [TBD]

0 0 0 266 100 33.3

FSA 66 PCIE_ICH 1 2 CLK_PCIE_ICH

CLK_SIO_14M R35 1 2 22_0402_5%~D 67 PCIE_ICH# 1 2 CLK_PCIE_ICH#

DOT_96#/27M_SS SRC_6 R39 33_0402_5%~D

TME PIN 32 CLKREQ_5# 29

0 overclocking enabled 58 PCIE_EXP 1 2 CLK_PCIE_EXP

SMBCLK PCIE_EXP# CLK_PCIE_EXP#

CLKREQ_4# 57 EXPCLK_REQ# <32>

4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# <10>

ITP_EN PIN 37 R47 33_0402_5%~D

42 50 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA <23>

68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# <23>

@ 0=UMA DOT96T DOT96C 96/100M_T 96/100M_C 48

1=DIS 27M_out 27M SSout SRCT0 SRCC0 DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

H_FERR# A5 C7 100K_0402_5%~D E19 AB13

100P_0402_50V8K~D ITP_BPM2#2 B2 R980 R981 G4 AC21

R65 1 2 ITP_TDO AF25

+V_CPU_GTLREF_2 1K_0402_1%~D +3.3V_ALW 51_0402_5%~D

Resistor placed within 0.5" of

Reserve for testing

FSB BCLK BSEL2 BSEL1 BSEL0 +1.05V_VCCP

Route VCCSENSE and VSSSENSE trace at

1067 266 0 0 0 R78

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

High Frequence Decoupling

Near VCORE regulator.

M36 TP_MCH_RSVD1 T172PAD~D

DDR CLK/ CONTROL/COMPENSATION

H_D#_38 H_BREQ# H_BR0# <7> <24> DMI_MRX_ITX_P0 DMI_RXP_0

F13 H_REQ#2 R32 DPRSLPVR DPRSLPVR <24,47>

H_CPUSLP# E11 CL_DATA0 AH36

H_RS#_1 CL_RST# NC_2

+H_VREF B11 BH47

499_0402_1%~D <12> DDPC_CTRLDATA DDPC_CTRLDATA M28 BH46 R85 10K_0402_5%~D

CLK_3GPLLREQ# SDVO_CTRLDATA NC_10

<24> MCH_ICH_SYNC# MCH_ICH_SYNC# H36 BH43 SM_PWROK 2 1

PAD~D T34 ICH_AZ_MCH_SDIN2 B29 BG1

R93 2 2 ICH_AZ_MCH_SYNC HDA_SDO NC_22

R94 SMRCOMP_VOL CANTIGA ES_FCBGA1329~D

1K_0402_1%~D PLTRST1#_R 2 1 PLTRST1# <22,32,51>

Q4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

DDR_A_D[0..63] <16> DDR_B_D[0..63] <17>

<16> DDR_A_MA[0..14] SA_DQS#_7 SA_DQ_35 SB_DQS#_6 SB_DQ_35

BG26 SA_MA_11 SA_DQ_48 AV5 BB16 SB_MA_10 SB_DQ_48 AV2