Professional Documents
Culture Documents
Compal Confidential
www.laptopblue.vn
Model Name : A4DBH
File Name : LA-B731P
1 1
BOM P/N:43
ZZZ1
LA-B731P
DAA0008X000
DA2@
Compal Confidential
ZZZ2
LS-A131P
DA4001PG010
DA2@
ZZZ3
2 LS-B733P 2
DA60018L000
DA2@
ZZZ4
LS-A134P
DA4001PH010
DA2@
ZZZ6
3
LS-B734P
DA6001B8000
DA2@
ZZZ7
2014-09-25 3
HDMI LOGO
Rev:0.4
RO0000003HM
HDMI@
ZZZ8
LS-B732P
DA4001YF00S
DA2@
ZZZZ1
PCB
DAZ18000300
DAZ@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Thursday, September 25, 2014 Sheet 1 of 56
A B C D E
A B C D E
Compal Confidential
www.laptopblue.vn Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X1
BANK 0, 1, 2, 3 page 15
OPI
HDMI CH1 HDMI Conn. USB 3.0 WLAN CMOS
HDMI/DP HDMI/DP SW. page 28 DOCK CONN.
page 28 TMDS/DP conn x3 for BT Camera
USB port 2 USB port 0,1,3 USB port 6 USB port 4
DOCK CONN. CRT CH2 CRT CRT Conn. page 38 page 36 page 35 page 25
CRT SW. PCH- LP
page 38 page 27
CH1 page 27
USBx8
PCH 3.3V 48MHz
3 3
DOCK CONN.
LS-A131P Fan ENE KB9022 G-Sensor page 37
FUN/B page 39 LIS3DHTR
page 40 page 37 page 29
LS-B733P
USB/B page 36
LS-A134P LS-A136P
LID/B page 39 DC/DC Interface CKT.
4
Docking1/B page 38 4
page 41
LS-B734P LS-A137P
FP/B Docking2/B Power Circuit DC/DC
page 39 Security Classification Compal Secret Data Compal Electronics, Inc.
page 42~53
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 2 of 56
A B C D E
A B C D E
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STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S0 S3 S4 S5 S3 S4 S5
+RTCVCC RTC power ON ON ON ON ON ON ON Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A ON ON ON OFF OFF OFF
S0(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
BATT+ Battery power supply (9V or 19V) N/A N/A N/A N/A ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON ON ON ON ON S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF OFF OFF OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON** OFF OFF OFF OFF OFF OFF
1 +5VALW +5VALWP to +5VALW power rail ON ON ON ON ON ON ON S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF 1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Friday, September 19, 2014 Sheet 3 of 56
A B C D E
5 4 3 2 1
HASWELL_MCP_E
UU1A
<26>
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CPU_DP1_N0
C54
C55 DDI1_TXN0 EDP_TXN0
C45
B46
EDP_TXN0 <25>
<26> CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 <25>
B58 A47
<26> CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 <25>
C58 B47
DP to CRT <26> CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 <25>
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
<28> CPU_DP2_N0 DDI2_TXN0
C50 A45
<28> CPU_DP2_P0 DDI2_TXP0 EDP_AUXN EDP_AUXN <25>
C53 B45
<28> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP EDP_AUXP <25>
B54
HDMI <28>
<28>
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP RU1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
<28> CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
<28> CPU_DP2_N3 DDI2_TXN3
B53
<28> CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL <25>
1 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@
CU1 1 2 6.8P_0402_50V8C
@ESD@ TU1 @ D61
TU2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R @ TU3
+1.35V <37> H_PECI PECI PRDY K62 XDP_PREQ#_R @ TU4
2 1 RU2 RU3 JTAG
PREQ E60 XDP_TCK_R @ TU5
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS_R @ TU6
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R @ TU7
<37,42> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_R @ TU8
PROC_TDI
1
UU1 UU1
B UU1 UU1 UU1 UU1 UU1 Ci75500U B
NON-VPRO NON-VPRO
NON-VPRO NON-VPRO NON-VPRO VPRO non-VPRO
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HASWELL_MCP_E
UU1C
HASWELL_MCP_E
UU1D
<15> DDR_B_DQS[0..7]
3 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168 4 OF 19 Rev1p2
@ HASW ELL-MCP-E-ULT_BGA1168
@
A A
RU9
1
YU1
2
10M_0402_5%
PCH_RTCX1
PCH_RTCX2
+RTCVCC
CU5
1U_0402_10V6K
1
+RTCVCC
ME CMOS
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PCH_RTCX1 AW5
UU1E HASWELL_MCP_E
1
D 20K_0402_1% 1 J8 D
<8> PCH_RTCRST# SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 <30>
CU6 CU7 CU8 RU13 H8
15P_0402_50V8J 15P_0402_50V8J 1U_0402_10V6K @ 0_0603_5% SATA_RP1/PERP6_L2 A17
SATA_PRX_DTX_P1 <30> mSATA
2 2 SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 <30>
B17
2 CMOS SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <30>
2
HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
<33> HDA_SDIN0
HDA_SDIN0
HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 CardReader Board
TU20 @ AU12 AUDIO SATA
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
+RTCVCC RTCRST close RAM door TU21 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
PCIE_PRX_DTX_N6 <39>
HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 PCIE_PRX_DTX_P6 <39>
TU22 @ AV10 C17 PCIE_PTX_DRX_N6 CU92 1 2 0.1U_0402_16V7K
HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 PCIE_PTX_C_DRX_N6 <39>
TU23 @ AY8 D17 PCIE_PTX_DRX_P6 CU91 1 2 0.1U_0402_16V7K
I2S1_SCLK SATA_TP3/PETP6_L0 PCIE_PTX_C_DRX_P6 <39>
PCH_INTVRMEN RU14 1 2 330K_0402_5%
RU16 1 @ 2 330K_0402_5%
V1 PCH_GPIO34
SATA0GP/GPIO34 PCH_GPIO34 <9>
INTVRMEN - U1 @
SATA1GP/GPIO35 TU33 +1.05VS_ASATA3PLL
* H:
L:
Integrated SUS 1.05V VRM Enable
Integrated SUS 1.05V VRM Disable
SATA2GP/GPIO36
V6
AC1
PCH_GPIO36
PCH_GPIO37
PCH_GPIO36
PCH_GPIO37
<9>
<9>
TU24 @
PCH_JTAG_RST# AU62 SATA3GP/GPIO37
51_0402_5% 1 @ 2 RU17 PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF RU132 1 @ 2 0_0402_5%
TU25 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
TU27 @ PCH_JTAG_TDO AE61 PCH_TDI RSVD K10
PCH_TDO RSVD within 500 mils
TU29 @ PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP RU19 1 2 3.01K_0402_1%
@RF@ AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED#
RSVD SATALED PCH_SATALED# <39>
C373 2 1 22P_0402_50V8J AC4
TU32 @ PCH_TCK_JTAGX AE63 RSVD RU20 1 2
HDA for AUDIO AV2 JTAGX 10K_0402_5%
+3VS
C RPU1 EMI@ RSVD C
1 8 HDA_RST#
<33> HDA_RST_AUDIO#
2 7 HDA_BIT_CLK
<33> HDA_BITCLK_AUDIO
3 6 HDA_SYNC
<33> HDA_SYNC_AUDIO
4 5 HDA_SDOUT 5 OF 19 Rev1p2
<33> HDA_SDOUT_AUDIO
HASW ELL-MCP-E-ULT_BGA1168
33_0804_8P4R_5% @
RU21 1 2 0_0402_5%
<37> HDA_SDO
+RTCBATT
20mil
1
B B
DU1
BAS40-04_SOT23-3
+RTCVCC
3
+CHGRTC
1
CU9
20mil
0.1U_0402_16V4Z
2
A A
CLK_PCI_TPM
10P_0402_50V8J
10P_0402_50V8J
2
2
CU17 CU16
@RF@ @RF@
XTAL24_IN C43 A25 XTAL24_IN
1
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
2 1 XTAL24_OUT PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT
<9> PCH_GPIO18 PCIECLKRQ0/GPIO18
1M_0402_5% RU24 K21
B41 RSVD M21
YU2 A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF RU25 1 2 3.01K_0402_1%
D +1.05VS_AXCK_LCPLL D
24MHZ_12PF_X3G024000DC1H PCH_GPIO19 Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
<9> PCH_GPIO19 PCIECLKRQ1/GPIO19
1 3 C35 RU26 1 2 10K_0402_5%
2 4 CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 RU27 1 2 10K_0402_5%
<31> CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
PCIE LAN CLK_PCIE_LAN B42 AK8 RU28 1 2 10K_0402_5%
<31> CLK_PCIE_LAN CLKOUT_PCIE_P2 TESTLOW_AK8
1
1
AD1 SIGNALS AL8 RU30 1 2 10K_0402_5%
<31,9> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CU10 CU11
10P_0402_50V8J 10P_0402_50V8J CLK_PCIE_WLAN# B38 AN15 CLKOUT_LPC0 RU31 2 EMI@ 1 22_0402_5% CLK_PCI_LPC
<35> CLK_PCIE_W LAN# CLK_PCI_LPC <37>
2
CLK_PCIE_WLAN C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLKOUT_LPC1 RU32 2 EMI@ 1 22_0402_5% CLK_PCI_TPM
<35> CLK_PCIE_W LAN CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <39>
WLAN W LAN_CLKREQ# N1
<35,8> W LAN_CLKREQ# PCIECLKRQ3/GPIO21 B35 CLK_BCLK_ITP# @ TU36
CLK_PEG_VGA# A39 CLKOUT_ITPXDP_N A35 CLK_BCLK_ITP @ TU37 +3VALW _PCH
<18> CLK_PEG_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
CLK_PEG_VGA B39
<18> CLK_PEG_VGA CLKOUT_PCIE_P4
VGA VGA_CLKREQ# U5 RPU2
+3VS <18> VGA_CLKREQ# PCIECLKRQ4/GPIO22 PCH_SMBDATA 1 8 2.2K_0804_8P4R_5%
CLK_PCIE_CARD# B37 PCH_SMBCLK 2 7
<39> CLK_PCIE_CARD# CLKOUT_PCIE_N5
CLK_PCIE_CARD A37 3 6
<39> CLK_PCIE_CARD CLKOUT_PCIE_P5
1
VGA_CLKREQ# @
SML0CLK RU174 2 1 499_0402_1%
1
HASWELL_MCP_E
UU1G SML0DATA RU175 2 1 499_0402_1%
RU34
@ 10K_0402_5% LPC_AD0 AU14 AN2 PCH_GPIO11
<37,39> LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 <9>
LPC_AD1 AW12 AP2 PCH_SMBCLK
<37,39> LPC_AD1 LAD1 SMBCLK
LPC_AD2 AY12 LPC AH1 PCH_SMBDATA
<37,39> LPC_AD2
2
UU25 0.1U_0402_16V4Z
PCH_SPI_CS0# 1 8
PCH_SPI_MISO_1 2 /CS VCC 7 PCH_SPI_IO3_1 7 OF 19 Rev1p2
PCH_SPI_W P1# 2 1 PCH_SPI_IO2_1 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_1 HASW ELL-MCP-E-ULT_BGA1168
RU50 33_0402_5% 4 /WP(IO2) CLK 5 PCH_SPI_MOSI_1 @
GND DI(IO0)
W 25Q64FVSSIQ_SO8 @ RPU3 +3VS
SA000039A30 PCH_SPI_MOSI_1 4 5 PCH_SPI_MOSI
PCH_SPI_CLK_1 3 6 PCH_SPI_CLK
PCH_SPI_IO3_1 2 7 PCH_SPI_HOLD1# +3VS
2
PCH_SPI_MISO_1 1 8 PCH_SPI_MISO
RU43 RU44
PCH_SPI_MOSI_1 RU62 1 @ 2 0_0402_5% 33_0804_8P4R_5% QU1A 4.7K_0402_5% 4.7K_0402_5%
EC_SPI_SO <37>
2
B PCH_SPI_CLK_1 RU76 1 @ 2 0_0402_5% EMI@ DMN66D0LDW -7_SOT363-6 B
PCH_SPI_MISO_1 RU133 1 @ 2 0_0402_5% EC_SPI_CLK <37>
1
PCH_SPI_CS0# RU162 1 @ 2 0_0402_5% EC_SPI_SI <37> PCH_SMBDATA 6 1 D_CK_SDATA
EC_SPI_CS# <37> D_CK_SDATA <15,29,35>
5
CU13
Reserve for EMI(Near SPI ROM)
10P_0402_50V8J PCH_SMBCLK 3 4 D_CK_SCLK
D_CK_SCLK <15,29,35>
1 2 2 1 PCH_SPI_CLK_1
RU47 @EMI@ 33_0402_5% QU1B
+3VM @EMI@ DMN66D0LDW -7_SOT363-6
2
PCH_SPI_W P1# 2 1 PCH_SPI_IO2_2 3 6 PCH_SPI_CLK_2 PCH_SPI_MISO_2 1 8 PCH_SPI_MISO DMN66D0LDW -7_SOT363-6
RU51 33_0402_5% 4 /WP/IO2 CLK 5 PCH_SPI_MOSI_2 PCH_SPI_IO3_2 2 7 PCH_SPI_HOLD1# PU 2.2K at EC side (+3VS)
GND DI/IO0 PCH_SPI_CLK_2 3 6 PCH_SPI_CLK SML1CLK 6 1
W 25Q32FVSSIQ_SO8 @ PCH_SPI_MOSI_2 4 5 PCH_SPI_MOSI EC_SMB_CK2 <16,18,37>
5
SA00003K820 EMI@
33_0804_8P4R_5%
UU25 UU25 SML1DATA 3 4
EC_SMB_DA2 <16,18,37>
+3VS
CU180 www.laptopblue.vn
1
@ESD@ 1 2 SYS_RESET#
RU52
* HL:
10K_0402_5% 0.01U_0402_16V7K DSWODVREN - On Die DSW VR Enable
:Enable(DEFAULT)
Disable
2
SYS_RESET# Reserved for ESD +RTCVCC
HASWELL_MCP_E
UU1H
D RU54 1 2 330K_0402_5% D
RU55 1 @ 2 330K_0402_5%
RU57 SYSTEM POWER MANAGEMENT
PM_APWROK RU56 1 2 0_0402_5% PCH_PWROK_R SUSWARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN
<46> PM_APWROK SUSACK DSWVRMEN
NOVPRO@ SYS_RESET# AC3 AV5 PCH_RSMRST#_R
SYS_PWROK RU58 1 @ 2 0_0402_5% SYS_PWROK_R AG2 SYS_RESET DPWROK AJ5 PCH_PCIE_WAKE#
SYS_PWROK WAKE PCH_PCIE_WAKE# <31,35>
RU59 1 2 0_0402_5% PCH_PWROK_R AY7 1K_0402_5% 1 2 RU60
+3VALW_PCH
<37> PCH_PWROK PCH_PWROK
RU61 1 @ 2 0_0402_5% PM_APWROK AB5
<11,37> VCCST_PG_EC APWROK
RU63 1 @ 2 PBTN_OUT#_R PLT_RST# AG7 V5 CLKRUN#
<37> PBTN_OUT# <30,37,39> PLT_RST# PLTRST CLKRUN/GPIO32 CLKRUN# <39>
0_0402_5% AG4 @ TU44
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK <30,35>
AP5 PM_SLP_S5#
SLP_S5/GPIO63 PM_SLP_S5# <37>
RU64 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6 @ TU41
<37> PCH_RSMRST# RSMRST
PCH_RSMRST# RU65 1 2 10K_0402_5% SUSWARN# AV4 @ TU42 @ TU43
<9> SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#
PWRBTN SLP_S4 PM_SLP_S4# <37>
Note: EC is +3VL change to @ PCH_ACIN AJ8 AT4 PM_SLP_S3#
PM_SLP_S3# <37>
RU66 1 2 8.2K_0402_5% PCH_BATLOW# AN4 ACPRESENT/GPIO31 SLP_S3 AL5 PM_SLP_A#
+3VALW_PCH BATLOW/GPIO72 SLP_A PM_SLP_A# <41,46>
TU45@ PM_SLP_S0# AF3 AP4 @ TU46
PM_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# RU67 1 @ 2
<37> PM_SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN +3VALW_PCH
10K_0402_5%
+3VALW_PCH
PM_SLP_LAN# <37>
not support Deep S4,S5 can NC
1
8 OF 19 Rev1p2
RU68 HASWELL-MCP-E-ULT_BGA1168
100K_0402_5% @
DU3
Note: Deep Sx need use EC GPIO for DDPB_CTRLDATA: Port B Detected
ACPRESENT function
2
RB751V-40-YS_SOD323-2
1: Port B or C is detected
+3VS * 0: Port B or C is not detected
(Have internal PD)
5
RU69
HASWELL_MCP_E +3VALW_PCH
PCH_PWROK 2 0_0402_5% UU1I
P
B 4 SYS_PWROK 1 2 PCH_PWROK
VGATE_3V 1 Y +3VS JAPS
A
G
1
1
1
UU10 PM_SLP_S3# 2
3
GPIO 14
UU11 RU73 SSD_DET# U7 PM_SLP_S0# 15 14
<30,9> SSD_DET# GPIO55 15
1 5 10K_0402_5% L1 16
NC VCC <25> TOUCH_RST GPIO52 16
@ PROJECT_ID1 L3 C8 17
2 R5 GPIO54 DDPB_HPD A8 CPU_DP_HPD <26> 18 17
G_SEN_INT
<11,49> VGATE <29> G_SEN_INT CPU_HDMI_HPD <28>
2
5
UMA@ 2
VCC
RU156 1 2 10K_0402_5% PCH_GPIO77 10K_0402_5% PLT_RST# 1 CU187
NOGC6@ SD028100280 IN1 4 PLT_RST_BUF#
OUT PLT_RST_BUF# <18,30,31,35> 0.1U_0402_16V4Z
S RES 1/16W 10K +-5% 0402 2 1
GND
IN2 @ESD@
1
RU161 2 UMA@ 1 DGPU_HOLD_RST#
DGPU_HOLD_RST# <18,8>
10K_0402_5% RU77
100K_0402_5%
3
+3VS +3VS UU13
MC74VHC1G08DFT2G_SC70-5
2
1
A A
RU78 RU79
10K_0402_5% 10K_0402_5% PROJECT_ID1 PROJECT_ID0
HSW@ NOVPRO@ PROJECT ID
GPIO54 GPIO53
2
PROJECT_ID1 PROJECT_ID0
BDW+Vpro 0 0
Security Classification Compal Secret Data Compal Electronics, Inc.
2
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B731P
Date: Wednesday, September 17, 2014 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT
+3VS +3VS
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1
HASWELL_MCP_E
UU1J
RPU6 1 8 TOUCH_INT RPU7 1 8 PCH_GPIO88 RU82
2 7 PCH_GPIO39 2 7 PCH_GPIO85 1K_0402_5%
3 6 PCH_GPIO92 3 6 PCH_GPIO89
4 5 PCH_GPIO0 4 5 DGPU_PW R_EN
DGPU_PW R_EN <41,51,8>
2
10K_0804_8P4R_5% 10K_0804_8P4R_5% PCH_GPIO76 P1 D60 H_THERMTRIP#
PCH_GPIO8 AU2 BMBUSY/GPIO76 THERMTRIP V4
GPIO8 RCIN/GPIO82 EC_KBRST# <37>
RU180 1 @ 2 PCH_GPIO70 LAN_DISABLE_N AM7 T4 SERIRQ
<31> LAN_DISABLE_N LAN_PHY_PWR_CTRL/GPIO12 SERIRQ SERIRQ <37,39>
10K_0402_5% EC_LID_OUT# AD6 CPU/ AW15 PCH_OPIRCOMP 1 2 RU83
PCH_GPIO16 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 49.9_0402_1%
NFC_DET T3 GPIO16 RSVD AB21
D <30> NFC_DET D
RPU9 1 8 PCH_GPIO5 PCH_GPIO24 AD5 GPIO17 RSVD
2 7 PCH_GPIO1 LAN_PME# AN5 GPIO24
<31> LAN_PME# GPIO27
3 6 PCH_GPIO94 NFC_RST# AD7
<30> NFC_RST# GPIO28
4 5 PCH_GPIO93 NFC_IRQ AN3
<30> NFC_IRQ GPIO26
10K_0804_8P4R_5% R6 PCH_GPIO83
RPU101 8 PCH_GPIO2 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
2 7 PCH_GPIO91 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
3 6 PCH_GPIO90 PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
4 5 R658 1 @ 2 0_0402_5% DEVSLP1 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 MINI_DET#
GPIO59 GSPI1_CS/GPIO87 MINI_DET# <35,9>
10K_0804_8P4R_5% PCH_GPIO44 AK4 L5 PCH_GPIO88
RPU111 8 PCH_GPIO19 RU178 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89
PCH_GPIO19 <7> GPIO47 GSPI1_MISO/GPIO89
2 7 PCH_GPIO36 2 @ 1 0_0402_5% PCH_GPIO48 U4 K2 PCH_GPIO90
PCH_GPIO36 <6> <18,37> DGPU_AC_DETECT GPIO48 GSPI_MOSI/GPIO90
3 6 NFC_DET DGPU_PRSNT# Y3 J1 PCH_GPIO91 +3VS
4 5 EC_KBRST# TOUCH_INT P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
<25> TOUCH_INT GPIO50 UART0_TXD/GPIO92
10K_0804_8P4R_5% PCH_GPIO71 Y2 J2 PCH_GPIO93
RPU121 8 PCH_GPIO18 PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PCH_GPIO94 @
PCH_GPIO18 <7> GPIO13 UART0_CTS/GPIO94
2 7 PCH_GPIO14 AH4 K4 PCH_GPIO0 I2C1_SDA RA38 1 2 2.2K_0402_5%
3 6 PCH_GPIO48 PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
4 5 PCH_GPIO34 DET_SIG#_R_1AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2 I2C1_SCL RA39 1 2 2.2K_0402_5%
PCH_GPIO34 <6> GPIO45 UART1_RST/GPIO2
10K_0804_8P4R_5% PCH_GPIO46 AG3 J4 PCH_GPIO3 @
RPU131 8 PCH_GPIO71 GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
2 7 PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
3 6 PCH_GPIO16 PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA
GPIO10 I2C1_SDA/GPIO6 I2C1_SDA <25>
4 5 PCH_GPIO37 DEVSLP0 P2 F1 I2C1_SCL
PCH_GPIO37 <6> <8> DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 I2C1_SCL <25>
10K_0804_8P4R_5% PCH_GPIO70 C4 E3 PCH_GPIO64
<30> PCH_GPIO70 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64
DEVSLP1 L2 F4 PCH_GPIO65
<30> DEVSLP1 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
RPU148 1 PCH_GPIO4 1 RU15 2 PCH_GPIO39 N5 D3 PCH_GPIO66
<37> EC_SMI#_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
7 2 PCH_GPIO65 0_0402_5% PCH_SPKR V2 E4 PCH_GPIO67
<33> PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
C 6 3 PCH_GPIO64 C3 PCH_GPIO68 DV4 C
5 4 PCH_GPIO84 SDIO_D2/GPIO68 E2 PCH_GPIO69 1 2
SDIO_D3/GPIO69 GPU_EVENT# <18>
10K_0804_8P4R_5%
RPU158 1 PCH_GPIO83 10 OF 19 Rev1p2 GC6@
7 2 SSD_DET# HASW ELL-MCP-E-ULT_BGA1168
SSD_DET# <30,8>
6 3 PCH_GPIO3 @
5 4 SERIRQ
10K_0804_8P4R_5%
RPU168 1 MINI_DET#
MINI_DET# <35,9>
7 2 CARD_CLKREQ#
CARD_CLKREQ# <39,7>
6 3 PCH_GPIO76
5 4 RU85
10K_0804_8P4R_5%
UMA@ on board ram flag
GPIO68 GPIO67 GPIO47
LAN_CLKREQ# <31,7>
10K_0402_5%
RU85 1NOGC6@ 2 PCH_GPIO69 SD028100280 0 0 0
10K_0402_5% S RES 1/16W 10K +-5% 0402 +3VALW _PCH
+3VALW _PCH 0 1 0 +3VALW _PCH
SHY0 4G SA00005AV50 1 0 0
1
RPU17 1 8 USB_OC1#
2 7 PCH_GPIO8
USB_OC1# <10>
DET_SIG#_R_1 SEP0 4G SA00005HT80 1 1 0 RU86 RU87
3 6 USB_OC3# +3VALW _PCH 10K_0402_5% 10K_0402_5%
USB_OC3# <10>
2
2
RPU188 1 PCH_GPIO13 0_0402_5% PCH_GPIO56 PCH_GPIO10
1
7 2 PCH_GPIO57
6 3 RU168 RU170 RU169
1
B 5 4 PCH_GPIO11 DET_SIG#_R B
PCH_GPIO11 <7> DET_SIG#_R <31,38> 10K_0402_5% 10K_0402_5% 10K_0402_5%
10K_0804_8P4R_5% @ X76SEP0@ +3VS
RPU191 8 DET_SIG#_R_1
2
2
+3VS 2 7 PCH_GPIO46 PCH_GPIO47 PCH_GPIO68 PCH_GPIO67 RU88 1 @ 2 1K_0402_1% PCH_SPKR
3 6 PCH_GPIO44
1
1
4 5
10K_0804_8P4R_5% RU171 RU173 RU172
RPU201 8 10K_0402_5% @ 10K_0402_5% 10K_0402_5%
2 7 PCH_GPIO24 X76SHY0@ SPKR / GPIO81 : NO REBOOT
3 6
2
2
4 5 NFC_RST#
10K_0804_8P4R_5% 1: ENABLED
RPU211 8 PCH_GPIO59
2 7 PCH_GPIO58 0: DISABLED (Have internal PD)
3
4
6
5
PCH_GPIO14
PCH_GPIO25 EC_LID_OUT# RU179 2 @ 1
LID_SW # <37,39>
*
10K_0804_8P4R_5% 0_0402_5%
RPU221 8 USB_OC2# +3VALW _PCH +3VS
USB_OC2# <10>
2 7 PCH_GPIO60 PCH_GPIO66 RU89 1 @ 2 1K_0402_1%
PCH_GPIO60 <7>
3 6 USB_OC0# PCH_GPIO86 RU90 1 @ 2 1K_0402_1%
USB_OC0# <10,36>
4 5 PCH_GPIO9 RU92 1 2 10K_0402_5% EC_LID_OUT# RU93 1 2 1K_0402_5%
10K_0804_8P4R_5%
RU91 1 2 SUSW ARN#
SUSW ARN# <8>
10K_0402_5% GPIO15 : TLS Confidentiality GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
+3VS
1: Intel ME TLS with confidentiality 1: ENABLED 1: ENABLED
*
1
RU94 0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
A
10K_0402_5%
UMA@
GPIO49 (Have internal PD) * * A
DGPU_PRSNT#
2
DGPU_PRSNT#
DIS,Optimus 0
Security Classification Compal Secret Data Compal Electronics, Inc.
2
RU95
UMA 1 2014/02/14 2015/02/14 Title
10K_0402_5%
Issued Date Deciphered Date HSW MCP(6/11) GPIO,LPIO
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Thursday, September 25, 2014 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1
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HASWELL_MCP_E
UU1K
11 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@
B B
A A
www.laptopblue.vn +1.35V
L59
J58
UU1L
RSVD
RSVD
HASWELL_MCP_E
VCC
VCC
C36
C40
C44
+CPU_CORE
AY40 E33
22U_0805_6.3V6M 22U_0805_6.3V6M AY44 VDDQ 1.5V~1.65V VCC E35
@ESD@ @ESD@ +CPU_CORE AY50 VDDQ VCC E37
CU90 VDDQ Operating Voltage : VCC E39
VCC
1 2 F59
N58 VCC 1.6V~1.84V VCC
E41
E43
22U_0805_6.3V6M +VCCIO_OUT AC58 RSVD VCC E45
@ESD@ +1.05VS_VTT RSVD VCC E47
VCC_SENSE_R E63 VCC E49
RU100 AB23 VCC_SENSE VCC E51
ESD Reserved 1 @ 2 0_0603_5% A59
E20
RSVD
VCCIO_OUT
VCC
VCC
E53
E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
+3VS RSVD VCC F32
+1.05VS_VTT H_CPU_SVIDALRT# L62 VCC F36
0_0402_5% 1 @ 2 RU101 H_CPU_SVIDCLK N63 VIDALERT VCC F40
<49> VR_SVID_CLK VIDSCLK VCC
1
1
RU104 VCCST_PG_EC_R B59 HSW ULT POWER F48
100K_0402_5% UU14 RU105 0_0402_5% 1 2 RU102 PCH_VR_EN F60 VCCST_PWRGD VCC F52
<49> VR_ON VR_EN VCC
@ 1 5 10K_0402_5% 0_0402_5% 1 2 RU103 VR_READY C59 F56
NC VCC <49,8> VGATE VR_READY VCC
RU106 @ CU38 G23
2
2
IN A 4 VCCST_PG_EC_R 1 @ 2 CPU_PW R_DEBUG H59 VSS VCC G27
Y VCCST_PW RGD <37,47> PWR_DEBUG VCC
3 Reserved Only P62 G29
GND CU158 ESD@ P60 VSS VCC G31
C SA00004BV00 1 2 P61 RSVD_TP VCC G33 C
NL17SZ07DFT2G_SC70-5 VCCST_PG_EC_R N59 RSVD_TP VCC G35
0.1U_0402_16V7K N61 RSVD_TP VCC G37
2 RSVD_TP VCC
T59 G39
CU157 AD60 RSVD VCC G41
AD59 RSVD VCC G43
0.1U_0402_16V7K RSVD VCC
+1.05VS_VTT 1 AA59 G45
ESD@ RSVD VCC
AE60 G47
AC59 RSVD VCC G49
near CPU AG58 RSVD VCC G51
RSVD VCC
2
+1.05VS_VTT U59 G53
RU107 V59 RSVD VCC G55
SVID ALERT 150_0402_1% RSVD VCC
VCC
G57
@ AC22 H23
+CPU_CORE AE22 VCCST VCC J23
100mA
1
+1.05VS_VTT AE23 VCCST VCC K23
VCCST VCC K57
Place the PU CPU_PW R_DEBUG
VCC
AB57 L22
resistors close to CPU VCC VCC
1
AD57 M23
VCC VCC
2
2 1 H_CPU_SVIDALRT# 12 OF 19 Rev1p2
<49> VR_ALERT#
HASW ELL-MCP-E-ULT_BGA1168
@
+1.35V
B B
SVID DATA VDDQ DECOUPLING
+1.05VS_VTT ESD@ ESD@
Place the PU
resistors close to CPU
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
CU39
CU40
CU41
CU42
RU111 + CU49
CU43
CU44
CU45
CU46
CU47
CU48
130_0402_1% PC@ 330U_2.5V_M
+1.05VS_VTT
RU112 2 2 2 2 2 2 2 2 2 2 2
2
0_0402_5%
2 @ 1 VIDSOUT
<49> VR_SVID_DATA
+CPU_CORE
1U_0402_6.3V6K
22U_0805_6.3V6M
1 1
CU51
SF000002Z00
CU50
PC@
1
2 2
RU113
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2
VCC_SENSE_R 2 @ 1 RU114
VCC_SENSE <49>
0_0402_5% 2.2UF/6.3V/0402 * 4
A A
2 @ 1 RU115
<13> VSS_SENSE_R VSS_SENSE <49>
0_0402_5%
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: W ednesday, September 17, 2014 Sheet 11 of 56
5 4 3 2 1
5 4 3 2 1
+RTCVCC
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+1.05VS_VTT HASWELL_MCP_E
VCC1_05 : 1714mA UU1M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
M9 VCCHSIO CU55 1 2 1U_0402_6.3V6K
1U_0402_6.3V6K
VCCHSIO 1 1 1
N8 mPHY AH11 @ @
P9 VCC1_05 RTC VCCSUS3_3 AG10
CU57
CU58
CU59
1 1 1 VCC1_05 VCCRTC +RTCVCC
+1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2
CU54 B11 VCCUSB3PLL DCPRTC CU56 0.1U_0402_16V7K 2 2 2
CU52
CU53
+1.05VS_ASATA3PLL VCCSATA3PLL +3VM
1U_0402_6.3V6K
2 2 2
Y20 SPI
18mA Y8 CU60 2 1 0.1U_0402_16V7K
AA21 RSVD OPI VCCSPI @
D +1.05VS_APLLOPI D
W21 VCCAPLL
Near K9 Near L10 Near M9
VCCAPLL AG14
VCCASW +1.05VM
VCCASW 685mA AG13
+3VALW _PCH VCCASW CU146
+1.05VS_VTT
HDA --> 3.3V or 1.5V TU76 @ J13 USB3 +PCH_VCCDSW 2 1
+1.05VS_VTT +1.05VS_AUSB3PLL I2C --> 1.8V DCPSUS3 +3VALW _PCH
41mA J11 CU61 1 2 10U_0603_6.3V6M @
Near B18 VCC1_05 H11 CU62 1 2 1U_0402_6.3V6K 0.1U_0402_16V7K
CU63 1 2 1U_0402_6.3V6K 2 1 CU64 AH14 AXALIA/HDA VCC1_05 H15 CU65 1 2 1U_0402_6.3V6K
LU1 1 2 CU66 1 2 47U_0805_6.3V6M 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 CU67
2.2UH_LQM2MPN2R2NG0L_30% CU182 1 2 47U_0805_6.3V6M VCC1_05 AF22 1U_0402_6.3V6K
Idc 1.2A Rdc 0.11ohm +/-30% TU77 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW _R 1 2
DCPSUS2 CORE DCPSUSBYP AG20 RU117 0_0402_5%
+1.05VS_ASATA3PLL +3VALW +3VALW _PCH DCPSUSBYP AE9
VCCASW +1.05VM
42mA CU69 AF9 CU68 1 2 22U_0805_6.3V6M
Near B11 Near AC9 2 1 22U_0805_6.3V6M AC9 VCCASW AG8 CU70 1 2 1U_0402_6.3V6K
CU71 1 2 1U_0402_6.3V6K AA9 VCCSUS3_3 VCCASW AD10 CU72@1 2 1U_0402_6.3V6K
LU2 1 2 CU73 1 2 100U_1206_6.3V6M AH10 VCCSUS3_3 DCPSUS1 AD8
2.2UH_LQM2MPN2R2NG0L_30% CU75 V8 VCCDSW3_3 GPIO/LCC DCPSUS1
Idc 1.2A Rdc 0.11ohm +/-30% Near V8 2 1 22U_0805_6.3V6M W9 VCC3_3
1 VCC3_3
@ J15 +1.5VS
+1.05VS_APLLOPI CU74 THERMAL SENSOR VCCTS1_5 K14
+3VS VCC3_3 +3VS
57mA Near AH10 0.1U_0402_16V7K K16 CU76 1 2 0.1U_0402_16V7K
Near AA21 2 VCC3_3
CU77 1 2 1U_0402_6.3V6K
LU3 1 2 CU78 1 2 47U_0805_6.3V6M +1.05VS_AXCK_DCB J18
2.2UH_LQM2MPN2R2NG0L_30% CU183 1 2 47U_0805_6.3V6M K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
Idc 1.2A Rdc 0.11ohm +/-30% A20 T9 CU79 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
+1.05VS_VTT J17
C CU80 R21 VCCCLK C
Near J17 2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER
+1.05VS_VTT +1.05VS_AXCK_DCB CU83 K18 VCCCLK SUS OSCILLATOR AB8 CU81 @1 2 1U_0402_6.3V6K
Near R21 2 1 1U_0402_6.3V6K M20 RSVD DCPSUS4
200mA V21 RSVD
Near J18
CU84 1 2 1U_0402_6.3V6K AE20 RSVD AC20
+3VALW _PCH VCCSUS3_3 RSVD
LU4 1 2 CU85 1 2 47U_0805_6.3V6M AE21 AG16 +1.05VS_VTT
2.2UH_LQM2MPN2R2NG0L_30% CU184 1 2 47U_0805_6.3V6M VCCSUS3_3 USB2 VCC1_05 AG17
Idc 1.2A Rdc 0.11ohm +/-30% VCC1_05 CU86 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
31mA
Near A20 13 OF 19 Rev1p2
CU87 1 2 1U_0402_6.3V6K HASW ELL-MCP-E-ULT_BGA1168
LU5 1 2 CU88 1 2 47U_0805_6.3V6M @
2.2UH_LQM2MPN2R2NG0L_30% CU185 1 2 47U_0805_6.3V6M
Idc 1.2A Rdc 0.11ohm +/-30%
A A
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HASWELL_MCP_E HASWELL_MCP_E
UU1N UU1O UU1P HASWELL_MCP_E
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R <11>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 HASW ELL-MCP-E-ULT_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS @
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
HASW ELL-MCP-E-ULT_BGA1168
@
14 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@
A A
UU1Q HASWELL_MCP_E
www.laptopblue.vn UU1R HASWELL_MCP_E
UU1S HASWELL_MCP_E
AC60 AV63
AC62 CFG0 RSVD_TP AU63
CFG3
AC63
AA63
CFG1
CFG2
RSVD_TP CFG Straps for Processor
CFG4 AA60 CFG3 C63
Y62 CFG4 RSVD_TP C62
C Y61 CFG5 RSVD_TP B43 C
Y60 CFG6 RSVD CFG3
V62 CFG7 A51
CFG8 RSVD_TP
1
V61 B51
V60 CFG9 RSVD_TP RU119
U60 CFG10 L60 1K_0402_1%
T63 CFG11 RESERVED RSVD_TP @
T62 CFG12 N60
2
T61 CFG13 RSVD
T60 CFG14 W23
CFG15 RSVD Y22
AA62 RSVD AY15 OPI_COMP
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62
U62 CFG17 RSVD D58
CFG19 RSVD Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
VSS 1: DISABLED
A5 CFG3
RSVD P20
RSVD 0: ENABLED; SET DFX ENABLED BIT
E1 R20
D1 RSVD RSVD IN DEBUG INTERFACE MSR
J20 RSVD
H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF
1
19 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168 RU120
@ 1K_0402_5%
B B
2
2 1 CFG_RCOMP
RU121 49.9_0402_1%
2 1 OPI_COMP
RU122 49.9_0402_1%
2 1 TD_IREF Display Port Presence Strap
RU123 8.2K_0402_5%
A A
+1.35V
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+1.35V +1.35V +1.35V
JDIMM1
1
+V_DDR_REFA 1 2
VREF_DQ VSS1 +5VALW +5VS
0.1U_0402_16V7K
3 4 DDR_B_D12
VSS2 DQ4
CU93
RU124 DDR_B_D8 5 6 DDR_B_D9 1
RU125 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8 @
2_0402_1% 9 DQ1 VSS3 10 DDR_B_DQS#1
2
1 2 11 VSS4 DQS#0 12 DDR_B_DQS1
<5> SB_DIMM_VREFDQ DM0 DQS0 2
2.2U_0402_6.3V6M
1 13 14
2
@ DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
1 1 DQ2 DQ6 +1.35V
CU95
0.1U_0402_16V7K
CU96
CU94 PC@ DDR_B_D11 17 18 DDR_B_D15 RU128 RU129
0.022U_0402_25V7K RU127 19 DQ3 DQ7 20 UU15
VSS7 VSS8 100K_0402_5% 100K_0402_5%
2 1.8K_0402_1% DDR_B_D28 21 22 DDR_B_D25 1 5 QU4
DQ8 DQ12 NC VCC @
1
2 2 DDR_B_D29 23 24 DDR_B_D24 LBSS138LT1G_SOT-23-3
1
25 DQ9 DQ13 26 2 D RU126 1 2 SB_ODT0
1 VSS9 VSS10 <4> DDR_PG_CTRL A 1
RU131 DDR_B_DQS#3 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_B_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# <16,17,4> GND
@ 31 32 S
2
3
DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT RU130 1 2 SB_ODT1
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31 66.5_0402_1%
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DQ16 DQ20 DDR_VTT_PG_CTRL <46>
DDR_B_D41 41 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
All VREF traces should DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60
Layout Note: have 10 mil trace width DDR_B_D57 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_B_DQS#7
+1.35V 63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
PC@ DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
DQ27 DQ31
1U_0402_6.3V6K
CU97
1U_0402_6.3V6K
CU98
1U_0402_6.3V6K
CU99
1U_0402_6.3V6K
CU100
71 72
VSS25 VSS26
1 1 1 1 <5> DDR_B_D[0..63]
PC@ <5> DDR_B_MA[0..15]
DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB
2 2 2 2 <5> DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB <5>
75 76 <5> DDR_B_DQS#[0..7]
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14 <5> DDR_B_DQS[0..7]
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
2 87 A9 A7 88 2
+1.35V DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
A3 A2
10U_0603_6.3V6M
CU101
10U_0603_6.3V6M
CU102
10U_0603_6.3V6M
CU103
10U_0603_6.3V6M
CU104
DDR_B_MA1 97 98 DDR_B_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
SB_CLK_DDR0 101 102 SB_CLK_DDR1
<5> SB_CLK_DDR0 CK0 CK1 SB_CLK_DDR1 <5>
SB_CLK_DDR#0 103 104 SB_CLK_DDR#1
<5> SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 <5>
105 106
2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <5> +1.35V
DDR_B_BS0 109 110 DDR_B_RAS#
<5> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <5>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
<5> DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# <5>
1
DDR_B_CAS# 115 116 SB_ODT0
<5> DDR_B_CAS# CAS# ODT0
117 118 RU134
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1 +VREF_CA 1.8K_0402_1%
DDRB_CS1_DIMMB# 121 A13 ODT1 122
+1.35V <5> DDRB_CS1_DIMMB# S1# NC2
123 124 RU135
2
125 VDD17 VDD18 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA <16,5>
PC@ 127 128 2_0402_1% 1
1
DDR_B_D4 129 VSS27 VSS28 130 DDR_B_D5 @
DQ32 DQ36
10U_0603_6.3V6M
CU105
10U_0603_6.3V6M
CU106
10U_0603_6.3V6M
CU108
2.2U_0402_6.3V6M
0.1U_0402_16V7K
DDR_B_D1 131 132 DDR_B_D0 CU107
133 DQ33 DQ37 134 RU136 0.022U_0402_25V7K
1 1 1 2 VSS29 VSS30 1 1
2
CU110
CU111
DDR_B_DQS#0 135 136 PC@ 1.8K_0402_1%
DQS#4 DM4
1
CU186 DDR_B_DQS0 137 138
2
139 DQS4 VSS31 140 DDR_B_D2
0.1U_0402_16V4Z
2 2 2 1 DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2 @ RU137
@ESD@ DQ34 DQ39
DDR_B_D7 143 144 24.9_0402_1%
145 DQ35 VSS33 146 DDR_B_D16
2
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
3 153 VSS36 DQS#5 154 DDR_B_DQS2 3
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
+0.675VS 161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
CU112
1U_0402_6.3V6K
CU113
1U_0402_6.3V6K
CU114
1U_0402_6.3V6K
CU115
G1 G2
2.2U_0402_6.3V6M
1
0.1U_0402_16V7K
CU116
0_0402_5%
RU138
1
CU117
PC@ @ CONN@
2
1
4
2 4
Channel B
<Address: SA1:SA0=10>
Security Classification Compal Secret Data Compal Electronics, Inc.
2014/02/14 2015/02/14 Title
DIMM_1 STD H:4mm Issued Date Deciphered Date DDRIII DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 15 of 56
A B C D E
5 4 3 2 1
+VREF0 +VREF1
M9
UU16
VREFCA DQL0
E4 DDR_A_D7
+VREF0 +VREF1
www.laptopblue.vn
M9
H2
UU17
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D22
DDR_A_D20
+VREF0 +VREF1
M9
H2
UU18
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D34
DDR_A_D33
+VREF0 +VREF1
M9
H2
UU19
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D55
DDR_A_D53
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
H2 F8 DDR_A_D0 F3 DDR_A_D18 F3 DDR_A_D38 F3 DDR_A_D49
VREFDQ DQL1 DQL2 DQL2 DQL2
0.047U_0402_25V7K
0.047U_0402_25V7K
F3 DDR_A_D3 DDR_A_MA0 N4 F9 DDR_A_D21 DDR_A_MA0 N4 F9 DDR_A_D32 DDR_A_MA0 N4 F9 DDR_A_D51
DDR_A_MA0 N4 DQL2 F9 DDR_A_D1 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D19 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D39 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D54
A0 DQL3 A1 DQL4 A1 DQL4 A1 DQL4
1
DDR_A_MA1 P8 H4 DDR_A_D6 DDR_A_MA2 P4 H9 DDR_A_D16 DDR_A_MA2 P4 H9 DDR_A_D37 DDR_A_MA2 P4 H9 DDR_A_D52
CU121
CU119
CU122
CU123
CU124
CU125
A1 DQL4 A2 DQL5 A2 DQL5 A2 DQL5
1
DDR_A_MA2 P4 H9 DDR_A_D5 DDR_A_MA3 N3 G3 DDR_A_D23 DDR_A_MA3 N3 G3 DDR_A_D35 DDR_A_MA3 N3 G3 DDR_A_D48
CU120
CU118
DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D2 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D17 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D36 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D50
2
DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D4 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA5 P3 A4 DQL7
2
DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5
DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D24 DDR_A_MA7 R3 A6 D8 DDR_A_D44 DDR_A_MA7 R3 A6 D8 DDR_A_D59
DDR_A_MA7 R3 A6 D8 DDR_A_D8 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D30 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D46 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D61
DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D14 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D29 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D40 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D62
D A8 DQU1 A9 DQU2 A9 DQU2 A9 DQU2 D
DDR_A_MA9 R4 C9 DDR_A_D12 DDR_A_MA10 L8 C3 DDR_A_D31 DDR_A_MA10 L8 C3 DDR_A_D43 DDR_A_MA10 L8 C3 DDR_A_D57
DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D11 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D25 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D41 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D58
DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D13 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D26 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D47 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D56
DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D15 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D28 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D45 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D63
DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D9 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D27 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D42 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D60
DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D10 A14 DQU7 A14 DQU7 A14 DQU7
A14 DQU7
<17,5> DDR_A_DQS[0..7]
<17,5> DDR_A_D[0..63]
+0.675VS
R Value =
34.8 Ohm
+1.35V SA_CLK_DDR0
1U_0402_6.3V6K
CU126
1U_0402_6.3V6K
CU127
1U_0402_6.3V6K
CU128
1U_0402_6.3V6K
CU129
DDR_A_WE# 4 5
+VREF0
DDR3L VREF DDRA_CS0_DIMMA# 3 6 1 1 1 1
1
DDR_A_CAS# 2 7
RU145 DDR_A_RAS# 1 8 36_0804_8P4R_5%
1.8K_0402_1% RPU23
+VREF0 DDRA_CKE0_DIMMA 4 5 2 2 2 2 SA_CLK_DDR#0
Frorm CPU DDR_A_MA12 3 6
RU146
2
<DDR3L_DQ> DDR_A_MA15 2 7
1
1 2 +VREF0 DDR_A_BS2 1 8 36_0804_8P4R_5% +0.675VS
<5> SA_DIMM_VREFDQ
1
RPU24 RU148
1
2.2U_0603_10V6K
CU132
2
1
2 DDR_A_MA3 1 8 36_0804_8P4R_5%
B B
2
1
DDR_A_MA5 1 8 36_0804_8P4R_5%
2
RPU26
RU151
DDR_A_MA14 4 5
DDR_A_MA11 3 6 1 2 DDRA_ODT0_R
DDRA_ODT0_R <16,17>
DDR_A_MA9 2 7
+1.35V DDR_A_MA1 1 8 36_0804_8P4R_5% 30_0402_1%
RPU27
+VREF1 +VREF_CA DDR_A_MA6 4 5
DDR_A_MA7 3 6
1
RU118 DDR_A_MA8 2 7
RU152 1 @ 2 0_0402_5% DDR_A_MA4 1 8 36_0804_8P4R_5%
@ 1.8K_0402_1% RPU28
From CPU @ RU153
<DDR3L_CA>
2
1 2
<15,5> SM_DIMM_VREFCA
1
External DDR Thermal Sensor
2.2U_0603_10V6K
@ 2.7_0402_1%
CU134
.1U_0402_16V7K
CU135
CU133
1
0.022U_0402_25V7K 1 1 +3VS
2 RU154 CU181
1
@ 1.8K_0402_1% @ @ 0.1U_0402_16V4Z
RU155 1 2
@ 24.9_0402_1% 2 2
2
2
+0.675VS UU24
1 8
VDD SCLK EC_SMB_CK2 <18,37,7>
2 7 EC_SMB_DA2 <18,37,7>
+1.35V D+ SDATA
3 6 1 2 +3VS
D- ALERT# RU165 10K_0402_5%
4 5
THERM# GND
SF000002Z00
W83L771AWG-2 TSSOP8P
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
CU147
CU148
10U_0603_6.3V6M
1U_0402_6.3V6K
SA00003PU00
CU136
CU137
CU138
CU139
CU140
CU141
CU142
CU143
CU144
CU145
1 1 1 1 1 1 1 1 1 1 1 1 1
+
SA00003PU00
A
CU89 A
330U_2.5V_M S IC W83L771AWG-2 TSSOP 8P SENSOR
2 2 2 2 2 2 2 2 2 2 2 2
2
LA-B731P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII ON BOARD CHIPS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1
+VREF0 +VREF1
M9
UU20
VREFCA DQL0
E4 DDR_A_D0
+VREF0 +VREF1
www.laptopblue.vn
M9
H2
UU21
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D20
DDR_A_D22
+VREF0 +VREF1
M9
H2
UU22
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D33
DDR_A_D34
+VREF0 +VREF1
M9
H2
UU23
VREFCA
VREFDQ
DQL0
DQL1
E4
F8
DDR_A_D53
DDR_A_D55
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
0.047U_0402_25V7K
H2 F8 DDR_A_D7 F3 DDR_A_D21 F3 DDR_A_D32 F3 DDR_A_D51
VREFDQ DQL1 DQL2 DQL2 DQL2
0.047U_0402_25V7K
0.047U_0402_25V7K
F3 DDR_A_D1 DDR_A_MA0 N4 F9 DDR_A_D18 DDR_A_MA0 N4 F9 DDR_A_D38 DDR_A_MA0 N4 F9 DDR_A_D49
DDR_A_MA0 N4 DQL2 F9 DDR_A_D3 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D16 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D37 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D52
A0 DQL3 A1 DQL4 A1 DQL4 A1 DQL4
1
DDR_A_MA1 P8 H4 DDR_A_D5 DDR_A_MA2 P4 H9 DDR_A_D19 DDR_A_MA2 P4 H9 DDR_A_D39 DDR_A_MA2 P4 H9 DDR_A_D54
CU150
CU151
CU152
CU153
CU154
CU155
A1 DQL4 A2 DQL5 A2 DQL5 A2 DQL5
1
DDR_A_MA2 P4 H9 DDR_A_D6 DDR_A_MA3 N3 G3 DDR_A_D17 DDR_A_MA3 N3 G3 DDR_A_D36 DDR_A_MA3 N3 G3 DDR_A_D50
CU149
CU156
DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D4 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D23 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D35 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D48
2
DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA5 P3 A4 DQL7
2
DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5
DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D30 DDR_A_MA7 R3 A6 D8 DDR_A_D46 DDR_A_MA7 R3 A6 D8 DDR_A_D61
DDR_A_MA7 R3 A6 D8 DDR_A_D14 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D24 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D44 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D59
DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D8 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D31 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D43 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D57
D A8 DQU1 A9 DQU2 A9 DQU2 A9 DQU2 D
DDR_A_MA9 R4 C9 DDR_A_D11 DDR_A_MA10 L8 C3 DDR_A_D29 DDR_A_MA10 L8 C3 DDR_A_D40 DDR_A_MA10 L8 C3 DDR_A_D62
DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D12 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D26 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D47 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D56
DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D15 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D25 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D41 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D58
DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D13 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D27 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D42 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D60
DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D10 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D28 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D45 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D63
DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D9 A14 DQU7 A14 DQU7 A14 DQU7
A14 DQU7
<16,5> DDR_A_DQS[0..7]
<16,5> DDR_A_D[0..63]
UU16 UU20
X76SHY0@ X76SHY0@
R Value = +0.675VS SA00005AV50 SA00005AV50
X76SHY0@ X76SHY0@
DDRA_CKE1_DIMMA RU166 1 2 36_0402_1% SA00005AV50 SA00005AV50
DDRA_CS1_DIMMA# RU167 1 2 36_0402_1%
X76SHY0@ X76SHY0@
SA00005AV50 SA00005AV50
SA_CLK_DDR1
RU163
RU164 26.1_0402_1%
26.1_0402_1%
2
UU16 UU20
2
X76SEP0@ X76SEP0@
SA00005HT80 SA00005HT80
X76SEP0@ X76SEP0@
SA00005HT80 SA00005HT80
X76SEP0@ X76SEP0@
SA00005HT80 SA00005HT80
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
CU167
CU168
CU169
CU170
CU171
CU172
CU173
CU174
CU175
CU176
CU178
CU179
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1
1 1
A A
2 2 2 2 2 2 2 2 2 2
2 2
LA-B731P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII ON BOARD CHIPS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1
<10>
<10>
<10>
PCIE_HTX_C_GRX_P5L0
PCIE_HTX_C_GRX_N5L0
PCIE_HTX_C_GRX_P5L1
PCIE_HTX_C_GRX_P5L0
PCIE_HTX_C_GRX_N5L0
PCIE_HTX_C_GRX_P5L1
PCIE_HTX_C_GRX_N5L1
AG6
AG7
AF7
AE7
UV1A
PEX_RX0
PEX_RX0_N
PEX_RX1
www.laptopblue.vn
Part 1 of 6
GPIO0
GPIO1
GPIO2
C6
B2
D6
C7
GC6_FB_EN
GC6_FB_EN <18,8>
GPIO9_ALERT#
1
2
RPV1
+3VS_VGA_AON
8
7
PCIE X4 Bus <10> PCIE_HTX_C_GRX_N5L1 PEX_RX1_N GPIO3
PCIE_HTX_C_GRX_P5L2 AE9 F9 GPIO8_OVERT# 3 6
<10> PCIE_HTX_C_GRX_P5L2 AF9 PEX_RX2 GPIO4 A3 4 5
(Link to SOC) PCIE_HTX_C_GRX_N5L2 3VSDGPU_MAIN_EN GPU_BUF
<10> PCIE_HTX_C_GRX_N5L2 PEX_RX2_N GPIO5 3VSDGPU_MAIN_EN <41,51>
PCIE_HTX_C_GRX_P5L3 AG9 A4 GPU_EVENT#
<10> PCIE_HTX_C_GRX_P5L3 PEX_RX3 GPIO6 GPU_EVENT# <9>
PCIE_HTX_C_GRX_N5L3 AG10 B6 10K_0804_8P4R_5%
<10> PCIE_HTX_C_GRX_N5L3 AF10 PEX_RX3_N GPIO7 A6 GPIO8_OVERT# VGA@
AE10 NC OVERT F8 GPIO9_ALERT#
AE12 NC GPIO9 C5
AF12 NC GPIO10 E7 DGPU_VID +3VS_VGA_AON
D NC GPIO11 DGPU_VID <51> D
AG12 D7 GPU_BUF
AG13 NC GPIO12 B4 PSI RPV2
NC GPIO13 PSI <51>
GPIO
AF13 B3 3VSDGPU_MAIN_EN 1 8
AE13 NC GPIO14 C3 SYS_PEX_RST_HOLD# 2 7
AE15 NC GPIO15 D5 VGA@ GPU_EVENT# 3 6
AF15 NC GPIO16 D4 GPU_BUF 2 1 DGPU_AC_DETECT GC6_FB_EN 4 5
AG15 NC GPIO17 C2 DGPU_AC_DETECT <37,9>
AG16 NC GPIO18 F7 DV3 RB751V-40_SOD323-2 10K_0804_8P4R_5%
AF16 NC GPIO19 E6 GC6@ +3VS_VGA_AON
AE16 NC GPIO20 C4 SYS_PEX_RST_HOLD#
AE18 NC GPIO21
AF18 NC AB6
AG18 NC PEX_WAKE_NC
AG19 NC SYS_PEX_RST_MON# RV90 2 @ 1 10K_0402_5%
AF19 NC
AE19 NC PSI RV21 2 VGA@ 1 10K_0402_5%
AE21 NC AG3
AF21 NC NC AF4
AG21 NC NC AF3
AG22 NC NC PLT_RST_VGA#
NC
2
G
DACs
PCIE_GTX_C_HRX_N5L0 CU197 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_N5L0 AB9 AE4
<10> PCIE_GTX_C_HRX_N5L0 PEX_TX0_N NC
PCIE_GTX_C_HRX_P5L1 CU198 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_P5L1 AB10 VGA@
<10> PCIE_GTX_C_HRX_P5L1 PEX_TX1
PCIE X4 Bus PCIE_GTX_C_HRX_N5L1 CU199 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_N5L1 AC10 GPIO8_OVERT# 3 1
<10> PCIE_GTX_C_HRX_N5L1 PEX_TX1_N GPU_OVERT# <37>
PCIE_GTX_C_HRX_P5L2 CU200 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_P5L2 AD11
D
PCI EXPRESS
<10> PCIE_GTX_C_HRX_P5L2 PEX_TX2
(Link to SOC) PCIE_GTX_C_HRX_N5L2 CU201 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_N5L2 AC11 W5 2N7002E_SOT23-3
<10> PCIE_GTX_C_HRX_N5L2 PEX_TX2_N NC
PCIE_GTX_C_HRX_P5L3 CU202 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_P5L3 AC12 AE2 QV9
<10> PCIE_GTX_C_HRX_P5L3 PEX_TX3 TSEN_VREF
PCIE_GTX_C_HRX_N5L3 CU203 VGA@ 1 2 0.22U_0402_10V6K PCIE_GTX_HRX_N5L3 AB12 AF2 RV88 1 2 0_0402_5%
<10> PCIE_GTX_C_HRX_N5L3 PEX_TX3_N NC
AB13 @
AC13 NC
AD14 NC
AC14 NC
+3VS_VGA_AON AC15 NC
AB15 NC
AB16 NC B7 RV7 1 VGA@ 2 1.8K_0402_5%
AC16 NC I2CA_SCL A7 RV8 1 VGA@ 2 1.8K_0402_5%
C C
NC I2CA_SDA
1
AD17 +3VS_VGA_AON
RV22 AC17 NC C9 RV9 1 VGA@ 2 1.8K_0402_5%
<18,51> VGA_PWROK NC I2CB_SCL
10K_0402_5% AC18 C8 RV10 1 VGA@ 2 1.8K_0402_5%
AB18 NC I2CB_SDA
I2C
VGA@ NC
AB19 A9 RV11 1 VGA@ 2 1.8K_0402_5%
2
NC I2CC_SCL
2
NC I2CS_SDA
2
NC PLLVDD
22U_0603_6.3V6M
AG24 M6 +VID_PLLVDD LV1 PBY160808T-300Y-N_2P
0.1U_0402_10V7K
AG25 NC SP_PLLVDD
CV1
NC 1 1
CV2
N6 1 VGA@ 2
NC 0_0402_5%
RV15 VGA@
AE8 2 2 +1.05VS_VGA
<7> CLK_PEG_VGA
CLK_PEG_VGA
PEX_REFCLK Trace wide 12~16 mil VGA@
PCIE CLK CLK_PEG_VGA# AD8
<7> CLK_PEG_VGA# PEX_REFCLK_N
PEX_CLKREQ# AC6
PEX_CLKREQ_N
2 @ 1 PEX_PLL_CLK_OUT AF22 LV2 1 2 1.05V
CLK
RV16 200_0402_1% PEX_PLL_CLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN PBY160808T-181Y-N_0603
PEX_TSTCLK_OUT_N XTAL_IN
22U_0603_6.3V6M
B10 XTAL_OUT VGA@
4.7U_0603_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
XTAL_OUT
CV6
CV3
1 1 1 1
CV5
PLT_RST_VGA# AC7 A10 VGA@ 2 RV17 1
CV4
PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10
90-OHM DIFF Impedance for XTALIN & XTALOUT. PEX_TERMP XTAL_OUTBUFF 1 RV18 2 @
10K_0402_1%
VGA@ VGA@
+3VS_VGA_AON 2 2 2
10K_0402_1% VGA@2 VGA@
VGA@ 1 RV19 2 VGA@
1
IN GND
1
B B
CV8
10P_0402_50V8J
1
10P_0402_50V8J VGA@
VGA@
Internal Thermal Sensor
2
+3VS_VGA_MAIN
Link to EC SMBus
2
VGA@
+3VS_VGA_AON DV2 GC6@ QV1A
2 RV96 1 VGA@ DAN202UT106_SC70-3 I2CS_SCL 1 6
EC_SMB_CK2 <16,37,7>
GC6_FB_EN 2
<18,8> GC6_FB_EN 1
10K_0402_5% UV2 2N7002KDWH_SOT363-6
1.5VS_DGPU_PWR_EN <41,48>
5
VGA@ 3
<18,51> VGA_PWROK
RV5 1 @ 2 0_0402_5%
VCC
DGPU_HOLD_RST# 1
<8> DGPU_HOLD_RST# IN1 4SYS_PEX_RST_MON#
OUT SYS_PEX_RST_MON# <19>
5
PLT_RST_BUF# 2 VGA@
GND
QV1B
RV93 RV49 1 20_0402_5% I2CS_SDA 4 3
EC_SMB_DA2 <16,37,7>
MC74VHC1G08DFT2G_SC70-5 10K_0402_5% NOGC6@
3
RV6 1 @ 2 0_0402_5%
RV25
0_0402_5%
+3VS_VGA_AON
NOGC6@
1
UV3
5
GC6@
A A
VCC
SYS_PEX_RST_HOLD# 1
IN1 4 PLT_RST_VGA#
SYS_PEX_RST_MON# 2 OUT
GND
IN2
1
MC74VHC1G08DFT2G_SC70-5 RV95
3
SA00000OH00 10K_0402_5%
VGA@
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(1/4)-PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 24, 2014 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1
www.laptopblue.vnSTRAP
UV1C
Part 3 of 6 F11
AC3 NC AD10
AC4 NC NC AD7
Y4 NC NC B19
Y3 NC FBA_CMD32 V5
AA3 NC NC V6
AA2 NC NC G1
AB1 NC NC G2 +3VS_VGA_MAIN
NC NC
NC
AA1 G3
AA4 NC NC G4
AA5 NC NC G5
NC NC
1
G6
NC G7 RV26 RV27 RV28
AB5 NC V1 10K_0402_1%
NC NC 10K_0402_1% 10K_0402_1%
AB4 V2 @ @ @
D
AB3 NC NC W1 D
2
AB2 NC NC W2
AD3 NC NC W3 ROM_SI
AD2 NC NC W4 ROM_SO
AE1 NC NC ROM_SCLK
AD1 NC
AD4 NC
AD5 NC D11 RV29 1 @ 2 10K_0402_5%
NC BUFRST_N RV33
1
D10
T2 NC RV31 RV32 RV33 X76VSA0@
T3 NC E9 SYS_PEX_RST_MON# 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
NC GPIO8 SYS_PEX_RST_MON# <18>
T1 VGA@ VGA@ X76VHY0@ 15K_0402_1%
R1 NC E10 SD034150280
2
R2 NC NC S RES 1/16W 15K +-1% 0402
GENERAL
NC
LVDS/TMDS
R3 F10
N2 NC NC
N3 NC
NC D1 STRAP0
STRAP0 D2 STRAP1
V3 STRAP1 E4 STRAP2
V4 NC STRAP2 E3 STRAP3
U3 NC STRAP3 D3 STRAP4 VGA_THERMDN and VGA_THERMDP:
U4
T4
T5
NC
NC
NC
STRAP4
NC
C1 1. 5mil track width and spacing
2. 5mil grounded gurad tracks width and spacing
STRAP
R4 NC F6 STRAPREF0 1 VGA@ 2 3. ground referenced
R5 NC MULTI_STRAP_REF0_GND F4 RV34 40.2K_0402_1% 4. Connect guard tracks to pin5 +3VS_VGA_AON
NC NC F5
NC
N1
M1 NC
M2 NC F12 +VGA_CORE
NC THERMDP
1
M3
K2 NC E12 RV36 RV37 RV38 RV39 RV40
NC THERMDN
1
K3 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 49.9K_0402_1%
K1 NC RV35 @ @ @ @ VGA@
J1 NC @ 100_0402_1%
C C
2
NC
2
M4 F2 VCCSENSE_VGA STRAP0
M5 NC VDD_SENSE VCCSENSE_VGA <51> To POWER STRAP1
L3 NC STRAP2
L4 NC STRAP3
K4 NC
NC
trace width: 16mils STRAP4
K5
differential voltage sensing.
NC
1
J4 F1 VSSSENSE_VGA differential signal routing.
NC GND_SENSE VSSSENSE_VGA <51>
RV41 RV42 RV43 RV44 RV45
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1
@ @ @ @ @
J5 RV46
2
N4 NC @ 100_0402_1%
N5 NC TEST
NC
2
P3 AD9 GPU_TESTMODE 1 VGA@ 2
P4 NC TESTMODE AE5 GPU_JTAG_TCK RV47 10K_0402_5%
NC JTAG_TCK TP@ T1
AE6 GPU_JTAG_TDI TP@ T2
JTAG_TDI AF6 GPU_JTAG_TDO
JTAG_TDO TP@ T3 For BSC using.
J2 AD6 GPU_JTAG_TMS TP@ T4
J3 NC JTAG_TMS AG4 GPU_JTAG_TRST#
NC JTAG_TRST_N TP@ T5
H3 1 VGA@ 2
H4 NC RV48 10K_0402_1%
NC SERIAL
D12
ROM_CS_N B12 ROM_SI
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
For N15S-GTstrap table
ROM_SCLK
GPU Frenq. Memory Size Memory Config Strap BitX ROM_SI
N15S-GT-S-A2_BGA595 VGA@
SA00007GJ10 N15S-GT 256M* 16* 4 Hynix R
1000 MHz
2G H5TC4G63AFR-11C 0x0 0000 PD 4.99K
B 256M* 16* 4 B
N15S-GT 1000 MHz Samsung R
2GB K4W4G1646D-BC1A 0x2 0010 PD 15K
Resistor Pull-up to
Values(1%) +3VS_MAIN Pull-down to Gnd
4.99K 1000 0000
10.0K 1001 0001
15.0K 1010 0010
20.0K 1011 0011
24.9K 1100 0100
A A
30.1K 1101 0101
34.8K 1110 0110
45.3K 1111 0111
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(2/4)-Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1
www.laptopblue.vn
Place near Place near GPU +1.05VS_VGA
balls 1.05V
1U_0402_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
CV10
CV12
1 1 1 1
CV13 VGA@
CV11 @
+1.5VSDGPU 2 2 2 2
VGA@
@
Place under GPU UV1D
Part 4 of 6
B26 AA10
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13
CV18
CV14
CV19
CV15
CV16
CV17
1 1 1 1 1 1 FBVDDQ_03 PEX_IOVDDQ_3
E26 AA16 Place near Place near GPU +1.05VS_VGA
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
D FBVDDQ_05 PEX_IOVDDQ_5 balls 1.05V D
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
F21 AA19
2 2 2 2 2 2 FBVDDQ_06 PEX_IOVDDQ_6
1U_0402_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
G13 AA20
4.7U_0603_6.3V6K
FBVDDQ_07 PEX_IOVDDQ_7
CV20
CV25
G14 AA21 1 1 1 1
FBVDDQ_08 PEX_IOVDDQ_8
CV26 @
G15 AB22
CV21 VGA@
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
FBVDDQ_11 PEX_IOVDDQ_11 2 2 2 2
VGA@
G19 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_AON
J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23 Under GPU Near GPU
L22 FBVDDQ_AON PEX_IOVDD_2 AC24 1 2
FBVDDQ_19 PEX_IOVDD_3 +3VS_VGA_AON
VGA@
L24 AD25 RV50 0_0402_5%
1U_0402_6.3V6K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
POWER
FBVDDQ_20 PEX_IOVDD_4
22U_0603_6.3V6M
L26 AE26
CV23
CV24
CV28
1 1 1
10U_0603_6.3V6M
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
CV22
1 1 FBVDDQ_22 PEX_IOVDD_6
CV27 VGA@
N21
FBVDDQ_23
VGA@
VGA@
VGA@
R21
FBVDDQ_24 2 2 2
VGA@
T21
2 2 V21 FBVDDQ_25
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON G12
3V3_AON G8
VDD33_3 G9 1 2
VDD33_4
Under GPU Near GPU +3VS_VGA_MAIN
VGA@
RV51 0_0402_5%
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
Place near GPU
CV29
CV30
CV31
CV32
1 1 1 1
V7
W7 NC
NC
VGA@
VGA@
VGA@
VGA@
AA6 Near Ball
W6 NC D22 1 2 2 2 2 2
Y6 NC FB_CAL_PD_VDDQ 40.2_0402_1% RV52
NC
VGA@ VGA@VGA@
C24 2 1
FB_CAL_PU_GND 42.2_0402_1% RV53
C M7 B25 2 1 +1.5VSDGPU C
N7 NC FB_CAL_TERM_GND 51.1_0402_1% RV54
T6 NC
P6 NC
NC
T7 Hubert 11/8:
R7 IFPD_PLLVDD_2 +3VS_VGA_AON
NC modify to +3VS_VGA_AON
U6 Place near BGA
R6 IFPD_RSET AA8
for GC6 2.0
NC PEX_PLL_HVDD_1 DG-06803-P51
0.1U_0402_16V7K
AA9
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PEX_PLL_HVDD_2
1 1 1
CV33 VGA@
AB8
CV34 VGA@
CV35 VGA@
PEX_SVDD_3V3
J7 2 2 2
K7 NC
K6 NC AA14 +PEX_PLLVDD_GPU
H6 NC PEX_PLLVDD_1 AA15 +1.05VS_VGA
NC PEX_PLLVDD_2 1.05V
J6
NC 1 2
VGA@
RV55 0_0402_5%
0.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
CV37
1 1 1
CV36 VGA@
CV38 VGA@
N15S-GT-S-A2_BGA595 VGA@
SA00007GJ10
2 2 2
VGA@
Place near BGA
UV1F
+VGA_CORE +VGA_CORE
Part 6 of 6
L13 U15
L15 VDD_007 VDD_035 U13
VDD_008 VDD_034
Page M16
M18
N11
VDD_012
VDD_013
VDD_014
VDD_015
VDD_030
VDD_029
VDD_028
VDD_027
T12
T10
R17
N13 R15
N15 VDD_016 VDD_026 R13
N17 VDD_017 VDD_025 R11
P10 VDD_018 VDD_024 P18
P12 VDD_019 VDD_023 P16
VDD_020 VDD_022 P14
VDD_021
A A
N15S-GT-S-A2_BGA595 VGA@
SA00007GJ10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(3/4)-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 20 of 56
5 4 3 2 1
5 4 3 2 1
UV1E
www.laptopblue.vn +3VS
AA7
GND AB7
GND
N15S-GT-S-A2_BGA595 VGA@
SA00007GJ10
A A
www.laptopblue.vn
UV1B
D D
Part 2 of 6
<23> FBA_D[0..31] FBA_CMD0 <23>
FBA_D0 E18 C27 FBA_CMD0
FBA_D1 F18 FBA_D00 FBA_CMD0 C26
FBA_D01 FBA_CMD1 FBA_CMD[2..16] <23,24>
FBA_D2 E16 E24 FBA_CMD2
FBA_D3 F17 FBA_D02 FBA_CMD2 F24 FBA_CMD3
FBA_D4 D20 FBA_D03 FBA_CMD3 D27 FBA_CMD4
FBA_D5 D21 FBA_D04 FBA_CMD4 D26 FBA_CMD5
FBA_D6 F20 FBA_D05 FBA_CMD5 F25 FBA_CMD6
FBA_D7 E21 FBA_D06 FBA_CMD6 F26 FBA_CMD7
FBA_D8 E15 FBA_D07 FBA_CMD7 F23 FBA_CMD8
FBA_D9 D15 FBA_D08 FBA_CMD8 G22 FBA_CMD9
FBA_D10 F15 FBA_D09 FBA_CMD9 G23 FBA_CMD10
FBA_D11 F13 FBA_D10 FBA_CMD10 G24 FBA_CMD11
FBA_D12 C13 FBA_D11 FBA_CMD11 F27 FBA_CMD12
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_CMD13
FBA_D14 E13 FBA_D13 FBA_CMD13 G27 FBA_CMD14
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CMD15
FBA_D16 B15 FBA_D15 FBA_CMD15 M24 FBA_CMD16
FBA_D17 C16 FBA_D16 FBA_CMD16 M23
FBA_D17 FBA_CMD17 FBA_CMD[18..30] <23,24>
FBA_D18 A13 K24 FBA_CMD18
FBA_D19 A15 FBA_D18 FBA_CMD18 K23 FBA_CMD19
FBA_D20 B18 FBA_D19 FBA_CMD19 M27 FBA_CMD20
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_CMD21
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_CMD22
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_CMD23
FBA_D24 B24 FBA_D23 FBA_CMD23 K22 FBA_CMD24
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_CMD25
FBA_D26 A25 FBA_D25 FBA_CMD25 J25 FBA_CMD26
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_CMD27
FBA_D28 A21 FBA_D27 FBA_CMD27 K27 FBA_CMD28
FBA_D29 B21 FBA_D28 FBA_CMD28 K25 FBA_CMD29
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_CMD30
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 FBA_DOT_L FBA_CMD2
<24> FBA_D[32..63] FBA_D31 FBA_CMD31
FBA_D32 R22
FBA_D32 DQMA[3..0] <23>
C FBA_D33 R24 D19 DQMA0 FBA_DOT_H FBA_CMD18 C
FBA_D33 FBA_DQM0
INTERFACE A
FBA_D34 T22 D14 DQMA1
FBA_D35 R23 FBA_D34 FBA_DQM1 C17 DQMA2 FBA_CKE_L FBA_CMD3
FBA_D36 N25 FBA_D35 FBA_DQM2 C22 DQMA3
FBA_D36 FBA_DQM3 DQMA[7..4] <24>
FBA_D37 N26 P24 DQMA4 FBA_CKE_H FBA_CMD19
MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM4 W24 DQMA5
FBA_D39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6
FBA_D39 FBA_DQM6
2
FBA_D40 V23 U25 DQMA7
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
FBA_D41 V22 FBA_D40 FBA_DQM7
FBA_D41 QSA#[3..0] <23>
VGA@
VGA@
VGA@
VGA@
FBA_D42 T23 F19 QSA#0
RV56
RV57
RV58
RV59
FBA_D43 U22 FBA_D42 FBA_DQS_RN0 C14 QSA#1
FBA_D44 Y24 FBA_D43 FBA_DQS_RN1 A16 QSA#2
1
FBA_D45 AA24 FBA_D44 FBA_DQS_RN2 A22 QSA#3
FBA_D45 FBA_DQS_RN3 QSA#[7..4] <24>
FBA_D46 Y22 P25 QSA#4
FBA_D47 AA23 FBA_D46 FBA_DQS_RN4 W22 QSA#5
FBA_D48 AD27 FBA_D47 FBA_DQS_RN5 AB27 QSA#6
FBA_D49 AB25 FBA_D48 FBA_DQS_RN6 T27 QSA#7
FBA_D50 AD26 FBA_D49 FBA_DQS_RN7
FBA_D51
FBA_D52
FBA_D53
AC25
AA27
AA26
FBA_D50
FBA_D51
FBA_D52
FBA_DQS_WP0
FBA_DQS_WP1
E19
C15
B16
QSA0
QSA1
QSA2
QSA[3..0] <23>
FBA_RST
FBA_D54 W26 FBA_D53 FBA_DQS_WP2 B22 QSA3
FBA_D54 FBA_DQS_WP3 QSA[7..4] <24>
FBA_D55 Y25 R25 QSA4 FBA_CMD5
FBA_D56 R26 FBA_D55 FBA_DQS_WP4 W23 QSA5
FBA_D57 T25 FBA_D56 FBA_DQS_WP5 AB26 QSA6
FBA_D57 FBA_DQS_WP6
2
FBA_D58 N27 T26 QSA7
FBA_D59 R27 FBA_D58 FBA_DQS_WP7 RV60
FBA_D60 V26 FBA_D59
FBA_D60 10K_0402_5%
FBA_D61 V27
VGA@
+FB_PLLAVDD FBA_D62 W27 FBA_D61
1
+1.05VS_VGA W25 FBA_D62
1.05V Close to F16 Close to P22 FBA_D63
VGA@ FBA_D63 D24 CLKA0
FBA_CLK0 CLKA0 <23>
1 2 +FB_PLLAVDD F16 D25 CLKA0# CLKA0# <23>
LV3 PBY160808T-300Y-N_2P P22 FB_PLLAVDD_1 FBA_CLK0_N
FB_PLLAVDD_2
22U_0603_6.3V6M
CV40
0.1U_0402_10V7K
CV41
0.1U_0402_10V7K
CV42
0.1U_0402_10V7K
N22 CLKA1
FBA_CLK1 CLKA1 <24>
1 1 1 2 T6 TP@ FB_VREFD23 M22 CLKA1# CLKA1# <24>
FB_VREF_PROBE FBA_CLK1_N
CV39 VGA@
D18
B FBA_WCK01 B
VGA@
VGA@
VGA@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/4)-MEMORY FBA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-B731P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 22 of 56
5 4 3 2 1
5 4 3 2 1
ADDRESS
ADDRESS
FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
A5 <22> FBA_D[0..31] A5
FBA_CMD22 R8 FBA_CMD22 R8
FBA_CMD7 R2 A6 D7 FBA_D17 FBA_CMD7 R2 A6 D7 FBA_D27
FBA_CMD21 T8 A7 DQU0 C3 FBA_D21 FBA_CMD21 T8 A7 DQU0 C3 FBA_D29
FBA_CMD6 R3 A8 DQU1 C8 FBA_D18 FBA_CMD6 R3 A8 DQU1 C8 FBA_D25
FBA_CMD29 L7 A9 DQU2 C2 FBA_D23 Group2 FBA_CMD29 L7 A9 DQU2 C2 FBA_D30 Group3
FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D19 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D24
FBA_CMD28 N7 A11 DQU4 A2 FBA_D22 FBA_CMD28 N7 A11 DQU4 A2 FBA_D28
FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D16 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D26
FBA_CMD4 T7 A13 DQU6 A3 FBA_D20 FBA_CMD4 T7 A13 DQU6 A3 FBA_D31
FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
NC +1.5VSDGPU NC +1.5VSDGPU
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2
FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_CMD26 M3 BA1 VDD G7 FBA_CMD26 M3 BA1 VDD G7
VGA@ CV43
VGA@ CV44
VGA@ CV45
VGA@ CV46
VGA@ CV47
VGA@ CV48
BA2 VDD 1 1 1 BA2 VDD 1 1 1
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
CLKA0 J7 VDD N9 2 2 2 CLKA0 J7 VDD N9 2 2 2
<22> CLKA0
CLKA0# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CLKA0# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST
<22> CLKA0# K9 CK VDD R9 TO THE MEMORY DEVICES K9 CK VDD R9 TO THE MEMORY DEVICES
FBA_CMD3 FBA_CMD3
POWER
POWER
CKE VDD CKE VDD
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
DQMA1 E7 A9 DQMA0 E7 A9
VGA@ CV49
VGA@ CV50
VGA@ CV51
VGA@ CV52
VGA@ CV53
VGA@ CV54
VGA@ CV55
VGA@ CV56
VGA@ CV57
VGA@ CV58
VGA@ CV59
VGA@ CV60
VGA@ CV61
VGA@ CV62
VGA@ CV63
VGA@ CV64
C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C
DQMA2 D3 DML VSS B3 DQMA3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
QSA#1 G3 VSS J2 2 2 2 2 2 2 2 2 QSA#0 G3 VSS J2 2 2 2 2 2 2 2 2
QSA#2 B7 DQSL VSS J8 QSA#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
RESET VSS T1 RESET VSS T1
RV64 1 VGA@ 2 243_0402_1% L8 VSS T9 RV65 1 VGA@ 2 243_0402_1% L8 VSS T9
ZQ VSS ZQ VSS
GND
GND
J1 B1 J1 B1
L1 NC VSSQ B9 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8 +1.5VSDGPU
NC VSSQ E2 NC VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ VSSQ
1
G1 G1
VSSQ G9 VSSQ G9 RV66
VSSQ VSSQ 1.33K_0402_1%
96-BALL 96-BALL VGA@
SDRAM DDR3 SDRAM DDR3
2
S IC D3 256MX16 H5TC4G63AFR-11C FBGA 96P S IC D3 256MX16 H5TC4G63AFR-11C FBGA 96P +VREFD_UV7
SA00006E840 SA00006E840
X76VHY0@ X76VHY0@ +1.5VSDGPU
1
1
RV67 CV65
1.33K_0402_1% 0.01U_0402_25V7K
1
VGA@ VGA@
RV68 2
Place close to Vram
2
1.33K_0402_1%
CLKA0 VGA@
2
1
+VREFC_UV7
B B
RV69
162_0402_1%
1
VGA@ 1
RV70 CV66
2
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 23 of 56
5 4 3 2 1
5 4 3 2 1
<22>
FBA_D[32..63]
DQMA[7..4]
www.laptopblue.vn
<22> QSA[7..4]
<22> QSA#[7..4]
<22,23> FBA_CMD[2..16]
ADDRESS
ADDRESS
FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
FBA_CMD7 R2 A6 D7 FBA_D53 FBA_CMD7 R2 A6 D7 FBA_D61
FBA_CMD21 T8 A7 DQU0 C3 FBA_D49 FBA_CMD21 T8 A7 DQU0 C3 FBA_D59
FBA_CMD6 R3 A8 DQU1 C8 FBA_D54 FBA_CMD6 R3 A8 DQU1 C8 FBA_D60
FBA_CMD29 L7 A9 DQU2 C2 FBA_D50 Group6 FBA_CMD29 L7 A9 DQU2 C2 FBA_D57 Group7
FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D52 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D63
FBA_CMD28 N7 A11 DQU4 A2 FBA_D48 FBA_CMD28 N7 A11 DQU4 A2 FBA_D56
FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D55 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D62
FBA_CMD4 T7 A13 DQU6 A3 FBA_D51 FBA_CMD4 T7 A13 DQU6 A3 FBA_D58
FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
NC +1.5VSDGPU NC +1.5VSDGPU
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2
FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_CMD26 M3 BA1 VDD G7 FBA_CMD26 M3 BA1 VDD G7
VGA@ CV67
VGA@ CV68
VGA@ CV69
VGA@ CV70
VGA@ CV71
VGA@ CV72
BA2 VDD 1 1 1 BA2 VDD 1 1 1
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
CLKA1 J7 VDD N9 2 2 2 CLKA1 J7 VDD N9 2 2 2
<22> CLKA1 K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST
CLKA1# CLKA1#
<22> CLKA1# CK VDD TO THE MEMORY DEVICES CK VDD TO THE MEMORY DEVICES
FBA_CMD19 K9 R9 FBA_CMD19 K9 R9
POWER
POWER
CKE VDD CKE VDD
F1 F1
Control & DQM
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
VGA@ CV73
VGA@ CV74
VGA@ CV75
VGA@ CV76
VGA@ CV77
VGA@ CV78
VGA@ CV79
VGA@ CV80
VGA@ CV81
VGA@ CV82
VGA@ CV83
VGA@ CV84
VGA@ CV85
VGA@ CV86
VGA@ CV87
VGA@ CV88
DML VSS 1 1 1 1 1 1 1 1 DML VSS 1 1 1 1 1 1 1 1
DQMA6 D3 B3 DQMA7 D3 B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
QSA#5 G3 VSS J2 2 2 2 2 2 2 2 2 QSA#4 G3 VSS J2 2 2 2 2 2 2 2 2
QSA#6 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
RESET VSS T1 RESET VSS T1
RV72 1 VGA@ 2 243_0402_1% L8 VSS T9 RV73 1 VGA@ 2 243_0402_1% L8 VSS T9
ZQ VSS ZQ VSS
GND
GND
J1 B1 J1 B1
L1 NC VSSQ B9 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8
NC VSSQ E2 NC VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
S IC D3 256MX16 H5TC4G63AFR-11C FBGA 96P S IC D3 256MX16 H5TC4G63AFR-11C FBGA 96P
SA00006E840 SA00006E840
X76VHY0@ X76VHY0@
B B
UV5
X76VSA0@
SA000076P20
+1.5VSDGPU +1.5VSDGPU S IC D3 256MX16 K4W4G1646D-BC1A FBGA 96P
UV6
1
X76VSA0@
RV74 RV75 SA000076P20
1.33K_0402_1% 1.33K_0402_1% S IC D3 256MX16 K4W4G1646D-BC1A FBGA 96P
VGA@ VGA@
UV7
2
+VREFC_UV9 +VREFD_UV9
X76VSA0@
SA000076P20
1
SA000076P20
S IC D3 256MX16 K4W4G1646D-BC1A FBGA 96P
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 24 of 56
5 4 3 2 1
5 4 3 2 1
1
0.1U_0603_50V7K~D
R400
@ 2
100K_0402_5%
2
R615 1 @ 2 INVTPW M
<8> PCH_INV_PW M
0_0402_5%
1 2
<4> EDP_DISP_UTIL +5VS +5VS_TOUCH
R617 @ 0_0402_5%
1
PC@ 2
R619 @EMI@
C 10K_0402_5% C800 1 R632 2 1_0402_5% C
220P_0402_50V7K @
1 W=60mils
2
BKOFF#
<37> BKOFF#
1
PC@
R311
2
C801
eDP PANEL Conn.
100K_0402_5% 220P_0402_50V7K
1
@EMI@ CONN@
2
ACES_50406-03071-001
1
+5VS_TOUCH W=60mils 21
21
R310 TOUCH_RST 20
<8> TOUCH_RST 20
19
100K_0402_5% 18 19
B +LCDVDD 18 B
CPU_EDP_HPD 17
2 16 17
15 16
BKOFF# 14 15
INVTPW M 13 14
12 13
W=20mils 11 12
10 11
+LED_VOUT 10
Place closed to JEDP1 9
+LCDVDD 8 9
7 8
C247 1 2 0.1U_0402_16V7K EDP_TXN1_C 6 7
<4> EDP_TXN1 6
C191 1 2 0.1U_0402_16V7K EDP_TXP1_C 5
<4> EDP_TXP1 5
1 4
C262 C237 1 2 0.1U_0402_16V7K EDP_TXN0_C 3 4
<4> EDP_TXN0 3
C190 1 2 0.1U_0402_16V7K EDP_TXP0_C 2
<4> EDP_TXP0 2
0.1U_0402_16V4Z 1
2 1
Camera JEDP1
(EMI request) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP CONN.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: W ednesday, September 17, 2014 Sheet 25 of 56
5 4 3 2 1
5 4 3 2 1
DP to VGA-IT6513 +3VS
+3VS_6513
+3VS_6513
www.laptopblue.vn +1.8V_VDDO +1.8V_RX_VCC +1.8V_VDDO +1.8V_RX_VDD +1.8V_VDDO +1.8V_DAC_VDD
RA40 2 @ 1 0_0603_5%
4.7U_0603_6.3V6K
RA2 1 @ 2 0_0603_5% RA3 1 @ 2 0_0603_5% RA4 1 @ 2 0_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
D
3 1
1U_0402_6.3V6K
1 1
CA6
1 1 1 1
QA3 DMG2301U-7_SOT23-3 @
2
CA1
CA2
CA3
CA5
CA7
G
D D
2
2 2
CA4
RA25
1K_0402_5% 2 2 2 2
6513_3V_PWR_EN# 2 1
<37> 6513_3V_PWR_EN#
1
CA19 Place near Pin 35,36 Place near Pin 13,48
0.1U_0402_16V7K
2
RA1 1 @ 2 0_0402_5%
+1.8V_VDDO
+5VS
22U_0805_6.3V6M
1
2
G
CA8
+3VS_6513 +1.8V_RX_VDD
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 1 DP_HPD 2
<8> CPU_DP_HPD
S
1 1 1
1
@ ISPSDA_R
CA9
CA10
CA12
QA1 RA10 ISPSCL_R
2N7002E_SOT23-3 4.7K_0402_5%
2 2 2
13
48
35
36
38
39
12
14
44
46
2
UA1
1
2
C C
IVDDO
IVDDO
DDCSCL
IVDD33
IVDD33
DDCSDA
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DP_HPD 40 +3VS_6513
HPD
45
CA11 2 1 0.1U_0402_16V7K CPU_DP1_C_P0 26 270mA 270mA MCUVDDH
<4> CPU_DP1_P0 RX0P
CA13 2 1 0.1U_0402_16V7K CPU_DP1_C_N0 27
<4> CPU_DP1_N0 RX0N
CA15 2 1 0.1U_0402_16V7K CPU_DP1_C_P1 29 47 @ T39
<4> CPU_DP1_P1 RX1P MCURSTN
CA16 2 1 0.1U_0402_16V7K CPU_DP1_C_N1 30
<4> CPU_DP1_N1 RX1N
28 @ T40
RA13 2 @ 1 1M_0402_5% URDBG
+3VS
CA17 15 ISPSCL_R 1 2 RA12 22_0402_5%
0.1U_0402_16V7K ISPSCL 16 ISPSDA_R 1 2 RA14 22_0402_5%
RA19 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DP 20 ISPSDA
<8> DDI1_AUX_DP RXAUXP
<8> DDI1_AUX_DN RA20 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DN 19 23 CRT_CLK 1 2 RA16 22_0402_5%
CA18 RXAUXN VGADDCCLK 21 CRT_DATA 1 2 RA18 22_0402_5% CRT_CLK_1 <27>
0.1U_0402_16V7K VGADDCSDA CRT_DATA_1 <27>
DDI1_AUX_DP_R 18 3
DCAUXP VSYNC PCH_CRT_VSYNC_R <27>
RA24 2 @ 1 1M_0402_5% DDI1_AUX_DN_R 17 4
DCAUXN HSYNC PCH_CRT_HSYNC_R <27>
+1.8V_DAC_VDD
CA14
CA24
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
+1.8V_RX_VCC 25 10
31 AVCC VDDC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 1 AVCC
CA23
CA25
1 2 22
PVCC
IT6513FN 2 2
11 PCH_CRT_R
IORP PCH_CRT_R <27>
B B
Place near Pin 22 9 PCH_CRT_G
IOGP PCH_CRT_G <27>
+1.8V_RX_VDD 2 24
DVDD18 8 PCH_CRT_B
IOBP PCH_CRT_B <27>
CA26
1
0.1U_0402_16V4Z 41
1 NC/VGADETECT
5 RA32 1 2 93.1_0402_1%
32 RSET
+1.8V_RX_VCC 2 ASPVCC
75_0402_1% 2
75_0402_1% 2
75_0402_1% 2
7
CA27
VDDA +1.8V_DAC_VDD
0.1U_0402_16V4Z RA37
1 1M_0402_5%
6 CA281 2 XTALOUT_6513 @ XTALIN_6513
RA34 1 2 2.2K_0402_5% 43 COMP
RA29
RA30
RA31
0.1U_0402_16V4Z
RA35 1 2 2.2K_0402_5% 42 PCSDA XA1
+3VS_6513 PCSCL 34 XTALIN_6513 27MHZ_10PF_X3G027000BA1H-U
XTALIN 33 XTALOUT_6513 Crystal
XTALOUT
PWDNB
3 4
Note: need external PU to 2K ~ 10K OUT GND
PAD
2 1
GND IN
1
IT6513FN_QFN48_6X6 CA21@ 1
37
49
15P_0402_50V8J @ @ CA22
15P_0402_50V8J
2
2
+3VS_6513 RA36 1 2 10K_0402_5% PWDNB
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ITE IT6513FN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 26 of 56
5 4 3 2 1
A B C D E
CRT Connector
www.laptopblue.vn +HDMI_5V_OUT
1 @ 2 +HDMI_5V_OUT_CRT
CRB1.0 use 47ohm@100Mhz Bead R328 0_0402_5%
L6 EMI@
1 BLM15BB470SN1D_2P L7 0_0603_5% 1
CRT_R 1 2 CRT_R_1 1 @ 2 CRT_R_2 JCRT1
L8 EMI@ 6
BLM15BB470SN1D_2P L9 0_0603_5% 11
CRT_G 1 2 CRT_G_1 1 @ 2 CRT_G_2 1
L10 EMI@ 7
BLM15BB470SN1D_2P L11 0_0603_5% 12
CRT_B 1 2 CRT_B_1 1 @ 2 CRT_B_2 2
8 G 16
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13 17
G
8
7
6
5
1 1 1 1 1 1 1 1 1 3
RP2 9
C238
C239
C240
C241
C242
C243
C244
C245
C246
150_0804_8P4R_5% @ 14
@EMI@ @EMI@ @EMI@ @ T41 4
2 2 2 2 2 2 2 2 2 10
1
2
3
4
15
5
SUYIN_070546FR015S251ZR
CONN@
L12 EMI@
BLM15BB470SN1D_2P
CRT_HSYNC_2 1 R645 2 CRT_HSYNC_3 1 2 CRT_HSYNC_4
33_0402_5% L13 EMI@ CRT_DATA_3
BLM15BB470SN1D_2P
CRT_VSYNC_2 1 R646 2 CRT_VSYNC_3 1 2 CRT_VSYNC_4
33_0402_5% 1 1
EMI@ C249 C251 EMI@ CRT_CLK_3
2 10P_0402_50V8J 10P_0402_50V8J 2
2 2
+5VS +3VS
SELx Function
L port 1 is chose
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1
C782 C779 C780 C781 H port 2 is chose
2 2 2 2
+5VS +3VS
+3VS U11
PCH_CRT_R 1 16
<26> PCH_CRT_R R 5V VDD +HDMI_5V_OUT
From PCH PCH_CRT_G 2
<26> PCH_CRT_G G
PCH_CRT_B 5 4
<26> PCH_CRT_B B VDD
1
PCH_CRT_HSYNC_R 6 23
3 <26> PCH_CRT_HSYNC_R H_SOURCE VDD 3
R647 R648 PCH_CRT_VSYNC_R 7 32
<26> PCH_CRT_VSYNC_R V_HOURCE VDD
4.7K_0402_5% 4.7K_0402_5% CRT_DATA_1 9
<26> CRT_DATA_1 SDA_SOURCE
1
CRT_CLK_1 10 27 CRT_R
<26> CRT_CLK_1 SCL_SOURCE R1 25 CRT_G R302 R303
2
CRT_DATA_1 G1 22 CRT_B
CRT_CLK_1 CRT_SEL 30 B1 20 CRT_HSYNC_2
To CRT CONN. 2.2K_0402_5% 2.2K_0402_5%
<37> CRT_SEL SEL H1_OUT SEL:Low
18 CRT_VSYNC_2
2
V1_OUT 12 CRT_DATA_3
0_0402_5% 2 @ 1 R549 29 SDA1 14 CRT_CLK_3
+3VS TEST SCL1
10K_0402_5% 1 2 R762 8 26 RED_DOCK
Reserved R2 RED_DOCK <38>
24 GREEN_DOCK
G2 GREEN_DOCK <38>
3 21 BLUE_DOCK
GND B2 BLUE_DOCK <38>
11 19 HSYNC_DOCK To Docking
GND H2_OUT HSYNC_DOCK <38>
28 17 VSYNC_DOCK
GND V2_OUT VSYNC_DOCK <38> SEL:High
31 13 CRT_DATA_DOCK
GND SDA2 CRT_DATA_DOCK <38>
33 15 CRT_CLK_DOCK
GPAD SCL2 CRT_CLK_DOCK <38>
PI3V713-AZLEX_TQFN32_6X3~D
SA00004R600
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: W ednesday, September 17, 2014 Sheet 27 of 56
A B C D E
A B C D E
+3VS
www.laptopblue.vn 0.1U_0402_16V4Z
+3VS
1
0.1U_0402_16V4Z
1 1
0.01U_0402_16V7K
1
HDMI_CLK+
R630 1 EMI@
1
L15
2 6.2_0402_5%
@EMI@
2
HDMI_R_CK+
2
U12
2
R411 14 40 2 2 2 2 4 3
+3VS VDD33 DP_D0p HDMI_DOCK_D2+ <38> 4 3
R474 4.7K_0402_5% 28 39
41 VDD33 DP_D0n HDMI_DOCK_D2- <38> HDMI_CLK- HDMI_R_CK-
@ 0_0402_5% 0.01U_0402_16V7K MURATA DLW21HN900HQ2L _0805
56 VDD33 37 SM070003Y00
HDMI_DOCK_D1+ <38>
1
VDD33 DP_D1p 36
HDMI_DOCK_D1- <38> Design Guide:
1
<38> DP_DOCK_SEL
2 @ 1 DPSW_SW 45 DP_CFG0/SCL_CTL 34
HDMI_DOCK_D0+ <38>
Place 0.1 uF, 0.01 uF decoupling capacitors
R519 0_0402_5% I2C_CTL_EN 38 SW/SDA_CTL DP_D2p 33
I2C_CTL_EN DP_D2n HDMI_DOCK_D0- <38> on each VDD33/VDD15 pin,
DPB_P0 3
IN_D0p DP_D3p
31
HDMI_DOCK_CK+ <38>
the capacitors should be placed as close to
DPB_N0 4 30 R633 1 EMI@ 2 6.2_0402_5%
IN_D0n DP_D3n HDMI_DOCK_CK- <38> the chip package pins as possible
DPB_P1 6 55 HDMI_TX0+ HDMI_R_D0+
DPB_N1 7 IN_D1p DP_AUXp_SCL 54 HDMI2_DOCK_SCL <38> L16
HDMI2_DOCK_SDA <38> to Docking @EMI@
IN_D1n DP_AUXn_SDA 32 1 2
from PCH DPB_P2 9 DP_HPD HDMI_HPD_DOCK <38> +3VS 1 2
+3VS DPB_N2 10 IN_D2p
IN_D2n 42 4 3
DP_CA_DET DP_DOCK_CAD <38> 4 3
R335 1 2 10K_0402_5% DDI2_CTRL_CK DPB_P3 12
R336 1 2 10K_0402_5% DDI2_CTRL_DATA DPB_N3 13 IN_D3p 29 DP_CFG1 HDMI_TX0- MURATA DLW21HN900HQ2L _0805 HDMI_R_D0-
IN_D3n DP_CFG1 HDMI2_DOCK_SDA 100K_0402_5% 1 @ 2 R586 SM070003Y00
DPB_AUXP 52 19 HDMI_TX0+ HDMI2_DOCK_SCL 100K_0402_5% 1 @ 2 R587
DPB_AUXN 51 IN_AUXp TMDS_CH0p 18 HDMI_TX0- R665 1 EMI@ 2 6.2_0402_5%
IN_AUXn TMDS_CH0n
DDI2_CTRL_CK 50 22 HDMI_TX1+
<8> DDI2_CTRL_CK IN_DDC_SCL TMDS_CH1p
DDI2_CTRL_DATA 49 21 HDMI_TX1-
<8> DDI2_CTRL_DATA IN_DDC_SDA TMDS_CH1n
11 25 HDMI_TX2+ R667 1 EMI@ 2 6.2_0402_5%
IN_CA_DET TMDS_CH2p 24 HDMI_TX2-
5 TMDS_CH2n HDMI_TX1+ HDMI_R_D1+
<8> CPU_HDMI_HPD IN_HPD 16 HDMI_CLK+
to HDMI Conn. L17
@EMI@
TMDS_CLKp
2
15 HDMI_CLK- 1 2
TMDS_CLKn 1 2
2.2U_0402_6.3V6M
R387
100K_0402_5% @ HDMI_CEXT 1 48 HDMI_SCLK
CEXT TMDS_SCL 47 HDMI_SDATA 4 3
TMDS_SDA 4 3
C538
1 DPSW_DDCBUF 2
1
35
GND
R41 2
@EMI@
1 2
1
1 2
4 3
4 3
HDMI_TX2- MURATA DLW21HN900HQ2L _0805 HDMI_R_D2-
I2C_CTL_EN Mode SM070003Y00
Low Pin Control Mode R671 1 EMI@ 2 6.2_0402_5%
High I2C Control Mode
+HDMI_5V_OUT
Control Switching Mode +5VS U53
SW DP Output HDMI Output HPD_SRC 3
W=40mils
OUT
0 Enable Z DP_HPD 1
IN
1
3 C802 3
1 Z Enable HDMI_HPD GND
2 0.1U_0402_16V4Z
2
AP2330W-7_SC59-3
AUTOSW_EN Power Mode
+3VS +3VS +3VS +3VS
Low Control port switching
High Automatic port switching HDMI connector
2
1
5
D1_shield
2
+3VS +3VS CPU_DP2_N3 C274 2 1 0.1U_0402_16V7K DPB_N3 R386 HDMI_R_D1+ 4
<4> CPU_DP2_N3 HDMI_R_D2- 3 D1+
100K_0402_5%
CPU_DP2_P3 C275 2 1 0.1U_0402_16V7K DPB_P3 R337 R338 @ 2 D2-
<4> CPU_DP2_P3 D2_shield
2
2
R478 R484 DDI2_AUX_DN C283 2 1 0.1U_0402_16V7K DPB_AUXN D2+
<8> DDI2_AUX_DN
1
4 HDMI_SCLK SUYIN_100042GR019M27SZL 4
4.7K_0402_5% 4.7K_0402_5%
DDI2_AUX_DP C288 2 1 0.1U_0402_16V7K DPB_AUXP HDMI_SDATA CONN@
<8> DDI2_AUX_DP
DC232000S00
1
TMDS_RT TMDS_PRE
2
R481 R482
4.7K_0402_5%
@
4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 28 of 56
A B C D E
A B C D E
0.01U_0402_16V7K
0.1U_0402_16V7K
1 1
R12
4.7K_0402_5%
C7
C8
@ 2 2
U1
2
7 10 JHDD1
EN VDD 20 1
1 SATA_PTX_DRX_P0 C9 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 1 VDD RDSATA_PTX_DRX_P0C279 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 2 1 1
<6> SATA_PTX_DRX_P0 A_INp 2
SATA_PTX_DRX_N0 C10 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 2 6 R11 1 X76TI@ 2 4.99K_0402_1% RDSATA_PTX_DRX_N0C280 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0 3
<6> SATA_PTX_DRX_N0 A_INn NC 3
16 R755 1 2 1K_0402_5% 4
SATA_PRX_DTX_P0 C11 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 5 NC RDSATA_PRX_DTX_N0C281 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 5 4
<6> SATA_PRX_DTX_P0 B_OUTp 5
SATA_PRX_DTX_N0 C12 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 4 9 A_DE RDSATA_PRX_DTX_P0C282 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 6
<6> SATA_PRX_DTX_N0 B_OUTn A_PRE0 8 7 6
B_DE
B_EQ1 19 B_PRE0 8 7
A_PRE1 +3VS 8
A_EQ1 17 15 RDSATA_PTX_DRX_P0 9
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 10 9
A_EQ2 18 A_OUTn 11 10
+3VS 3 TEST 11 RDSATA_PRX_DTX_P0 +5VS +5VS_HDD 12 11
B_EQ2 13 GND B_INp 12 RDSATA_PRX_DTX_N0 J2 13 12
R15 1 @ 2 4.7K_0402_5% A_DE 21 GND B_INn +5VS_HDD 1 2 14 13
EPAD 15 14
R17 1 @ 2 4.7K_0402_5% B_DE SN75LVCP601RTJR_A.4_TQFN20_4X4 JUMP_43X118 16 15
SA00003ZX00
100mils @ 17 16
R14 1 @ 2 4.7K_0402_5% B_EQ1 X76TI@ 18 17
18
0.1U_0402_16V4Z
C286
1000P_0402_50V7K
C287
R11 1 1 1 19
R20 1 @ 2 4.7K_0402_5% A_EQ1 U1 C284 20 19
21 20
R22 1 @ 2 4.7K_0402_5% A_EQ2 10U_0805_10V4Z @ 22 G1
2 2 2 23 G2
R13 1 @ 2 4.7K_0402_5% B_EQ2 24 G3
7.5K +-5% 0402 G4
PS8527CTQFN20GTR2-A1 X76PAR@ ACES_50406-02071-001
2
X76PAR@ SD028750180 CONN@ 2
R21 1 @ 2 4.7K_0402_5% A_DE SA00007JU00
SP010016L00
R16 1 @ 2 4.7K_0402_5% B_DE
+3VS
APS G-Sensor
1
R523 +3VS
0_0402_5%
3 @ U26 PC@ 3
1 C633 1 2 10U_0603_6.3V6M
2
8 Vdd_IO
4 CS 14 C628 1 2 0.1U_0402_16V4Z
<15,35,7> D_CK_SCLK 6 SCLSPC Vdd
<15,35,7> D_CK_SDATA 7 SDA/SDI/SDO
R521 1 @ 2 10K_0402_5% SDO/SA0 11 1 2 G_SEN_INT
+3VS INT1 G_SEN_INT <8>
R522 1 2 10K_0402_5% 16 9
15 ADC1 INT2 R524
13 ADC2 10 0_0402_5%
ADC3 RES @
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
SA00004VF00
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B731P
Date: Wednesday, September 24, 2014 Sheet 29 of 56
A B C D E
5 4 3 2 1
1
www.laptopblue.vn
JSSD1
2
+3VS
J13
+3VS_SSD_NGFF
R660
59 60 SUSCLK_SSD 1 @ 2 0_0402_5%
N/C SUSCLK SUSCLK <35,8>
SSD_DET# 61 62
<8,9> SSD_DET# 63 PEDET 3.3VAUX 64
65 GND 3.3VAUX 66
GND 3.3VAUX +3VS_SSD_NGFF
67
GND
C 69 68 C
MTG77 MTG76
LTCX005V800
BELLW_80159-3221_67P-T
+3VS
+3VALW +3V_NFC
+3VS +5VALW +5V_BST_NFC
2
R638 R639 @ @
Q53A 499_0402_1% 499_0402_1% 0_0603_5% 1 2 R663 0_0603_5% 1 2 R637
2
DMN66D0LDW-7_SOT363-6
+5VS +3VS
1
SML0CLK 6 1 SML0CLK_NFC
<31,7> SML0CLK
0_0603_5% 1 2 R662 0_0603_5% 1 2 R640
B 1 @ 2 B
R643 0_0402_5%
5
SML0DATA 3 4 SML0DATA_NFC
<31,7> SML0DATA +3V_NFC
Q53B CONN@
DMN66D0LDW-7_SOT363-6 HB_A511510-SCHR22
NFC_DET 1
1 @ 2 <9> NFC_DET 2 1
R642 0_0402_5% 3 2
4 3
PCH_GPIO70 5 4
<9> PCH_GPIO70 NFC_RESET# 6 5
7 6
+3V_NFC +3V_NFC SML0CLK_NFC 8 7
R664 SML0DATA_NFC 9 8
0_0402_5% 10 9
1 2 NFC_RESET# 11 10
+3V_NFC <9> NFC_IRQ 12 11
+5V_BST_NFC 12
1
13
@ TU12 13
1
14
R644 @ 15 14
15
5
1 NC VCC GND
<9> NFC_RST#
2
IN1 4 2 JNFC1
PLT_RST_BUF# 2 OUT IN A 4 NFC_RESET#
GND
U57 SA00004BV00
3
1 @ 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
mSATA & NFC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 30 of 56
5 4 3 2 1
5 4 3 2 1
www.laptopblue.vn
UL1
+3VALW
0_0603_5% 1 @ 2 RL2
+3V_LAN
UL3
LAN_CLKREQ# 48 13 LAN_MIDI0+ 1
<7,9> LAN_CLKREQ# CLK_REQ_N MDI_PLUS0 VOUT
1 @ 2 36 14 LAN_MIDI0- 5
<18,30,35,8> PLT_RST_BUF# PE_RST_N MDI_MINUS0 VIN
RL1 0_0402_5%
44 17 LAN_MIDI1+ 2
<7> CLK_PCIE_LAN PE_CLKP MDI_PLUS1 GND
45 18 LAN_MIDI1- 4
<7> CLK_PCIE_LAN# PE_CLKN MDI_MINUS1 VIN
PCIE
MDI
1
D
0.1U_0402_10V7K 1 2 CL1 PCIE_PRX_C_DTX_P3 38 20 LAN_MIDI2+ CL15 3 LAN_PWR_ON
<10> PCIE_PRX_DTX_P3 PETp MDI_PLUS2 EN D
0.1U_0402_10V7K 1 2 CL2 PCIE_PRX_C_DTX_N3 39 21 LAN_MIDI2- 1U_0402_10V6K
<10> PCIE_PRX_DTX_N3 PETn MDI_MINUS2 AP2821KTR-G1_SOT23-5
41 23 LAN_MIDI3+ 2
<10> PCIE_PTX_C_DRX_P3 PERp MDI_PLUS3
42 24 LAN_MIDI3-
<10> PCIE_PTX_C_DRX_N3 PERn MDI_MINUS3
+3V_LAN
LAN_SCLK 28 6
LAN_SDATA 31 SMB_CLK SVR_EN_N
SMBUS
SMB_DATA 1 RL4 1 2 4.7K_0402_5%
RSVD_VCC3P3_1 *IMPORTANT NOTE: LAN_PWR_EN Controls PHY Power
NOTE: LANWAKE_N must be LAN_PME# 2 5
<9> LAN_PME# LANWAKE_N VDD3P3_IN
connected to PCH's GPIO27. <9> LAN_DISABLE_N
LAN_DISABLE_N 1 @ 2 LAN_DISABLE_N_R 3
LAN_DISABLE_N
RL5 0_0402_5% 4 1 2 1
VDD3P3_4
22U_0805_6.3V6M
CL14
0.1U_0402_16V4Z
CL13
CL4
15 1U_0402_10V6K LAN_PWR_ON
LAN_LINK# 26 VDD3P3_15 19
LAN_ACTIVITY# 0_0402_5% 1 @ 2 RL6 LAN_R_ACTIVITY# 27 LED0 VDD3P3_19 29 2 1 2
NOTE: LAN_DISABLE_N must be connected 25 LED1 VDD3P3_29
LED
LED2
to PCH's GPIO12/LAN_PHY_PWR_CTRL. RL14 1 2 1K_0402_5%
LAN_PWR_EN <37>
47
This GPIO12 pin must be set as VDD0P9_47 46
32 VDD0P9_46 37
"LAN_PHY_PC" function through FITC TL1
TL2
@
@
JTAG_TDI_LAN
JTAG_TDO_LAN 34 JTAG_TDI VDD0P9_37
tool. TL3 @ JTAG_TMS_LAN 33 JTAG_TDO 43
JTAG
TL4 @ JTAG_TCK_LAN 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
LAN_XTALO RL8 1 @ 2 LAN_XTALO_R 9 40 +0.9V_PHY_CORE
0_0402_5% LAN_XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8
RL9 1 2 1K_0402_5% 30 VDD0P9_8
25MHZ_10PF_7V25000014 TEST_EN
RL10 1 2 3.01K_0402_1% 12 7 +0.9V_LAN_OUT 2 1 LL1
3 1 RBIAS CTRL0P9 4.7UH_PG031B-4R7MS_1.1A_20%
C 3 1 49 C
GND GND VSS_EPAD 2 1 1
22U_0805_6.3V6M
CL7
0.1U_0402_16V4Z
CL8
10U_0805_10V4Z
CL9
1 1 @
CL5 CL6 WGI218LM-QQJY-B0_QFN48_6X6~D NOTE: Total requirement Cout>=20uF. ESR<50mohm.
10P_0402_50V8J 4 YL1 2 10P_0402_50V8J SA000066W60
1 2 2
2 2 LAYOUT NOTE: Place LL1, CL7, CL8, CL9, and close to PHY
0.1U_0402_16V4Z
+3VALW +3V_LAN
CL10
1 1
CL11
1
CL12
LAN Switch
RL17 1 2 4.7K_0402_5%
0.1U_0402_16V4Z
+3V_LAN 2 2 2
LAN_PME# 0.1U_0402_16V4Z
39
30
21
14
8
4
1
B RL16 RL15 UL2 B
RL19 1 @ 2 0_0402_5% 499_0402_1% 499_0402_1%
VDD
VDD
VDD
VDD
VDD
VDD
VDD
<35,8> PCH_PCIE_WAKE#
2
38
B0+ LAN_MIDI3-_DOCK <38>
37
LAN_MIDI3+_DOCK <38>
1
SML0CLK 6 1 LAN_SCLK LAN_MIDI3- 2 B0-
<30,7> SML0CLK A0+ 34
B1+ LAN_MIDI2-_DOCK <38>
QL2A LAN_MIDI3+ 3 33
A0- B1- LAN_MIDI2+_DOCK <38>
DMN66D0LDW-7_SOT363-6
5
29 To Docking.
B2+ LAN_MIDI1-_DOCK <38>
LAN_MIDI2- 6 28
A1+ B2- LAN_MIDI1+_DOCK <38> SEL:Low
SML0DATA 3 4 LAN_SDATA
+3V_LAN <30,7> SML0DATA
LAN_MIDI2+ 7 25
A1- B3+ LAN_MIDI0-_DOCK <38>
QL2B 24
B3- LAN_MIDI0+_DOCK <38>
DMN66D0LDW-7_SOT363-6
RL7 1 2 10K_0402_5% DET_SIG#_R LAN_MIDI1- 9 17
A2+ LEDB0 LAN_ACTIVITY#_DOCK <38>
18
LEDB1 LAN_LINK#_DOCK <38>
LAN_MIDI1+ 10 41
RL12 @1 2 10K_0402_5% JTAG_TMS_LAN A2- LEDB2
36
NOTE: Default SMBus LAN_MIDI0- 11 C0+ 35
LAN_MIDI3-_RJ45 <32>
A3+ C0- LAN_MIDI3+_RJ45 <32>
RL11 @1 2 10K_0402_5% JTAG_TCK_LAN Address is 0xC8
LAN_MIDI0+ 12 32
A3- C1+ LAN_MIDI2-_RJ45 <32>
31
C1- LAN_MIDI2+_RJ45 <32>
SMBUS PULL-UP OPTIONS @ To RJ45 conn
DET_SIG#_R RL13 1 2 0_0402_5% 13 27
<38,9> DET_SIG#_R SEL C2+ LAN_MIDI1-_RJ45 <32> SEL:High
26
C2- LAN_MIDI1+_RJ45 <32>
SMBUS SPEED RL15 & RL16
LAN_LINK# 15 23
LEDA0 C3+ LAN_MIDI0-_RJ45 <32>
LAN_ACTIVITY# 16 22
LEDA1 C3- LAN_MIDI0+_RJ45 <32>
1MHz(Defaul setting) 499ohm 42
LEDA2 19
5 LEDC0 20
PD LEDC1 40
100KHz/400KHz 2.2Kohm LEDC2
2
43
RL18 PAD_GND
A 10K_0402_5% A
1
PI3L720ZHEX_TQFN42_9X3P5~D
SA00003B200
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Intel I218
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 31 of 56
5 4 3 2 1
5 4 3 2 1
T36 JRJ1
1 24
TCT1 MCT1 12
D D
LAN_MIDI0+_RJ45 2 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND
<31> LAN_MIDI0+_RJ45 TD1+ MX1+ PR4- 11
LAN_MIDI0-_RJ45 3 22 RJ45_MIDI0- RJ45_MIDI3+ 7 GND
<31> LAN_MIDI0-_RJ45 TD1- MX1- PR4+
4 21 RJ45_MIDI1- 6
TCT2 MCT2 PR2-
LAN_MIDI1+_RJ45 5 20 RJ45_MIDI1+ RJ45_MIDI2- 5
<31> LAN_MIDI1+_RJ45 TD2 MX2+ PR3-
LAN_MIDI1-_RJ45 6 19 RJ45_MIDI1- RJ45_MIDI2+ 4
<31> LAN_MIDI1-_RJ45 TD2- MX2- PR3+
7 18 RJ45_MIDI1+ 3 40mil
TCT3 MCT3 PR2+
LAN_MIDI2+_RJ45 8 17 RJ45_MIDI2+ RJ45_MIDI0- 2
<31> LAN_MIDI2+_RJ45 TD3+ MX3+ PR1- 10
LAN_MIDI2-_RJ45 9 16 RJ45_MIDI2- RJ45_MIDI0+ 1 GND
<31> LAN_MIDI2-_RJ45 TD3- MX3- PR1+ 9
10 15 GND
TCT4 MCT4
LAN_MIDI3+_RJ45 11 14 RJ45_MIDI3+ SINGA_2RJ1660-000111F
<31> LAN_MIDI3+_RJ45 TD4+ MX4+
LAN_MIDI3-_RJ45 12 13 RJ45_MIDI3- CONN@
<31> LAN_MIDI3-_RJ45 TD4- MX4-
DC234007U00
1 1 1 1 350UH_IH-160
C335 C336 C337 C338 SP050006F00
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C 2 2 2 2 C
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C339
8
7
6
5
RP3 RJ45_GND 1 2 LANGND
1
2
3
4
2
1
D31
L27 SCA00002M00
MESC5V02BD03_SOT23-3
100UH +-20% TLPH4018C-101M 0.35A ESD@
RJ45_GND
SH00000N700 EMI@
2
40mil
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: W ednesday, September 17, 2014 Sheet 32 of 56
5 4 3 2 1
A B C D E
+5VS
1
60mil
RC4 1 @
60mil
2 0_0603_5%
+VDDA
<9> PCH_SPKR
2
RC1
47K_0402_5%
1 BEEP#_R
www.laptopblue.vn CC1
1 2 MONO_IN
1U_0402_6.3V6K
SPKL+
SPKL-
40mil
RC2
RC3
1
1
2 0_0603_5%
2 0_0603_5%
SPKL+_1
SPKL-_1
1
2
JSPK1
1
2
2
CC2 4.75V 1 3
CC3 RC5 DC1 4 G1
0.1U_0402_16V4Z G2
4.7K_0402_5% AZ5125-02S.R7G_SOT23-3
2 100P_0402_50V8J 3800-F02N-00R
(output = 300 mA) 2
Int. Speaker Conn. CONN@
1
@ESD@
DC2
POP 2 1 HDA_RST_AUDIO#
<38> POP
SM010014520 3000ma 220ohm@100mhz DCR 0.04
1
+PVDD_HDA @
1 40mil RB751V-40-YS_SOD323-2
1
26
40
41
46
36
9
2 2
UC1
CPVDD
DVDD
AVDD1
AVDD2
PVDD1
PVDD2
DVDD_IO
2 1 HP_DR_L CC15 1 2 HP_DC_L 24
<38> HP_DOCK_L LINE2_L
RC8 1K_0402_5% 4.7U_0603_6.3V6K
2 1 HP_DR_R CC19 1 2 HP_DC_R 23
<38> HP_DOCK_R
RC12 1K_0402_5% 4.7U_0603_6.3V6K LINE2_R 35mA 42 SPKL+
2 1 MIC2_DR_L CC20 1 2 MIC2_DC_L 17 68mA600mA SPK_OUT_L+
<38> MIC2_DOCK_L MIC2_L
RC9 1K_0402_5% 4.7U_0603_6.3V6K
2 1 MIC2_DR_R CC21 1 2 MIC2_DC_R 18 43 SPKL-
<38> MIC2_DOCK_R MIC2_R SPK_OUT_L-
RC10 1K_0402_5% 4.7U_0603_6.3V6K
2 1 LINE1_R_L CC16 1 2 LINE1_C_L 22 45 SPKR+
<38> LINE1_LEFT LINE1_L SPK_OUT_R+ SPKR+ <36>
RC11 1K_0402_5% 4.7U_0603_6.3V6K
2 1 LINE1_R_R CC17 1 2 LINE1_C_R 21
<38> LINE1_RIGHT LINE1_R
RC13 1K_0402_5% 4.7U_0603_6.3V6K 44 SPKR-
SPK_OUT_R- SPKR- <36> +MIC1_VREFOR +MIC1_VREFOL
MIC1_LEFT 2 1 MIC1_R_L CC18 1 2 MIC1_C_L 19
RC14 1K_0402_5% 4.7U_0603_6.3V6K MIC1_L 32 HP_LEFT
MIC1_RIGHT 2 1 MIC1_R_R CC22 1 2 MIC1_C_R 20 HPOUT_L
RC15 1K_0402_5% 4.7U_0603_6.3V6K MIC1_R 33 HP_RIGHT
1 35
CBN
HPOUT_R Mic In
1
8 HDA_SDIN0_AUDIO 1 RC16 2
SDATA_IN HDA_SDIN0 <6>
CC23 33_0402_5%
2.2U_0402_6.3V6M 37 5 RC17 RC18 JEMIC1
2 CBP SDATA_OUT HDA_SDOUT_AUDIO <6>
3K_0402_5% 3K_0402_5% 6
+MIC2_VREFO
10mil 29 10
HDA_SYNC_AUDIO <6>
LC7 1
2
MIC2_VREFO SYNC MIC1_LEFT RC19 1 2 47_0603_5% MIC1_LEFT_1 1 2 EMI@ MIC1_LEFT_2 2
11 HDA_RST_AUDIO# NBQ100505T-800Y-N
RESETB HDA_RST_AUDIO# <6>
+MIC1_VREFOR
10mil 30 MIC1_RIGHT RC20 1 2 47_0603_5% MIC1_RIGHT_1 1 2 EMI@ MIC1_RIGHT_2 3
MIC1_VREFO_R 6 NBQ100505T-800Y-N
External MIC BCLK HDA_BITCLK_AUDIO <6>
+MIC1_VREFOL
10mil 31
MIC1_VREFO_L
LC8 4
@EMI@ @EMI@ SM01000DS00
CC24 1 2 27 1 2 1 2 CC25 MIC1_JD 5
10U_0603_6.3V6M LDO1_CAP RC21 0_0402_5% 22P_0402_50V8J
CC26 1 2 39 SINGA_2SJ-0960-D11
10U_0603_6.3V6M LDO2_CAP 2 DMIC_DATA CONN@
GPIO0/DMIC_DATA For EMI
CC27 1 2 7 DC230006Y00
3 10U_0603_6.3V6M LDO3_CAP 3 DMIC_CLK 3
RC22 2 1 20K_0402_1% 15 GPIO1/DMIC_CLK
JDREF 47 EC_MUTE#
PD# EC_MUTE# <37>
JDMIC1
+3VS_DMIC 1
HP_PLUG# RC24 2 1 39.2K_0402_1% SENSE_A J5 J7 DMIC_CLK_R 2 1
JUMP_43X39 JUMP_43X39 DMIC_DATA_R 3 2 5
MIC1_JD RC25 2 1 20K_0402_1% 1 2 1 2 4 3 G1 6
@ 1 2 @ 1 2 4 G2
RC26 2 1 10K_0402_1% J6 J10 ACES_50208-0040N-001
<38> LINEIN_JD
4 JUMP_43X39 JUMP_43X39 4
1 2 1 2 SP02000K200
CONN@
@ 1 2 @ 1 2
RC27 2 1 39.2K_0402_1% SENSE_B J8 J9
<38> HP_DOCK_DET
JUMP_43X39 JUMP_43X39
RC28 2 1 20K_0402_1% 1 2 1 2
<38> MIC2_DOCK_DET
@ 1 2 @ 1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3225X
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V4DA2 M/B LA-9581P Schematic
Date: Wednesday, September 17, 2014 Sheet 33 of 56
A B C D E
www.laptopblue.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 34 of 56
A B C D E
+3VALW
U66
+3VS_WLAN www.laptopblue.vn NGFF(Wireless LAN & BT)
+3VS_WLAN +3VS_WLAN
1 0.1U_0402_16V4Z
5 VOUT
VIN 40mil(1A) 1 1 1
JWLAN1 C879 C880 C881
2 1 2
4 GND USB20_P6 3 GND_1 3.3VAUX_2 4
VIN <10> USB20_P6 5 USB_D+ 3.3VAUX_4 6 2 2 2
USB20_N6
3 <10> USB20_N6 7 USB_D- LED1# 8
1 0.01U_0402_25V7K 4.7U_0805_10V4Z 1
EN WLAN_ON <37> 9 GND_7 PCM_CLK 10
1 SDIO_CLK PCM_SYNC
C882 AP2821KTR-G1_SOT23-5 11 12 Place closely NGFF CONN. PIN2,4
SDIO_CMD PCM_OUT
1
1U_0402_10V6K 13 14
R726 15 SDIO_DAT0 PCM_IN 16
2 @ 17 SDIO_DAT1 LED2# 18
100K_0402_5% 19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_W AKE 22
2
23 SDIO_W AKE UART_TX
SDIO_RST
24
25 UART_RX 26
PCIE_PTX_C_DRX_P4 27 GND_33 UART_RTS 28
<10> PCIE_PTX_C_DRX_P4 29 PET_RX_P0 UART_CTS 30
40mil PCIE_PTX_C_DRX_N4
+3VS +3VS_WLAN <10> PCIE_PTX_C_DRX_N4 PET_RX_N0 CLink_RST CL_RST <7>
31 32
PCIE_PRX_DTX_P4 33 GND_39 CLink_DATA 34 CL_DATA <7>
<10> PCIE_PRX_DTX_P4 PER_TX_P0 CLink_CLK CL_CLK <7>
R727 1 @ 2 0_0603_5% PCIE_PRX_DTX_N4 35 36
<10> PCIE_PRX_DTX_N4 37 PER_TX_N0 COEX3 38
CLK_PCIE_WLAN 39 GND_45 COEX2 40
<7> CLK_PCIE_WLAN 41 REFCLK_P0 COEX1 42 2 1
CLK_PCIE_WLAN# SUSCLK_R R728 @ 0_0402_5%
<7> CLK_PCIE_WLAN# 43 REFCLK_N0 SUSCLK(32KHz) 44 PLT_RST#_W 2 1 SUSCLK <30,8>
R729 @ 0_0402_5%
GND_51 PERST0# PLT_RST_BUF# <18,30,31,8>
R730 1 @ 2 0_0402_5% WLAN_CLKREQ#_R 45 46 BT_ON#_R R731 1 @ 2 0_0402_5%
<7,8> WLAN_CLKREQ# 47 CLKREQ0# W _DISABLE2# 48 1 2 BT_ON# <37>
WLAN_WAKE#_RR WL_OFF#_R R732 @ 0_0402_5%
49 PEW AKE0# W _DISABLE1# 50 1 2 WL_OFF# <37>
NGFF_SMBDATA R733 @ 0_0402_5%
51 GND_57 I2C_DAT 52 NGFF_SMBCLK R734 1 @ 2 0_0402_5% D_CK_SDATA <15,29,7>
53 RSVD/PCIE_RX_P1 I2C_CLK 54 D_CK_SCLK <15,29,7>
55 RSVD/PCIE_RX_N1 I2C_IRQ 56
57 GND_63 RSVD_64 58 E51TXD_P80DATA
RSVD/PCIE_TX_P1 RSVD_66 E51TXD_P80DATA <37> +3VS_WLAN
59 60 E51RXD_P80CLK
61 RSVD/PCIE_TX_N1 RSVD_68 62 E51RXD_P80CLK <37>
GND_69 RSVD_70
1
63 64 0.1U_0402_16V4Z
PCH_PCIE_WAKE# R736 1 @ 2 WLAN_WAKE#_R 65 RSVD_71 3.3VAUX_72 66 R760
2 <31,8> PCH_PCIE_WAKE# RSVD_73 3.3VAUX_74 1 1 1 2
0_0402_5% 67 100K_0402_5% C883 C885 C884
WLAN_PME# R737 1 2 GND_75 68
<37> WLAN_PME# GND1
0_0402_5% 69
2
R738 1 2 GND2 2 2 2
+3VS_WLAN
10K_0402_5% SP070013E00 0.01U_0402_25V7K 4.7U_0805_10V4Z
BELLW_80152-3221
CONN@ Place closely NGFF CONN. PIN64,66
1
JMINI2
2
+3VS_3G
+3VALW TO +3VS_3G
TU155 @ 3G_CONFIG3 R401 1 3G@ 2 10K_0402_5%
+3VS_3G 3 CONFIG_3 3.3V 4 +3VALW +3VS_3G
5 Ground 3.3V 6 JSIM1 CONN@ U52
R406 2 3G@ 1 10K_0402_5% WAKE_OUT_WWAN USB20_P5_L 7 Ground Power_On_Off 8 3G_OFF# DMN3030LSS-13_SOP8L-8
USB20_N5_L 9 USB_D+ W _DISABLE# 10 3G_OFF# <35,37> 4 8 8 1
240mil
USB_D- LED# RFU RFU
4.7U_0603_6.3V6K
11 UIM_CLK 3 7 UIM_DATA 7 2
Ground CLK I/O
2
UIM_RST 2 6 2 6 3
RST VPP
C812
UIM_PWR 1 5 3G@ 5 R616
3G_CONFIG0 13 12 VCC GND 470_0603_5%
TU156 @ CONFIG_0 Reserved
TU157 @ WAKE_OUT_WWAN 15 14 3G@ 3G@
4
R402 1 2 10K_0402_5% BODYSAR_DET# 17 W ake_On_W W AN# Reserved 16 TAI_CPMPAT5-08GLBS1ZZ4H0 1
+3VS_3G
6 1
3G@ 19 BODYSAR_N Reserved 18 GPS_DISABLE# LTCX0060A00
21 Ground GPS_DISABLE# 20
23 NC Reserved 22 UIM_RST
25 NC UIM-RESET 24 UIM_CLK
10mil
20mil 470K_0402_5%
27 Ground UIM-CLK 26 UIM_DATA 3G@ 2 R620 1 3G_PWR_ON#_R 2 3G_PWR_ON#
NC UIM-DATA B+
3
29 28 UIM_PWR UIM_CLK C523 33P_0402_50V8K 3G@ 3
MINI_DET# 31 NC UIM-PW R 30 3G@ Q51A
<9> MINI_DET#
1
Ground NC
3
33 32 UIM_RST C524 33P_0402_50V8K 3G@ DMN66D0LDW-7_SOT363-6
35 NC Reserved 34 3G@ 3G@
NC Reserved 1
37 36 UIM_DATA C525 33P_0402_50V8K C813
33P_0402_50V8K C520 @ 39 Ground Reserved 38 3G@ 3G_PWR_ON# 5 0.1U_0603_25V7K
NC Reserved <37> 3G_PWR_ON#
330P_0402_50V7K 2 1 C445 @ 41 40 UIM_PWR C526 33P_0402_50V8K 3G@
330P_0402_50V7K 2 1 C446 @ 43 NC Reserved 42 Q51B 2
4
330P_0402_50V7K 2 1 C447 @ 45 Ground NC 44 3G@ DMN66D0LDW-7_SOT363-6
330P_0402_50V7K 2 1 C448 @ 47 NC NC 46 C809 1 2 1U_0402_10V6K
49 NC NC 48
ANT_TUNE_0_AP R621 1 @ 2 0_0402_5% ANT_TUNE_0 51 Ground NC 50
TU149 @ ANTCTL0 NC
TU150 @ ANT_TUNE_1_AP R622 1 @ 2 0_0402_5% ANT_TUNE_1 53 52
ANT_TUNE_2_AP R623 1 @ 2 0_0402_5% ANT_TUNE_2 55 ANTCTL1 Reserved 54
TU151 @ ANTCTL2 Reserved
ANT_TUNE_3_AP R624 1 @ 2 0_0402_5% ANT_TUNE_3 57 56 SM070003Y00
TU152 @ ANTCTL3 Reserved
R416 1 3G@ 2 10K_0402_5% 3G_RESET# 59 58 +3VS_3G EMI@
+3VS_3G Reset# SIM_DET
TU153 @ 3G_CONFIG1 61 60 MURATA DLW21HN900HQ2L _0805
63 CONFIG_1 NC 62
65 Ground 3.3V 64 USB20_P5_D 2 1 USB20_P5_L
3G_CONFIG2 67 Ground 3.3V 66 2 1
TU154 @ CONFIG_2 3.3V
69 68 +3VS_3G
GND GND USB20_N5_D 3 4 USB20_N5_L
3 4 3G@ 3G@ 3G@ 3G@
BELLW_80149-3223_67P CONN@ L37
USB20_N5 R420 1 @ 2 0_0402_5% USB20_N5_D
220U 4V Y D2 ESR15M
220U 4V Y D2 ESR15M
220U 4V Y D2 ESR15M
33P_0402_50V8K
330P_0402_50V7K
R419 2 @ 1 10K_0402_5%
+3VALW
R421 1 2 0_0402_5%
22U_0805_6.3V6M
USB20_P5 @ USB20_P5_D
0.1U_0402_16V4Z
1 1 1
@EMI@ C522
1U_0402_10V6K
2 1 1 1 3G@ 3G@ 3G@
+ + +
C444
C807
C803
C804
C805
R418 2 @ 1 10K_0402_5%
3G_OFF# <35,37>
C806
C808
U59
USB20_N5 1 10 R417 2 @ 1 10K_0402_5%
<10> USB20_N5 Y+ SEL +3VS 1 2 2 2 2 2 2
USB20_P5 2 9
4 <10> USB20_P5 Y- Vdd +3VALW 4
3 8 Truth Table
4 GND OE 7 USB20_N5_D
5 M- D+ 6 USB20_P5_D
M+ D-
SEL OE# Y+ Y-
@ PI3USB102ZLEX_TQFN10_1P6X1P3
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
H L D+ D- Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Tuesday, September 23, 2014 Sheet 35 of 56
A B C D E
A B C D E
<10> USB20_N1
USB20_N1
3
L36
3
www.laptopblue.vn
4
4
U2DN1_L
+5VALW
1
U33
8
+USB3_VCCA
W=40mils
2 GND VOUT 7
2 1 3 VIN VOUT 6
2 1 4 VIN VOUT 5 USB_OC0#
<36,37,38> USB_PW R_EN# EN FLG USB_OC0# <10,36,9>
USB20_P1 MURATA DLW 21HN900HQ2L _0805
U2DP1_L SY6288D10CAC _MSOP8
<10> USB20_P1
EMI@
0.1U_0402_16V4Z
C395
1 SA00004KB10
1 SM070003Y00 1
SM070000S80 WCM2012F2SF-670T04 67ohm
2
+USB3_VCCA
For ESD request
JUSB1
SM070003Y00 D37 @ESD@ U3TXDP2 9
1 1
W=80mils SSTX+
DLW 21HN900HQ2L_4P U3RXDN2 10 9 U3RXDN2 1
PCH_USB3_RX2_P 2 1 U3RXDP2 U3TXDN2 8 VBUS
<10> PCH_USB3_RX2_P 2 1 1 2 SSTX-
470P_0402_50V7K
C399
U3RXDP2 2 2 9 8 U3RXDP2 C398 U2DP1_L 3
+ 7 D+
3 4 4 4 GND
<10> PCH_USB3_RX2_N
PCH_USB3_RX2_N U3RXDN2 U3TXDN2 7 7 U3TXDN2 100U_B2_6.3VM_R35M U2DN1_L 2 10
3 4 1 U3RXDP2 6 D- GND 11
5 5 2 SSRX+ GND
L48 EMI@ U3TXDP2 6 6 U3TXDP2 4 12
U3RXDN2 5 GND GND 13
3 3 SSRX- GND
8 CONN@
L05ESDL5V0NA-4 SLP2510P8
SM070003Y00
DLW 21HN900HQ2L_4P D44 @ESD@
PCH_USB3_TX2_P 2 1 PCH_USB3_TX2_P_C 2 1 U3TXDP2 U2DP1_L 3 6
<10> PCH_USB3_TX2_P 2 1 I/O2 I/O4
C798 0.1U_0402_16V7K
1 4 U2DN1_L
I/O1 I/O3
AZC099-04S.R7G_SOT23-6
USB3.0 Conn.(MB)
SC300001G00
R661 1 2 0_0402_5%
+3VALW 20mil(250mA) +3V_USB +3VS
20mil
JIO1
U60 @ +3V_USB 1
1 USB_OC0# 2 1
VOUT <10,36,9> USB_OC0# 2
5 3
VIN <10> PCH_USB3_RX1_N 3
2 4
<10> PCH_USB3_RX1_P 4
2 5
4 GND C832 6 5
VIN <10> PCH_USB3_TX1_N 6
1 7
<10> PCH_USB3_TX1_P 7
C833 3 @ 1 4.7U_0603_6.3V6K 8
1U_0402_10V6K @ EN USB20_P0 9 8
<10> USB20_P0 9
AP2821KTR-G1_SOT23-5 USB20_N0 10
2 <10> USB20_N0 10
11
3 12 11 3
<10> PCH_USB3_RX4_N 12
<37,41,46> SYSON 13
<10> PCH_USB3_RX4_P 13
14
15 14
<10> PCH_USB3_TX4_N 15
16
<10> PCH_USB3_TX4_P 16
17
USB20_P3 18 17
<10> USB20_P3 18
<10> USB20_N3 USB20_N3 19
20 19
21 20
<37> USB_CHARGE_2A# 21
USB_PW R_EN# 22
<36,37,38> USB_PW R_EN# 22
23
<37,38> USB_CHARGE_CB0 23
USB_CEN 24
<37> USB_CEN 24
SPKR- 25
<33> SPKR- 25
SPKR+ 26
<33> SPKR+ 26
27
<37,38> SELCDP 27
+5VALW 28
29 28
30 29
31 30 34
32 31 GND2 33
32 GND1
ACES_51547-03201-W 01
CONN@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 & SSD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: W ednesday, September 17, 2014 Sheet 36 of 56
A B C D E
A B C D E
+3VALW L40
www.laptopblue.vn
NBQ100505T-800Y
1 @ 2 +3VALW_EC 1 2 +EC_VCCA
C407 R452 0_0603_5% 1 1 1 1 1
+3VALW
0.1U_0402_16V4Z
C408
0.1U_0402_16V4Z
C409
0.1U_0402_16V4Z
C410
0.1U_0402_16V4Z
C411
22P_0402_50V8J @EMI@
2 1 2 1 CLK_PCI_LPC C414
R454 33_0402_5% +3VLP 0.1U_0402_16V4Z USB_CEN R465 1 2 10K_0402_5%
@EMI@ 2 2 2 2 2 ECAGND
ECAGND <43>
R456 1 @ 2 0_0603_5% +EC_VCC
+EC_VCC <43> 1 2 100K_0402_5%
PC@ PC@ LID_SW# R453
111
125
R459 2 9012@ 1 47K_0402_5% EC_RST# +3VS
22
33
96
67
+3VALW_EC U36
9
C415 2 1 0.1U_0402_16V4Z TP_CLK R455 1 2 4.7K_0402_5%
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
9012@
1 1
TP_DATA R457 1 2 4.7K_0402_5%
KB_BL_EN 1 21 PKEY_LED#
+3VALW_EC <39> KB_BL_EN GATEA20/GPIO00 GPIO0F PKEY_LED# <39>
EC_KBRST# 2 23 6513_3V_PWR_EN# +3VS
<9> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 6513_3V_PWR_EN# <26>
RP4 SERIRQ 3 26 USB_PWR_EN#
+3VS 1 8 <39,9> SERIRQ 4 SERIRQ GPIO12 27 USB_PWR_EN# <36,38>
EC_SMB_CK1 LPC_FRAME# FAN_PWM
2 7 <39,7> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 FAN_PWM <40> 1 2 10K_0402_5%
EC_SMB_DA1 LPC_AD3 EC_MUTE# R458 @
3 6 EC_SMB_CK2 <39,7> LPC_AD3 LPC_AD2 7 LPC_AD3 C416 2 1 100P_0402_50V8J ECAGND
<39,7> LPC_AD2 LPC_AD2 PWM Output
4 5 EC_SMB_DA2 LPC_AD1 8 63 BATT_TEMP
<39,7> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <43>
LPC_AD0 10 LPC & MISC 64 3G_OFF#
<39,7> LPC_AD0 LPC_AD0 GPIO39 3G_OFF# <35>
2.2K_0804_8P4R_5% 65 ADP_I
12 ADP_I/GPIO3A 66 ADP_I <43,44>
CLK_PCI_LPC AD Input AD_BID0
<7> CLK_PCI_LPC 13 CLK_PCI_EC GPIO3B 75
PLT_RST# AUDIO_MUTE# R462
<30,39,8> PLT_RST# PCIRST#/GPIO05 GPIO42 AUDIO_MUTE# <33>
EC_RST# 37 76 PM_SLP_LAN#
<40> EC_RST# EC_SMI#_SCI# 20 EC_RST# IMON/GPIO43 PM_SLP_LAN# <8>
0_0402_5%
<9> EC_SMI#_SCI# 38 EC_SCII#/GPIO0E
WLAN_ON
<35> WLAN_ON GPIO1D 68 2 1
FAN_VSET @ H_PROCHOT#
DAC_BRIG/GPIO3C 70 FAN_VSET <40> <49> VR_HOT# H_PROCHOT# <4>
SELCDP
EN_DFAN1/GPIO3D 71 SELCDP <36,38>
DA Output DOCK_CRT_DET#
KSI0 55 IREF/GPIO3E 72 USB1_CEN DOCK_CRT_DET# <38>
KSI0/GPIO30 CHGVADJ/GPIO3F USB1_CEN <38>
1
+3VS KSI1 56 D
KSI2 57 KSI1/GPIO31 H_PROCHOT#_EC 2
KSI3 58 KSI2/GPIO32 83 EC_MUTE# Q31 G 9012@
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <33>
R486 1 2 10K_0402_5% DOCK_CRT_DET# KSI4 59 84 LAN_PWR_EN R487 2N7002E_SOT23-3 S
LAN_PWR_EN <31>
3
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 WLAN_PME# CRT_SEL 1 2
61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 WLAN_PME# <35>
KSI6 PS2 Interface COMM_LED#
1 2 10K_0402_5% 62 KSI6/GPIO36 EAPD/GPIO4D 87 COMM_LED# <39>
R469 @ EC_SMI#_SCI# KSI7 TP_CLK TP_CLK <39> 10K_0402_5%
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <39>
KSO1 40
C417 1 2 0.01U_0402_16V7K PLT_RST# KSO2 41 KSO1/GPIO21
KSI[0..7] KSO3 42 KSO2/GPIO22 97 USB1_CHARGE_2A# H_PROCHOT#_EC R745 2 9022@ 1 0_0402_5% H_PROCHOT#
<39> KSI[0..7] 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 USB1_CHARGE_2A# <38>
2 ESD@ KSO4 USB_CHARGE_2A# 2
KSO[0..17] KSO4/GPIO24 W OL_EN/GPXIOA01 USB_CHARGE_2A# <36>
ESD request KSO5 44 99 HDA_SDO
<39> KSO[0..17]
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 VCIN0_PH
HDA_SDO <6>
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <43>
KSO7 46 SPI Device Interface
KSO8 47 KSO7/GPIO27
KSO9 48 KSO8/GPIO28 119 EC_SPI_SI
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_SO EC_SPI_SI <7>
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPI_CLK EC_SPI_SO <7> ENBKL R472 1 @ 2 0_0402_5%
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SPI_CLK <7> ACIN <44,8>
KSO12 51 128 EC_SPI_CS#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <7>
1
KSO13 52
KSO14 53 KSO13/GPIO2D R470 EC_ACIN C418 2 1 100P_0402_50V8J
KSO15 54 KSO14/GPIO2E 73 ENBKL @ 100K_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <8>
KSO16 81 74 BT_ON#
82 KSO16/GPIO48 PECI_KB930/GPIO41 89 BT_ON# <35>
KSO17 GPU_OVERT# GPU_OVERT# <18>
2
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 91 BATT_BLUE_LED# <39>
USB_CHARGE_CB0
CAPS_LED#/GPIO53 USB_CHARGE_CB0 <36,38>
EC_SMB_CK1 77 GPIO 92 PWR_LED#
<43,44> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PW R_LED#/GPIO54 PWR_LED# <38,39>
Battery , Charger IC EC_SMB_DA1 78 93 BATT_AMB_LED#
<43,44> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW _LED#/GPIO55 BATT_AMB_LED# <39>
EC_SMB_CK2 79 SM Bus 95 SYSON SYSON
<16,18,7> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <36,41,46>
PCH ,Onboard RAM Thermal ,GPU Thermal sensor EC_SMB_DA2 80 121 USB2_CHARGE_2A#
<16,18,7> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 USB2_CHARGE_2A# <38>
1
127 PM_SLP_S4# +EC_VCC R471 1 @ 2 0_0402_5%
PM_SLP_S4#/GPIO59 PM_SLP_S4# <8> +3VLP
R526
100K_0402_5% Pin 111 is a power source for HW operation of KB9012.
PM_SLP_S3# 6 100 PCH_RSMRST#
<8> PM_SLP_S3#
PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_FIXCODE_3VM
PCH_RSMRST# <8> So, power plan will be different between KB930 and KB9012.
<8> PM_SLP_S5# EC_FIXCODE_3VM <41>
2
CRT_SEL 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 VCIN1_PROCHOT
<27> CRT_SEL EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_PROCHOT <43>
<36> USB_CEN USB_CEN 16 103 H_PROCHOT#_EC
17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 H_PROCHOT#_EC <43>
<39> CAP_LED# CAP_LED# MAINPWON
18 GPIO0B VCOUT0_PH/GPXIOA07 105 MAINPWON <43,45>
MUTE_LED# GPO BKOFF#
<39> MUTE_LED# GPIO0C BKOFF#/GPXIOA08 BKOFF# <25>
WL_OFF# 19 GPIO 106 PBTN_OUT#
<35> WL_OFF# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <8>
SPOK 25 107 PM_SLP_WLAN#
<45> SPOK EC_INVT_PW M/GPIO11 PCH_APW ROK/GPXIOA10 PM_SLP_WLAN# <8>
FAN_SPEED1 28 108 USB2_CEN
3 <40> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 USB2_CEN <38> 3
VCCST_PG_EC 29
<11,8> VCCST_PG_EC EC_PME#/GPIO15
E51TXD_P80DATA 30
<35> E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN
<35> E51RXD_P80CLK 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112
PCH_PWROK EC_ON
<8> PCH_PWROK PCH_PW ROK/GPIO18 EC_ON/GPXIOD02 EC_ON <45>
PWR_SUSP_LED# 34 114 ON/OFF# ON/OFF#
<39> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF# <39>
NUM_LED# 36 GPI 115 LID_SW#
<39> NUM_LED# NUM_LED#/GPIO1A LID_SW #/GPXIOD04 116 LID_SW# <39,9>
SUSP# 1
SUSP#/GPXIOD05 117 SUSP# <38,41,47,48>
VCCST_PWRGD C421
GPXIOD06 118 R634 1 2 VCCST_PWRGD <11,47>
0.1U_0402_16V4Z
122 PECI_KB9012/GPXIOD07 H_PECI <4>
AGND/AGND
3G_PWR_ON# 43_0402_1%
<35> 3G_PWR_ON# 123 XCLKI/GPIO5D 124 2
DGPU_AC_DETECT +V18R R744 1 2 0_0402_5% +3VALW_EC
GND/GND
GND/GND
GND/GND
GND/GND
9012@ PM_SLP_S5#
C422
4.7U_0603_6.3V6K 2
S IC KB9022D LQFP 128P 2 C436
11
24
35
94
113
69
PM_SLP_S3#
+3VALW_EC U36
9012@
Board ID C437
2
2
AD_BID0
1
1
C424
Rb R483 0.1U_0402_16V4Z
20K_0402_1%
2
Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 37 of 56
A B C D E
2 1
www.laptopblue.vn +3VS
1
R127
1M_0402_5% @
2
JDOCK3 1K_0402_5% DP_DOCK_CAD
1 2 SYS_IN# 2 1 R547
1 2
2
LAN_MIDI0+_DOCK 3 4
<31> LAN_MIDI0+_DOCK 3 4 +3V_LAN width=10 mil
LAN_MIDI0-_DOCK 5 6 LAN_ACTIVITY#_DOCK R124
<31> LAN_MIDI0-_DOCK 7 5 6 8 LAN_LINK#_DOCK LAN_ACTIVITY#_DOCK <31>
7 8 LAN_LINK#_DOCK <31> 1M_0402_5%
LAN_MIDI1+_DOCK 9 10
<31> LAN_MIDI1+_DOCK LAN_MIDI1-_DOCK 11 9 10 12 DP_DOCK_SEL DP_DOCK_CAD <28>
<31> LAN_MIDI1-_DOCK DP_DOCK_SEL <28>
1
13 11 12 14
LAN_MIDI2+_DOCK 15 13 14 16 USB1_CEN <37>
<31> LAN_MIDI2+_DOCK LAN_MIDI2-_DOCK 17 15 16 18 USB2_CEN <37>
<31> LAN_MIDI2-_DOCK 19 17 18 20 USB1_CHARGE_2A# <37>
21 19 20 22 USB2_CHARGE_2A# <37>
LAN_MIDI3+_DOCK
<31> LAN_MIDI3+_DOCK LAN_MIDI3-_DOCK 23 21 22 24 DOCK_CRT_DET# <37>
<31> LAN_MIDI3-_DOCK 25 23 24 26
27 25 26 28 CRT_DATA_DOCK
29 27 28 30 CRT_DATA_DOCK <27>
CRT_CLK_DOCK
31 29 30 32 CRT_CLK_DOCK <27>
33 31 32 34 RED_DOCK
B 35 33 34 36 RED_DOCK <27> B
37 35 36 38 BLUE_DOCK
39 37 38 40 BLUE_DOCK <27>
41 39 40 42 GREEN_DOCK
43 41 42 44 GREEN_DOCK <27>
45 43 44 46 HSYNC_DOCK
47 45 46 48 VSYNC_DOCK HSYNC_DOCK <27>
49 47 48 50 VSYNC_DOCK <27>
51 49 50 52
53 51 52 54 HDMI_HPD_DOCK
55 53 54 56 HDMI_HPD_DOCK <28>
57 55 56 58 HDMI_DOCK_D2+_R R649 1 EMI@ 2 0_0402_5% HDMI_DOCK_D2+_CC290 2 1 0.1U_0402_16V7K HDMI_DOCK_D2+
59 57 58 60 HDMI_DOCK_D2+ <28>
HDMI_DOCK_D2-_R R650 1 EMI@ 2 0_0402_5% HDMI_DOCK_D2-_C C291 2 1 0.1U_0402_16V7K HDMI_DOCK_D2-
61 59 60 62 HDMI_DOCK_D2- <28>
63 61 62 64 HDMI_DOCK_D1+_R R651 1 EMI@ 2 0_0402_5% HDMI_DOCK_D1+_CC292 2 1 0.1U_0402_16V7K HDMI_DOCK_D1+
65 63 64 66 HDMI_DOCK_D1+ <28>
HDMI_DOCK_D1-_R R652 1 EMI@ 2 0_0402_5% HDMI_DOCK_D1-_C C293 2 1 0.1U_0402_16V7K HDMI_DOCK_D1-
<33> DOCK_CODEC_DET LINEIN_JD 67 65 66 68 HDMI_DOCK_D1- <28>
<33> LINEIN_JD 69 67 68 70
MIC2_DOCK_DET HDMI_DOCK_D0+_R R653 1 EMI@ 2 0_0402_5% HDMI_DOCK_D0+_CC295 2 1 0.1U_0402_16V7K HDMI_DOCK_D0+
<33> MIC2_DOCK_DET 71 69 70 72 HDMI_DOCK_D0+ <28>
HP_DOCK_DET HDMI_DOCK_D0-_R R654 1 EMI@ 2 0_0402_5% HDMI_DOCK_D0-_C C294 2 1 0.1U_0402_16V7K HDMI_DOCK_D0-
<33> HP_DOCK_DET 73 71 72 74 HDMI_DOCK_D0- <28>
<33> POP 75 73 74 76 HDMI_DOCK_CK+_R R655 1 EMI@ 2 0_0402_5% HDMI_DOCK_CK+_CC296 2 1 0.1U_0402_16V7K HDMI_DOCK_CK+
LINE1_RIGHT 77 75 76 78 HDMI_DOCK_CK-_R R656 1 EMI@ 2 0_0402_5% HDMI_DOCK_CK-_C C297 2 1 0.1U_0402_16V7K HDMI_DOCK_CK- HDMI_DOCK_CK+ <28>
<33> LINE1_RIGHT 79 77 78 80 HDMI_DOCK_CK- <28>
LINE1_LEFT
<33> LINE1_LEFT 81 79 80 82 HDMI2_DOCK_SDA
81 82 HDMI2_DOCK_SDA <28>
MIC2_DOCK_R 83 84 HDMI2_DOCK_SCL
<33> MIC2_DOCK_R 83 84 HDMI2_DOCK_SCL <28>
MIC2_DOCK_L 85 86
<33> MIC2_DOCK_L 87 85 86 88
HP_DOCK_R 89 87 88 90
<33> HP_DOCK_R 91 89 90 92
HP_DOCK_L
<33> HP_DOCK_L 93 91 92 94
95 93 94 96
97 95 96 98 ON/OFFBTN#
+MIC2_VREFO 97 98 ON/OFFBTN# <39,8>
99 100 DET_SIG# 0_0402_5% 2 @ 1 R546 DET_SIG#_R
101 99 100 102 DET_SIG#_R <31,9>
DOCK_SPOK#
103 101 102 104 USB_PWR_EN#
105 103 104 106 SUSP# USB_PWR_EN# <36,37> SUSP#
107 105 106 108 PWR_LED# SUSP# <37,41,47,48>
109 107 108 110 PWR_LED# <37,39>
109 110 USB_CHARGE_CB0 <36,37>
1U_0402_6.3V6K
C814
111 112 1
113 111 112 114 SELCDP <36,37>
<10> PCH_USB3_TX3_P 115 113 114 116
<10> PCH_USB3_TX3_N 117 115 116 118
119 117 118 120 2
121 119 120 122
<10> PCH_USB3_RX3_N 123 121 122 124
<10> PCH_USB3_RX3_P 125 123 124 126
USB20_P2_L 127 125 126 128
USB20_N2_L 129 127 128 130
131 129 130 132
133 131 132 134
135 133 134 136
137 135 136 138
139 137 138 140
141 139 140 142
143 141 142 144
USB20_N2 R628 1 EMI@ 2 0_0402_5% 143 144
<10> USB20_N2
145 149
SM070003Y00 146 GND1 PWR2 150 MB_VIN
2 1 USB20_N2_L 147 PWR1 PWR2 151
2 1 148 PWR1 PWR2 152
L38 @EMI@ PWR1 GND2
3 4 USB20_P2_L 153 159
3 4 154 Shield_G Shield_G 160
MURATA DLW21HN900HQ2L _0805 155 Shield_G Shield_G 161
A 156 Shield_G Shield_G 162 A
USB20_P2 R629 1 2 0_0402_5% 157 Shield_G Shield_G 163
<10> USB20_P2 Shield_G Shield_G
EMI@ 158 164
Shield_G Shield_G
JAE_WD2F144WB5R400
CONN@
SP0300013A0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
E Series Dcok CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 17, 2014 Sheet 38 of 56
2 1
A B C D E
TPM
+3VALW
R742 1 @ 2 0_0603_5%
+3VALW_TPM +3VS
R741 1 @ 2 0_0603_5%
+3VS_TPM www.laptopblue.vn
KB Conn.
KSI[0..7]
KSO[0..17]
KSI[0..7]
KSO[0..17]
<37>
<37>
KSO0
KSO1
KSO2
KSO3
KSO4
26
25
24
23
22
JKB1
GND2
GND1
26
25
24
23
28
27
KB Backlight Conn
+5VALW
22
10U_0603_6.3V6M
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 KSO5 21
KSO6 20 21
20
C889
C890
C891
C892
C893
C894
KSO7 19
19
1
KSO8 18 +5VS CONN@
2 2 2 2 2 2 KSO9 17 18 ACES_50504-0040N-001
17
D
KSO10 16 R511 3 1 +5VS_BL 4 6
KSO11 15 16 100K_0402_5% 3 4 G2 5
KSO12 14 15 Q23 DMG2301U-7_SOT23-3 2 3 G1
2
1
near pin5 KSO13 13 14 1 2 1
G
2
near pin10, 19, 24 KSO14 12 13 1
KSO15 11 12 JBL1
KSO16 10 11
+3VS_TPM KSO17 9 10
KSI0 8 9
U67 KSI1 7 8 KB_BL_EN#
R743 1 2 10K_0402_5% CLKRUN# 5 KSI2 6 7
VSB +3VALW_TPM 6
1 10 KSI3 5
2 GPIO0/XOR_OUT VDD 19 KSI4 4 5
GPIO1 VDD +3VS_TPM 4
1
GPIO3/BADD with Internal PH (default) 6 24 KSI5 3 D
0_0402_5% 1 @ 2 R739 TPM_BADD 9 GPIO2/GPX VDD KSI6 2 3 2 Q24
GPIO3/BADD 2 <37> KB_BL_EN
CLKRUN# 15 8 KSI7 1 G 2N7002E_SOT23-3
<8> CLKRUN# GPIO4/CLKRUN# TEST 1
S
3
<37,7> LPC_AD0 LPC_AD0 26 ACES_50565-0260N-001_26P
LPC_AD1 23 LAD0/MISO CONN@
<37,7> LPC_AD1 LAD1/MOSI
LPC_AD2 20 3 SP01001IE00
<37,7> LPC_AD2 LAD2/SPI_IRQ# NC
<37,7> LPC_AD3 LPC_AD3 17 12
LAD3 NC 13
NC 14
LPCPD# had internal PH 28 NC
CLK_PCI_TPM 21 LPCPD#
<7> CLK_PCI_TPM LCLK/SCLK BADD SELECTION
LPC_FRAME# 22
<37,7> LPC_FRAME# 16 LRFAME#/SCS# 4
PLT_RST#
<30,37,39,8> PLT_RST# LRSET#/SPI_RST# GND
<37,9> SERIRQ SERIRQ 27 11 0 EEh - EFh
7 SERIRQ GND 18
PP GND 25
GND
*1 7Eh - 7Fh
NPCT650AA0WX_TSSOP28
SA00007IO00
@EMC@ @EMC@
CLK_PCI_TPM R740 1 2 33_0402_5% C886 1 2 22P_0402_50V8J
2 2
+3VS
JTP1
2
4 6
R513 3 4 G2 5
<37> TP_DATA 2 3 G1
100K_0402_5%
<37> TP_CLK 2
1
JLID1 1
Test Only
1
3
CardReader Board FP Board Function Board 3
+3VALW
JREAD1 JFUN1
1 1
PCIE_PTX_C_DRX_P6 2 1 +3VS PWR_LED# 2 1
<6> PCIE_PTX_C_DRX_P6 3 2 <37,38,39> PWR_LED# 3 2
PCIE_PTX_C_DRX_N6 MUTE_LED#
<6> PCIE_PTX_C_DRX_N6 3 <37> MUTE_LED# 3
4 JFP1 PKEY_LED# 4
5 4 1 <37> PKEY_LED# 5 4
CLK_PCIE_CARD COMM_LED#
<7> CLK_PCIE_CARD 5 1 <37> COMM_LED# 5
CLK_PCIE_CARD# 6 USB20_N7 2 NUM_LED# 6
<7> CLK_PCIE_CARD# 6 <10> USB20_N7 2 <37> NUM_LED# 6
7 USB20_P7 3 5 CAP_LED# 7
8 7 <10> USB20_P7 4 3 G1 6 <37> CAP_LED# 8 7
PCIE_PRX_DTX_P6
<6> PCIE_PRX_DTX_P6 8 4 G2 8
PCIE_PRX_DTX_N6 9 KSO0 9
<6> PCIE_PRX_DTX_N6 10 9 <37> KSO0 10 9
+3VALW ACES_50504-0040N-001 KSI3
10 <37> KSI3 10
CARD_CLKREQ# 11 CONN@ KSI4 11
<7,9> CARD_CLKREQ# 11 <37> KSI4 11
PLT_RST# 12 KSI5 12
<30,37,39,8> PLT_RST# 13 12 <37> KSI5 13 12
D22 @ESD@ ON/OFFBTN#
<37,38,39> PWR_LED# 13 <38,8> ON/OFFBTN# 13
14 3 6 USB20_N7 14
<37> PWR_SUSP_LED# 15 14 I/O2 I/O4 15 14
<37> BATT_BLUE_LED# 15 15
BATT_AMB_LED# 16 16
<37> BATT_AMB_LED# 16 16
17 19 0.1U_0402_16V4Z C820 1 2 ESD@ PWR_LED#
<6> PCH_SATALED# 18 17 G1 20 2 5 1 2 17
+3VS +3VS 0.1U_0402_16V4Z C821 ESD@ MUTE_LED#
18 G2 GND VDD 0.1U_0402_16V4Z C822 1 2 ESD@ PKEY_LED# 18 GND
ACES_50505-0184N-001 0.1U_0402_16V4Z C823 1 2 ESD@ COMM_LED# GND
CONN@ 0.1U_0402_16V4Z C824 1 2 ESD@ NUM_LED# ACES_51524-0160N-001
BATT_AMB_LED# USB20_P7 1 4 0.1U_0402_16V4Z C825 1 2 ESD@ CAP_LED# CONN@
I/O1 I/O3
1
C831 AZC099-04S.R7G_SOT23-6 0.1U_0402_16V4Z C826 1 2 @ KSO0 SP01001C600
0.1U_0402_16V4Z 0.1U_0402_16V4Z C827 1 2 @ KSI3
ESD@ 0.1U_0402_16V4Z C828 1 2 @ KSI4 07/26 Add
2 0.1U_0402_16V4Z C829 1 2 @ KSI5
0.1U_0402_16V4Z C830 1 2 ESD@ ON/OFFBTN#
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/LID/TPM/FUN/FP/CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B731P
Date: Wednesday, September 17, 2014 Sheet 39 of 56
A B C D E
FAN Conn
C895
www.laptopblue.vn WIFI Stand off
H1
3G Stand off
H2
SSD Stand off
H3
FAN Stand off
H4 H5
20mil
+5VS R514 2 @ 1 +5VS_FAN 1 2 H_3P3 H_3P3 H_3P3 H_3P8 H_3P8
0_0603_5%
2
4.7U_0603_6.3V6K
R761
1
0_0603_5% U68
@ 1 8
2 EN GND 7
1 +VCC_FAN1 3 VIN GND 6 @ @ @ @ @
FAN_VSET 4 VOUT GND 5
<37> FAN_VSET VSET GND
NCT3942S SOP 8P
SA00005CA00
+3VS H8 H9 H10 H11 H12 H15 H16 H17
H_2P5 H_2P5 H_2P5 H_2P5 H_2P5 H_3P0 H_2P5 H_2P5
1
R515
1
10K_0402_5%
CONN@
ACES_88266-04001_4P
2
+VCC_FAN1 4 6 @ @ @ @ @ @ @ @
FAN_SPEED1 3 4 G2 5
<37> FAN_SPEED1
FAN_PWM 2 3 G1 H18 H19 H20 H21 H22 H23 H24
<37> FAN_PWM
1 2 H_3P0N H_3P0N H_3P8 H_3P8 H_3P8 H_4P0 H_4P0 H25 H26
1 H_5P0X3P0N H_3P5X3P0N
JFAN1
SP02000K200
1
+VCC_FAN1 10U_0805_10V4Z 1 2 C481
@ @ @ @ @ @ @ @ @
0.1U_0402_16V4Z 1 2 C896
locate MB
+RTCVCC +3VLP +3VLP
EC_RST# <37>
1
DU2 R415
BAV70W_SOT323-3 10K_0402_5%
6
2
1
2 DMN66D0LDW-7_SOT363-6
2 Q52A
1
3
1
0.1U_0402_16V4Z
C370
R525
<43> BI 1K_0402_5%
5
1
2
Q22 Q52B
4
D
1
2N7002E_SOT23-3 DMN66D0LDW-7_SOT363-6
2
SW2
G FD1 FD2
2
S 1 3 1
3
R527 C369
1M_0402_5% 0.1U_0402_16V4Z 4 2 @ @
1
2 SN100009500 FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
DTSJ-62N-Q-T-R_4P
FD3 FD4
@ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
FAN & Screw Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B731P
Date: Wednesday, September 17, 2014 Sheet 40 of 56
A B C D E
+5VALW
www.laptopblue.vn
+1.05VS_VTT
2
+0.675VS
+3VALW to +3VM for Intel AMT R598
2
100K_0402_5%
+3VALW to +3VS
1
@ R605
R604 470_0603_5%
20mil(68mA) +5VALW to +5VS
1
+3VALW +3VM +3VALW SUSP @
470_0603_5%
U56 VPRO@ @
1
1 2 R635 1 +1.05VS_VTT_R
2
5 VOUT 0_0402_5% U48 @ J11
VIN 1 14 1 2 2N7002E_SOT23-3 +0.675VS_R
2 NOVPRO@ +3VALW VIN1 VOUT1 1 2 +3VS
1
2 2 13 Q44 D D
GND VIN1 VOUT1
1
4 C810 47K_0402_5% C786 JUMP_43X118 2 D Q46 2 SUSP
VIN <37,38,47,48> SUSP#
1 VPRO@ SUSP# 2 R600 1 3VS_ON 3 12 2 1 330P_0402_50V7K G Q45 2 SUSP 2N7002E_SOT23-3 G
ON1 CT1
1
C817 3 1 4.7U_0603_6.3V6K C787 S@ 2N7002E_SOT23-3 G S
3
1U_0402_10V6K @ EN 1 2 4 11 R603
+5VALW S @ @
3
1
AP2821KTR-G1_SOT23-5 0.1U_0402_16V4Z VBIAS GND 10K_0402_5%
1
2 2 R601 1 5VS_ON 5 10 2 1 @
0_0402_5% ON2 CT2 330P_0402_50V7K
2
C789 6 9 C788 @ J12
<46,8> PM_SLP_A# +5VALW VIN2 VOUT2 +1.35V +5VALW
1 2 7 8 1 2 +5VS
0.1U_0402_16V4Z VIN2 VOUT2 1 2
@ 15 JUMP_43X118
GPAD
2
+3VALW +3VALW +3VM
+1.05VS_VTT +1.05VM
VPRO@ AOZ1331DI_DFN14 R609 R610
470_0603_5% 100K_0402_5%
D
3 1 @ @
1
1 R636 2 0_0603_5% R512 Q25 DMG2301U-7_SOT23-3 SYSON#
NOVPRO@ 100K_0402_5% +1.35V_R
G
2
3
VPRO@
6
5 SYSON
2 SYSON <36,37,46>
SYSON# Q49B
1
D Q49A DMN66D0LDW-7_SOT363-6
4
2 Q26 DMN66D0LDW-7_SOT363-6 @
<37> EC_FIXCODE_3VM
1
G 2N7002E_SOT23-3 @
S VPRO@
3
1
R516
100K_0402_5%
VPRO@
2
10U_0603_6.3V6M
CV93
4 CV91 6 3
IN
CV94
10U_0603_6.3V6M
0.1U_0603_25V7K
CV95
2 VGA@ 5 1
1
CV92 3 1 4.7U_0603_6.3V6K VGA@ VGA@
4.7U_0603_6.3V6K EN VGA@ VGA@ VGA@ RV78
4
VGA@ G5243T11U_SOT23-5 47_0402_5%
2
1 2
2
+1.05VSDGPU_R
10mil
6
DGPU_PWR_EN 10mil
DGPU_PWR_EN <41,51,8,9>
B+ RV79 1 VGA@ 2 100K_0402_5% 1.05VSDGPU_GATE
1
1 2 3VSDGPU_MAIN_EN#
3
RV97 VGA@ QV2A
+3VS_VGA_AON +3VS_VGA_MAIN 10K_0402_5% CV96 DMN66D0LDW-7_SOT363-6
1
@ J20 @ 0.22U_0603_25V7K VGA@
1 2 3VSDGPU_MAIN_EN# 5 2
2
1 2 QV2B
JUMP_43X79 DMN66D0LDW-7_SOT363-6 VGA@
4
J20 mount when no GC6
+3VLP
+3VS to +3VSDGPU_MAIN for GC6-2.0
2
+3VS +3VS_VGA_MAIN VGA@
UV11 RV80
1 100K_0402_5%
3
5 OUT 3
IN 100mil(1.5A)
2
1
2
4 GND CV97 RV92 1 2 0_0402_5% 3VSDGPU_MAIN_EN#
IN <41,51,8,9> DGPU_PWR_EN
2 GC6@ NOGC6@
1
CV98 3 1 4.7U_0603_6.3V6K VGA@ D
GC6@ EN RV94 1 2 0_0402_5% 2
<18,41,51> 3VSDGPU_MAIN_EN
1U_0402_6.3V6K G5243T11U_SOT23-5 GC6@ G
1 GC6@ S
3
2
QV3 L2N7002LT1G_SOT23-3
VGA@
RV81
100K_0402_5%
1
3VSDGPU_MAIN_EN
3VSDGPU_MAIN_EN <18,41,51>
3VSDGPU_MAIN_EN From GPU
+5VALW +1.5VSDGPU
+5VALW +VGA_CORE
2
RV82
2
47_0603_5%
2
@ @ RV83
2
@ RV85 47_0603_5%
1
+VGA_CORE_R
1
L2N7002LT1G_SOT23-3
1
@ D
1.5VS_DGPU_PWR_EN# 2 DGPU_PWR_EN# 2
QV4A G
3
DMN66D0LDW-7_SOT363-6 L2N7002LT1G_SOT23-3 S
1
3
1
4 @ @ D QV5 4
DGPU_PWR_EN 2
<41,51,8,9> DGPU_PWR_EN
1.5VS_DGPU_PWR_EN 5 G
<18,48> 1.5VS_DGPU_PWR_EN
@ QV4B S
3
2
@ DMN66D0LDW-7_SOT363-6 QV6
4
RV86 @
100K_0402_5% RV87
100K_0402_5%
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B731P
Date: Wednesday, September 24, 2014 Sheet 41 of 56
A B C D E
A B C D
www.laptopblue.vn PD101
VIN
PDS1040-13_POW ERDI5-3
2
1
MB_VIN 3
1 1
6 PL101 EMI@
GND 5 FBMA-L11-322513-151LMA50T_1210 2
GND 4 DC_IN_S1 1 2 DC_IN_S2 1
4 3 3
3 2 PD102
2 1 PDS1040-13_POW ERDI5-3
1
1
ACES_87302-0401-003
@ PJP101 PC101 PC104
1000P_0603_50V7K 1000P_0603_50V7K
2
EMI@ EMI@
EMI
BOM Config
2 2
UMA EMI@
DDR3L
DIS EMI@/VGA@/VGAEMI@
3 3
+3VLP
Rshort@
PR101
1 2
+CHGRTC
0_0402_5%
2014/9/17
DIS@ DIS@
PBJ101 @DIS@ PR102 PR103
560_0603_5% 560_0603_5%
2 1 1 2 1 2
DIS: RTC at FAN
+RTCBATT
ML1220T13RE
4 4
UMA@ UMA@
PBJ102 @UMA@ PR105 PR104
560_0603_5% 560_0603_5%
2 1 1 2 1 2
+RTCBATT
UMA: RTC at Docking
ML1220T13RE Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/19 Deciphered Date 2012/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V4DA2 LAA131P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, September 17, 2014 Sheet 42 of 55
A B C D
A B C D
1
1
3 PR202 @ PC202
1
1
100_0402_1% 0.1U_0603_25V7K
<40,41>
2
1
1
PJP201
VMB @ PR204 @ PR205
2
@ PR203 10K_0402_1% 10K_0402_1%
100_0402_1%
EC_SMB_DA1 <37,44>
2
PL201 EMI@
<40,41>
1
FBMA-L11-322513-151LMA50T_1210 @ PU201
2
BATT_S1 1 2 @ PR207 1 8
VCC TMSNS1
BATT+ 100K_0402_1%
1
2 7 2 1
EC_SMB_CK1 <37,44> GND RHYST1
1
1
PR201
1
PC201 EMI@ PC203 EMI@ 0_0402_5% 3 6 @ PR208
1000P_0402_50V7K 0.01U_0402_25V7K <37,45> MAINPW ON OT1 TMSNS2 47K_0402_1%
2
2
PR211 4 5 @ PH201
2
6.49K_0402_1% OT2 RHYST2 100K_0402_1%_NCP15W F104F03RC
2 1 G718TM1U_SOT23-8
+3VLP
2
EMI
1
2013/10/28 update PH201 chang
PR212
1K_0402_1% Common part SL200002H00
2
BATT_TEMP <37>
BI <40>
2 2
2013/10/14 update
For KB9022
sense 20mΩ
Active Recovery
40W PR202 52W,0.54V 40W,0.42V
10K ohm
65W PR20284.5W,0.54V 65W,0.42V
22.6K ohm
1
Iada=0~3.42A (65W/19v=3.42A) PR214
1
3 3
21K_0402_1%
ADP_I=20*Iada*Rsense PR217
=20*3.42*0.02=1.368V 22.6K_0402_1%
2
VCIN1_PROCHOT=1.368*10/(10+22.6)=0.42V <37> VCIN0_PH
2
2014/09/12 Change PR214 16.9kohm to 21kohm, VCIN1_PROCHOT <37>
84.5W: change OTP trigger temperture to 85 degree
Iada=0~4.447A (84.5W/19v=4.447A) @ PR206
60.4K_0402_1%
ADP_I=20*Iada*Rsense 1 2 H_PROCHOT#_EC <37>
=20*4.447*0.02=1.788V
VCIN1_PROCHOT=1.788*10/(10+22.6)=0.55V
1
PR223
100K_0402_1%_NCP15WF104F03RC
1
10K_0402_1%
2
@ PC207
此此此此此EC pin
PH203
1000P_0402_50V7K
CPU thermal protection at 92 degree C
2
PH203 under CPU botten side :
(92 degree = 7.3K ohm) => VCIN0_PH = 1V 2014/03/24 update PH203 chang
(56 degree = 26.11k ohm) => VCIN0_PH = 2V Common part SL200002H00
3.3*7.3/(7.3+16.9)=1
3.3*26.11/(26.11+16.9)=2
4 4
ECAGND <37>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V4DA2 LAA131P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, September 17, 2014 Sheet 43 of 55
A B C D
A B C D
Vgs = 20V
max Power loss 0.22W for 90W;0.12W for 65W system
CSR rating: 1W
VACP-VACN spec < 80.64mV
www.laptopblue.vn
1
PQ301 D
2 Vds = 60V B+
G Id = 250mA
S 2N7002KW_SOT323-3
3
PR302 Rds(on) = 35mohm max
PR301
1 2 1 2 Vgs = 20V
1 1
1M_0402_5% 3M_0402_5% Vds = 30V
ID = 7.7A (Ta=70C)
Need check the SOA for inrush 2014/03/24 update PL301 chang
VIN MDU1512RH_POWERDFN56-8-5 PQ303 Common part SH00000YG00
PQ302 P1 AON7506_DFN33-8-5 P2 PR303 PQ304
1 1 0.02_1206_1% EMI@ PL301 CHG_B+ AON7506_DFN33-8-5
2 2 1UH_NRS4018T1R0NDGJ_3.2A_30% 1
5 3 3 5 1 4 1 2 2
Isat: 4A 5 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2 3
DCR: 27mohm
0.1U_0402_25V6
4
4
1
1
0_0402_5%
PC302
PC303
PC304
@EMI@ PC306
@EMI@ PC305
2200P_0402_50V7K
0.01U_0402_50V7K
@ PR304
4
1
1 VIN
PC301
PC308
2
2
2
VF = 0.5V
2
2
3
2
PD301
BQ24725A_ACDRV_1 BAS40CW_SOT323-3
0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PC311
PR306
PC309
Vgs = 20V
1 1
1 2
10_1206_1%
PC310 4.12K_0603_1%
change PQ301 AON6414AL to MDU1512 0.047U_0402_25V7K Vds = 30V
PR309
2
PC307 1 2
change PQ303 AON6414AL to AON7506 0.1U_0402_25V6
ID = 7A (Ta=70C)
VF = 0.37V
5
change PQ304 AON6414AL to AON7506
2.2_0603_5%
PR310
change PQ306 AON7408L to AON7406L PD302
AON7408L_DFN8-5
BQ24725A_VCC2
20140702 RB751V-40_SOD323-2 Support max charge 3.5A
PQ305
Rshort@
PR311 Power loss: 0.245W
BQ24725A_REGN
BQ24725A_BST 2
2
change PC302 0.1u to0.01u DH_CHG 1 2 4 2014/03/24 update PL302 chang CSR rating: 1W
BQ24725A_LX
4.12K_0603_1%
4.12K_0603_1%
PR308
1 2
DH_CHG
PL302 PR312
change PC302 00.1u to0.1u
3
2
1
1U_0603_25V6K 1 2 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 0.01_1206_1%
BQ24725A_ACP
BQ24725A_ACN
20140804 BQ24725A_LX 1 2 CHG 1 4
2
PC313
5
1U_0603_25V6K 2 3
20
19
18
17
16
PU301
CSON1
CSOP1
4.7_1206_5%
AON7406L_DFN8-5
BTST
PHASE
HIDRV
VCC
REGN
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
@EMI@
PR313
PC318
21
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC314
PC315
1
1
PQ306
1 15 DL_CHG 4
ACN LODRV
PC316
PC317
2
@EMI@
2
2
2 14
680P_0402_50V7K
ACP GND PR314
3
2
1
2
1
@EMI@
10_0603_1%
PC321
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PR315
2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN PC320
0.1U_0603_16V7K
+3VLP 1 2 BQ24725A_ACOK 5 11 BQ24725A_BATDRV
PR316 100K_0402_1% ACOK BATDRV
ACDET
IOUT
SDA
SCL
ILIM
**Design Notes**
<37,8> ACIN #For 65 /90W system, 3S1P/3S2P battery
6
10
BQ24735RGRR_QFN20_3P5X3P5 +3VLP Maximum Charging current 3.5A
Battery discharge power 55W.
BQ24725A_ACDET
BQ24725A_ILIM 1 2
#Register Setting
BQ24725A_IOUT
PR317
3
Module model information 3
100K_0402_1%
316K_0402_1% 1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
0.01U_0402_25V7K
1
2. 0X12 bit3 set 1 (default 0) to enable turbo boost function
PC322
PR319
1
PR318
BQ24735A_V1.mdd 422K_0402_1% 3. Disable turbo when AC only
VIN 1 2 #Circuit Design
2
BQ24735A_V2.mdd 1. ACOK,ILIM pull high voltage need base on 3/5V enable control
2
EC_SMB_CK1 <37,43>
with PR222 for ACDET setting)
100P_0402_50V8J
1
1
PC323
EC_SMB_DA1 <37,43>
#Protect function
2
Rshort@ PR321
1. ACOVP : ACDET voltage > 3.14V
2
0_0402_5%
1 2 2. Charger timeout : No communication within 175s(default)
ADP_I <37,43>
3. ACOC : 3.33 X Input current DAC setting(default)
4. CHGOCP : 3/4.5/6A based on current current setting
1
Vin Dectector
PC325 @ 5. BATOVP : 103-106%
Min. Typ Max. 100P_0402_50V8J 6. BATLOWV : 2.5V
2
ILIM = 3.3*100/(100+107)/20/0.02
= 3.986 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z4DBH M/B LA-B731P Schematic
Date: Wednesday, September 17, 2014 Sheet 44 of 55
A B C D
5 4 3 2 1
PR402
www.laptopblue.vn 499K_0402_1%
1 2
B+
1
150K_0402_1%
SY8208B_V1.mdd
PR403
2
EN1 and EN2 dont't floating
PU401
D B+ EMI@ PL401 7 1 3V5V_EN PC425 PR411 D
HCB2012KF-121T50_0805 IN EN1 0.01U_0402_25V7K 1K_0402_1%
1 2 3V_VIN 8 3 1 2 1 2
IN EN2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
Rshort@ PR401 PC403
@EMI@ PC401
EMI@ PC402
PC404
PC405
6 BST_3V 1 2 1 2
BS
1
0_0603_5% 0.1U_0603_25V7K
@ PL402
2
10 LX_3V 1 2
LX +3VALWP
@EMI@ PR404
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
4.7_1206_5%
2 5
PG LDO +3VLP
PC406
PC407
PC408
PC409
1
100K_0402_5%
SPOK <37> SY8208BQNC_QFN10_3X3
2
1
PC410
PR413
4.7U_0603_6.3V6M
13V_SN 2
Check pull up resistor of SPOK at HW side
680P_0603_50V7K
@EMI@ PC411
3.3V LDO 150mA~300mA
Vout is 3.234V~3.366V
2
@PR405
@ PR405 +3VALW
4.3K_0402_5% TDC=8A
1 2
+3VLP
PR406 @ PJ401
2.2K_0402_5% +3VALWP 1 2 +3VALW
C 1 2 1 2 C
<37> EC_ON JUMP_43X118
Rshort@ PR407
1 2
<37,43> MAINPWON 0_0402_5%
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR408
PC412
2
B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
Vout is 4.998V~5.202V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU402 TDC=8A
8 1 3V5V_EN PC426 PR412
IN EN1 6800P_0402_25V7K 1K_0402_1%
1
1
PC413
PC414
EMI@ PC415
@EMI@ PC416
3 1 2 1 2
B EN2 Rshort@ PR409 B
6 BST_5V 1 2 1 2
2
@ BS PC417
0_0603_5% 0.1U_0603_25V7K
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3.3V 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT
1
@EMI@
4.7_1206_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PR410
2 7
PG LDO VL
1
PC418
PC419
PC420
PC421
PC422
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
@ PJ402
2
15V_SN 2
1
PC423
1 2
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
JUMP_43X118
2
680P_0603_50V7K
@EMI@
PC424
2
5V LDO 150mA~300mA
SY8208C_V1.mdd
www.laptopblue.vn
Pin19 need pull separate from +1.5VP.
If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
EMI@ PL501
HCB2012KF-121T50_0805
you can change from +1.5VP to +1.5VS. TDC 0.7A
B+ 1 2 1.35V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
22U_0805_25V6M
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
@EMI@ PC501
EMI@ PC502
@EMI@ PC510
PC503
PC504
DH_1.35V +0.675VSP
2
1 1
SW _1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC505
PC506
PC507
5
0.1U_0603_25V7K
16
17
18
19
20
2
PU501
2
PHASE
UGATE
BOOT
VLDOIN
VTT
21
PQ501 PAD
2014/03/24 update PL502 chang AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Common part SH00000YE00
14 2
PL502 PR502 PGND VTTSNS
1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 13.7K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS RT8207MZQW _W QFN20_3X3 GND
1
1U_0603_10V6K
5
1 2 12 4 VTTREF_1.35V
@EMI@ PR503 PR504 VDDP VTTREF
4.7_1206_5% 5.1_0603_5%
330U_2.5V_M
1
1 2 VDD_1.35V 11 5
1 2
+5VALW VDD VDDQ
+1.35VP
1
+
PGOOD
PC509
PQ502
ESR=17m ohm AON7506_DFN8-5 4 PC511
TON
1
@EMI@ PC513 0.033U_0402_16V7K
FB
S5
S3
2
2 680P_0402_50V7K PC512
+5VALW
2
1U_0603_10V6K
10
6
1
2
3
FB_1.35V
TON_1.35V
EN_0.675VSP
EN_1.35V
2014/08/18 update PC509 chang PR506
8.2K_0402_1%
2 Common part SF000006S00 MOSFET: 3x3 DFN PR507 1 2 +1.35VP 2
887K_0402_1%
H/S Rds(on): 27mohm(Typ), 34mohm(Max) 1.35V_B+ 1 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
1
L/S Rds(on): 9.8mohm(Typ), 15.8mohm(Max) Rshort@ PR509 PR508
Idsm: 13.5A@Ta=25C, 11A@Ta=70C 0_0402_5% 10K_0402_1%
1 2
<36,37,41> SYSON
2
Mode Level +0.675VSP VTTREF_1.35V
Choke: 7x7x3 @ PJ501
S5 L off off
1
@ PC514 +1.35VP 1 2 +1.35V
S3 L off on Rdc=8.3mohm(Typ), 10mohm(Max) 0.1U_0402_10V7K 1 2
S0 H on on JUMP_43X118
2
@ PJ502
Switching Frequency: 285kHz 1 2
Note: S3 - sleep ; S5 - power off Ipeak=10A Rshort@ PR510 1 2
0_0402_5% JUMP_43X118
Iocp~13A 1 2
OVP: 110%~120% <15> DDR_VTT_PG_CTRL @ PJ503
VFB=0.75V, Vout=1.355V 1 2
+0.675VSP 1 2 +0.675VS
1
MOSFET footprint: SIS412DN @ PC515 JUMP_43X39
0.1U_0402_10V7K
Vpro - 1.05VM
2
@
PJ531
1 2
Vpro@ PC531 +1.05VMP 1 2 +1.05VM
22U_0805_6.3VAM
JUMP_43X79
1 2
3
STATE S3 S5 1.35VP VTT_REFP 0.675VSP @
Imax= 2A, Ipeak= 3A 3
+3VALW
PJ532
1
JUMP_43X79
2
FB=0.6V
S0 Hi Hi On On On 1 2
2014/03/24 update PL531 chang
Vpro@ PL531
Off 1UH_PH041H-1R0MS_3.8A_20% Common part SH00000YG00
S3 Lo Hi On On (Hi-Z) <8> PM_APW ROK 4 3 LX_1.05VMP 1 2
IN LX +1.05VMP
1 2 5 2
Vpro@ PC532
68P_0402_50V8J
S4/S5 Lo Lo Off Off Off +3VALW PG GND
1
10K_0402_5% 6 1
22U_0805_6.3VAM
22U_0805_6.3VAM
FB EN
1
(Discharge) (Discharge) (Discharge) Vpro@ PR531
Vpro@ PC533
Vpro@ PC534
Vpro@ PU531
2
2014/06/09 Change PR531 100k to Vpro@ PC624 SY8032ABC_SOT23-6 @EMI@ PR532 Vpro@ PR533
2
2
4.7_0603_5% 7.87K_0402_1%
Note: S3 - sleep ; S5 - power off 10k for CL_RST1# high > 500us .1U_0402_16V7K
2
after APWROK high Rup
2
Rshort@ FB_1.05VMP
PR534
<41,8> PM_SLP_A# 1 2 +1.05VMP_ON
1
0_0402_5% @EMI@ PC536
0.1U_0402_16V7K
1
@Vpro@ PC535
2
1
2
2
2
4 4
Note:
Vout=0.6V* (1+Rup/Rdown)
When design Vin=5V, please stuff snubber
to prevent Vin damage Vout=1.0722
Security Classification Compal Secret Data
Issued Date 2012/06/19 Deciphered Date 2012/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35VP/0.675VSP/1.05VMP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V4DA2 LAA131P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, September 17, 2014 Sheet 46 of 55
A B C D
5 4 3 2 1
www.laptopblue.vn
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
Rshort@
PR631
<37,38,41,48> SUSP#
1 2
0_0402_5%
1
D @ PC631 D
1M_0402_1%
0.22U_0402_10V6K
2
PR632
2
PR633 PC632
4.7_1206_5% 680P_0603_50V7K
EMI@ PL601 1 2 SNB_1.05V1 2 +1.05VSP PJ601
HCB2012KF-121T50_0805 PU601 1 2
1 2 +1.05VS_VTT
1 2 B+_1.05V 8 1 TDC 8A
B+ IN EN
PC633
10U_0805_25V6K
10U_0805_25V6K
Rshort@ PR634 0.1U_0603_25V7K 2014/03/24 update PL602 chang JUMP_43X118 @
6 BST_1.05V 1 2 1 2
2200P_0402_50V7K
0.1U_0402_25V6
PL602
LDO_1.05V BS Common part SH00000YE00
1
EMI@ PC634
@EMI@ PC635
PC636
PC637
1UH_VMPI0703AR-1R0M-Z01_11A_20%
9
GND LX
10 LX_1.05V 0_0603_5% 1 2
+1.05VSP
2
1
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
15.4K_0402_1%
1
330P_0402_50V7K
1
1
PR636
PR635 @ 4 FB_1.05V
FB
PC638
PC639
PC640
PC641
PC642
@ PC643
0_0402_5%
ILMT_1.05V3 7
Rup
+3VALW
2
2
ILMT BYP
4.7U_0603_6.3V6K
2
ILMT_1.05V 1 2 VCCST_PWRGD 2 5 LDO_1.05V
+3VS
4.7U_0603_6.3V6K
PG LDO
1
PC610
PR639
PC609
PR637 10K_0402_5% SY8208DQNC_QFN10_3X3
0_0402_5% FB = 0.6V
1
Rshort@
2
PR638
2
C
<11,37> VCCST_PWRGD
Rdown 20K_0402_1%
C
2
Pin 7 BYP is for CS.
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.062V
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V4DA2 LAA131P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 47 of 55
5 4 3 2 1
5 4 3 2 1
1
@VGA@ PC701
1M_0402_1% +1.5VS_DIS @ PJ701
0.22U_0402_10V6K
2
VGA@ PR702 1 2 +1.5VSDGPU
1 2
2
The current limit is set to 8A, 12A or 16A when this pin JUMP_43X118
is pull low, floating or pull high
@EMI@ PR703 @EMI@ PC702
4.7_1206_5% 680P_0603_50V7K
VGA_EMI@ PL701 1 2SNB_1.5V_DIS
1 2
HCB2012KF-121T50_0805 PU701 VGA@ VGA@ VGA@
1 2 B+_1.5V_DIS 8 1 PR704 PC705 TDC 8A
B+ IN EN 0_0603_5% 0.1U_0603_25V7K 2014/03/24 update PL702 chang
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
VGA_EMI@ PC706
@VGA_EMI@ PC703
VGA@ PC707
VGA@ PC704
6 1
BST_1.5V_DIS 2 1 2 VGA@ PL702
1 BS Common part SH00000YE00
1
1UH_VMPI0703AR-1R0M-Z01_11A_20%
9 10 LX_1.5V_DIS 1 2
GND LX
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
15.4K_0402_1%
VGA@ PR705
+1.5VS_DIS
330P_0402_50V7K
1
1
LDO_1.5V_DIS 4 FB_1.5V_DIS
Rup
FB
VGA@ PC708
VGA@ PC709
VGA@ PC710
VGA@ PC711
VGA@ PC712
ILMT_1.5V_DIS 3 7
+3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
2
1
VGA@ PC714
4.7U_0603_6.3V6K
2 5 LDO_1.5V_DIS
PG LDO
1
VGA@ PC713
@VGA@
1
PR706 SY8208DQNC_QFN10_3X3
0_0402_5% FB = 0.6V
1
2
2
ILMT_1.5V_DIS PR709 VGA@
Rdown 10K_0402_1%
2
1
C
PR708 Pin 7 BYP is for CS.
VFB=0.6V C
B
+1.35V 9.31k 10k B
+3VS +5VALW
+1.2V 7.15K 10k 105K
1
PC715
1
1U_0402_6.3V6K
JUMP_43X79
2
@ PJ702
2
@ PJ703
+1.5VSP 1 2 +1.5VS
2
1 2
JUMP_43X79
PC716 PU702
1
4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
6
5 VCNTL 3
2
1.54K_0402_1%
1 2 8
<37,38,41,47> SUSP# EN
1
7 2
GND
POK FB
PR712
0_0402_5% PC717
1
0.1U_0402_16V7K
0.01U_0402_25V7K
Rup
2
1
PC719
@ PR713 PC718
1
47K_0402_5% 22U_0805_6.3VAM
2
@
2
PR714
A
1.74K_0402_1%
Vout=0.8V* (1+Rup/Rdown) A
Rdown
Vout=1.508
2
15W @ PR845
90.9K_0402_1% Note: CPU_B+ EMI@ PL803
<11> VR_SVID_CLK 1 2 HCB2012KF-121T50_0805
PR845=113K
VR_SVID_ALRT#
=>Icc(max)=40A CPU_B+ 1 2
VR_SVID_DATA
B+
VR_SVID_CLK
2200P_0402_50V7K
0.01U_0402_50V7K
28W @ PR845 fsw=700KHz
10U_0805_25V6K
10U_0805_25V6K
1 1
EMI@ PC818
EMI@ PC825
33U_25V_M
33U_25V_M
<11> VR_ON 113K_0402_1% Height 8 mm
PRGM1
1
+ +
PC820
PC806
PC807
PR832
AON7518_DFN8-5
100u_SF000000I80
1
C C
PC824
1.91K_0402_1%
PQ801
1 2
2
PR844 2 2
2
0_0603_5% Height 6 mm
21
20
19
18
17
PU803 1 2 4
68u_SF000000W00
PAD
SCLK
ALERT#
SDA
PRGM1
<11,8> VGATE
PC833 VR_ON 1 16 LAGTE 2014/01/21 update PL804 change PL804
3
2
1
1000P_0402_50V7K VR_ON LGATE
+CPU_CORE
1 2 Common part SH000011H00 0.22UH 20% FDUE0640J -H 25A
2 15 PHASE 1 4
PR854 PGOOD PHASE
@EMI@ PR842
102K_0402_1% 2 3
4.7_1206_5%
1
1 2 IMON 3 14 UAGTE
IMON UGATE PR849 PC832 28W @
5
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K PQ803 PQ802
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
1
VR_HOT_1# 4 13 BOOT 1 2 1 2
<37> VR_HOT# PH804 VR_HOT# BOOT PR838
2
470K_0402_5%_ TSM0B474J4702RE PR834
47P_0402_50V8J
3.65K_0603_1%
Over temperature protection: 1 2 1 2 NTC 5 12
NTC VCC +5VS
1
PC838
4 4
@EMI@ PC829
680P_0603_50V7K
OTP Setting: 100C active
2
1
3.83K_0402_1%
Pin5 (NTC) voltage <0.88V, Protect PR836 COMP 6 11 PRGM2
2
COMP PRGM2
1
27.4K_0402_1% ISUMN
Pin5 (NTC) voltage >0.92v, recovery
ISUMP
2
1 2 PC834
RTN
3
2
1
3
2
1
0.1U_0402_25V6
124K_0402_1%
FB
2
1
PR840
2013/10/28 update PH804 chang
7
10
B B
2
FB
ISUMN
ISUMP
Note:
PR833
10_0402_1%
6800P_0402_25V7K
2
Vboot = 1.7V
2
PR851
1.27K_0402_1%
1
10M_0402_5%
390P_0402_50V7K
1
PR852
330P_0402_50V7K
2
1
@ PC830
PR835
10K_0402_1%
RC Match
2
PC822
Droop
2
2
1
1
28W @ PR839 15W @
1.58K_0402_1% PC828 PC827 PR853
@ 0.022U_0402_16V7K 0.1U_0402_16V4Z 11K_0402_1%
2
2
28W @ PR850
499_0402_1%
1
<11> VCC_SENSE OCP Setting
28W @ PC828 PH803
15W: 38A 0.022U_0402_16V7K 10KB_0402_5%_ERTJ0ER103J
28W: 48A
@ PC839 2013/10/28 update PH803 chang
2
1 2
0.082U_0402_16V7K
330P_0402_50V7K 1 2
1
A 475_0402_1% A
@ PC821 @ PR847
2
PC836
1 2 1 2 1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
Local sense put on HW site AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, September 17, 2014 Sheet 49 of 55
5 4 3 2 1
5 4 3 2 1
www.laptopblue.vn +CPU_CORE
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
PC1015
1
1
PC994
PC996
PC997
PC999
PC1016
D D
2
@ @
@
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PC998
PC1000
PC1017
PC1018
PC1019
PC995
2
2
@
@
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PC934
PC935
PC936
PC937
PC938
PC939
2
2
@ @ @
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
C C
1
PC946
PC947
PC948
PC949
PC950
PC951
2
2
@
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
@ PC1020
PC1021
@ PC1022
@ PC968
PC969
PC967
2
2
CPU LL=2m ohm dedign 22uF *18, 22uF*12(un-pop)
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V4DA2 LAA131P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 50 of 55
5 4 3 2 1
8 7 6 5 4 3 2 1
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting Different VGA Chip (different EDP-Peak Current) need select different solution
www.laptopblue.vn
Rt=Rrefadj // (Rboot+Rref2) Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Module model information:
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] I_ripple=(19-0.9)*0.9/ VGA Chip N14P-GV N14P-GV2 N14M-GS N14M-LP N14P-LP N14P-GE N14P-GS N14P-GT N15S-GT N15V-GM
RT8813A_V1A for IC module (304.89Khz*0.36u*19)=7.811A
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
RT8813A_V1B for SW module OpenVReg Configurations Config B Config B Config B Config B Config B Config B Config B Config B Config B Config C
H Vout=Vmin+N*Vstep OCP=54A/2=27A per phase H
Vstep=(Vmax-Vmin)/Nmax Ivalley=27A-7.811A/2=23.1A Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W 18W 18.16W
PWM-VID Spec and component Values Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W 25W 24.72W
H-side MOS:AON6552 L-side MOS:AON6554
PWM-VID Spec Config B Config C Config D Rds(on): Rds(on): EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A 31A 29.2A
5.6mohm@Vgs=10V 3.2mohm@Vgs=10V
Vmin 0.6V 0.65V 0.9V 6.7mohm@Vgs=4.5V 3~3.8mohm@Vgs=4.5V EDP-Peak at Tj=102C 35A 55A 45A 35A 35A 40A 60A 75A 60A 44.3A
Vmax 1.2V 1.15V 1.15V Id :20A@Ta=25 degC Id :85A@Ta=25 degC
Vboot 0.9V 0.9V 1.028V Istep max (Evaluation) 15A 27A 25A 20A 14A 12A 31.5A 35A
Voltage step 6.25mV 25mV 12.5mV Choke: 0.22uH (Size:7*7*4)
Rdc=0.97mohm +-5% OCP Setting Current 42A 66A 54A 42A 42A 48A 72A 90A 72A 54A
N of Voltage level 96 20 20
G
Heat Rating Current=34A G
Rrefadj PR1206 20K 39K 27K Saturation Current=25A Rocset 8.96K 12.45K 10.7K 8.96K 8.96K 9.83K 8.3K 9.39K 13K 10.2K
Rref1 PR1208 20K 30K 7.5K
Recommendation 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H2L 2phase 1H2L 2phase 1H1L 2phase 1H1L
Rboot PR1233 2K 3K 0 C=3*330uF (9mohm)=990uF
Rref2=PR1209 PR1209 18K 24K 6.2K Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV 6mohm * 3 4.5mohm * 3
+PR1212 Polymer Cap (330uF) 6mohm * 2 9mohm * 3 9mohm * 3 6mohm * 2 6mohm * 2 6mohm * 2 (L=0.22uH) (L=0.15uH)
PR1212 0 3K 1.74K
C PC1210 2.7nf 1.8nf 5.6nf
@VGA@ PR1202
Or OSCON (390uF) 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 NULL NULL GT@ GM@
N15S-GT N15V-GL N15V-GM 1K_0402_5%
1 2 +3VS
PWM VID and Output voltage control GM@ PR1208 GL@ PR1208 GM@ PR1206
7.5K_0402_1% 30K_0402_1% 27K_0402_1%
1.Boot mode
F 1 2 DGPU_VID <18> F
2.Standby mode (don't support) GPU_B+
3.Normal mode @VGA@ PR1203
0_0402_1% Operation phase Number PSI Voltage setting
GL@ PR1206
39K_0402_1% 1 phase with DEM 0V to 0.8V VGA_EMI@ PL1201
1
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2
1
2K_0402_5% 20K_0402_1% 1 2 PSI <18> 1
U2_BOOT1 2 VGA@
PC1223
VGA_EMI@ PC1204
VGA@ PC1205
VGA@ PC1206
1 2 1 2
GM@ PR1209 GL@ PR1209 0_0402_1% PQ1201
1 +VGA_CORE
2
AON6552_DFN5X6-8-5
5
6.2K_0402_1% 24K_0402_1% GC6@ PR1227 Pull high on HW side
GT@ PR1209
18K_0402_1%
1
@VGA_EMI@
2700P_0402_50V7K
0.01U_0402_16V7K
E E
1800P_0402_50V7K 1 2 3VSDGPU_MAIN_EN <18,41> 0.22U_0603_25V7K
PC1208
2 EDP-Peak 60A
GPU_VID
1
1
0.22U_0402_6.3V6K
1 2 U2_UGATE1 1 2 4
2
1
NOGC6@ PR1226 DGPU_PWR_EN <41,8,9> VGA@ PR1211
VGA@ PC1222
2
2 0_0603_5%
@VGA@
GPU_REFADJ
GT@ PR1212
U2_BOOT1
1
U2_UGATE1
2
1.74K_0402_1% 3K_0402_1% For NV power sequence change VGA@ PL1202
GPU_PSI
GPU_EN
3
2
1
GM@ PC1210 PR1227 and PC1222 20140401 0.22UH 20% FDUE0640J -H 25A +VGA_CORE
5600P_0402_50V7K 1 4
2
GPU_FBRTN U2_PHASE1
2 3
VGA@ VGA@
6
5
PU1201 PQ1202
AON6554_DFN5X6-8-5
1
VGA@ PR1201 @VGA_EMI@
UGATE1
BOOT1
VID
PSI
EN
REFADJ
2
<19> VSSSENSE_VGA 0_0402_1% @VGA@ GPU_VREF 8 23 U2_LGATE1
1 2 PC1201 VREF LGATE1 @VGA_EMI@
1
2 0.01UF_0402_25V7K GPU_TON 9 22 U2_PWM3 U2_PWM3 PC1211
13K_0402_1%
TON GND/PWM3 GM@ PR1216 GL@ PR1216 680P_0603_50V7K
GT@ PR1216
3
2
1
1 2 GPU_FBRTN 10 21 10.2K_0402_1% 10.2K_0402_1%
2
RGND PVCC
Rocset
1
11 20 U2_LGATE2
TALERT/ISEN2
2
100_0402_1% PC1212 VSNS LAGTE2
TSNS/ISEN3
VCC/ISNE1
SS PHASE2
UGATE2
PGOOD
@VGA@ PR1217
BOOT2
<19> VCCSENSE_VGA
1 2 GPU_FB
GND
0_0402_1%
@VGA@ PC1213 RT8813AGQW_WQFN24_4X4
25
13
14
15
16
17
18
1 2 Css 0.01U_0402_16V7K
+VGA_CORE 1 2
VGA@ PR1218 GPU_B+
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3
C 100_0402_1% C
GPU_HOT#
U2_UGATE2
VGA_PWROK
2.2_0603_5%
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
U2_BOOT2 1 2 PQ1203
PC1217
PC1218
@VGA_EMI@
AON6552_DFN5X6-8-5
5
PC1215
VGA_EMI@
1
1
PC1203
VGA@ PC1214
0.22U_0603_25V7K
2
GPU_VREF 2
VGA@
VGA@
1. VSNS Soft-Start time (Internal) is 0.7ms (PC1213 un-pop) 1 2 4
U2_UGATE2
Tss=(Css*Vrefin)/Iss+2.3ms
=0.01U*0.9V/5uA+2.3ms=4.1ms (PC1213 pop) VGA@ PR1223
18.7K_0402_1%
1
+3VS 0_0603_5%
VGA@ PL1203
PR1229
2013/10/28 update PH1201 chang
3
2
1
VGA@
U2_PHASE2 1 4
Common part SL200002E00
VGA@ PR1222
10K_0402_1%
B 2 3 B
5
PQ1204 @VGA_EMI@
1U_0402_6.3V6K
(VGPU_VREF-VTSNS)/PR23=VTSNS/Rth
2
AON6554_DFN5X6-8-5
1
+5VS PR1230
1
4.7_1206_5%
VGA@
VGA@ PH1201
PC1219
VGA_PWROK <18>
T_min T_typical T_max
2
VGA@ U2_LGATE2 4
1 2
PR1221=18.7K 96.73C 100C 103.1C PR1224 @VGA_EMI@
2.2_0603_5% PC1220
1 2 680P_0603_50V7K
3
2
1
2
PR1221=13K 106.38C 110C 113.4C VGA@
PR1225
1
VGA@
+3VS 1 2 PC1221
1U_0402_6.3V6K
2
A
100K_0402_1% A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/19 Deciphered Date 2012/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z4DBH M/B LA-B731P Schematic
Date: Wednesday, September 17, 2014 Sheet 51 of 55
8 7 6 5 4 3 2 1
5 4 3 2 1
PC1306
PC1307
PC1308
PC1309
PC1310
PC1311
PC1312
PC1313
PC1314
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
D
2014/08/18 update PC1302 & PC1304 chang D
Common part SGA00009S00
2
2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1 1 N15x 2013/12/10
330U_D2_2V_Y
330U_D2_2V_Y
+ + Under
VGA@ PC1302
VGA@ PC1304
4.7uF_0603_10pcs
2 2 1uF_0402_4pcs
Near
47uF_0805_1pcs
47U_0805_6.3V6M 22uF_0603_1pcs(2PCS unpop)
4.7uF_0805_5pcs
1
VGA@ PC1342
N15x2013/10/17
2
+VGA_CORE Under
4.7uF_0603_15pcs
Near VGA Core 1uF_0402_8pcs
C Near C
47uF_0805_0pcs
22uF_0603_9pcs(2PCS unpop)
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7uF_0805_5pcs
1
PC1326 @
PC1327 VGA@
PC1328 @
VGA@ PC1335
VGA@ PC1336
VGA@ PC1337
VGA@ PC1338
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
N15x2013/10/07
Under
2
4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_9pcs(2PCS unpop)
4.7uF_0805_5pcs
N15x2013/10/02
Under
B B
4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_14pcs
change 0805 to 0603 20140206 4.7uF_0805_5pcs
N14x
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
VGA@ PC1341
VGA@ PC1346
VGA@ PC1343
VGA@ PC1344
VGA@ PC1345
Under
1
1
4.7uF_0603_10pcs
0.1uF_0402_4pcs
2
2
Near
47uF_0805_1pcs
22uF_0805_1pcs
4.7uF_0805_5pcs
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z4DBH M/B LA-B731P Schematic
Date: Wednesday, September 17, 2014 Sheet 52 of 55
5 4 3 2 1
5 4 3 2 1
www.laptopblue.vn
D D
(PU801)
VR_ON TPS51622RSM
+CPU_CORE
QFN32_4X4 Page 49
(PU1101)
VGA_ON_R ISL62883CHRTZ
+VGA_CORE
TQFN40_5X5 Page 52
C C
ADAPTER SYSON (PU501)
RT8207MZQW +1.35V
DDR_VTT_PG_CTRL
WQFN20_3X3 Page 46 +0.675VS
SUSP# (PU601)
BATTERY
SY8208DQKC +1.05VSP
QFN10_3X3 Page 47
B+
(PU701)
VGA_PG SY8208DQKC
+1.5VS_DIS
CHARGER QFN10_3X3 Page 48
(PU1001)
B
VGA_PG SY8208DQKC B
+0.95VSDGPU
QFN10_3X3 Page 51
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Z4DBH M/B LA-B731P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 17, 2014 Sheet 53 of 55
5 4 3 2 1
5 4 3 2 1
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
01 Design Change. Design Change for common part circuit 0.2 46 Delete PR505 resister 2014/03/24 DVT
D D
Design Change. Design Change for CPU transient test 0.2 49 Change PR833, 1.91k ohm to 3.65k ohm
02
Design Change. Design Change for CPU transient test 0.2 49 Change PR835, 4.99M ohm to 10M ohm
03
Design Change. Design Change for CPU transient test 0.2 49 Change PR850, 392 ohm to 475 ohm
04
Design Change. Design Change for CPU transient test 0.2 49 Change PR852, 2.61k ohm to 10k ohm
05
Design Change. Design Change for CPU transient test 0.2 49 Change PR854, 121k ohm to 102k ohm
06
Design Change. Design Change for CPU transient test 0.2 49 Change PC828, 0.033u F to 0.022u F
07
Design Change. Design Change for Efficiency test 0.2 47 Change PC639, 47u F to 22u F
08
Design Change. Design Change for Efficiemcy test 0.2 47 Change PC640, 47u F to 22u F
C
09 C
Design Change. Design Change for Efficiemcy test 0.2 47 Add PC643 22u F
10
Design Change. Design Change for 1.05VMP circuit 0.2 46 Change PR531 100k to 10k for CL_RST1# high > 500us after APWROK high
11
Design Change. Design Change for charger circuit 0.2 44 Change PQ302 AON6414AL to MDU1512
12
Design Change. Design Change for charger circuit 0.2 44 Change PQ303 AON6414AL to AON7506
13
Design Change. Design Change for charger circuit 0.2 44 Change PQ304 AON6414AL to AON7506
14
Design Change. Design Change for charger circuit 0.2 44 Change PQ306 AON7408 to AON7406
15
Design Change. Design Change for charger circuit 0.2 44 Change PC302 0.1uF to 0.01uF
16
B Design Change. Design Change for charger circuit 0.2 44 Change PC302 0.01uF to 0.1uF B
17
Design Change. Design Change for 3VALW 5VALW 0.2 45 Del PR405 4.3k ohm
18
Del PQ101, PD103, PD104, PR107, PR109, PC107, PC106, PR108, PR105,
19 Design Change. Design Change for DCIN circuit 0.2 42 PU101, PC105, PR104, PR109
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V4DA2 LAA131P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, September 17, 2014 Sheet 54 of 55
5 4 3 2 1
5 4 3 2 1
VIN
MOS
B+
PU401
EN1 www.laptopblue.vn
+3VALWP
+3VLP
1
+3VALW_PCH
PU402
PJ401 2
+5VALWP
2
+1.05VM +3VM
D D
+3VALW_PCH +3VALW_PCH
+3VLP
RSMRST
PCH_RTCRST#
3 PBTN_OUT#
RTCRST
PM_SLP_S5# 4
SLP_S5
PM_SLP_S4# 5
SLP_S4
PM_SLP_S3# 7
SUSP# SLP_S3
PM_SLP_A#
8 VGA_ON 6 SLP_A
C C
SYSON PCH_PWROK 9
APWROK
EC
PCH_PWROK VccCore(PCH) +1.05VS_VTT
VCCST +1.05VS_VTT
SYS_PWROK
VDDQ +1.35V
B+ VCCST_PWRGD DDR_PG_CTRL DDR_VTT_PG_CTRL
SM_PG_CNTL1 UU15
SUSP# +1.5VS
PU702
VR_ON
VR_EN
+CPU_CORE
B+ PU801
VGATE
VR_READY
SUSP# +1.05VS_VTT
PU601
+CPU_CORE
VCCIN
+3VALW +5VALW
B B
PLT_RST#
HasWell ULT PLT_RST# 10
+3VS
SUSP# +3VALW
U48
+5VS
PM_SLP_A# +3VM
B+ U56
SYSON +1.35V
PU501
DDR_VTT_PG_CTRL +3VALW
+0.675V
PM_SLP_A# +1.05VM
PU531
A A
Title
Power Block
V4DA2
+RTCVCC (VccRTC)
AC insertion
(G3->S5)
Power On
(1st G3->S0) www.laptopblue.vn S3 entry S3 resume ← S5
+RTCVCC (VccRTC)
PCH_RTCRST#
PCH_RTCRST# (RTCRST#)
(RTCRST#)
+3VLP(VCCDSW3_3)
+3VLP
← 124us EC_ON
EC_O EC_ON
1
←2.93ms +5VALW 1
+5VALW
←2.93ms +3VALW
+3VALW
EC_O(PCH_I)
PCH_RSMRST#
EC_O(PCH_I) PCH_RSMRST#
239ms 236ms
EC_O(PCH_I) SUSP# 30.8ms 8.83ms SUSP#
+1.35V 21.7ms
← 297ms +1.35V
+1.05VS_VTT
31.4ms 248ms
9.93ms
← 250ms +1.05VS_VTT
← ← min 1ms
← 233ms
EC_O(PCH_I) VCCST_PWRGD 33ms 233ms 11.8ms
VCCST_PWRGD
+0.675VS
← ← <= 35us 20.2us
← 117ms 19.4ms ← 116ms
+0.675VS
← 116ms
PCH_O VR_ON 42ms max 100ns ← 116ms 18.9ms VR_ON
VGATE
42.6ms < 1us ← 274ms 19.9ms ←← 115ms
VGATE
3
4 4
Title
AC-sequcenc
A B C D E
5 4 3 2 1
www.laptopblue.vn
A4DBH
S4 entry S4 resume
+RTCVCC (VccRTC) +RTCVCC (VccRTC)
PCH_RTCRST# (RTCRST#) PCH_RTCRST#
D (RTCRST#) D
+3VLP +3VLP(VCCDSW3_3)
+5VALW +5VALW
+3VALW +3VALW
14.9ms 144ms
+5VS +5VS
52.1ms 171ms
+3VS +3VS
52.1ms 153ms
+1.5VS +1.5VS
40.5ms 185ms
+1.35V +1.35V
50.5ms 164ms
+1.05VS_VTT +1.05VS_VTT
53.7ms 154ms
EC_O(PCH_I) VCCST_PWRGD
VCCST_PWRGD
62.9ms 33.3ms
PCH_O DDR_PG_CTRL
DDR_VTT_PG_CTRL
B
63.7ms 34.1ms B
+0.675VS
+0.675VS
63.7ms 28.5ms
PCH_O VR_ON VR_ON
720us 44.5ms
+CPU_CORE +CPU_CORE
24.2ms VGATE
VGATE
EC_O(PCH_I) PCH_PWROK
160ms 24.2ms PCH_PWROK
SYS_PWROK
SYS_PWROK
13.6ms 28.8ms
CPU_O PLT_RST# PLT_RST#
A A
Title
<Title>
EVT2-->DVT www.laptopblue.vn
1.Page 40, Add Fan driver IC
2.Page 18, Remove Alert of GPU
3.Page 37,Update EC version to D
4.Page 28,R633,R665,R667,R668,R669,R671,R630,R631 change to 6.2ohm
5.Page 28,L15~L18 change to @EMI@
D 6.Page 31,Add RL18 for second source D
7.Page 35,Add CLP1 and CLP2 for 3G door
8.Page 37,R483 change to 15K for EC ID
9.Page 29,remove R746~R749,R757~R759
10.Page 11, Add CU157 and CU158 for ESD@
11.Page 37,Remove JDB1
12.Page 27,Add R762
13.Page 4,Update CPU BOM option
DVT-->PVT
1.Page 35, remove CLP1 and CLP2
2.Page 41,U48 change PN to SA00006U300
3.Page 18, GPU thermal SMBUS connect change to EC SMBUS_2
4.Page 18,DGPU_HOLD_RST# change to Pull-Low
5.QA3 and Q23 and Q25 change PN to SB00000PJ00
C 6.Page 36, D37 and D44 change to @ESD@ C
7.Page 37,EC Board ID, R483 change to 20K
8.Page 8, RU161 BOM structure change to UMA@
9.Page1,change DAZ number to DAZ18000300
10.Page 1,LS-A135P change to LS-B734P (Finger Print)
11.Page 29,Create X76PAR@ and X76TI@
12.Page 4, Add CPU BOM option
13.Page ,C520,C522,C523,C524,C525,C526 form SE068330K80 change to SE071330J80
14.Page9 ,RU176 change to mount
B B
A A
Title
<Title>