1 10212-102 K-Pbu

ENGINEERING DATA 1(57)
Uppgjord (även faktaansvarig om annan) - Prepared (also subject responsible if other) Nr - No.
EAB/RWI/KZ BENY 1/102 12-102 Uen

Dokansv/Godkänd - Doc respons/Approved Kontr - Checked Datum - Date Rev File
EAB/RWI/KZ (LIH) 2003-06-05 K
DESIGN RULES FOR PB AND PBA WITH HOLE- AND

SURFACE-MOUNTED COMPONENTS
Abstract
This standard contains design rules (physical implementation) for printed

boards (PB) and printed board assemblies (PBA) with hole and surface-
mounted components. In addition to this document further information such
as guideline and background information to this rules is found in design
guideline 3/102 12-102 under the same sections as in this document. Design
rules for mounting modes (BYZ), such as calculation of pad and hole size, is
also stated in 3/102 12-102. If no text is included in a section, then the
information is found in 3/102 12-102.
The electrical dimensioning of the conductive patterns regarding voltage,

current intensity, resistance and other signal characteristics is stated in
2/102 12-102.
Specific rules for microvia, such as hole and land size etc. are included in a
separate section.
General addition or deviations from this standard may exist and in such
cases these are stated in 170 05-216.
Application
This standard is to be applied within Ericsson for the design of new PB and
PBA according to the abstract.
/var/spool/gaprqueue/EDFS/FIU-3EDF32BB-OR
1/102 12-102 Uen

2003-06-05 K
Contents
1 GENERAL 10
1.1 DEVIATION 10
1.2 PRODUCT SAFETY 10
1.3 ENVIRONMENT 10
1.4 TERMINOLOGY 11
2 CHOICE OF EQUIPMENT PRACTICE 11
2.1 CHOICE OF COMPONENTS 11
2.2 CHOICE OF PB MATERIAL AND LAYER DESIGN 11
2.3 CHOICE OF MOUNTING TECHNIQUE 11
3 PRINTED BOARD (PB) 11
3.1 GENERAL 11
3.1.1 Documentation 11
3.1.2 Producibility 12
3.2 MATERIAL 12
3.2.1 General information 12
3.2.2 Halogen free materials 13
3.2.2.1 General information 13
3.2.2.2 Guidelines for the choice of material 13
3.2.3 Safety Requirements (UL requirements) 13
3.3 LAYER STRUCTURE 14
3.3.1 Board thickness 14
3.3.2 Layer design 15
3.4 DIMENSIONING OF CONDUCTIVE PATTERN 17
3.4.1 Electrical dimensioning 17
3.4.2 Copper thickness 17
3.4.3 Pattern classes 18
3.4.3.1 General 18
3.4.3.2 Conductor width 18
3.4.3.3 Conductor spacing 19
3.4.3.4 Land size, microvia excluded 20
3.5 DESIGN OF CONDUCTIVE PATTERNS 21
3.5.1 General 21
3.5.1.1 Orientation of conductors 21
3.5.1.2 Teardrops 21
3.5.1.3 Angles and small surfaces 21
3.5.1.4 Reducing of the pattern dimension 21
3.5.1.5 External layers 22
3.5.1.6 Internal layers 22
3.5.2 Soldering surfaces 23
3.5.2.1 Soldering surface surrounded by foil 23
3.5.2.2 Connection between soldering surface and land 24
3.5.2.3 Connection to soldering surfaces 25
3.5.3 Supplementary pattern 25
3.5.3.1 Supplementary pattern for external layers 25
3.5.3.2 Supplementary pattern in internal layers (signal layers) 25
3.5.4 Shielding 26
3.5.5 Screw connections 26
1/102 12-102 Uen

2003-06-05 K
3.6 HOLES 26
3.6.1 Hole information 26
3.6.2 Mechanically drilled 26
3.6.2.1 Plated-through holes 26
3.6.2.2 Hole dimension. 27
3.6.2.3 Hole diameter tolerances 27
3.6.2.4 Positions tolerance for hole - hole and hole - pattern 28
3.6.2.5 Hole spacing 28
3.6.2.6 Buried via 28
3.6.2.7 Blind via 29
3.6.2.8 Combination of holes/connection between layers 29
3.6.2.9 Plated-through holes in soldering surface 29
3.6.2.10 Blind via in soldering surface 29
3.6.2.11 Maximum hole density using thermal relief lands or
clearance holes 29
3.6.2.12 Not plated holes with lands 30
3.6.2.13 Inner location holes 30
3.7 DIMENSIONING OF MECHANICS CHARACTERISTICS30
3.7.1 Reference system 30
3.7.2 Fiducial marks 30
3.7.2.1 General 30
3.7.2.2 Design 31
3.7.2.3 Placement of fiducial marks for the board 31
3.7.2.4 Placement of fiducial marks for components 32
3.7.3 Spacing to edge and foil 32
3.7.3.1 Edge spacing to shielding foil 32
3.7.3.2 Edge spacing to conductive pattern 32
3.7.4 Outline 34
3.7.4.1 Tolerance for outline dimension 34
3.7.4.2 Radii 34
3.7.4.3 Panel 34
3.8 TESTING 35
3.8.1 General 35
3.9 SOLDER MASK AND OTHER TEMPORARY/
PERMANENT SOLDER RESIST COATINGS 36
3.9.1 Requirements on solder mask 36
3.9.2 Design of the solder mask 36
3.9.2.1 General 36
3.9.2.2 Openings for components holes 36
3.9.2.3 Openings for vias 37
3.9.2.4 Openings for soldering surface 37
3.9.3 Temporary solder resist coating (peelable mask) 38
3.9.4 Permanent, selectively applied, solder resist coating 38
3.10 SURFACE TREATMENT 38
3.10.1 Surface protection 38
3.11 MASK FOR SOLDER PASTE 38
3.11.1 General 38
3.11.2 Fiducial marks 38
3.11.3 Size of the opening 39
1/102 12-102 Uen

2003-06-05 K
3.12 MARKING 39
3.12.1 Position of product number and indicating
primary/secondary side 39
3.12.2 Space for other markings 40
4 MICROVIA 41
4.1 MATERIAL 41
4.2 LAYER DESIGN 41
4.3 HOLES 41
4.4 LAND SIZE 42
4.5 ADDITIONAL RULES FOR SPECIFIC COMPONENTS 43
4.5.1 Chip Scale Packages (CSP) 43
4.5.2 Design of thermal vias for components with
heat sink (pad) 43
4.5.2.1 Design with only plated-through holes 43
4.5.2.2 Design with micro-, buried via and plated-through holes 44
5 PRINTED BOARD ASSEMBLIES (PBA) 45
5.1 GENERAL 45
5.1.1 Documentation 45
5.1.2 Lead free solder 45
5.2 GENERAL POSITIONING RULES 46
5.2.1 Component and insulation spacing 46
5.2.2 Component positioning 47
5.2.3 Adjusting components 48
5.3 SURFACE MOUNTED COMPONENTS. REFLOW
SOLDERING 48
5.3.1 Size of the soldering surfaces and solder paste opening 48
5.3.2 Positioning rules 49
5.3.2.1 Plated-through holes under components 49
5.3.2.2 Heavy components 49
5.3.2.3 Components with large thermal mass 49
5.3.2.4 Number of components, primary/secondary side 49
5.3.2.5 BGA and CSP 49
5.3.3 Component spacing 50
5.3.4 Additional components 52
5.3.5 Rules for specific component types 52
5.4 HOLE- AND SURFACES MOUNTED COMPONENTS, 52
5.4.1 Size of the soldering surfaces, wave soldering 52
5.4.2 Component holes 52
5.4.2.1 Pin-in-paste 52
5.4.3 Positioning rules 53
5.4.3.1 General 53
5.4.3.2 Component direction for wave soldering 53
5.4.3.3 Plated-through holes under components 53
5.4.3.4 Spacing between plated-through hole and
component hole 53
5.4.3.5 Press fit 53
5.4.4 Component spacing 53
5.4.4.1 Surface mounting on the primary side 54
5.4.4.2 Surface mounting on the secondary side 54
1/102 12-102 Uen

2003-06-05 K
5.4.5 Vertical dimensioning 54

5.4.6 Fastening 54
5.5 BOW AND TWIST 54
5.6 DESIGN FOR TESTING 54
5.6.1 General 54
5.6.2 Specific rules. 55
5.7 MARKING 55
5.7.1 R-state 56
5.7.2 Other markings 56
6 REFERENCES 56
Supplementary documents
3/102 12-102 Uen Design guidelines for PB and PBA with hole-
and surface-mounted components
10/109 42-ROA+ Uen Document structure specification.

Printed board assemblies ROA, ROE, ROF,
ROJ etc. stored as a GenCAD file 130 35-
1/109 42-TVA+ Uen Document structure specification. Printed boards

TVA, TVE, TVF and others that is stored as
a container file
1/102 12-102 Uen

2003-06-05 K
Survey
This table gives an overview of the design rules in an abbreviated form. See
the reference paragraph for the full description of the rules.
Characteristic Rules Paragraph
Printed Board (PB)

According to IPC-4101, IPC/JPCA-4104 & IPC4562
Material 3.2
Material database. http://supplytech.ericsson.se/techserv/areas/standards/pb/
Safety requirements Flammability rating, normally V-1 or better is required. 3.2.3
(UL) Recognition according to UL 796 is normally not required but can be necessary
for some applications for the North American market.
Layer design The number of layer must be even 3.3.2

The voltage/ground layers must be placed symmetrically in relation to an
imaginary centre line
Layer pairs The pattern density for a layer pair must be similar, also the distribution of the
pattern within a layer must be even.
Preferences for different combinations of connection between layers, see fig. 3.3.2 b--d
Conductor width Class 53 54 55 56 3.4.3.2

(mm) Width. 0.150 0.125 0.10 0.075
Tol. +/-0.040 +/-0.040 +/-0.030 +/-0.030
Max Cu Plated/Not plated 55/35 um 50/35 um 50/35 um 50/35 um 3.4.2
The most common Cu-thickness see 3/102 12-102.
Conductor spacing Class 53 54 55 56 3.4.3.3

(mm) C Covered/covered 0.20 0.175 0.150 0.10
Tol. -0.050 -0.050 -0.050 -0.030
C1&C2 Open/open 0.250 for all classes, reflow soldering
C3 Covered/open 0.20 0.175 0.175 0.175
Lands
Annular ring (mm) Class 52 53 54 55 3.4.3.4
Via holes 0.275 0.225 0.20 0.150
Component holes ---”--- ---”--- ---”--- 0.20
Minimum annular ring where the holes start/end Class 55
on internal layers on other internal layers Class 54 or 55, due to
board thickness
Land design Non-functional lands on internal layers should not be used, with the exception
of start/stop layers.
Use teardrops for class 53--55 (u-via excluded). 3.5.1.2
Thermal relief lands Use thermal relief lands for component holes, press fit holes and for microvias 3.5.1.5/
that are placed in pads for BGA & CSP component. 3.5.1.6
1/102 12-102 Uen

2003-06-05 K
Edge spacing Edge spacing to shielding foil (no insulating requirements). Min 0.20 mm 3.7.3.1
Edge spacing to conductive pattern. Tol. class 1 2 3.7.3.2
D1 D3 D5 D1 (external layer, foil -- board edge) 0.70 mm 0.50 mm
D2 (internal layer, foil -- board edge) 1.15 mm 0.63 mm
D3 (external layer, foil -- non plated drilled hole edge 0.55 mm 0.38 mm
D4/D5 (class 52&53 internal layer, foil -- plated hole) 0.38 mm 0.38 mm
D4/D5 (class 54 internal layer, foil -- plated hole) 0.31 mm 0.31 mm
D2 D4
Conductive patterns
Orientation, conductors The main direction should be perpendicular between adjacent layers. 3.5.1.1
Angels & small areas Avoid angles less than 90 degrees and no angles less than 45 degrees. 3.5.1.3
Areas (with or without Cu) must not be smaller than 0.015 mm2.
Large Cu areas Cu areas larger than 25 x 25 mm should be sectioned. 3.5.1.5
Reducing of pattern If needed within a specific area, reduce the pattern in the following order: 3.5.1.4
Conductor width
Conductor spacing
Land dimension
Clearance holes The Cu-string (B1) between two clearance holes must not be less than the 3.5.1.6
Land in foil area conductor width for the layer.
C Conductor spacing C must not be less than 0.175 mm 3.5.1.5/.6
Pad (soldering surface)
C3 The width (B) and spacing (C3) shall not be less than the pattern class for the 3.5.2.1
board.
B For chip components, the relationship between conductor width must not be
more than 1 to 2.
The distance pad - land (not covered by mask) and pad - hole wall (via hole 3.5.2.2
covered by mask A1) must be at least 0.230 mm
A1
Connection to pad The conductor width should be less than the pad.
For BGA, LGA, CSP and 0402 or less, the conductor width must be max 70%
of the pad.
Conductors parallel to a pad must have a spacing of C3.
Connection between 2 soldering surfaces for one component, see ==> 3.5.2.3
Supplementary pattern Supplementary pattern must be added to achieve an even pattern density 3.5.3
within a layer and also between the layer pairs. Design, see 3/102 12-102
Shielding Shielding (board edges) see ===> 3.5.4

1/102 12-102 Uen

2003-06-05 K
Holes
Aspect ratio Maximum aspect ratio for hole diameter / board thickness is 1:8 alt. 1:10. 3.6.2.2
Hole dimension Minimum 0.3 mm alt. 0.2 mm.
Buried via for boards Diameter 0.2 or 0.3 mm 3.6.2.6
having NO u-via Depth Min 0.125 mm Max 1.6 mm
Buried via for boards Diameter 0.2 mm
having u-via. Depth Min 0.125 mm Max 1.2 mm
Blind via Diameter 0.2 or 0.3 mm 3.6.2.7
Depth Min 0.125 mm Max 1.5 mm
Hole spacing Min spacing between plated holes (hole walls) electrically separated, 0.55 mm 3.6.2.5
not electrically separated, 0.20 mm
Hole tolerances Not plated holes + 0.10/-0 3.6.2.3
---”--- H > 6.2 mm +/- 0.20 mm
HASL Not HASL
Plated holes < 1 mm + 0.15/-0 mm +0.15/-0 mm
------”------- 1-- 6.2 mm + 0.15/-0.05 mm +0.15/-0 mm
PTH in pads Not permitted 3.6.2.9
Blind via in pads The size of the pads must, at least, be equal to the min land size. 3.6.2.10
Hole density Maximum hole density using thermal relief lands and/or clearance holes, see 3.6.2.11
Microvia Avoid vias that connect layer 1 to 3. Instead use staggered vias (layer 1 to 2 & 4.2
2 to 3), same rules for the other side of the board.
Hole size 0.10 mm.
Land size, start layer 0.30 mm 4.4
Land size, stop layer 0.340 mm (1) or 0.30 mm. (1) Will be possible to use different drilling techniques.
Special rules: If CSP 0.275 mm on start/stop layer for boards having CSP with a pitch of 0.5 mm. 4.5.1
components are used. Min conductor spacing 0.075 mm if a conductor is routed between those lands
on stop layer and only permitted underneath CSP body area.
Thermal relief, see 3.5.1.6
Conductor width, see 3.5.2.2
Underfill, see 5.3.3
Design of thermal vias Two different design alternatives for thermal vias, see 4.5.2
for components with
heat sink (pad)
Primus datum point The point must be physically discernible on the PB. 3.7.1
Fiducial marks: Use 3 or at least 2 fiducial marks diagonally placed. Land diameter 1.50 mm, 3.7.2.2/
-for the board solder mask opening 2.90 mm and minimum 5 mm from board edge if panel is 3.7.2.3
not used. Marks placed in a foil area, then the openings in the foil area must be
- for the components at least 3.1 mm 3.7.2.4
The centre of components (having a pitch of 0.50mm or less) shall be within a
distance of 50 mm from the fiducial mark.
Tolerance on outline Distance. Class 1. Class 2. 3.7.4.1

dimension 0 -- 30 mm +/- 0.2 mm +/- 0.1 mm
(30) -- 120 mm +/- 0.3 mm +/- 0.15 mm
(120) -- 315 mm +/- 0.5 mm +/- 0.2 mm
Radii If panel is not used the board shall have a radii or bevel at the corner. 3.7.4.2
Internal radius 1.2 mm, however 1.0 or 0.8 mm can be used.
1/102 12-102 Uen

2003-06-05 K
Panel The position of board, tabs etc. must be stated in a location information 107 73-. 3.7.4.3
Solder mask State a breakdown voltage of 250 V. 1000V is not recommended. 3.9.1
The mask can extend to the outline.
Openings in the mask for NPTH hole diameter + 0.25 mm 3.9.2.1--
Component holes. land diameter + 0.12 mm 3.9.2.4
Pads pad + 0.12 mm
Via holes hole diameter + 0.13 mm. For HASL special rules
Blind and micro vias No openings
Solder dam Min. width of solder dam is 0.10 mm with the exception for CSP/LGA comp.
Surfaces protection Electroless Ni/Au, hot air solder levelling (HASL) or OSP 3.10.1
Mask for solder paste The inf 107 64- must have fiducial marks (size/placement) in the same way as 3.11
for the board.
Openings for pads The same size as for the pad or as stated in the BYZ- information.
Marking Mark the PB with product number and R-state on the secondary side. Also a P- 3.12.1
mark on primary side and a S-mark on secondary side and this should be within
a frame. The flammability rating can also be included by design.
Space, other markings Space fore other markings (manufacturer’s code, time of manufacturing and
flammability rating) must be available, see ===> 3.12.2
Printed Board Assemblies (PBA)

Alignment marks BGA, CSP & LGA components shall have alignment marks, as two corner 5.3.1
marks or two lines at the component’s adjacent sides.
Placement of comp. Max voltage Pref. 1 Pref. 2 Pref. 3 5.3.3
15 0.25 mm 0.19 mm 0.125 mm
Min component spacing
50 0.38 mm
outside comp. or pad
100 0.50 mm
(shadow) for reflow
soldering.
Space for BGA 3 mm outside the comp. if repair shall be possible
Space for CSP 0.5 mm outside the comp. With underfill, 1.0 mm on two sides (L-shaped) are
needed. 5.2.2 --
- within the component space according to 1057-. 5.3.3
Place the components:
- not closer than 5 mm to the board edge on at least two opposite sides,
preferable the longest side.
- so change & repair is possible and trimming point is accessible.
- not over PTH (uninsulated comp.)
- so the number are as equal as possible between primary & secondary side.
- ceramic capacitors 0805 or larger, not closer than 5 mm to board edge or
screw holes.
- width a free zone of 15 mm on the secondary side for centre support, if needed
- so BGA and CSP do not overlap each other (opposite side of the board)
Different height of components must be considered due to inspection & rework.
Rules for hole- and surfaces mounted components (wave soldering, pin-in 5.4
Hole & SMT comp.
paste & press fit) see ===>
1/102 12-102 Uen

2003-06-05 K
Rules for testing Place the trimming points on one side of the PB and test points (TP) on the 5.6.2
other side (e.g. secondary side)
Distribute the TP as evenly as possible on the board area.
The diameter of the TP should be 1.5 mm but at least 1.0 mm
The distance between TPs, centre -- centre, must be at least 2.5 mm.
The distance between TP and pad, edge--edge, should not be less than
1.0 mm.
The distance between board edge and the centre of the TP must be at least 3.8
mm.
The distance between the edge of the TP and a comp. body must be at least
0.5 mm. Comp. higher than 6.3 mm it must be at least 5.0 mm.
Marking Where possible, place the marking on the front of the PBA, otherwise on the 5.7
board’s primary side and indicate its placement with corner marks in the solder
mask, see 3.12.2.
Lead-free soldering Consideration must be taken for components having large thermal mass/heat- 5.1.2
absorbing since it affect the soldering, see ==>
The text “Lead-free soldering” is to be stated in top of 131 32- Also the
maximum soldering temperature must be stated if it’s below 260 degrees C.
1 GENERAL
1.1 DEVIATION
If the design or product requirements of type or individual PB or PBA deviate

from this standard or general requirement specification, these deviation must
be specified in the product documentation.
1.2 PRODUCT SAFETY
Product safety requirements; see

http://regulations.ericsson.se/safety/req/index.shtml
1.3 ENVIRONMENT
Design for environment, see

http://inside.ericsson.se/sustainability/dfe/
1/102 12-102 Uen

2003-06-05 K
1.4 TERMINOLOGY
CAD-data
is defined as the information interface between design and production.
Chip Scale Packages (CSP)
refers to components of Area Array-type when CSP is specified in this

document.
Organic Solderability Preservative (OSP)
organic surface treatment on copper to preserve the solderability.
2 CHOICE OF EQUIPMENT PRACTICE
2.1 CHOICE OF COMPONENTS
All components that are used in the printed board assembly, must be
approved for their field of application.
2.2 CHOICE OF PB MATERIAL AND LAYER DESIGN
Material, see section 3.2.1. Layer design, se section 3.3.2.
2.3 CHOICE OF MOUNTING TECHNIQUE
It is important to reduce the production complexity (e.g. number of

processes) and thereby obtain a maximum yield. Choose, if possible, the
mounting technique according to the preference order given in 3/102 12-102.
3 PRINTED BOARD (PB)
The dimensions stated in this document refer to the dimension in the CAD-
data if nothing else is stated.
3.1 GENERAL
3.1.1 Documentation
For documentation of printed boards, see 1/109 42-TVA+.

1/102 12-102 Uen

2003-06-05 K
3.1.2 Producibility
As a general rule, use as low pattern or tolerance class as possible, i.e.

larger dimensions or tolerances than the minimum stated in this document.
The pattern class of a board (and thereby the cost) is determined by the
highest pattern class for which it has been designed even if the highest class
is only used on a part of the board area.
If a first and/or a second choice is indicated in this document, be aware of

that the second choice have a great influence on the yield/price and the
number of suppliers may be reduced.
3.2 MATERIAL
3.2.1 General information
General properties and requirements are found in:
• IPC-4101 Specification for base materials for rigid and

multilayer printed boards
• IPC-4562 Metal foil for printed wiring applications.
• IPC/JPCA-4104 Specifications for high density interconnect
and microvia materials.
• http://supplytech.ericsson.se/techserv/areas/standards/pb/
Database for PB-material
If the electrical properties for permittivity and loss tangent (may also be
denoted as dielectric constant and dissipation factor respectively) will be
specified in 1301- this should be defined at a test frequency of 1 Mhz, (alt
1 Ghz or 10 Ghz) and with a resin contents of 50%. Test method to be used
is IPC-TM-650 number 2.5.5.3, 2.5.5.9 or 2.5.5.5 depending on the stated
test frequency.
During the design step, a more specific information on these properties may
be needed, depending on the operating frequency etc.
The material cost has a great influence on the total cost for the PB. Therefore
it is important to utilize the production panel in the best way. This panel size
may wary between suppliers.
1/102 12-102 Uen

2003-06-05 K
3.2.2 Halogen free materials
The definition of halogen free material is that the maximum contents, by

weight, is as follow:
Cl 0.3%
Br 0.09%.
3.2.2.1 General information
Due to the use of different flame retardant in the material, the properties for
permittivity and loss tangent will differ between different material suppliers.
However, the development is going in the direction of less variation between
different supplier and also towards better electrical properties.
3.2.2.2 Guidelines for the choice of material
The variations of permittivity and loss tangent for halogen free material are
here divided into the following two groups and it reflects the number of
material suppliers for the time being. The range stated in-group 1 is what the
most suppliers have today.
Note that this is the situation today and these values may be changed or new
group may be added later on. So the time for product release and the volume
will also be an important factor for the choice of material.
Group 1 Group 2
Permittivity at 1 Mhz and 50% resin contents 4.9 +/- 0.4 4.9 +/- 0.2
Loss tangent at 1 Mhz and 50% resin contents 0.01 - 0.02 0.01 - 0.02
3.2.3 Safety Requirements (UL requirements)
The safety requirements that is valid for each PB-design has to be taken into
consideration in an early developing phase. It has to be determined one case
by another depending on the application and sales market for which the
finished product is intended.
1/102 12-102 Uen

2003-06-05 K
Today, many PB have (as default) the recognition requirement stated as

“YES” in 1301- but that may not be needed for all boards. In general the PB-
design has to meet the following criteria.
• Normally, flammability rating (according to UL 94) of class V-1

or better is required for the boards.
• Recognition according to UL 796 is normally not required. It

can be necessary for some applications for the North American
Market, however it is not normally required for boards having
secondary circuits classified as SELV.
Definition of SELV (Safety Extra-Low Voltage) according to UL 1950. “A

secondary circuit which is so designed and protected that under normal and
single fault conditions, the voltage between any two parts of the SELV circuit
and for class 1 equipment, between any one such part and the equipment
protective earthing terminal does not exceed a safe value of 42.4 V peak or
60 V dc”.
Instructions and further information see

http://regulations.ericsson.se/safety/instructions/index.shtml
and 3/102 12-102
3.3 LAYER STRUCTURE
3.3.1 Board thickness
The total thickness of the PB that is stated in the layer drawings includes the
plating thickness but not the thickness of solder mask.
1/102 12-102 Uen

2003-06-05 K
3.3.2 Layer design
To be able to produce boards with the general requirements of maximum

bow and twist of 0.7% (even a more stringent requirements are required for
some boards, see 5.5, depending on components, board size and how the
board is attached in the superior product, fixed or not) the following must be
fulfilled regarding the layer design:
• The number of layer must be even

• The voltage/ground layers must be placed symmetrically in
relation to the board’s centre line, i.e. layer pairs according to
fig 3.3.2 a
• The pattern density for a layer pair (fig 3.3.2 a) must be similar,
also the distribution of the pattern within a layer must be even.
Design of supplementary pattern, see 3.5.3.
The different layers in a multilayer board are numbered with L1 for the
primary side.
L1
L2
L3 Layer pairs
L4
L5
L6
Figure 3.3.2 a
Choose in the first place a layer structure according to an existing 1301- or

a layer drawing (general or individual). 105 83-101 contain a list of old layer
drawings with preference classes.
If a new layer design must be developed, this shall be done in consultation

with the technical responsible - or the production department.
Thickness tolerances for laminate that are normally used by the suppliers,
see 3/102 12-102. Laminates with a thickness below 0.10 mm shall only be
used as a second choice.
1/102 12-102 Uen

2003-06-05 K
Some examples of different combinations of holes/connection between

layers are shown in figures 3.3.2 b -- d. The preference numbers (given
under each illustration) are ranked to reflect the production complexity such
as production flow, yield and thereby the production cost. Moreover, there
may be a number of other factors that need to be taken into account, such
as functional requirements, component choice etc.
If possible, use a layer design with 1 + 1 microvia layer instead of using blind
or buried vias.
Blind via
PTH Buried via
1 2 3 4 5
Figure 3.3.2 b
Microvia
1 2 3 4
Figure 3.3.2 c
1 2 3 4
Figure 3.3.2 d
1/102 12-102 Uen

2003-06-05 K
3.4 DIMENSIONING OF CONDUCTIVE PATTERN
3.4.1 Electrical dimensioning
Electrical dimensioning see 2/102 12-102. The tolerances on a completed

PB must be considered in this case.
3.4.2 Copper thickness
Do not use nominal copper thickness above the values stated in the
table 3.4.2. Information about the most common used copper thickness and
tolerances is given in 3/102 12-102.
Table 3.4.2
PATTERN CLASS 51 52 53 54 55 56
Copper (1) Plated 140 100 55 50

thickness
(2) Not plated 105 70 35
um
(1) Plated = Base copper + plating

(2) Not plated = Base copper
Some restriction exist if using copper thickness of 17 um, see 3/102 12-102.
1/102 12-102 Uen

2003-06-05 K
3.4.3 Pattern classes
3.4.3.1 General
The dimension (width, space and land size) refers to the dimension in the
CAD-data as well as the nominal dimension on a completed PB. Therefore,
the CAD-dimensions (also for soldering surfaces) may require adaption at
the manufacturing of PB. The minimum permitted dimension for each pattern
class is stated in the following tables in 3.4.3.X
The combination of different pattern classes (conductor width/conductor

spacing) can be used as long as the minus tolerance for conductor spacing
is larger or equal to the plus tolerance for conductor width.
Solder mask
Conductive pattern
C3 C C1
B C2
C3
C2
C2
H C
C
L
Covered land, by mask or internal layers
Figure 3.4.3.1
3.4.3.2 Conductor width
Table 3.4.3.2.
PATTERN CLASS 51 52 53 54 55 56
Conductor width B >= mm 0.50 0.250 0.150 0.125 0.10 0.075
Tolerance on PB, mm +/-0.040 +/0.040 +/-0.040 +/-0.040 +/-0.030 +/-0.030

1/102 12-102 Uen

2003-06-05 K
3.4.3.3 Conductor spacing
Minimum spacing C2 between soldering surfaces refers to two different

components and depends on the soldering methods. The restriction area for
components (5.3.3) may increase this space.
If selective OSP is used, the spacing between OSP surfaces and Ni/Au
surfaces must not be less than 0.35 mm. The OSP surfaces must be masked
(with a separate mask information) and the size is to be 0,4 mm larger than
the surfaces.
General rule regarding minimum spacing between soldering surfaces for one
component is not stated in this document.
Table 3.4.3.3
PATTERN CLASS 51 52 53 54 55 56
C >= mm 0.50 0.250 0.200 0.175 0.150 0.100
Tolerance on PB, mm - 0.050 - 0.050 - 0.050 -0.050 - 0.050 -0.030
C1 and C2 Wave soldering mm 0.50 0.380

>=
Reflow soldering mm 0.50 0.250
C3 >= mm 0.50 0.200 0.175

1/102 12-102 Uen

2003-06-05 K
3.4.3.4 Land size, microvia excluded
Table 3.4.3.4
PATTERN CLASS 51 52 53 54 55
Land sizes (L) Component hole mm 0.40

0.80 0.550 0.450 0.40
(1) L-H >= Via hole mm 0.30
(2) Annular ring Component hole mm 0.20

0.40 0.275 0.225 0.20
(L-H)/2 Via hole mm 0.150
(1) H = nominal hole diameter

(2) Is to be stated in 1301-. See fig 3.4.3.4 a
Use, as the first choice, class 54 or a larger land for internal layers as shown
in fig 3.4.3.4 b. As a second choice class 55 can be used but this must be
done restrictively, especially if the board is thicker than 1.8 mm. Also others
factors such as material, layer structure etc. must be considered.
Class 55 can be used on layers where the via starts/ends.
Lands for class 52 and upward require plated-through holes.
55 55
55 55
54 54 54 55
Annular
H ring 55 55
55 55
L
Fig 3.4.3.4 a Fig 3.4.3.4 b
Non-functional lands on internal layers should not be included in the pattern

information. However, there must be lands on start and stop layers.
Bit soldering by robot requires larger lands so the size should be 0.7 mm
larger than the hole diameter. However, it must not be less than class 52.
Decisions on the use of robot soldering must be taken in consultation with
the production department.
The dimension of a multi-corner land shall correspond to an inscribed circle

having a diameter as stated in table 3.4.3.4.
1/102 12-102 Uen

2003-06-05 K
3.5 DESIGN OF CONDUCTIVE PATTERNS
3.5.1 General
3.5.1.1 Orientation of conductors
Use as short conductor lengths as possible. Orientates as large a portion of

the pattern as possible in one main direction for each layer. For multilayer
boards the main direction should be perpendicular between adjacent layers.
3.5.1.2 Teardrops
Lands smaller than class 52 and connected to conductors, microvias are

excluded from this rule, must have the land designed with a teardrops (in a
suitable way) according to the dimension in figure 3.5.1.2.
Minimum 0.120 mm
Conductive pattern
Figure 3.5.1.2
3.5.1.3 Angles and small surfaces
Angles less than 90 degrees should be avoided and acute angles less than
45 degrees are not to be used.
Avoid small foil surfaces or small surfaces that are surrounded by copper foil.
It's size must not be less than 0.015 mm2. Otherwise, the PB manufacturer
may remove, functional pattern excluded, or fill in those small areas.
3.5.1.4 Reducing of the pattern dimension
If there are narrow passages on a specific area on the board, reduce the
pattern in the following order:
• Conductor
• Conductor spacing
• Land dimension
1/102 12-102 Uen

2003-06-05 K
3.5.1.5 External layers
Large foil areas (> 25 x 25 mm) should be sectioned with a recess width
corresponding to the minimum conductor spacing. However, it is essential
that the electrical function is taken under consideration at the design of the
sectioned area.
Use the largest possible pattern symbol when drawing large foil areas in the
CAD system.
If the land is placed in a foil area according to figure 3.5.1.6 b, the conductor
spacing C is to be 0.175 mm as a minimum.
Use thermal relief lands according to figure 3.5.1.6 c or d for components

hole and for press fit holes (but not for via holes) if they are connected to a
large foil area
3.5.1.6 Internal layers
Use the pattern in figure 3.5.1.6 a for holes which are to be insulated from
the internal layer.
Use the pattern in figure 3.5.1.6 b for holes which are to be insulated from
the internal layer and when the foil thickness of the internal layer is >= 70 um
and when blind-/buried via ends in a foilplane. The conductor spacing C is to
be 0.175 mm as a minimum. Other symbols, for example a square, may also
be used.
For thermal relief lands the same rules apply as for external layers. Use also
thermal relief lands for microvias if they are connected to a large foil area and
are placed in a pad for BGA and CSP component.
The dimension of the recess width (W) should not be less than 0.150 mm,
but 0.10 mm can be used as a minimum if conductor spacing class 56 is used
for the layer in question.
C= min 0.175 mm W Conductive pattern

Max 0,7 mm
Figure 3.5.1.6 a Figure 3.5.1.6 b Figure 3.5.1.6 c Figure 3.5.1.6 d

1/102 12-102 Uen

2003-06-05 K
The B1-measure according to figure 3.5.1.6 e must not be less than the
conductor width for the layer in question. If the measure B1 is below the
minimum value, then there must be no foil-string between the clearance
holes especially for high volume boards.
Note however, the design tools may have some limitations to make the
design according to this rule.
Conductive pattern
B1
Figure 3.5.1.6 e
3.5.2 Soldering surfaces
3.5.2.1 Soldering surface surrounded by foil
Soldering surfaces must be separated from the surrounding foil, see figure
3.5.2.1 a, by a conductor spacing C3 according to the pattern class of the
board. If the distance between the soldering surfaces is so small that the B-
measure is less than the conductor width of the board, then it shall be left
open, i.e. there must be no foil-string between the soldering surfaces.
For chip components that will be reflow soldered (non-glued) the relationship
between the width of conductors that are connected to the soldering surfaces
for the component must not be more than 1 to 2. If more than one connection
to a soldering surface is required (for functional reasons), a wider conductor
to the other soldering surface must be chosen in order to obtain the required
relationship. See figure 3.5.2.1 b.
C3 Conductive pattern
Figure 3.5.2.1 a Figure 3.5.2.1 b

1/102 12-102 Uen

2003-06-05 K
3.5.2.2 Connection between soldering surface and land
When reflow soldering, the connection between a via/component hole and a

soldering surface is to be design as follows:
• The conductor width should be less than the soldering surface.

However, for BGA, LGA, CSP and chip components 0402 or
less the conductor width (total width if more than one conductor
are connected) must not be more than 70% of the soldering
surface.
• For plated-through holes with open land (not covered) the

distance A, according to figure 3.5.2.2 a, must be at least
0.230 mm.
• For plated-through holes with covered land, the distance A1

(hole wall - soldering surface) according to figure 3.5.2.2 b
must be at least 0.230 mm. A conductor must be connected
between land and soldering surface.
• For blind via the distance A can be 0 but a conductor must be

connected between land and soldering surface.
On boards which are to be wave soldered, the measure A can be 0

.
Solder mask Conductive patten
A A1

1/102 12-102 Uen

2003-06-05 K
3.5.2.3 Connection to soldering surfaces
Use conductor spacing C3 if the conductor is connected as shown in figure

3.5.2.3 a.
The connection between soldering surfaces for one component must be as

shown in figure 3.5.2.3 b. The measure C3 is to be according to the pattern
class for the board.
C3
C3
3.5.3 Supplementary pattern
3.5.3.1 Supplementary pattern for external layers
A supplementary pattern shall be added to the boards if the electrical

function allows that.
The design of this supplementary pattern may be done according to the

following alternatives:
• A1or A2 where the pattern is connected.

• B1--B3 where the pattern is not connected.
The density and design of these alternatives are described in 3/102 12-102.
3.5.3.2 Supplementary pattern in internal layers (signal layers)
The same rules as for external layers. The design may be done according to
one of the alternatives A2 or B1--B3.
1/102 12-102 Uen

2003-06-05 K
3.5.4 Shielding
Avoid using plated edges, because of manufacturing problems. Instead,

design a foil-frame that goes round the board on external as well internal
layers and connect these with plated-through holes. The distance between
the holes shall be a maximum of 10 mm at clock frequencies up to 25 MHz,
at higher frequencies the distance shall be a maximum of 5 mm. Minimum
edge spacing to shielding foil, see 3.7.3.1.
3.5.5 Screw connections
Screw connections with electrical connections are, if possible, to be

soldered.
Screw connections without electrical connection shall have no lands.
3.6 HOLES
3.6.1 Hole information
All circular holes on a PB shall be stated in the hole information.
3.6.2 Mechanically drilled
3.6.2.1 Plated-through holes
Holes and slots that are to be plated-through shall have lands on both sides
1/102 12-102 Uen

2003-06-05 K
3.6.2.2 Hole dimension.
The minimum hole diameter is determined by the ratio between hole

diameter and board thickness. At present this is about 1:8 and as a second
choice 1:10 can be used for plated-through holes.
However, the minimum hole diameter is 0.3 mm as the first choice and
0.2 mm as the second choice. Use different diameters instead of using only
the smallest diameter for all plated-through holes on a single board.
Note. If using Hot Air Solder Levelling (HASL) as surface

protection in combination with 0.3 mm holes or smaller,
special rules for solder mask opening applies, see 3.9.2.3.
The sizes of component holes, see 5.4.2.
3.6.2.3 Hole diameter tolerances
Table 3.6.2.3 shows the general tolerances, including surface protection, for
hole diameters.
Table 3.6.2.3
DIAMETER, mm TOLERANCE, mm
H = nominal hole Not plated holes Plated holes with HASL Plated holes that do not
diameter as surfaces protection. have HASL as surfaces
protection.
H<1 + 0.10 + 0.150

-0 -0 + 0.150
-0
1 <= H <= 6.2 + 0.10 + 0.150
-0 - 0.050
H > 6.2 +/- 0.20 ------ ------
Note: Tolerances are not applied for via holes. Using HASL the via holes
may be filled up.
1/102 12-102 Uen

2003-06-05 K
3.6.2.4 Positions tolerance for hole - hole and hole - pattern
Tolerance for hole position:
Generally, tolerance class 4 applies to all holes, including location radius.

Holes that are drilled separately after etching the pattern, only tolerance
class 3 can be obtained.
The tolerance values for each class and at different distance from a
reference hole, see 3/102 12-102. If required, the reference hole must be
stated in the product documentation, otherwise the PB manufacturer may
freely choice a reference hole.
Tolerance between hole (plated/not plated) and conductive pattern:
The general tolerance is +/- 0.15 mm within a distance of 150 mm.
3.6.2.5 Hole spacing
For plated holes that are electrically separated the minimum spacing
between the hole walls is 0.55 mm.
Plated holes that are not electrically separated, e.g. for heat transfer, the
minimum spacing between the hole walls is 0.20 mm. (Note that the Cu area
in the hole wall, for heat transfer, only increase with about 14% if the hole
dimension is changed from 0.5 mm to 0.3 mm and the number of holes will
increase a lot). If the intention is to solder a pad with heat transfer vias, then
the vias must be plugged (3.6.2.9).
3.6.2.6 Buried via
Boards with no microvias.

Hole diameter 0.2 or 0.3 mm.
The depth of the via min 0.125 mm max 1,6 mm.
Boards with microvias.

Hole diameter 0.2 mm.
The depth of the via min 0.125 mm. max 1,2 mm.
This limitation is to avoid a separate hole filling operation before application
of the dielectric layer for microvia if RCC-foil are used. However, some
manufactures are using separate filling independently of the hole depth. If
liquid epoxy is used as dielectric layer, separate filling must always be done.
1/102 12-102 Uen

2003-06-05 K
3.6.2.7 Blind via
Blind vias must not pass through odd numbers of layers, because the layer
structure (prepreg/laminate) must be symmetrical, see 3.3.2.
Hole diameter 0.2 or 0.3 mm.

The depth of the via: min 0.125 mm max 1,5 mm.
3.6.2.8 Combination of holes/connection between layers
See section 3.3.2.
3.6.2.9 Plated-through holes in soldering surface
No plated-through holes are to be placed in the soldering surface. This is

valid for both reflow- and wave soldering. Only blind via can be used.
3.6.2.10 Blind via in soldering surface
If a blind via is placed in a soldering surface, then the size of the soldering
surface must at least be equal to the minimum land size for the hole. There
is no need to place the hole in the centre of the soldering surface.
3.6.2.11 Maximum hole density using thermal relief lands or clearance holes
To permit connections to the centre hole, the B1-measure according to figure

3.6.2.11 a must not be less than the conductor width for the layer in question.
The number of connections may, however, vary depending on e.g. current
load.
The L1-measure (according to figure 3.6.2.11 b) must not be less than the
minimum permissible annular ring according to the table for land size. The
L1-measure also applies if the pattern features overlap each other. There is
no requirement on measure L0
L1
B1 B1
L1
L0

1/102 12-102 Uen

2003-06-05 K
3.6.2.12 Not plated holes with lands
A mixture of plated-through and not plated holes with lands on any side of
the PB is to be used only in exceptional cases. If the design or the
component requires this, you can use one of the alternatives described in
3/102 12-102.
3.6.2.13 Inner location holes
The positions of inner location holes for each new outline are to be
established in consultation with the production-engineering department. The
location hole system is shown on the design data 1057-.
3.7 DIMENSIONING OF MECHANICS CHARACTERISTICS
3.7.1 Reference system
The PB and PBA shall have a primus datum point that is physically
discernible on the PB (normally one of the fiducial marks), see figure 3.7.1.
Primus datum point
.
Figure 3.7.1
3.7.2 Fiducial marks
3.7.2.1 General
Use, if possible, three but at least two diagonally placed fiducial marks on
boards or panels holding surface-mounted components.
1/102 12-102 Uen

2003-06-05 K
3.7.2.2 Design
The following fiducial marks and openings in the solder mask must be used:
Alternative 1
Land diameter 1.50mm.
Mask opening, diameter 2,90 mm.
If the marks are placed in a foil area the openings in this area must be at least
3.1 mm.
On the internal layer(s) adjacent to the fiducial mark the area within the mask
opening must either be totally covered by foil or no foil at all.
On the external layers an area of 5 mm from the centre of the fiducial marks
must be free from round pattern with a diameter of 0.5 -- 2.5 mm. There is
no restriction for via/component holes within this area.
Alternative 2
Has only been used on boards having Ni/Au as surface treatment (consumer
products).
A ring with a diameter of 2.0 mm.
and the inner diameter 0.70 mm.
Mask opening, diameter 2.120 mm.
If the fiducial mark is placed in a foil area.
diameter of the opening 0.70 mm.
mask opening, diameter 2.120 mm.
3.7.2.3 Placement of fiducial marks for the board
Place the marks on the side(s) of the PB where surface mounted

components will be located and as far from each other as possible. At least
two diagonal placed fiducial marks must not be obscured by any components
or detail.
Depending on the space available on the PB, place these fiducial marks
according to fig. 3.7.2.3. This is normally stated in the design data 1057-. If
panel is not used, the distance (F) between the mark and the board’s edge
shall be a minimum of 5 mm. The placing of fiducial marks are to be stated
in the mounting information n/1319- or computer stored information 130 35-.
Preference 1 Preference 2
Fiducial mark (3x) Fiducial mark (2x)
Figure 3.7.2.3
1/102 12-102 Uen

2003-06-05 K
If the fiducial marks cannot be placed within the board outline, the board
must be manufactured as a panel.
The location of the boards and the fiducial marks on the panel is to be given
in location information 107 73-. The department responsible for this
document is the user of the PB, i.e. the PBA manufacturer.
3.7.2.4 Placement of fiducial marks for components
Components with a lead pitch of 0.50 mm or less must have a fiducal mark
within a distance of 50 mm measured from the centre of the component.
3.7.3 Spacing to edge and foil
3.7.3.1 Edge spacing to shielding foil
For shielding foil (with no insulating requirements foil to board edge) the
following alternatives can be used:
To be used as preference 1: The measures D1 and D2 according to figure

3.7.3.2 must be at least 0.20 mm. On a completed board the distance can be
0 mm.
To be used as preference 2: Only to be used when the foil must go to the

edge on a final board, the foil shall go half the milling diameter (3.7.4.2)
outside the board edge.
3.7.3.2 Edge spacing to conductive pattern
The minimum edge spacing D1--D5, according to figure 3.7.3.2, in the CAD-
data as well as on a completed PB are stated in table 3.7.3.2.
If tolerance class 2 is used, then:
• this must be stated in the product documentation.

• V-score can not be used for outline tooling.
• Tabs according to method 2, see 3.7.4.3, can not be used.
1/102 12-102 Uen

2003-06-05 K
If 100 V d.c. or peak value is exceeded, then add 0.10 mm for D5-spacing.
Milled holes are holes that are larger than 6.2 mm and drilled holes are holes
that are 6.2 mm or smaller
Table 3.7.3.2
Tolerance class 1 2
D-measure in mm Measure Tolerance Measure Tolerance
D1 0.70 - 0.40 0.50 - 0.30
D2 1.15 - 0.55 0.63 - 0.38
D3 0.55 ---- 0.38 ----
D4/D5 Class 51 (1) 0.53 - 0.43 0.53 - 0.43
D4/D5 Class 52 & 53 (1) 0.38 - 0.28 0.38 - 0.28
D4/D5 Class 54 (1) 0.31 - 0.21 0.31 - 0.21
(1) The pattern class for the land size on the

internal layer in question
D1 D3 D5
Board edge or
milled hole
D2 D4 Drilled hole
Figure 3.7.3.2
Distance d (see figure 3.7.3.2) between not plated holes and the board's
edge must be at least 0.5 mm. There must be larger distance for riveting, but
it is difficult to give any indication on a general measurement, as this will vary
depending on the type of rivet used.
1/102 12-102 Uen

2003-06-05 K
3.7.4 Outline
3.7.4.1 Tolerance for outline dimension
Tolerances for outline dimension are stated in table 3.7.4.1. These

tolerances are not applicable if the V-scoring method is used.
If using tolerance class 2, then it must be explicitly stated either for each
measure on the drawing or be specified as “general” (for example in the
document head), in the case it apply to all measures on the drawing.
Table 3.7.4.1 Tolerances for outline dimension
MEASURE mm TOLERANCE CLASS
AboveUp to 1 2
0 - 30 +/- 0.20 +/- 0.10
(30) - 120 +/- 0.30 +/- 0.150
(120) - 315 +/- 0.50 +/- 0.20
(315) - 1000 +/- 0.80 +/- 0.40
3.7.4.2 Radii
Boards that are not manufactured as panel should have radii or bevel at the
corners.
The internal radius should be 1.2 mm. 1.0 mm or 0.8 mm can be used as a
second alternative. If sharp corners are required, milling as shown in figure
3.7.4.2 is recommended.
Figure 3.7.4.2
3.7.4.3 Panel
If the boards are to be manufactured as panels or not, this must be stated in

the design prerequisites. The position of these boards on the panel, the
choice of method (according to figure 3.7.4.3) and the positioning of the tabs,
1/102 12-102 Uen

2003-06-05 K
is to be given in location information 107 73-. The department responsible for

this document is the user of the PB, i.e. the PBA manufacturer.
If there are any limitations of the placing of the tabs or where excess material
is not allowed to protrude outside the board outline, then these limitations are
to be stated in the outline/hole information 1077.-
Method 1 requires a milling or punching operation to separate the PB from

the panel. In the area where the tabs have been placed, the edge spacing
(D1/D2 according to figure 3.7.4.3) must be 0.20 mm larger than stated in
section 3.7.3.2.
Method 2. The edge spacing to the hole wall (D1/D2 in figure 3.7.4.3) must
be according to tolerance class 1 in section 3.7.3.2 as a minimum. However,
this alternative to separate the PB from panel together with the break-away
method is not recommended, otherwise the edge spacing should be
increased. It is even more obvious if material such as BT or boards with
microvia is used. Use alternative 1 instead.
Guidelines for the design of tabs are found in 1058-002.
Method 3. For boards that will be wave soldered, the use of V-score is
recommended. However, only right angles can be used and general outline
tolerance can’t be applied. All manufacturers do not have the equipment for
V-scoring.
Further requirements and rules for PB on panel, see 1058-002 and 1013-227
respectively.
D1/D2
Method 1 Method 2 Method 3

min 0.71 mm
==>
Conductive pattern D1/D2
Figure 3.7.4.3
3.8 TESTING
3.8.1 General
There are no general rules for PB, but as a guideline some limitations are
stated in 3/102 12-102. So for complex boards this has to be done in
consultation with the manufacturer of the PB.
1/102 12-102 Uen

2003-06-05 K
3.9 SOLDER MASK AND OTHER TEMPORARY/PERMANENT SOLDER

RESIST COATINGS
3.9.1 Requirements on solder mask
The breakdown voltage below only pertains to functional insulation, and is

only to be applied where there are no requirements as to basic,
supplementary or reinforced insulation for electrical safety, according to
applicable standards such as IEC-950, UL-1950 or EN-60950.
Requirement of breakdown voltage is to be stated in the product

documentation and is chosen in the following order:
• 250 V. Conductive pattern underneath an uninsulated

component (direct contact with the board) is not allowed.
• 1000 V. Conductive pattern underneath an uninsulated

component (direct contact with the board) is allowed.
However, this alternative is not recommended because of the
risk of short circuits and the increased cost.
3.9.2 Design of the solder mask
3.9.2.1 General
Design the solder mask so it covers the whole conductive pattern (including
blind- and microvias) except soldering points, test points etc. The mask is
allowed to extend to the outline of the PB or to the edge of milled holes. For
drilled holes (not plated holes with no lands), i.e. holes with a diameter of <=
6.2 mm, the openings in the solder mask must be as a minimum 0.250 mm
larger than the hole diameter.
3.9.2.2 Openings for components holes
The size of the opening in the solder mask must be 0.120 mm larger than the
land’s diameter.
1/102 12-102 Uen

2003-06-05 K
3.9.2.3 Openings for vias
Blind vias shall be covered by solder mask, if they are not used as test points.
The size of the opening in the solder mask for plated-through via must be
0.130 mm larger than the nominal hole diameter. Applies on both sides of the
board.
Note however, using HASL as surfaces protection the rule stated above can
NOT be used if the holes diameter are less than 0.3 mm or if the holes are
0.3 mm and the board thickness is more than 1.8 mm.
If so, the opening in the mask on one side of the board must be 0.130 mm
larger than the nominal hole diameter. On the other side, the size of the
opening in the solder mask must be 0.120 mm larger than the land’s
diameter.
If electrical test is to be done to a plated-through via, the size of the opening

is to be the same as for component holes.
3.9.2.4 Openings for soldering surface
The size of the opening in the solder mask must be 0.120 mm larger than the
soldering surface (i.e. shadow 0.060 mm).
The solder dam between soldering surfaces must not be less than 0.10 mm.
However, for CSP and LGA components with a pitch of 0.5 mm the dam will
be less than 0.10 mm and for those components leave it as it is.
For all other components, use only one opening for all soldering surfaces in
a row. The opening is to be 0.060 mm outside the outer edge of the soldering
surfaces. Examples, see figure 3.9.2.4.
Solder dam
Solder
mask
Conductive
pattern
Figure 3.9.2.4
Chip-components 0402 and smaller shall have no solder mask between the
soldering surfaces.
1/102 12-102 Uen

2003-06-05 K
3.9.3 Temporary solder resist coating (peelable mask)
3.9.4 Permanent, selectively applied, solder resist coating
3.10 SURFACE TREATMENT
The surface treatment must be noted in the PB's product specification

(1301-)
3.10.1 Surface protection
The following treatments are, at present, most common.
• Electroless nickel/gold plating, requirements see 105 82-110

• Hot air solder levelling (HASL), requirements see 105 82-110
• The use of OSP is in the process of introduction. If used, state
“OSP” in 1301-.
If the spacing between soldering surfaces is less than 0.220 mm, using
HASL will then be more difficult and thereby the PB will be more expensive.
3.11 MASK FOR SOLDER PASTE
3.11.1 General
Solder paste information 107 64- must be documented for all boards where
solder paste is to be screen printed. For boards with OSP it also includes test
points, areas with electrical connection without soldering and surfaces that
will be post-soldered. However, it is not needed to make a 107 64- only for
test points, e.g. boards having components on one side and only some test
points on the other side.
3.11.2 Fiducial marks
The soldering paste information 107 64- must have fiducial marks with the
same design and location as for the PB:
Alternative 1. A land with a diameter of 1.50 mm.

Alternative 2. A land with a diameter of 0.70.
The solder paste information must not contain fiducial marks for individual
components.
1/102 12-102 Uen

2003-06-05 K
3.11.3 Size of the opening
Normally, the size of the opening in the mask for solder paste is to be the
same as the size of the soldering surface. If other size is required,
recommended size will be stated in 1301-BYZ=.
3.12 MARKING
The PB is to be marked with product number and R-state. Letters and digits
shall be in straight type and the size is given in 3/102 12-102. The characters
must not reduce the minimum permissible conductor spacing.
Different product versions of the PB are marked with a R-state. The R-state
for a PB is formed by adding a figure and a letter after the letter R.
The R-state for a PB forms part of the complete identity code of the board
concerned. This code consists of a basic number, a space and an R-state.
Example: TVF 123 4567 R2B
Function change of a PB, i.e. increase of figure, is done when the change
affects:
• the electrical characteristics of the board

• superior product, design as well as handling
Realisation change of a PB, i.e. increase of letter, is done when the change
do NOT affects:
• the electrical characteristics of the board

• superior product, design as wells as handling
Additional rules, see 1092-212.
3.12.1 Position of product number and indicating primary/secondary side
Mark the primary side with letter P and secondary side with letter S and place
the product number, if possible, on the board’s secondary side and as close
as possible to the S-mark. The P and S should be drawn within a frame.
1/102 12-102 Uen

2003-06-05 K
3.12.2 Space for other markings
The PB is also marked with manufacturer’s code, time of manufacturing, the

flammability rating (e.g. 94V-0, 94V-1 etc. if space is available) and with the
letter HF in the solder mask if HF (halogen free) is stated in 1301-. If the
boards must be recognized according to UL 796, they must be marked
according to UL Recognized Component Directory. However, the
flammability rating can be included by design in the Cu-pattern or in the
solder mask.
The manufacturer is responsible for this marking but the space must be
available on the board. Figure 3.12.2 gives two examples of required area
using a text height of 1.5 mm and a frame. This marking can also be
subdivided and should be brought together with the product number. The
frame can be placed in the solder mask or as a Cu-pattern.
94V-0 94V-0
4.5
6.5
9.0 15.0
Figure 3.12.2
Examples of required space and marking on boards having lack of space

and where UL recognized as well as flammability marking aren’t required,
see 3/102 12-102.
If this marking must to be screen printed, e.g. because of space limited,

boards will then be more expensive.
For PBA:s that are to be marked with a label on the PB (and place is
available), its placement on the primary side shall be indicated with corner
marks in the solder mask information. It must also be a free space of 4 mm
around the label to any soldering surfaces for components with a pitch of
0.65 mm or less and chip components 0402 and 0201.
1/102 12-102 Uen

2003-06-05 K
4 MICROVIA
4.1 MATERIAL
The material should be chosen in consultation with the board manufacturer.

RCC (resin coated copper foil), liquid epoxy or prepreg can be used for
microvias. It must be stated in the product specification 1301- if there is a free
choice or not for the manufacturer.
See also 3.2.1.
4.2 LAYER DESIGN
Avoid using microvia that are connected between layer 1 and 3 (primary side)
because it is still difficult to achieve and will reduce the number of board
suppliers. Also be aware of that it is not possible to have a connection to layer
2 for such microvia (1--3).
The nominal layer distance (tolerances excluded) can be selected within a

span of 40--70 um. Due to factors such as material, pattern/hole density,
copper thickness etc. the distance as well as the tolerance must be decided
for each board design together with the board manufacturer. The layer
distance is measured between the copper-surfaces on a final board.
4.3 HOLES
Nominal hole diameter for microvia is defined as the drilled size of the hole,
i.e. plating excluded, and is measured at the top of the hole.
The hole diameter must not be less than the thickness of the dielectric layer
(layer distance). For the most application a nominal diameter of 0.10 or
0.20 mm can be used as shown in figure 4.3. This will give, as a minimum on
a final board, a connection area to the internal layer corresponding to a
conductor width of 0.10 mm.
Mechanically drilled buried vias (figure 4.3) see 3.6.2.6.

1/102 12-102 Uen

2003-06-05 K
0.30 0.450 Definition of layer/land

1 1 Start layer
0.10 0.20 2 Stop layer
2
0.040--0.070
0.30/
0.340
Buried via
2 0.30/0.340
0.30 1 Min 0.230
Figure 4.3, however, see the note under 4.2
4.4 LAND SIZE
Minimum land size, see also figure 4.3.
With a hole diameter of 0.10 mm
• Start layer 0.30 mm.

• Stop layer 0.30 mm / 0.340 mm
To have the possibility of using different drilling techniques, and
thereby increasing the number of suppliers, a land size of
0.340 mm shall be used.
With a hole diameter of 0.20 mm.
• Start/stop layer 0.450 mm.

1/102 12-102 Uen

2003-06-05 K
4.5 ADDITIONAL RULES FOR SPECIFIC COMPONENTS
4.5.1 Chip Scale Packages (CSP)
If the board will be designed with Chip Scale Packages (CSP), the following
rules apply:
• Thermal relief, see 3.5.1.6.

• Conductor width, see 3.5.2.2.
• If underfill will be used, see 5.3.3.
If the board will be designed with CSP having a pitch of 0.5 mm, also the
following rules apply:
• Land size, start layer 0,275 mm.

Land size, stop layer 0,275 mm.
Those land sizes can be applied for the entire board
• The minimum conductor spacing is 0.075 mm. However, this

must only be used at the point where a conductor is routed
between lands on a stop layer and underneath the CSP area.
On other areas, pattern class 56 applies as the minimum
conductor spacing.
4.5.2 Design of thermal vias for components with heat sink (pad)
The following examples shows two different via configuration and layout
rules for heat transfer through the board. These components (L/TQFP,
SOIC/SSOP and MLF/MLP) have an exposed pad under the die that are
soldered to the board.
4.5.2.1 Design with only plated-through holes
The thermal vias, as PTH, are placed within the pad around the soldering
area for heat transfer. These vias, having a maximum size of 0.5 mm and
solder mask opening according to the general rules are to be added at the
layout of the board.
1/102 12-102 Uen

2003-06-05 K
Pad
Solder joint
= =
(*) Solder paste opening: 80% of the solder mask opening

Solder mask
(*) Solder mask opening
Vias to be added at design

Max size 0.5 mm
(*) Pad according to

3/102 12-102
Pad edge
(*) Min 0.175 mm (C3) (*) Min 0.9 mm (*) Information used for creating 1301-BYZ
4.5.2.2 Design with micro-, buried via and plated-through holes
Beside PTH also microvias and buried vias are used as thermal vias in this
case. The design of the PTH, pad dimension, mask and solder paste
opening is done in the same way as in section 1.1.
The microvias are connected between layer 1 and 2 and between (n-1) and
n respectively. The buried vias are connected between layer 2 and (n-1). The
microvias must be staggered in relation to the buried vias, i.e. not placed on
top of buried vias. Figure 4.3 shows an example of staggered microvias.
1/102 12-102 Uen

2003-06-05 K
Holes configuration on layer 1 and 2
Microvia Buried via

PTH
Buried via layer 2 Microvia layer 1
5 PRINTED BOARD ASSEMBLIES (PBA)
5.1 GENERAL
5.1.1 Documentation
For documentation of printed board assemblies, see 10/109 42-ROA+.
5.1.2 Lead free solder
The use of components with large thermal mass and heat-absorbing should
be avoided if lead free solder is to be used. Since the soldering temperature
for lead free solder is higher (requires 235˚ C as a minimum) than solder with
lead, this may give the result that the soldering temperature for small
components will be higher than what the component can withstand.
If this is not possible, the way to reduce this problem on the board level is to
place the components with large thermal mass so they are spread as equally
as possible on the board area (5.3.2.3). Furthermore, it is also very important
that the supplementary pattern (alternative A2 or A1 according to 3.5.3.1)
and ground/voltage foils is spread on the entire board area. This is done to
reduce the temperature difference on the board during soldering. A
verification of the soldering process for the specific board may also be
needed.
1/102 12-102 Uen

2003-06-05 K
If the maximum permitted soldering temperature for the board is lower than
260˚ C (depending on the component that have the lowest permitted
soldering temperature), then the maximum temperature must be stated in
the product documentation (131 32-).
If this maximum temperature is close to the minimum soldering temperature

(235˚ C) then it is very important to verify (e.g. by process verification) that
the board can be soldered within the limits for the maximum and minimum
temperature.
5.2 GENERAL POSITIONING RULES
5.2.1 Component and insulation spacing
If the board is designed for complying with UL requirements, this must be

taken into consideration when determining the insulation spacing. Special
requirements, such as IEC, UL etc. apply to the design of boards for power
units with primary voltage. Otherwise, the minimum insulation spacing, on a
completed PBA, between an uninsulated component and another
uninsulated component or surface is as follow:
Maximum V d.c. or Minimum insulation

peak value spacing mm
15 0.130
50 0.40
100 0.50
300 0.80
This value applies for a completed board so mounting tolerances must

therefore be added in the design phase as done in section 5.3.3.
1/102 12-102 Uen

2003-06-05 K
5.2.2 Component positioning
Place the components:
• within the component space, e.g. according to the engineering

data 1057-. The general rule is that no components or
soldering surfaces can be placed closer to the board edge than
5 mm on at least two opposite sides, preferably on the board’s
longest side.
• so that they do not block each other and complicate changes
and repairs.
• so that they do not obstruct free convection or the flow of
cooling air produced by forced cooling.
• so that their trimming points (trimming components) are easily
accessible.
Polarised or asymmetrical components of the same type should be oriented

in one direction to make inspection easier.
If the board’s dimension is more than 200 mm, ask the production
department if a centre support is needed. It depends on board thickness and
material, the components weight etc.
If needed, a 15 mm wide area needs to be kept free from components on the

secondary side for the centre support. The area shall be placed along the
direction of transport of the board through the oven and shall be within 30
mm on any side from the centre of the board.
Be also aware of not to place hole-mounted components in that area on the
primary side.
30 mm 30 mm
Zone of 15 mm for centre support
Direction of transport
Figure 5.2.2
1/102 12-102 Uen

2003-06-05 K
5.2.3 Adjusting components
The adjusting components are preferably placed on the primary side and do
not use component size of 0805 or less. Furthermore, avoid surface mounted
components that are to be manually mounted after testing. If surface
mounted components are required, increase the spacing of the components
so as to facilitate the accessibility for mounting or de-mounting.
5.3 SURFACE MOUNTED COMPONENTS. REFLOW SOLDERING
5.3.1 Size of the soldering surfaces and solder paste opening
The size of the soldering surfaces for each component is stated in

1301-BYZ=.
Sections 5.3.1.1 -- 5.3.1.14 are not included in this document, only in

3/102 12-102.
Alignment marks for components
BGA, CSP and LGA components shall have alignment marks (Cu-patten), if
space is available, according to the following alternatives:
• Two diagonal placed corner marks according to the figure

5.3.1 a. It shall be placed 0.25 mm outside the component’s
maximum size.
• At least two lines placed on 2 of the component adjacent sides
according to figure 5.3.1 b. The opening in the solder mask is
to be the line width + 0.12 mm.
Corner marks will be added in future footprints on an information layer as

guidance only. PB-designers will have to manually place the actual corner
marks on appropriate layer(s) in the layout database. Note: Information layer
is used as an expression here and PB’s CAD-systems may use other
terminologies.
min 0.75 mm min 0.75 mm
0.15 mm
0.15 mm
0.25 mm
0.25 mm
Solder mask 0.27 mm
Figure 5.3.1 a Figure 5.3.1 b

1/102 12-102 Uen

2003-06-05 K
5.3.2 Positioning rules
5.3.2.1 Plated-through holes under components
Plated-through holes can not be placed under uninsulated components.
5.3.2.2 Heavy components
5.3.2.3 Components with large thermal mass
Place those components so the thermal mass is as equally divided as

possible on the board area.
5.3.2.4 Number of components, primary/secondary side
The number of components on the primary and secondary side should be as

equal as possible
5.3.2.5 BGA and CSP
Do not place BGA and CSP component on the opposite side with any
overlap.
Do not place large fine pitch BGA or CSP components (leadless

components) on places were the board can be bent, for example under push
buttons.
1/102 12-102 Uen

2003-06-05 K
5.3.3 Component spacing
The minimum spacing around the components (dimension A, measured

from the maximum component body or the soldering surface, see figure
5.3.3 a) is shown in the table. This restriction area (dimension A) around the
components must not overlap each other.
A Preferences Maximum
Voltage
1 2 3
0.250 mm 0.190 mm 0.125 mm 15 V
0.380 mm ----- ----- 50 V
0.50 mm ----- ----- 100 V
0.80 mm ----- ----- 300 V
A 2A 1.5 mm
0.50 mm
With underfill
Small
A <=
15 mm
1.0 mm
Small
<=
15 mm
2A
0.5 mm + A 1.0 mm
A
3 mm 3 mm
Large
A-A > 15 mm
1.8 mm
Heat nozzle
A A
PGA
5.7 mm
PB
1.5 mm
3 mm
Figure 5.3.3 a
1/102 12-102 Uen

2003-06-05 K
Components such as BGA (Ball Grid Array), CSP (Chip Scale Package),
LGA (Land Grid Array) and MLF(LGA) (Micro Lead Frame) are divided into
the following two groups:
• Small Component’s longest side up to 15 mm

• Large Component’s longest side more than 15 mm.
These components need a restriction area around the component due to

access for repair tool. Beside the rules below the restriction area is also
dependent on the layer design for the PB such as number of layers, Cu
thickness and Cu areas. An increase of the space may in some cases be
needed for “small” components. Since the method and equipment for repair
may vary between different manufactures the following rules may not be
exactly in all cases. If the possibility of repair is not an issue for the board in
question, the restriction area can be reduced.
“Small” components must have a restriction area around the component of

minimum 0.50 mm. If underfill will be used, a restriction area of 1.0 mm is
needed on 2 of the component sides (L-shaped) see fig 5.3.3 a and no
through holes can be placed within this area as well as under the component.
Also adjacent components that are higher than this component must not be
placed closer than 2 mm from the component’s edge.
“Large” components must have a space of minimum 3 mm to the next

component. If the height of the adjacent component is more than 1.5 mm the
space must be increased, se figure 5.3.3 a.
Ceramic capacitors 0805 and larger shall not be placed closer than 5 mm to
the board edge or screw holes.
Furthermore, consideration must be taken regarding mounting of

components, inspection (AOI= Automatic Optical Inspection) and rework in
combination with high components that may require more space between
the components. Examples see figure 5.3.3 b. To utilize a maximum package
density on the board, all these special combinations has to be decided
together with the production department for each individual PBA..
AOI
45--60 degrees
Figure 5.3.3 b
1/102 12-102 Uen

2003-06-05 K
5.3.4 Additional components
If additional components are planned (post-mounting), e.g. in the case of a

modification, the board has to be prepared with soldering surfaces for these
components. As these components are to be manually mounted, increase
the spacing of the components so as to facilitate the accessibility for
mounting or de-mounting.
5.3.5 Rules for specific component types
5.4 HOLE- AND SURFACES MOUNTED COMPONENTS,
Besides wave soldering this section also deals with pin-in-paste and press
fit.
5.4.1 Size of the soldering surfaces, wave soldering
The size of the soldering surfaces is stated in 1301-BYZ=.
5.4.2 Component holes
The size of the hole is stated in 1301-BYZ=. Otherwise, calculation is found

in 3/102 12-102.
5.4.2.1 Pin-in-paste
Due to the required size for solder paste deposit area, a free space to other
components or conductive pattern (not covered by solder mask) is needed.
It is not possible to give an exact figure for this, because it depends on the
process used, board thickness, the lead's cross-section area and the space
between lead and hole. However, a free space of 2.0 mm from the edge of
hole to adjacent component or pattern (not covered by solder mask) will
cover the most applications.
Conductors routed between lands must be placed symmetrically in relation

to the centre of the lands.
1/102 12-102 Uen

2003-06-05 K
5.4.3 Positioning rules
5.4.3.1 General
SOT- components should be placed on the primary side, if the other

components are placed according to preference 6, 8 or 9, see section
“choice of mounting techniques” in 3/102 12-102.
5.4.3.2 Component direction for wave soldering
All components having an indication (e.g. in 1301-BYZ) of transport direction

for wave soldering shall be placed in the same direction on a board.
5.4.3.3 Plated-through holes under components
Plated-through holes under components must be placed so that the gas flow
is not obstructed, the component is not damaged by penetrating solder or
flux and no short circuits occur.
A prerequisite for placing plated-through holes under components, without

using raised mounting, is that the opening in the solder mask is as described
in section 3.9.2.3. However, all types of components do not meet the
requirements according to this rule. When mounting modes apply, any
limitations as regards the placing of plated-through holes under components
are given in 1301-BYZ.
5.4.3.4 Spacing between plated-through hole and component hole
5.4.3.5 Press fit
For press fit a free space of 2 mm around the hole centre on the board’s
opposite side is required.
5.4.4 Component spacing
Components that are to be wave soldered, a minimum spacing of 0.50 mm,

space A according to 5.3.3, is required.
Combination of hole- and surfaces mounted components, see 3/102 12-102.

1/102 12-102 Uen

2003-06-05 K
5.4.4.1 Surface mounting on the primary side
5.4.4.2 Surface mounting on the secondary side
5.4.5 Vertical dimensioning
5.4.6 Fastening
5.5 BOW AND TWIST
The general requirements for PBA is a maximum of 1% and for PB a

maximum of 0.7%. This requirement applies to double sided and multilayer
board of glass epoxy or composite material (CEM-3) and having symmetrical
layer design.
If a specific board require less bow and twist, then it is very important that
the layer design (3.3.2) is correct and the requirement must be stated in the
product documentation. If the layer design is correct it is possible to have a
maximum bow and twist of 0.5% for PB and 0.75% for PBA.
5.6 DESIGN FOR TESTING
5.6.1 General
If testing has to be done to a surface mounted component a test surface must

be made, because testing cannot be done on terminals or leads. The
conductor width between the soldering surface and the test surface must not
be wider than the soldering surface, if using reflow soldering.
Using test jig (bed-of-nails), test surfaces must be created on the secondary
side if connection cannot be made to a component hole or a plated-through
hole. It must be decided early on in the design stage (not later than the
pattern lay-out stage), which nodes are to have test points and its position
should not be change after the jig has been set up.
Vacuum fixture can only be used if the PBA is wave soldered or by using any
other plugging method of the vias (plated-through holes).
1/102 12-102 Uen

2003-06-05 K
5.6.2 Specific rules.
• Place the trimming points on one side of the board (for example
on primary side) and the test points on the opposite side.
• The test points should be distributed as evenly as possible on
the board, so as to distribute the pressure from the test pins.
• The distance between the outer edge of the test point and the
adjacent component body (the component symbol) must be at
least 0.5 mm. If the component is higher than 6.3 mm the
distance must be at least 5 mm.
• The distance between the board edge and the centre of the test
point must be at least 3.8 mm.
Within BT a minimum distance of 3.3 mm applies.
• The distance between the centre of test points must not be less
than 2.5 mm.
• The edge distance between test point and soldering surface
should not be less than 1.0 mm.
• The diameter of the test points should be 1.5 mm but at least
1.0 mm. For manual location of faults, so called "Service point"
can have a diameter down to 0.3 mm.
• Test points for HF shall be designed in such away that coaxial
probes can be used. The design has to be done in consultation
with the production test department.
• For hole mounted components. Do not place the test points
closer to the component holes than what is stated for plated-
through holes.
5.7 MARKING
The PBA is to be marked with product number, R-state, manufacturer’s code

and time of manufacturing.
Where possible, place the marking on the front or on the handle, otherwise
on the primary side, see section 3.12.2. The position of the product number
is to be stated in the product documentation if the board is included in an
equipment practice.
General rules for marking of products, see 102 01-101.

1/102 12-102 Uen

2003-06-05 K
5.7.1 R-state
Different product versions of a PBA are marked with an R-state, which is

formed by adding a digit and a letter after the letter R.
The R-state of a PBA forms part of the complete identity code of the PBA
concerned. This code consists of a basic number, a space and an R-state.
Example: ROA 123 4567 R1B
Rules for product changes are given in 1092-212.
5.7.2 Other markings
State in the product documentation if other markings are required, such as

warning marks, bare-code markings, market associated markings etc.
General rules, see 0012-101 and 102 01-109.
6 REFERENCES
0012-101 Uen Serial numbers
1013-227 Uen Placement information 107 73- for printed

boards
102 01-101 Uen Marking of products
102 01-109 Uen Bar code identification
2/102 12-102 Uen Electrical dimensioning of printed

board and printed board assemblies.
1058-002 Uen Breaks-off marks for printed boards on

break-off panels
105 82-102 Uen Requirement specification. Printed board

assemblies with hole- and surface-mounted
components. Mechanical product
requirements
105 82-110 Uen Requirement specification. Printed board for

hole- and surface-mounted components
105 83-101 Uen Layer drawings for multilayer printed boards.

Introduction
1092-212 Uen Product changes

1/102 12-102 Uen

2003-06-05 K
109 42-BYZ 101+ Uen Document structure Mounting modes

BYZ 101--119
IPC-4101 Specification for base materials for rigid

and multilayer printed boards
IPC-4562 Metal foil for printed wiring applications.
IPC/JPCA-4104 Specifications for high density interconnect

and microvia materials.
IPC-TM-650 Test methods

1 10212-102 K-Pbu

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

1 10212-102 K-Pbu

Uploaded by

Copyright:

Available Formats

ENGINEERING DATA 1(57)

EAB/RWI/KZ BENY 1/102 12-102 Uen

DESIGN RULES FOR PB AND PBA WITH HOLE- AND

This standard contains design rules (physical implementation) for printed

The electrical dimensioning of the conductive patterns regarding voltage,

1/102 12-102 Uen

1/102 12-102 Uen

1/102 12-102 Uen

1/102 12-102 Uen

5.4.5 Vertical dimensioning 54

10/109 42-ROA+ Uen Document structure specification.

1/109 42-TVA+ Uen Document structure specification. Printed boards

1/102 12-102 Uen

Characteristic Rules Paragraph

Printed Board (PB)

Layer design The number of layer must be even 3.3.2

Conductor width Class 53 54 55 56 3.4.3.2

Conductor spacing Class 53 54 55 56 3.4.3.3

1/102 12-102 Uen

Pad (soldering surface)

Shielding Shielding (board edges) see ===> 3.5.4

1/102 12-102 Uen

Tolerance on outline Distance. Class 1. Class 2. 3.7.4.1

1/102 12-102 Uen

Printed Board Assemblies (PBA)

1/102 12-102 Uen

If the design or product requirements of type or individual PB or PBA deviate

1.2 PRODUCT SAFETY

Product safety requirements; see

Design for environment, see

1/102 12-102 Uen

is defined as the information interface between design and production.

Chip Scale Packages (CSP)

refers to components of Area Array-type when CSP is specified in this

Organic Solderability Preservative (OSP)

organic surface treatment on copper to preserve the solderability.

2 CHOICE OF EQUIPMENT PRACTICE

2.1 CHOICE OF COMPONENTS

2.2 CHOICE OF PB MATERIAL AND LAYER DESIGN

Material, see section 3.2.1. Layer design, se section 3.3.2.

2.3 CHOICE OF MOUNTING TECHNIQUE

It is important to reduce the production complexity (e.g. number of

3 PRINTED BOARD (PB)

For documentation of printed boards, see 1/109 42-TVA+.

1/102 12-102 Uen

As a general rule, use as low pattern or tolerance class as possible, i.e.

If a first and/or a second choice is indicated in this document, be aware of

3.2.1 General information

General properties and requirements are found in:

• IPC-4101 Specification for base materials for rigid and

1/102 12-102 Uen

3.2.2 Halogen free materials

The definition of halogen free material is that the maximum contents, by

3.2.2.1 General information

3.2.2.2 Guidelines for the choice of material

3.2.3 Safety Requirements (UL requirements)

1/102 12-102 Uen

Today, many PB have (as default) the recognition requirement stated as

• Normally, flammability rating (according to UL 94) of class V-1

• Recognition according to UL 796 is normally not required. It

Definition of SELV (Safety Extra-Low Voltage) according to UL 1950. “A

Instructions and further information see

3.3 LAYER STRUCTURE