Chapter03 Solutions-5th

Problem Solutions – Chapter 3
CHAPTER 3
© 2016 Pearson Education, Inc.
3-1.
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
Y
1 This is the same function as the carry
This is the same function as the
F =FXZ
= XZ
+ XY+ +XY
YZ+ YZ for the full adder.
X 1 1 1 carry f or the f ull adder
.
Z
3-2.*
C
B F = AB + AC
1 1 1 1
A
1 1
)
D
eb
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ed id n
W
no the iss tea s
itt W tio
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t p W em ch
e
d on g. in t la
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an ing rnin tors igh
.
r
3-3.
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
Assuming inputs G3, G2, G1, G0 and outputs B3, B2, B1, B0, with G3 and B3 being the most significant bits, and treating the invalid
is
te f t ss th nite
input combinations as don’t cares:

e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
G1G0 G1G0 G1G0 G1G0

de o rse de ot
G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10

ill le u vi pr
w r sa co pro is
o eir is rk
00 00 00 1 1 00 1 1
th nd wo
a his
01 01 1 1 1 1 01 1 1 01 1 1
T
11 1 1 X X 11 X X 11 X X 11 1 X X
10 X X X X 10 X X X X 10 X X X X 10 X X X X
B0  G3G0  G2G1G0  G2G1 G0

B3  G3 B2  G3G2 B1  G2G1  G3G2 G1
 G2 G1G0  G3G2 G1 G0
3-4. a) For the 3 x 3 pattern, there are exactly three row, three column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 + X4 X5 X6 + X7 X8 X9 + X1 X4 X7 + X2 X5 X8 + X3 X6 X9 + X1 X5 X9 + X3 X5 X7 Gate Input cost = 32
b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30
3-5. a) For the 4 x 4 pattern, there are exactly four row, four column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 X4 + X5 X6 X7 X8 + X9 X10 X11 X12 + X13 X14 X15 X16 + X1 X5 X9 X13 X2 X6 X10 X14 + X3 X7 X11
X15 + X4 X8 X12 X16 + X1 X6 X11 X16 + X4 X7 X10 X13 Gate Input cost = 50
b) W = X1(X2 X3 X4 + X5 X9 X13 + X6 X11 X15) + X7(X5 X6 X8 + X3 X11 X15 + X4 X10 X13) + X9 X10 X 11 X12
+ X13 X14 X15 X16 + X2 X6 X10 X14 + X4 X8 X12 X16 Gate Input Cost = 48
1
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3-6.
a) Detecting a change in one-out-of- X1 X2 X3 Z
three inputs can be done using a parity 0 0 0 0
function as Z. The truth table shown is
for even parity. For this case, 0 0 1 1
Z  X1  X 2  X 3 0 1 0 1
0 1 1 0
If odd parity is chosen, then an
1 0 0 1
alternative result for Z is:
1 0 1 0
Z  X1  X 2  X 3
1 1 0 0
1 1 1 1
3-7.+
ABCD GNS YNS ABCD

RNS GNS GEW YEWGEWREW
YNS RNS YEW REW B B
ABCD GNS B
0000 1 0000
0 ABCD 1 YNS
0 GNS 0 0 RNS
0 0 GEW
0 YEW REW
10 REW1 B
0000 1 YNS0 RNS
0 GEW
0 YEW0 1 B
A GNS B
A GEW
0001 1 0 0 0 0 1 A GNS
0001 1 0 0000
00010 11 0 00 00 0 00 100 11 A GEW
0011 1 0 0 0 0 1 A
C GNS A
C GEW
0011 1 0 0001
00110 11 0 00 00 0 00 100
0 11
0010 1 0 0 0 1 C C GEW = AB + AC
0011
0010 11
1 00
0 00 00 00 11 C GNS = AC + AB
0010 1 0 0110
0010
0
11 0
0 00 0
00 00
10
00
1
11  AC= AC
GNSGNS AB+ AB CGEW  AB
GEW = AB
AC+ AC
0110
01110 1 00 0 00 0 0 1 GNS = AC + AB GEW = AB + AC
0110 1 0 0110 11 00 00 00 100 11 A A
0111
0101 0 1 0 0 0 1
)
0111 1 0 0 10 0 01 00 0 00 100
eb
0111
0101 11 A
B A
B
er or in ing
YNS
ed id n
0100 0 0 1 0 0 1 YEW
W
no the iss tea s
itt W tio
0101 00 0 10 01 0 00 A
B
C w A
B
C
100 11
t p W em ch
0101 0 1 01000 0 YNS YEW
e
d on g. in t la
m ld a
1100 0 0 1 1 0 B
C
D B
C
D
0100 00 0 11 01 00 10 YNS YEW
0100 0 0 1100
11011 0 00 0 10 1 10 0 C
D YNS = ABCD C
D YEW = ABCD
.
r
or ud a uc y
1100
1101 00 0 11 11 00 00 D YNS = ABCD D YEW = ABCD
0 10
w cl le tr p
1100 0 0 11111 0 10 1 0 0 0
e in nt ns co
1101
1111 00 00 11 11 00 00  ABCD
YNS
YNS = ABCD YEW
YEW  ABCD
= ABCD
th k ( de f i es
1110 0 0 1 1 0 0 B B
1101 0 0 11101 00 1 00 11 0 11 000
of or stu e o tat
1111 00
1010 0 0 1 1 0 0
ity s w g us d S
B
C B
C
1111 0 0 1110
10101 00 1 00 11 0 11 000
0 00 B B
C
is
C D
te f t ss th nite
1011 0 0 1 1 0 D
1010
1011 00 0 11 11 00 00 C
D RNS C
D
1110 0 0 1 0 10 10 0 01
e rt ss fo U
1001 0 0
gr hi in e
A A
th a a ly by
1011 00 0 11 10 01 00 D RNS D
k
1001
1000 0 10 0 10 0 0 1 A A
1010 0 0 1 0
in o e r
y y p d le d
RNS = A RNS
+ BCD REW = A + BCD
ro n an o te
1001
1000 00 00 11 00 10 01 A A
st f a s d s ec
1011 0 0 1000 1 0 1 0 1 0 0 00 1 RNS = A + BCD REW = A + BCD

de o rse de ot
RNS = A + BCD REW = A + BCD

ill le u vi pr
1001 0 0 1 0 1 0 RNS  A  BCD REW  A  BCD

w r sa co pro is
o eir is rk
th nd wo
1000 0 0 1 0 0 1
a his
T
3-8.
A B C S5 S4 S3 S2 S1 S0 S0  C
0 0 0 0 0 0 0 0 0 S1  0
0 0 1 0 0 0 0 0 1 S2  ABC  ABC
0 1 0 0 0 0 1 0 0 S3  ABC  ABC
0 1 1 0 0 1 0 0 1 S4  AB  AC
1 0 0 0 1 0 0 0 0 S5  AB
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
3-9.+
A B C D S2 S1 S0
0 0 0 0 0 0 0
S0  BCD  BCD  AB  ACD  ABCD
0 0 0 1 0 0 1
S1  AB  AB  ACD  BCD
0 0 1 0 0 0 1
S2  ABC  ABD
0 0 1 1 0 1 0
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 1 0
0 1 1 1 0 1 1
1 0 0 0 0 1 1
1 0 0 1 0 1 1
1 0 1 0 0 1 1
1 0 1 1 0 1 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
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d on g. in t la
m ld a
3-10.
.
r
or ud a uc y
w cl le tr p
W  AC  BD  BD
e in nt ns co
A B C D W X Y Z
th k ( de f i es
of or stu e o tat
0 0 0 0 0 0 1 1 X  BCD  BC+BD
ity s w g us d S
0 0 0 1 0 1 0 0
is
te f t ss th nite
Y  CD +CD
e rt ss fo U
0 0 1 0 0 1 0 1
gr hi in e
th a a ly by
ZD
in o e r
0 0 1 1 0 1 1 0
y y p d le d
ro n an o te
st f a s d s ec
0 1 0 0 0 1 1 1
de o rse de ot
ill le u vi pr
0 1 0 1 1 0 0 0
w r sa co pro is
o eir is rk
th nd wo
0 1 1 0 1 0 0 1
a his
0 1 1 1 1 0 1 0
T
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1010 to
XXXX
1111
3-11. a) PS LS RS RR PL LL RL
0 0 0 0 0 0 0 PL = PS
a) PS LS RS RR PL LL RL PL  PS
0 0 0 1 0 0 0 LL = PSLS RS+ PSLS RR
0 0 0 0 0 01 00 0 00
0 1 LL  PS LS RS  PS LS RR
0 0 0 0 0 11 01 0 00
0 1 RL = PSLS RS + PSRS RR
RL  PS LS RS  PS RS RR
0 0 0 1 1 00 00 0 11 0
b)
0 0 0 1 1 10 01 0
0 11 0
0 1 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 0 1 0
0 1 1 0 10
0 00 1 00
1 0
0 1 1 1 0 00 01 0 01
1 0
0 1 1 1 0 11 00 1 00 0
1 0 1 0 0 01 11 1
0 00 0
1 1 0 0 1 0 0
1 0 0 1 1 0 0
1 1 0 1 1 0 0
1 0 1 1 01
1 10 1 00
0 0
1 0 1 1 1 11 11 0 00
1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
)
eb
3-12.
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
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d on g. in t la
m ld a
.
r
or ud a uc y
C C C C
w cl le tr p
a)
e in nt ns co
D
th k ( de f i es
1 1 1 1 1 1 1 1 1 1 1 1 1
of or stu e o tat
ity s w g us d S
1 1 1 1 1 1 1 1 1 1 1
is
te f t ss th nite
B B B B
e rt ss fo U
gr hi in e
th a a ly by
A A A A
k
in o e r
y y p d le d
1 1 1 1 1 1 1 1
ro n an o te
st f a s d s ec
de o rse de ot
D D D D
ill le u vi pr
w r sa co pro is
o eir is rk
a b c d
th nd wo
a his
T
a C C C
1 1 1 1 1
1 1 1 1 1 1 1
B B B
A A A
1 1 1 1 1
D D D
e f g
b)
ab)= AC + ABD + ABD + ABC
ba=
=AC
AB
+ +ABC
BD++
ACD
ABD++ACD
AB C
cb=
= AB
AB ++ BC
B C++AD
A C D + ACD
dc= B+ B +
A
= ABCD C ABC
+ AD+ ABD + ABC + ACD
ed= BCD ++ACD
A
= BCD AB C + A B D + A BC + ACD
fe=
=BC D+
ABC + ABD
ACD + ABC + ACD
f=ABC + ABD
g = ABC + ABC ++A BC ++ ACD
ABC ACD
g=ABC + ABC + A BC + ACD
c)c)The
Thefollowing
followinggate
gateinput counts
input include
counts input
include inverters
input and and
inverters shareshare
ANDAND
gates.
gates.
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
3-13.
X Hierarchy
X
Y Y W
W=XZ + YZ
Z
Z
Hierarchy
X
Y W F = A(CE + DE) + AD
Z
Hierarchy
Hierarchy
X
X
Y W G = B(CE + DE) + BC
Y W
Z
Z
3-14.
Hierarchy
X
Y H G
G = A(BC
A(BC+ +BD)+ A(BC
BD) + A(BC +BD)
+ BD)
Hierarchy
Z = ABC + ABD + ABC + ABD
X = ABC + ABD + ABC + ABD
Y H
Z BC+BD
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
Hierarchy
.
r
BC+BD
or ud a uc y
w cl le tr p
Y H
e in nt ns co
Z
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
3-15.+
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
a) b) c) c)
de o rse de ot
ill le u vi pr
Part b requires 6 fewer gates.

w r sa co pro is
Part b requires 6 f ewer gates.

o eir is rk
th nd wo
a his
T
3-16.
AA A AA A
BB B
BB B CC C
CC C
DD D GG G
EE E GG G
DD D
FF F EE E
a)a)Original circuit
a) Original FF F
Original circuitcircuit
a) Original circuit b)b)Replacement
Replacement with
withequiv
b) Replacement withalents
equiv equiv
alentsalents
b) Replacement with equivalents
AA A
BB B
CC C
GG G
DD D
EE E
FF F
c)c)Cancel inv
inverters
c) Cancel
Cancel inv erters
erters
c) Cancel inverters
3-17.
A
)
eb
A A
er or in ing
ed id n
W
no the iss tea s
A
itt W tio
B B w
t p W em ch
A
e
d on g. in t la
m ld a
AB C B
A C
A BC D G BC D
.
r
or ud a uc y
CD E
w cl le tr p
B G B CD
e in nt ns co
G
C DE F G D E G
th k ( de f i es
EF C
D
of or stu e o tat
G D E G
a) Original circuit
ity s w g us d S
E F a) Original circuit E
a) Original circuit G
is
te f t ss th nite
F E F
a) Original circuit
e rt ss fo U
F
gr hi in e
a) Original circuit
th a a ly by
F b) Replacement with equiv alents

in o e r
y y p d le d
ro n an o te
A F b) Replacement with equiv alents

st f a s d s ec
A A b) Replacement
b) Replacement withwithequiv
equivalents
alents
de o rse de ot
B A
ill le u vi pr
A b)BReplacement with equiv alents

B
w r sa co pro is
A C A
B
o eir is rk
BC A C
th nd wo
D BC
B CD D
a his
BG CD G G
T
C D E
E G
D E GC DE
E G D G
E F E G
F E F
F c) Manipulate inv erters F
c) Manipulate inv erters F d) Cancel inv erters
F d) Cancel inv erters
c) Manipulate inv erters F
c) Manipulate inv erters d) Cancel inv erters
c) Manipulate inverters d) Cancel inverters
d) Cancel inv erters
3-18.
a) Using Inverter, 2NAND, 3NAND and 4NAND gates.
1) Original circuit using AND, OR, Inverter
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
2) Mapped to Inverter, 2NAND, 3NAND, and 4NAND

e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
b) Using Inverter and 2NAND gates. There is not a one to one correspondence to the above schematics because common terms with only
y y p d le d
ro n an o te
st f a s d s ec
two literals become available ( AB,BC )

de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
3-19.
For original circuit, see 3-18 part (a) above.
a) Mapped to Inverter, 2NOR, 3NOR, and 4NOR
b) Mapped to 2NOR and Inverter
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
3-20.
X T 1  XY T1 = X Y
T2 T2 = X Y
T1 F T 2  XY T3 = X Y
T3
Y T 3  XY F = XY + X Y
F  XY  XY
Y0 = ABCE Except f or G1 = 1 and G2A and G2B = 0,

3-21.
G1 Y1 = ABCE Except forthe
G1 outputs Y 0 through Y 7 are all 1’s. Oth
= 1 and G2A and G2B =
Y 0 = ABCE erwise, one of Y7
Y 0are
through
Y2 = ABCE 0, the outputs Y0 through all 1’s. Y 7 is equal to 0
G2A E Y 1= ABCE Oth-erwise, one of Y0 through Y71.isThe output that is
with all others equal to
Y3 = ABCE
equal to 0 equal
with alltoothers
0 hasequal
index i =The
to 1. decimal v alue of
G2B Y2
Y4 == ABCE
ABCE output thatthe
is vequal
aluestoof0 has
(A,B,C)
indexini binary
= . E.g., if
Y5 ==
ABCE (A,B,C)
decimal value of the= (1,1,0),
values ofthen Y 6 = 0.
(A,B,C)
 G2A  G2B Y3 ABCE
E =EG1
= G1  G2A  G2B in binary. E.g., if (A,B,C) = (1,1,0), then
Y6 = ABCE
Y 4 = ABCE Y6 = 0.
Y7 = ABCE
Y 5 = ABCE
Y 6 = ABCE
Y 7 = ABCE
8
3-22.
3-23.
a)
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
b) Treating the input values 1010-1111 as don’t cares changes the behavior for those values:
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
a  A  C  BD  BD, b  B  CD  CD, c  B  C  D, d  A  CD  BC  BD  BCD,

The equations in this case are:
e  BD  CD, f  A  CD  BC  BD, g  A  BC  BC  CD
3-24. *
a) b)
VDD
F7 A G7
F6 A G6
F5 0 G5
F4 1 G4
F3 A G3
F2 A G2
F1 1 G1
F0 1 G0
3-25.
a) b)
VDD VDD
F7 G7
3
2
F6 G6
A F5 8 G5
F
F4 G4
F3 1 G3
0
F2 G2
F1 G1
F0 G0
3-26.
a) b)
11 5
9 4 4
12 6 G(3:0) 7:4 8
7 3
F 5 2 G 4 H
3 F(3:0) 3:0
1
1 0
3-27.
A =  S 0  S1  S 2  SA3 S( S40 SS51  S+2 M
 S3  S4  S5  M S5
) S4
L = A L  A S3
S2
)
eb
S1
 S2 AS ( S  S  S 2 M S3  S 4  S 5  M
er or in ing
ed id n
V = A =  S0  S1 V 3  S04  S1 5  +
W
no the iss tea s
itt W tio
S0 w
t p W em ch
e
d on g. in t la
m ld a
C V M
C = V L
.
r
or ud a uc y
w cl le tr p
V
e in nt ns co
C
th k ( de f i es
of or stu e o tat
ity s w g us d S
3-28.
is
te f t ss th nite
e rt ss fo U
DECODER
gr hi in e
th a a ly by
A0 A0 0
k
D0
in o e r
y y p d le d
A1 A1 1
ro n an o te
st f a s d s ec
A2 A2 2
de o rse de ot
3 D1
ill le u vi pr
4
w r sa co pro is
5
o eir is rk
D2
th nd wo
6
7
a his
T
D3
D4
D5
D6
D7
DECODER D8
A3 A0 0
A1 1
A2 2 D9
3
4
5 D 10
6
7 D 11
D 12
D 13
D 14
D 15
10
3-29.
DECODER
A0 A0 0 D0
A1 A1 1 D1
2 D2
DECODER
A2 A0 0 En 3 D3
A3 A1 1
2 DECODER
EN EN 3 A0 A0 0 D4
A1 A1 1 D5
2 D6
En 3 D7
DECODER
A0 A0 0 D8
A1 A1 1 D9
2 D10
En 3 D11
DECODER
A0 A0 0 D12
A1 A1 1 D13
2 D14
En 3 D15
3-30.*
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
11
3-31. (Errata: Replace “4” with “3” in “4-to-6-line decoder”)

DECODER
A0 A0 0
A1 A1 1 D0
2
3 D1
D2
DECODER D3
A2 A0 0
1
D4
D5
3-32. a) The Truth Table:
)
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Note: a = g, b = f , and c = e.
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e
d on g. in t la
X 2Truth
X 1 Table:
X0 a b c d e f g
m ld a
a) The Note: a = g, b = f, and c = e.
0 0 0 d d d d d d d
.
r
or ud a uc y
DECODER
w cl le tr p
X2 X01 X00 1 a 0b 0c 0 d 1 e 0f 0
g 0 X0 A0 0
e in nt ns co
1 a
X1 A1
th k ( de f i es
0 0 0 1 0 0 d 1d 0d 0 d 0 d 0 d 0
d 1
2
g
of or stu e o tat
0 1 1 1 0 0 1 0 0 1 X2 A2
ity s w g us d S
3
0 0 1 0 0 0 1 0 0 0 b
1 0 0 1 1 0 0 0 1 1 4
is
te f t ss th nite
f
0 1 1 0 0 1 1 10 10 0 0 1 0 0 0 1 5 c
e rt ss fo U
1 1 e
gr hi in e
6
th a a ly by
a)
0 The 1 Truth
1 Table:
k
1 1
0 0 10 1 0 1 0 1 1 Note: a = g, b =7 f , and c = e.
in o e r
y y p d le d
d
ro n an o te
1X 2 10X 1 1
0X 0 1
1a d
1b d
0c d0d d 0e d1f d
1g d
st f a s d s ec
de o rse de ot
ill le u vi pr
10 00 10 1d 1d 0d 1d 0d 1d 1d
w r sa co pro is
DECODER
b) A = {d}
1 10 10 A X B XX0 0 C X0 D X0
1 0 1 0B =0{a,g} 1 0 0 1 01 0 1 0 10
o eir is rk
0 A0
th nd wo
X1 A1 1 a
0 1C = {c.0 e} 1 0 0 d 01 0 0 1 d d g
1 1 D =1{b, f}d d d d d d d
a his
X2 A2 2 d
0 1 1 1 0 0 1 0 0 1
T
1 3
1 b
1 0 0 1 1 0 01 0 1 1 4 f
b) 1A =0{d}1 1 1 0 1 d 0X 1 1 1 1 d
X1 5
1 d
X1 c
e1 d
X1
6X
1B =1{a,g}0 1 1X 2 1 0 1 1 1 X2
7 2
X2
d1
1 1 1 d d d d1 d d
C = {c.e} d 1 1
D = {b, f}
A = X0 B = X1 + X2 C = X1X 2 D = X2
b) A = {d} A X0 B X0 C X0 D X0
B = {a,g} Gate input cost: b = 4 compared to a = 27 + 11 = 38
C = {c. e} d 1 d d d
D = {b, f}
1 1 1
X1 X1 X1 X1
d 1 d d
X2 X2 X2 1 X2 1 d
1 1 1 1
A = XX00 BB
=X1X+1 X2X 2 =
CC X1X
X12X 2 DD = X
X22
Gate input cost: b = 4 compared to a = 27 + 11 = 38
Gate input cost: b = 4 compared to a = 27 + 11 = 38
12
3-33.
A0
D0
A1 D1
D2
A2 D3
D4
D5
D6
D7
EN
3-34.
K-Map for GE5: BCD = (C3,C2, C1, C0)
)
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C1
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d on g. in t la
m ld a
.
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or ud a uc y
w cl le tr p
e in nt ns co
1 1 1
th k ( de f i es
C2
of or stu e o tat
d d d d
ity s w g us d S
C3
is
te f t ss th nite
1 1 d d
e rt ss fo U
gr hi in e
th a a ly by
C0
in o e r
y y p d le d
ro n an o te
GE5 = C3 + C2 (C1 + C0)

st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
C2
o eir is rk
C1 GE5
th nd wo
C0 C3
a his
T
Equations for output logic:

P0 = D0 + GE5·D1
P1 = D2 + GE5·D1
P2 = D3 + GE5·D4
P3 = D5 + GE5·D4
P4 = D6 + GE5·D7
P5 = D8 + GE5·D7
P6 = D9 + GE5·D10
P7 = D11 + GE5·D10
P8 = D12+ GE5·D13
P9 = D14 + D15 + GE5·D13
13
3-35.*
D3 D2 D D A1 A V A1 D1
D3 1D2 D0 1 D0 A 10 A0 V D0
X A1
0 0 0 0 0 00 X0 XX X0 0 D1
X X X X X 1X 01 00 01 1 1
X X 1 0 0 1 1 D2 D2
X X 1 0 0 1 1 1 A0
X 1 0 0 1 0 1 D3
X 1 1 0 0 00 10 10 11 1 1
1 0 V
V = 0D 0 +0 D1 1+ D 21+ D13 D0 D3
A0 D1
V A
D00 = DD
1 
0 D21+D
D32 
X 1
A0 AD
1 0 (=D1D0 D 12
1
A1  D0 D1 D2
1
D3
1 1
D0
3-36.
Decimal Inputs Binary Outputs
9 8 7 6 5 4 3 2 1 0 A3 A2 A1 A0 V
)
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0 0 0 0 0 0 0 0 0 0 X X X X 0
e
d on g. in t la
m ld a
0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
.
r
or ud a uc y
w cl le tr p
e in nt ns co
0 0 0 0 0 0 0 0 1 X 0 0 0 1 1
th k ( de f i es
of or stu e o tat
ity s w g us d S
0 0 0 0 0 0 0 1 X X 0 0 1 0 1
is
te f t ss th nite
e rt ss fo U
0 0 0 0 0 0 1 X X X 0 0 1 1 1
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
0 0 0 0 0 1 X X X X 0 1 0 0 1
st f a s d s ec
de o rse de ot
ill le u vi pr
0 0 0 0 1 X X X X X 0 1 0 1 1
w r sa co pro is
o eir is rk
th nd wo
0 0 0 1 X X X X X X 0 1 1 0 1
a his
T
0 0 1 X X X X X X X 0 1 1 1 1
0 1 X X X X X X X X 1 0 0 0 1
1 X X X X X X X X X 1 0 0 1 1
3-37.
a) b)
DECODER
S0 A0 0
S1 A1 1 I0
4x1 MUX
S2 A2 2
3 I1 S0 S0
4 S1 S1
5 I0 0 Y
6 I2 I1
7 1
I2 2 2x1 MUX
I3 I3 3 S2 S
Y Y Y
4x1 MUX
0
I4 1
S0 S0
S1 S1
I5
I4 0 Y
I5 1
I6 I6 2
I7 3
I7
14
3-38.
)
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d on g. in t la
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.
r
3-39.
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
DECODER
ity s w g us d S
S0 A0 0
is
te f t ss th nite
S1 A1 1 IA0
e rt ss fo U
S2 A2 2
gr hi in e
th a a ly by
3
k
IA1
in o e r
y y p d le d
4
ro n an o te
st f a s d s ec
5
de o rse de ot
6 IA2
ill le u vi pr
7
w r sa co pro is
o eir is rk
th nd wo
IA3
YA
a his
T
IA4
IA5
IA6
IA7
IB0
IB1
IB2
IB3
YB
IB4
IB5
IB6
IB7
15
3-40.
3-41.
)
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d on g. in t la
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.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
3-42.*
8x1 MUX
D(7:0) D(7:0) Y
0
A(2:0) S(2:0)
8x1 MUX
D(14:8) D(6:0) Y
0
D(7)
S(2:0)
A(3)
3 OR gates
16
3-43.*
A1 A0 E D0 D1 D2 D3 Consider E as the data input and A0, A1 as the
0 0 0 0 0 0 0 select lines. For a given combination on (A1,
0 0 1 1 0 0 0 A0), the value of E is distributed to the
0 1 0 0 0 0 0 corre-sponding D output. For example for
0 1 1 0 1 0 0 (A1, A0) = (10), the value of E appears on D2,
1 0 0 0 0 0 0 while all other outputs have value 0.
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
3-44.
DECODER
X A0 0
1 F1
Y A1
Z A2 2
3
4 F2
5
6
7 F3
3-45.
)
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d on g. in t la
m ld a
a) LR = LT·BL + LT·BR + EM·BL = BL·(LT + EM) + LT·BR
RR = R
a) LR  LT·BL T·BL + RT·BR
LT·BR + EM·BL
 EM·BL = BR·(R
 BL·(LT TEM)
+ EM) + RT·BR
 LT·BR
.
r
or ud a uc y
w cl le tr p
e in nt ns co
RR b)RT·BL+RT·BR  EM·BL
inputsonBR·(RT  EM)  RT·BR
th k ( de f i es
Maximum of four ORgates assumed.

of or stu e o tat
ity s w g us d S
is
te f t ss th nite
b) Maximum of four inputs on OR gates assumed.

LT EM BR BL LR
e rt ss fo U
gr hi in e
th a a ly by
LT EM 0 BR0 BL0 0
LR 0
in o e r
y y p d le d
ro n an o te
0 0 0 00 10 0
st f a s d s ec
0 0
de o rse de ot
0 0 1 0 1
ill le u vi pr
0 0 0 1 0
w r sa co pro is
0 0 1 1 1
o eir is rk
0 0 0 1 1 00 01
th nd wo
0
a his
0 0 0 1 1 10 11 1 LR
T
0 1 0 0 1 01 00 1
0 1 0 0 1 11 11 1
1 0 0 0 0
0 1 1 0 1
1 0 0 1 1
0 1 1 1 0 11 01 0
1 0 1 0 0 01 10 1
1 0 1 0 1 10 01 0 For For
RR, RR,
samesame
circuit with L
Twith
replace by RT. by RT.
circuit LT replace
1 0 1 1 1 00 10 1
1 1 1 0 0
1 0 1 1 1
1 1 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
17
3-46.
A B C D F 8 x 1 MUX
A B C D F C S0
0 0
0
0
0
0
0 0 0
0 F0 B S1
0 0 00 F=0 A S2
0 011 00
D0
0 0 0 10 100 11 Y F
0 0 1 1 0
FF=DD D D1
0 0 1 1 0 D2
VDD D3
0 1 0 0 1
0 1 01 001 01
F =D D4
0 FD D5
0 1 0 01 110 10 D6
0 1 1 1 0
F =D D7
0 1 1 0 1
1 0 0 0 0 FD
0 1 1 10 011 10
F=D
1 0 1 00 100 10
1 0 1 1 1
FF = D
1
1 0 0 1 1
1 1 0 0 0
1 0 1 11 001 01
F=0
F 1
1 0 1 11 110 01
1 1 1 1 1 F =D
1 1 0 0 0
F0
1 1 0 1 0
1 1 1 0 0
FD
1 1 1 1 1
)
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d on g. in t la
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3-47.*
.
r
or ud a uc y
w cl le tr p
e in nt ns co
A B AC B D C FD C
th k ( de f i es
F
D
of or stu e o tat
0 0 00 0 0 0 00 0
ity s w g us d S
0 0 0 1 1
is
te f t ss th nite
0 0 0 1 1 F=D
0F  D
e rt ss fo U
0 0 1 0
gr hi in e
th a a ly by
4 x 1 MUX
k
0 0 0 0 1 01
1 0 1
in o e r
y y p d le d
S0
ro n an o te
B
0 0 01 1 1 0 10 1
st f a s d s ec
A S1
de o rse de ot
0 1 0 1 0
ill le u vi pr
0 1 0 0 1 F=C D D0 Y F
w r sa co pro is
0 1 1 0 0 VDD D1
o eir is rk
0 1 0 1 1 01
0 1 D2
th nd wo
0
F0  CD D3
a his
0 1 11 0 0 0 00
T
0 1 11 0 1 0 01 0
1 0 1 0 0
F=C D
1 0 0 0 0
1 0 1 1 1
1 0 10 1 1 0 00 1
11 1 0 0 01 F1  CD
1 0
1 1 1 0 1
F=1
1 0 1 1 1
1 1 1 1 1
1 1 0 0 1
1 1 0 1 1
F 1
1 1 1 0 1
1 1 1 1 1
18
3-48.
DECODER
D A0 0
C A1 1
B A2 2
3
4
5
6
A EN 7
DECODER
F
D A0 0
C A1 1
B A2 2
3
4
5
6
EN 7
3-49.
S0  C0 A0 B0  C0 A0 B0  C0 A0 B0  C0 A0 B0 C1  C0 A0  A0 B0  C0 B0
S1  C1 A1 B1  C1 A1 B1  C1 A1B1  C1 A1B1 C2  C1 A1  A1B1  C1B1
S1  C0 A0 A1 B1  A0 B0 A1 B1  C0 B0 A1 B1 C2  C0 A0 A1  A0 B0 A1  C0 B0 A1
C0 A0 B1  A0 B0 B1  C0 B0 B1  A1B1
)
 C0 A0 A1 B1  A0 B0 A1 B1  C0 B0 A1 B1
eb
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d on g. in t la
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C0 A0 A1B1  A0 B0 A1B1  C0 B0 A1B1
.
r
C0 A0 A1B1  A0 B0 A1B1  C0 B0 A1B1

or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
* These are the three equations for the outputs. The logic diagram consists of a sum-of-products implementation of these equations.
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
3-50.*
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
C1  T3  T2  T1C0  T2  A0 B0 C0  A0  B0  ( A0  B0 )C0  A0 B0  ( A0 B0  C0 )( A0  B0 )
w r sa co pro is
o eir is rk
th nd wo
C1  A0 B0  A0C0  B0C0
a his
T
S0  C0  T4  C0  TT
1 2  C0  A0 B0 ( A0  B0 )  C0  ( A0  B0 )( A0  B0 )  C0  A0 B0  A0 B0
S0  A0  B0  C0
T3
T1
T4
T2
3-51.*
Unsigned 1001 1100 1001 1101 1010 1000 0000 0000 1000 0000
1’s Complement 0110 0011 0110 0010 0101 0111 1111 1111 0111 1111
2’s Complement 0110 0100 0110 0011 0101 1000 0000 0000 1000 0000
19
3-52.
a) 11010 b) 11110 c) 1111110 d) 101001
+ 01111 + 10010 + 0000010 + 111011
01001 10000 0000000 100100
3-53.
a) 11010 b) 11110 c) 1111110 d) 101001
+ 01111 + 00010 + 0000010 + 000011
01001 00000 0000000 101100
3-54.*
+36 = 0100100 36 0100100
- 24 = 1101000 +(–24) + 1101000
- 35 = 1011101 10001100
= 12 = 0001100
–35 1011101
- (–24) + 0011000
= –11 = 1110101
)
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d on g. in t la
m ld a
3-55.
.
r
or ud a uc y
w cl le tr p
a) b) c) d)
e in nt ns co
D
th k ( de f i es
100111 -25 0010011 11 110001 -15 101110 -18

of or stu e o tat
+ 111001 -7 + 100110 -26 + 101110 -18 + 001001 9

ity s w g us d S
is
te f t ss th nite
100000 -32 110001 -15 011111 -33 110111 -9

e rt ss fo U
Overflow
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
3-56.+
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a) H  D
a his
G C D A B C D E F G H
T
0 0 0 0 0 0 0 0
F  BC  BD  BCD 0 0 0 1 1 1 1 1
E  AB  ABCD  AC  AD 0 0 1 0 1 1 1 0
0 0 1 1 1 1 0 1
b) Bit Cin S Cout S  Bit  Cin 0 1 0 0 1 1 0 0
0 1 0 1 1 0 1 1
0 0 0 0 Cout  Bit  Cin
0 1 1 1 0 1 1 0 1 0 1 0
1 0 1 1 0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
1 1 0 1 1 0 0 1 0 1 1 1
1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1
c) Using shared inverters, XOR cost = 6. Gate input cost for a = 4 + 0 + 6 + 10 + 14 = 34 Gate input cost for
b = 4 x (2 + 6 + 2) = 40 In terms of gate cost, a is the better design.
20
3-57.
A3 A2 A1 A0
C4 S3 S2 S1 S0
3-58.
B0  1 Cin  0
S0  A0  1  0  A0
C0  A0  1  0( A0  1) A0
B1  S
B2  S
B3 7  S
Bits 1-6 use regular full adder/subtractor logic. For bit 7, the carry logic is omitted.
)
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no the iss tea s
itt W tio
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t p W em ch
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d on g. in t la
m ld a
.
r
A7 A6 A5 A4 A3 A2 A1 A0
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
B A B A B A B A B A B A B A
is
te f t ss th nite
FA Cin Cout FA Cin C out FA Cin Cout FA Cin Cout FA Cin Cout FA C in Cout FA Cin
e rt ss fo U
gr hi in e
S S S S S S S
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
S7 S6 S5 S4 S3 S2 S1 S0
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
3-59.
a his
Proceeding from MSB to LSB: A  B if Ai  Bi ( Ai Bi  1) and for all j  i, Aj  B j ( Aj B j  Aj B j  1) Based on the above,
T
X  A3 B3  ( A3 B3  A3 B3 ) A2 B2  ( A3 B3  A3 B3 )( A2 B2  A2 B2 ) A1B1
( A3 B3  A3 B3 )( A2 B2  A2 B2 )( A1B1  A1B1 ) A0 B0
21
3-60.+
B A
Cout
B Cout
Cin Cin
A3
X B3 A2
C4 B2 A1
C3 B1 A0
C2 B0
+
C1 Logic 0
3-61.
In a subtractor, the sum is replaced by the difference and the carry is replaced by the borrow. The borrow at
Inany given point
a subtractor is asum
, the 1 onlyisifreplaced
in the LSB bydirection
the dif fromand
f erence thatthe
point, A B
carry is. replaced by the .borrow
The borrow at any given point is a 1 only if in the LSB direction from that point,in
Only borrow logic is needed to produce X, so the difference logic is discarded A <contraction.
B. The remaining
equation for borrow into the i + 1 position is: Bri 1  Ai Bi  Ai Bri  Bi Bri for i = 0,1,2,3. Br0  0 giving
Only borrow logic is needed to produce X, so the diff erence logic is discarded in contrac
Br1  A0remaining
tion.The B0 When the equation 4  1, then
borrowforBrborrow  B.i +Thus,
intoAthe 1 position
X = Bris:
Br i+ 1 =resulting
4. The Ai Bi + Acircuit
i Bri +Bi Bri the borrow logic
using
for
is: i = 0,1,2,3. Br = 0 giving Br = A 0 B When the borrow Br 4 = 1, then A < B. Thus,
)
0 1 0
eb
er or in ing
X = Br 4 . The resulting circuit using the borrow logic is:
ed id n
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no the iss tea s
itt W tio
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t p W em ch
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d on g. in t la
m ld a
B3 A3 B2 A2 B1 A1 A0 B0
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
Bi Ai Bi Ai Bi Ai
of or stu e o tat
ity s w g us d S
X Bri+1 Bri Bri+1 Bri Bri+1 Bri

is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
3-62.+
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
This problem requires two decisions: Is A > B? Is A = B? Two “carry” lines are required to build an iterative
a his
circuit, Gi and Ei. These carries are assumed to pass through the circuit from right to left with G0 = 0 and E0 = 1.
T
Each cell has inputs Ai, Bi, Gi, and Ei and outputs Gi+1 and Ei+1. Using K-maps, cell equations are:
Ei 1  Ai Bi Ei  Ai Bi Ei
Gi 1  Ai Bi Ei  ( Ai  Bi ) Ei
Using multilevel circuit techniques, the cost can be reduced by sharing terms:
Ei 1  ( Ai Bi  Ai Bi ) Ei B3 A3 B2 A2 B1 A1 B0 A0
Ei+1 = (Ai Bi + Ai Bi ) Ei
Gi 1  ( Ai Bi  ( Ai Bi )Gi
Gi+1 = (Ai Bi + (Ai Bi ) Gi Ei+1 Bi Ai E Ei+1 Bi Ai E Ei+1 Bi Ai Ei Ei+1 Bi Ai Ei
E4 i E0 = 1
G4 Gi+1 Gi Gi+1 Gi Gi+1 Gi Gi+1 Gi G0 = 0
22
3-63.+
Circuit Diagram:
Control Logic A 3 A2 A1 A 0 B3 B2 B1 B0
Adder/Subtractor
Add/Subtract
A4 SignA Sub
B4 SignB
Sub/Add 2’s Complementer
S/A
Cout 4-bit Adder Cin 0

S3 S2 S1 S0
Control Logic
ResultCorrection
SignA
Sub Corr 2’s Complementer
Cout Sign
S4 S3 S2 S1 S0
Control Logic Truth Tables
Control Logic Truth Tables Sub Sub A 
= S/  SignA
S/ASignA   SignB
SignB
Inputs Inputs Inputs Inputs = SubCout
Corr Corr Sub Cout
S/A Sign A SignB Sub Sub SignA Cout Corr Sign Over
Overflow Sign Sign  SignA
= SignA  Corr
 Corr
S/A SignA SignB Sub Sub SignA Cout Corr Sign
flow0
0 0 0 0 0 0 0 0 0 Overflow
Overflow Cout
= Sub Sub Cout
0 0 0
1 01 0 0 0 00 01 0 0 0 00 01
)
eb
0 1 01 1 0 1 10 00 1 0 0 10 10
er or in ing
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0 1 1 10 0 0 1 10 11 0 0 0 11 01
e
0
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1 0 0
0 11 1 1 0 00 10 1 1 0 11 10
.
r
1 0 1 00 0 1 1 01 01 0 0 1 01 00
or ud a uc y
w cl le tr p
1
e in nt ns co
1 1 0 0 1 1 0 1 0 0
1 0 1 0 1 0 1 0 0 0
th k ( de f i es
1 1 1 1 1 1 1 0 1 0
of or stu e o tat
1 1 0 0 1 1 0 1 0 0
ity s w g us d S
1 1 1 1 1 1 1 0 1 0
is
te f t ss th nite
e rt ss fo U
gr hi in e
3-64.*
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
S A B C4 S3 S2 S1 S0
de o rse de ot
ill le u vi pr
a) 0 0111 0111 0 1 1 1 0
w r sa co pro is
o eir is rk
b) 1 0100 0111 0 1 1 0 1
th nd wo
c) 1 1101 1010 1 0 0 1 1
a his
T
d) 0 0111 1010 1 0 0 0 1
e) 1 0001 1000 0 1 0 0 1
23
3-65.
-- Full Adder: Structural VHDL Description
-- (See Figure 4-28 for logic diagram)
library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; --X is input vector (A0, B0, C0).
entity full_adder_st is
port(X: in std_logic_vector(0 to 2);
C1, S0: out std_logic);
end;
architecture logic of full_adder_st is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component NAND2
port(in1, in2: in std_logic;
end component;
component NOR2
end component;
component AND2
)
eb
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end component;
.
r
or ud a uc y
component XOR2
w cl le tr p
e in nt ns co

th k ( de f i es
of or stu e o tat

ity s w g us d S
end component;
is
te f t ss th nite
signal S: std_logic_vector(0 to 6); -- S(0 to 6) is the vector of six gate output signals
e rt ss fo U
gr hi in e
th a a ly by
-- from upper left to lower right.

in o e r
y y p d le d
ro n an o te
--The following is the circuit netlist.

st f a s d s ec
de o rse de ot
begin
ill le u vi pr
w r sa co pro is
g0: NAND2 port map (X(1), X(0), S(0));

o eir is rk
th nd wo
g1: NOR2 port map (X(1), X(0), S(1));

a his
g2: NOT1 port map (X(2), S(2));

T
g3: AND2 port map (S(0), S(2), S(3));

g4: NOT1 port map (S(1), S(4));
g5: NOT1 port map (S(2), S(5));
g6: AND2 port map (S(0), S(4), S(6));
g7: NOR2 port map (S(1), S(3), Z(1));
g8: XOR2 port map (S(6), S(5), Z(0));
end logic;
24
3-66.
The solution
Thegiven is very
solution thorough
giv en is v erysince it checks
thorough each
since of the carry
it checks eachconnections between
of the carry adjacentbetween
connections cells transferring
adjacent 0cells
and 1. In transferring
contrast a test applying
0 and C0 = 1aand
1. In contrast testAapplying
= 15 with
C0 B= 1=and
0 would
A = 15allow a=
with B whole variety
0 would allowofa incorrect
whole connections
variety
between cells of would
that incorrect
notconnections
be detected.between cells that would not be detected.
)
eb
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ed id n
3-67.*
W
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.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
The solution given is very thorough since it checks each of the carry connections between adjacent cells transferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
25
3-68.+
-- prob_4-30 adder-subtractor with overflow detection
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_unsigned.all;
entity addsubov is
port(A,B: in std_logic_vector(3 downto 0);
S: in std_logic;
SD: out std_logic_vector(3 downto 0);
C, V: out std_logic);
end addsubov;
architecture behavior of addsubov is
signal Y: std_logic_vector(3 downto 0);
signal temp4: std_logic_vector(3 downto 0);
signal temp2: std_logic_vector(4 downto 3);
signal CI: std_logic_vector(4 downto 3);
begin
with S select
Y(2 downto 0) <= B(2 downto 0) when '0',
not B(2 downto 0) when '1',
"XXX" when others;
with S select
Y(3) <= B(3) when '0',
not B(3) when '1',
)
eb
'X' when others;
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no the iss tea s
itt W tio
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temp4 <= ('0' & A(2 downto 0)) + ('0' & Y(2 downto 0)) + ("000" & S);
e
d on g. in t la
m ld a
CI(3) <= temp4(3);
.
r
or ud a uc y
temp2 <= ('0' & A(3)) + ('0' & Y(3)) + ('0' & CI(3));
w cl le tr p
e in nt ns co
CI(4) <= temp2(4);

th k ( de f i es
of or stu e o tat
SD <= (temp2(3) & temp4(2 downto 0));

ity s w g us d S
C <= CI(4);
is
te f t ss th nite
V <= CI(4) xor CI (3);

e rt ss fo U
gr hi in e
th a a ly by
end behavior;
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0 and 1.
In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections between cells
that would not be detected.
26
3-69.
// Full Adder: Structural Verilog Description
// (See Figure 4-28 for logic diagram)
module full_adder_st(C1, S0, X);
input [2:0] X; //X is the vector of inputs (A0, B0, C0).
output C1, S0;
wire [0:6] N; //N[0:6] is the six bit vector of gate
//outputs from upper left to lower right.
//The netlist for the gate types:
nand
gna(N[0],X[1],X[0]);
nor
gno1(N[1],X[1],X[0]),
gno2(C1,N[1],N[3]);
not
gn0(N[2], X[2]),
gn1(N[4], N[1]),
gn2(N[5], N[2]);
and
ga0(N[3], N[0], N[2]),
ga1(N[6], N[0], N[4]);
xor
gx(S0, N[5], N[6]);
)
eb
endmodule
er or in ing
ed id n
W
no the iss tea s
itt W tio
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t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
3-70.
a his
T
27
3-71.*
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
3-72.
)
eb
er or in ing
ed id n
W
no the iss tea s
// Adder-Subtractor Behavioral Model
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
module addsub_4b_v (S, A, B, SD, C4);
.
input[3:0] A, B;
r
or ud a uc y
w cl le tr p
e in nt ns co
input S;
th k ( de f i es
output[3:0] SD;
of or stu e o tat
ity s w g us d S
output C4;
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
assign {C4, SD} = S?(A - B):(A + B);

k
in o e r
y y p d le d
ro n an o te
endmodule
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
28

Chapter03 Solutions-5th

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Chapter03 Solutions-5th

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Problem Solutions – Chapter 3

input combinations as don’t cares:

G1G0 G1G0 G1G0 G1G0

G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10

B0  G3G0  G2G1G0  G2G1 G0

b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30

ABCD GNS YNS ABCD

1011 0 0 1000 1 0 1 0 1 0 0 00 1 RNS = A + BCD REW = A + BCD

RNS = A + BCD REW = A + BCD

1001 0 0 1 0 1 0 RNS  A  BCD REW  A  BCD

Part b requires 6 fewer gates.

Part b requires 6 f ewer gates.

F b) Replacement with equiv alents

A F b) Replacement with equiv alents

A b)BReplacement with equiv alents

1) Original circuit using AND, OR, Inverter

2) Mapped to Inverter, 2NAND, 3NAND, and 4NAND

two literals become available ( AB,BC )

b) Mapped to 2NOR and Inverter

Y0 = ABCE Except f or G1 = 1 and G2A and G2B = 0,

a  A  C  BD  BD, b  B  CD  CD, c  B  C  D, d  A  CD  BC  BD  BCD,

3-31. (Errata: Replace “4” with “3” in “4-to-6-line decoder”)

3-32. a) The Truth Table:

GE5 = C3 + C2 (C1 + C0)

Equations for output logic:

Maximum of four ORgates assumed.

b) Maximum of four inputs on OR gates assumed.

C0 A0 A1B1  A0 B0 A1B1  C0 B0 A1B1

100111 -25 0010011 11 110001 -15 101110 -18

+ 111001 -7 + 100110 -26 + 101110 -18 + 001001 9

100000 -32 110001 -15 011111 -33 110111 -9

X Bri+1 Bri Bri+1 Bri Bri+1 Bri

Cout 4-bit Adder Cin 0

port(in1, in2: in std_logic;

out1: out std_logic);

-- from upper left to lower right.

--The following is the circuit netlist.

g0: NAND2 port map (X(1), X(0), S(0));

g1: NOR2 port map (X(1), X(0), S(1));

g2: NOT1 port map (X(2), S(2));

g3: AND2 port map (S(0), S(2), S(3));

CI(3) <= temp4(3);

CI(4) <= temp2(4);

SD <= (temp2(3) & temp4(2 downto 0));

V <= CI(4) xor CI (3);

assign {C4, SD} = S?(A - B):(A + B);

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