Chapter 03 - Solutions

lOMoARcPSD|38429838
Chapter 03 solutions-5th
디지털논리와 컴퓨터설계 (Chungnam National University)
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lOMoARcPSD|38429838
Problem Solutions – Chapter 3
CHAPTER 3
© 2016 Pearson Education, Inc.
3-1.
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
Place a 1 in eac
Y
1 This is the same function as the carry
F = XZ + XY + YZ for the full adder.
X 1 1 1
Z
3-2.*
C
B F = AB + AC
1 1 1 1
A
1 1
)
D
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
an ing rnin tors igh
.
r
3-3.
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
Assuming inputs G3, G2, G1, G0 and outputs B3, B2, B1, B0, with G3 and B3 being the most significant bits, and treating the invalid
is
te f t ss th nite
input combinations as don’t cares:

e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
G1G0 G1G0 G1G0 G1G0

de o rse de ot
G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10

ill le u vi pr
w r sa co pro is
o eir is rk
00 00 00 1 1 00 1 1
th nd wo
a his
01 01 1 1 1 1 01 1 1 01 1 1
T
11 1 1 X X 11 X X 11 X X 11 1 X X
10 X X X X 10 X X X X 10 X X X X 10 X X X X
B0 ý G3G0 û G2G1G0 û G2G1 G0

B3 ý G3 B2 ý G3G2 B1 ý G2G1 û G3G2 G1
û G2 G1G0 û G3G2 G1 G0
3-4. a) For the 3 x 3 pattern, there are exactly three row, three column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 + X4 X5 X6 + X7 X8 X9 + X1 X4 X7 + X2 X5 X8 + X3 X6 X9 + X1 X5 X9 + X3 X5 X7 Gate Input cost = 32
b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30
3-5. a) For the 4 x 4 pattern, there are exactly four row, four column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 X4 + X5 X6 X7 X8 + X9 X10 X11 X12 + X13 X14 X15 X16 + X1 X5 X9 X13 X2 X6 X10 X14 + X3 X7 X11
X15 + X4 X8 X12 X16 + X1 X6 X11 X16 + X4 X7 X10 X13 Gate Input cost = 50
b) W = X1(X2 X3 X4 + X5 X9 X13 + X6 X11 X15) + X7(X5 X6 X8 + X3 X11 X15 + X4 X10 X13) + X9 X10 X 11 X12
+ X13 X14 X15 X16 + X2 X6 X10 X14 + X4 X8 X12 X16 Gate Input Cost = 48
1
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lOMoARcPSD|38429838
3-6.
a) Detecting a change in one-out-of- X1 X2 X3 Z
three inputs can be done using a parity
0 0 0 0
function as Z. The truth table shown is
for even parity. For this case, 0 0 1 1
Z ý X1  X 2  X 3 0 1 0 1
0 1 1 0
If odd parity is chosen, then an
1 0 0 1
alternative result for Z is:
1 0 1 0
Z ý X1  X 2  X 3
1 1 0 0
1 1 1 1
3-7.+
ABCD GNS YNS RNS GEW YEW REW B B

0000 1 0 0 0 0 1 A GNS A GEW
0001 1 0 0 0 0 1
C C
0011 1 0 0 0 0 1
= + GEW = AB + AC
0010 1 0 0 0 0 1 GNS ý AC û AB GEW ý AB û AC
0110 1 0 0 0 0 1
)
eb
0111 1 0 0 0 0 1 A A
er or in ing
ed id n
W
no the iss tea s
itt W tio
w B B
t p W em ch
YNS YEW
e
0101 0 1 0 0 0 1
d on g. in t la
m ld a
C C
0100 0 0 1 0 0 1 D D
.
r
or ud a uc y
YNS = ABCD YEW = ABCD

w cl le tr p
e in nt ns co
1100 0 0 1 1 0 0 YNS ý ABCD YEW ý ABCD

th k ( de f i es
of or stu e o tat
1101 0 0 1 1 0 0
ity s w g us d S
1111 0 0 1 1 0 0 B B
is
te f t ss th nite
C C
e rt ss fo U
1110 0 0 1 1 0 0
gr hi in e
th a a ly by
D D
k
in o e r
y y p d le d
1010 0 0 1 1 0 0 RNS
ro n an o te
A A
st f a s d s ec
1011 0 0 1 1 0 0
de o rse de ot
ill le u vi pr
RNS ý A û BCD REW ý A û BCD

w r sa co pro is
1001 0 0 1 0 1 0
o eir is rk
th nd wo
1000 0 0 1 0 0 1
a his
T
3-8.
A B C S5 S4 S3 S2 S1 S0 S0 ý C
0 0 0 0 0 0 0 0 0 S1 ý 0
0 0 1 0 0 0 0 0 1 S2 ý ABC û ABC
0 1 0 0 0 0 1 0 0 S3 ý ABC û ABC
0 1 1 0 0 1 0 0 1 S4 ý AB û AC
1 0 0 0 1 0 0 0 0 S5 ý AB
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
lOMoARcPSD|38429838
3-9.+
A B C D S2 S1 S0
0 0 0 0 0 0 0
S0 ý BCD û BCD û AB û ACD û ABCD
0 0 0 1 0 0 1
S1 ý AB û AB û ACD û BCD
0 0 1 0 0 0 1
S2 ý ABC û ABD
0 0 1 1 0 1 0
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 1 0
0 1 1 1 0 1 1
1 0 0 0 0 1 1
1 0 0 1 0 1 1
1 0 1 0 0 1 1
1 0 1 1 0 1 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
3-10.
.
r
or ud a uc y
w cl le tr p
W ý AC û BD û BD
e in nt ns co
A B C D W X Y Z
th k ( de f i es
of or stu e o tat
0 0 0 0 0 0 1 1 X ý BCD û BC+BD
ity s w g us d S
0 0 0 1 0 1 0 0
is
te f t ss th nite
Y ý CD +CD
e rt ss fo U
0 0 1 0 0 1 0 1
gr hi in e
th a a ly by
ZýD
in o e r
0 0 1 1 0 1 1 0
y y p d le d
ro n an o te
st f a s d s ec
0 1 0 0 0 1 1 1
de o rse de ot
ill le u vi pr
0 1 0 1 1 0 0 0
w r sa co pro is
o eir is rk
th nd wo
0 1 1 0 1 0 0 1
a his
0 1 1 1 1 0 1 0
T
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1010 to
XXXX
1111
lOMoARcPSD|38429838
3-11.
a) PS LS RS RR PL LL RL PL ý PS
0 0 0 0 0 0 0 LL ý PS LS RS û PS LS RR
0 0 0 1 0 0 0
RL ý PS LS RS û PS RS RR
0 0 1 0 0 0 1 b)
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 1 0 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
)
eb
3-12.
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
C C C C
w cl le tr p
a)
e in nt ns co
D
th k ( de f i es
1 1 1 1 1 1 1 1 1 1 1 1 1
of or stu e o tat
ity s w g us d S
1 1 1 1 1 1 1 1 1 1 1
is
te f t ss th nite
B B B B
e rt ss fo U
gr hi in e
th a a ly by
A A A A
k
in o e r
y y p d le d
1 1 1 1 1 1 1 1
ro n an o te
st f a s d s ec
de o rse de ot
D D D D
ill le u vi pr
w r sa co pro is
o eir is rk
a b c d
th nd wo
a his
T
a C C C
1 1 1 1 1
1 1 1 1 1 1 1
B B B
A A A
1 1 1 1 1
D D D
e f g
b)
a = AC + ABD + ABD + ABC
b = AB + BC + ACD + ACD
c = AB + BC + AD
d = ABCD + ABC + ABD + ABC + ACD
e = BCD + ACD
f = ABC + ABD + ABC + ACD
g = ABC + ABC + ABC + ACD
c) The following gate input counts include input inverters and share AND gates.
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
lOMoARcPSD|38429838
3-13.
X Hierarchy
X
Y Y W
W=XZ + YZ
Z
Z
Hierarchy
X
Y W F = A(CE + DE) + AD
Z
Hierarchy
Hierarchy
X X
W Y W G = B(CE + DE) + BC
Y
Z Z
3-14.
Hierarchy
X
Y H G
G = A(BC +BD)+ A(BC +BD)
Hierarchy
Z
X = ABC + ABD + ABC + ABD
Y H
Z BC+BD
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
Hierarchy
.
r
BC+BD
or ud a uc y
H
w cl le tr p
Y
e in nt ns co
Z
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
3-15.+
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
a) b) c)
de o rse de ot
ill le u vi pr
Part b requires 6 fewer gates.

w r sa co pro is
o eir is rk
th nd wo
a his
T
lOMoARcPSD|38429838
3-16.
A A A
B B
B C C
C
D G
E G G
D D
F E E
a) Original circuit F F
a) Original circuit b) Replacement with equiv
b) Replacement withalents
equiv alents
b) Replacement with equivalents
A A
B B
C C
G G
D D
E E
F F
c) Cancel
c) Cancel inv erters
inv erters
c) Cancel inverters
3-17.
)
eb
A A
er or in ing
ed id n
W
no the iss tea s
itt W tio
B w
t p W em ch
e
d on g. in t la
m ld a
C B
D G C
.
r
or ud a uc y
E
w cl le tr p
D
e in nt ns co
F G
th k ( de f i es
E
of or stu e o tat
ity s w g us d S
a) Original circuit
is
te f t ss th nite
e rt ss fo U
F
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
b) Replacement with equiv alents

st f a s d s ec
b) Replacement
b) Replacement withequiv
with equivalents
alents
de o rse de ot
ill le u vi pr
w r sa co pro is
A A
o eir is rk
th nd wo
B B
a his
C
T
C
D D
G G
E E
F F
c) Manipulate inv erters d) Cancel inv erters

c) Manipulate inverters d) Cancel inverters
lOMoARcPSD|38429838
3-18.
a) Using Inverter, 2NAND, 3NAND and 4NAND gates.
1) Original circuit using AND, OR, Inverter
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
2) Mapped to Inverter, 2NAND, 3NAND, and 4NAND

e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
b) Using Inverter and 2NAND gates. There is not a one to one correspondence to the above schematics because common terms with only
y y p d le d
ro n an o te
st f a s d s ec
two literals become available ( AB,BC )

de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
lOMoARcPSD|38429838
3-19.
For original circuit, see 3-18 part (a) above.
a) Mapped to Inverter, 2NOR, 3NOR, and 4NOR
b) Mapped to 2NOR and Inverter
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
3-20.
X T 1 ý XY
T2
T1 F T 2 ý XY
T3
Y T 3 ý XY
F ý XY û XY
3-21.
G1 Except forthe
G1 outputs Y 0 through Y 7 are all 1’s. Oth
= 1 and G2A and G2B =
Y 0 = ABCE
0, the outputs Y0 through Y7 are all 1’s.
G2A E Y 1= ABCE Oth-erwise, one of Y0 through Y7 is
equal to 0 with all others equal to 1. The
G2B Y 2 = ABCE output that is equal to 0 has index i =
Y 3 = ABCE decimal value of the values of (A,B,C)
  G2A
E = G1   G2B in binary. E.g., if (A,B,C) = (1,1,0), then
Y 4 = ABCE Y6 = 0.
Y 5 = ABCE
Y 6 = ABCE
Y 7 = ABCE
8
lOMoARcPSD|38429838
3-22.
3-23.
a)
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
b) Treating the input values 1010-1111 as don’t cares changes the behavior for those values:
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
a ý A û C û BD û BD, b ý B û CD û CD, c ý B û C û D, d ý A û CD û BC û BD û BCD,

The equations in this case are:
e ý BD û CD, f ý A û CD û BC û BD, g ý A û BC û BC û CD
3-24. *
a) b)
VDD
F7 A G7
F6 A G6
F5 0 G5
F4 1 G4
F3 A G3
F2 A G2
F1 1 G1
F0 1 G0
lOMoARcPSD|38429838
3-25.
a) b)
VDD VDD
F7 G7
3
2
F6 G6
A F5 8 G5
F
F4 G4
F3 1 G3
0
F2 G2
F1 G1
F0 G0
3-26.
a) b)
11 5
9 4 4
12 6 G(3:0) 7:4 8
7 3
F 5 2 G 4 H
3 F(3:0) 3:0
1
1 0
3-27.
 A ý ( S0  S1 ù S2 M
 S3  S4  S5 û M S5
) ø   S4
A LýA S3
S2
)
eb
S1
 ý A ý ( S0 S1  ùS2  S3  S4  S5 û M
er or in ing
ed id n
ø  V
W
no the iss tea s
itt W tio
S0
w
t p W em ch
e
d on g. in t la
m ld a
C ýV M
V L
.
r
or ud a uc y
w cl le tr p
V
e in nt ns co
C
th k ( de f i es
of or stu e o tat
ity s w g us d S
3-28.
is
te f t ss th nite
e rt ss fo U
DECODER
gr hi in e
th a a ly by
A0 A0 0
k
D0
in o e r
y y p d le d
A1 A1 1
ro n an o te
2
st f a s d s ec
A2 A2
de o rse de ot
3 D1
ill le u vi pr
4
w r sa co pro is
5
o eir is rk
D2
th nd wo
6
7
a his
T
D3
D4
D5
D6
D7
DECODER D8
A3 A0 0
A1 1
A2 2 D9
3
4
5 D 10
6
7 D 11
D 12
D 13
D 14
D 15
10
lOMoARcPSD|38429838
3-29.
DECODER
A0 A0 0 D0
A1 A1 1 D1
2 D2
DECODER
A2 A0 0 En 3 D3
A3 A1 1
2 DECODER
EN EN 3 A0 A0 0 D4
A1 A1 1 D5
2 D6
En 3 D7
DECODER
A0 A0 0 D8
A1 A1 1 D9
2 D10
En 3 D11
DECODER
A0 A0 0 D12
A1 A1 1 D13
2 D14
En 3 D15
3-30.*
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
11
lOMoARcPSD|38429838
3-31. (Errata: Replace <4= with <3= in <4-to-6-line decoder=)

DECODER
A0 A0 0
A1 A1 1 D0
2
3 D1
D2
DECODER D3
A2 A0 0
1
D4
D5
3-32. a) The Truth Table:
)
eb
Note: a = g, b = f , and c = e.
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
X 1 Table:
X 2Truth X0 a b c d e f g
m ld a
a) The Note: a = g, b = f, and c = e.
0 0 0 d d d d d d d
.
r
or ud a uc y
DECODER
w cl le tr p
X2 X01 X00 1 a 0b 0c 0 d 1 e 0f 0
g 0 X0 A0 0
e in nt ns co
1 a
X1 A1
th k ( de f i es
0 0 0 1 0 0 d 1d 0d 0 d 0 d 0 d 0
d 1
2
g
of or stu e o tat
0 1 1 1 0 0 1 0 0 1 X2 A2
ity s w g us d S
3 b
0 0 1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0 1 1 4
is
te f t ss th nite
f
0 1 1 0 0 1 1 10 10 0 0 1 0 0 0 1 5 c
e rt ss fo U
1 1 e
gr hi in e
6
th a a ly by
a)
0 The 1 Truth
1 Table:
k
0
1 10 10 1 0 1 0 1 1 Note: a = g, b =7 f , and c = e.
in o e r
y y p d le d
d
ro n an o te
1X 2 10X 1 1
0X 0 1
1a d
1b d
0c d0d d 0e d d d
st f a s d s ec
1f 1g
de o rse de ot
ill le u vi pr
10 00 10 1d 1d 0d 1d 0d 1d 1d
w r sa co pro is
DECODER
b) A = {d}
1 10 10 A X B XX0 0 C X0 D X0
1 0 1 0B =0{a,g} 1 0 0 1 01 0 1 0 10
o eir is rk
0 A0
th nd wo
X1 A1 1 a
0 1C = {c.0 e} 1 0 0 d 01 0 0 1 d d g
a his
1 1 D =1{b, f}d d d d d d d X2 A2 2 d
0 1 1 1 0 0 1 0 0 1
T
1 3
1 b
1 0 0 1 1 0 01 0 1 1 4 f
b) 1A =0{d}1 1 1 0 1 d 0X 1 1 1 1 d
X1 5
1 d
X1 c
e1 d
X1
6X
1B =1{a,g}0 1 1X 2 1 0 1 1 1 X2
7 2
X2
d1
1 1 1 d d d d1 d d
C = {c.e} d 1 1
D = {b, f}
A = X0 B = X1 + X2 C = X1X 2 D = X2
b) A = {d} A X0 B X0 C X0 D X0
B = {a,g} Gate input cost: b = 4 compared to a = 27 + 11 = 38
C = {c. e} d 1 d d d
D = {b, f}
1 1 1
X1 X1 X1 X1
d 1 d 1 d 1 d
X2 X2 X2 X2
1 1 1 1
A =ý XX00 BB
=Xý1X+1 Xû2X 2 =ý
CC X1X
X12X 2 DD ý= X
X22
Gate input cost: b = 4 compared to a = 27 + 11 = 38
Gate input cost: b = 4 compared to a = 27 + 11 = 38
12
lOMoARcPSD|38429838
3-33.
A0
D0
A1 D1
D2
A2 D3
D4
D5
D6
D7
EN
3-34.
K-Map for GE5: BCD = (C3,C2, C1, C0)
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
C1
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
1 1 1
th k ( de f i es
C2
of or stu e o tat
d d d d
ity s w g us d S
C3
is
te f t ss th nite
1 1 d d
e rt ss fo U
gr hi in e
th a a ly by
C0
in o e r
y y p d le d
ro n an o te
GE5 = C3 + C2 (C1 + C0)

st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
C2
o eir is rk
C1 GE5
th nd wo
C0 C3
a his
T
Equations for output logic:

P0 = D0 + GE5·D1
P1 = D2 + GE5·D1
P2 = D3 + GE5·D4
P3 = D5 + GE5·D4
P4 = D6 + GE5·D7
P5 = D8 + GE5·D7
P6 = D9 + GE5·D10
P7 = D11 + GE5·D10
P8 = D12+ GE5·D13
P9 = D14 + D15 + GE5·D13
13
lOMoARcPSD|38429838
3-35.*
D3 D2 D1 D0 A1 A0 V A1 D1
D0
X A1
0 0 0 0 X X 0 D1
X X X 1 0 0 1 1
D2 D2
X X 1 0 0 1 1 1 A0
D3
X 1 0 0 1 0 1 1
1 0 0 0 1 1 1 V
D0 D3
A0 D1
V ý D0 û D1 ûøD2 û D3 ù
X 1
A0 ý D0 ( D1 û D2
1
A1 ý D0 D1 D2
1
D3
1 1
D0
3-36.
Decimal Inputs Binary Outputs
9 8 7 6 5 4 3 2 1 0 A3 A2 A1 A0 V
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
0 0 0 0 0 0 0 0 0 0 X X X X 0
m ld a
.
r
0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
0 0 0 0 0 0 0 0 1 X 0 0 0 1 1
of or stu e o tat
ity s w g us d S
0 0 0 0 0 0 0 1 X X 0 0 1 0 1
is
te f t ss th nite
e rt ss fo U
gr hi in e
0 0 0 0 0 0 1 X X X 0 0 1 1 1
th a a ly by
k
in o e r
y y p d le d
ro n an o te
0 0 0 0 0 1 X X X X 0 1 0 0 1
st f a s d s ec
de o rse de ot
ill le u vi pr
0 0 0 0 1 X X X X X 0 1 0 1 1
w r sa co pro is
o eir is rk
th nd wo
0 0 0 1 X X X X X X 0 1 1 0 1
a his
T
0 0 1 X X X X X X X 0 1 1 1 1
0 1 X X X X X X X X 1 0 0 0 1
1 X X X X X X X X X 1 0 0 1 1
3-37.
a) b)
DECODER
S0 A0 0
S1 A1 1 I0
4x1 MUX
S2 A2 2
3 I1 S0 S0
4 S1 S1
5 I0 0 Y
6 I2 I1
7 1
I2 2 2x1 MUX
I3 I3 3 S2 S
Y Y Y
4x1 MUX
0
I4 1
S0 S0
S1 S1
I5
I4 0 Y
I5 1
I6 I6 2
I7 3
I7
14
exist. No portion of this material may be reproduced, in anyby
Downloaded form
?? or by any means, without permission in writing from the publisher.
? (soobin3116@gmail.com)
lOMoARcPSD|38429838
3-38.
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
3-39.
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
DECODER
ity s w g us d S
S0 A0 0
is
te f t ss th nite
S1 A1 1 IA0
2
e rt ss fo U
S2 A2
gr hi in e
th a a ly by
3
k
IA1
in o e r
y y p d le d
4
ro n an o te
st f a s d s ec
5
de o rse de ot
6 IA2
ill le u vi pr
7
w r sa co pro is
o eir is rk
th nd wo
IA3
YA
a his
T
IA4
IA5
IA6
IA7
IB0
IB1
IB2
IB3
YB
IB4
IB5
IB6
IB7
15
lOMoARcPSD|38429838
3-40.
3-41.
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
3-42.*
8x1 MUX
D(7:0) D(7:0) Y
0
A(2:0) S(2:0)
8x1 MUX
D(14:8) D(6:0) Y
0
D(7)
S(2:0)
A(3)
3 OR gates
16
lOMoARcPSD|38429838
3-43.*
A1 A0 E D0 D1 D2 D3 Consider E as the data input and A0, A1 as the
0 0 0 0 0 0 0 select lines. For a given combination on (A1,
0 0 1 1 0 0 0 A0), the value of E is distributed to the
0 1 0 0 0 0 0 corre-sponding D output. For example for
0 1 1 0 1 0 0 (A1, A0) = (10), the value of E appears on D2,
1 0 0 0 0 0 0 while all other outputs have value 0.
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
3-44.
DECODER
X A0 0
1 F1
Y A1
Z A2 2
3
4 F2
5
6
7 F3
3-45.
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
a) LR ý LT·BL û LT·BR û EM·BL ý BL·(LT û EM) û LT·BR
.
r
or ud a uc y
w cl le tr p
e in nt ns co
RR ý RT·BL+RT·BR û EM·BL ý BR·(RT û EM) û RT·BR

th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
b) Maximum of four inputs on OR gates assumed.

e rt ss fo U
gr hi in e
th a a ly by
LT EM BR BL LR
in o e r
y y p d le d
ro n an o te
st f a s d s ec
0 0 0 0 0
de o rse de ot
ill le u vi pr
0 0 0 1 0
w r sa co pro is
o eir is rk
0 0 1 0 1
th nd wo
a his
0 0 1 1 1 LR
T
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
For RR, same circuit with LT replace by RT.
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
17
lOMoARcPSD|38429838
3-46.
A B C D F 8 x 1 MUX
C S0
0 0 0 0 0 Fý0 B S1
0 0 0 1 0 A S2
D0 Y F
0 0 1 0 1 FýD D D1
0 0 1 1 0 D2
VDD D3
0 1 0 0 1 D4
FýD D5
0 1 0 1 0 D6
D7
0 1 1 0 1
FýD
0 1 1 1 0
1 0 0 0 0
FýD
1 0 0 1 1
1 0 1 0 1
F ý1
1 0 1 1 1
1 1 0 0 0
Fý0
1 1 0 1 0
1 1 1 0 0
FýD
1 1 1 1 1
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
3-47.*
.
r
or ud a uc y
w cl le tr p
e in nt ns co
C
th k ( de f i es
A B C D F
D
of or stu e o tat
ity s w g us d S
0 0 0 0 0
is
te f t ss th nite
0 0 0 1 1
FýD
e rt ss fo U
gr hi in e
th a a ly by
4 x 1 MUX
k
0 0 1 0 0
in o e r
y y p d le d
S0
ro n an o te
B
st f a s d s ec
0 0 1 1 1 A S1
de o rse de ot
ill le u vi pr
0 1 0 0 1 D0 Y F
w r sa co pro is
VDD D1
o eir is rk
0 1 0 1 0 D2
th nd wo
F ý CD D3
a his
0 1 1 0 0
T
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
F ý CD
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
F ý1
1 1 1 0 1
1 1 1 1 1
18
lOMoARcPSD|38429838
3-48.
DECODER
D A0 0
C A1 1
B A2 2
3
4
5
6
A EN 7
DECODER
F
D A0 0
C A1 1
B A2 2
3
4
5
6
EN 7
3-49.
úS0 ý C0 A0 B0 û C0 A0 B0 û C0 A0 B0 û C0 A0 B0 C1 ý C0 A0 û A0 B0 û C0 B0
S1 ý C1 A1 B1 û C1 A1 B1 û C1 A1B1 û C1 A1B1 C2 ý C1 A1 û A1B1 û C1B1
úS1 ý C0 A0 A1 B1 û A0 B0 A1 B1 û C0 B0 A1 B1 úC2 ý C0 A0 A1 û A0 B0 A1 û C0 B0 A1
ûC0 A0 B1 û A0 B0 B1 û C0 B0 B1 û A1B1
)
û C0 A0 A1 B1 û A0 B0 A1 B1 û C0 B0 A1 B1
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
ûC0 A0 A1B1 û A0 B0 A1B1 û C0 B0 A1B1
.
r
ûC0 A0 A1B1 û A0 B0 A1B1 û C0 B0 A1B1

or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
* These are the three equations for the outputs. The logic diagram consists of a sum-of-products implementation of these equations.
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
3-50.*
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
C1 ý T3 û T2 ý T1C0 û T2 ý A0 B0 C0 û A0 û B0 ý ( A0 û B0 )C0 û A0 B0 ý ( A0 B0 û C0 )( A0 û B0 )
w r sa co pro is
o eir is rk
th nd wo
C1 ý A0 B0 û A0C0 û B0C0
a his
T
S0 ý C0  T4 ý C0  TT
1 2 ý C0  A0 B0 ( A0 û B0 ) ý C0  ( A0 û B0 )( A0 û B0 ) ý C0  A0 B0 û A0 B0
S0 ý A0  B0  C0
T3
T1
T4
T2
3-51.*
Unsigned 1001 1100 1001 1101 1010 1000 0000 0000 1000 0000
1’s Complement 0110 0011 0110 0010 0101 0111 1111 1111 0111 1111
2’s Complement 0110 0100 0110 0011 0101 1000 0000 0000 1000 0000
19
lOMoARcPSD|38429838
3-52.
a) 11010 b) 11110 c) 1111110 d) 101001
+ 01111 + 10010 + 0000010 + 111011
01001 10000 0000000 100100
3-53.
a) 11010 b) 11110 c) 1111110 d) 101001
+ 01111 + 00010 + 0000010 + 000011
01001 00000 0000000 101100
3-54.*
+36 = 0100100 36 0100100
- 24 = 1101000 +(–24) + 1101000
- 35 = 1011101 10001100
= 12 = 0001100
–35 1011101
- (–24) + 0011000
= –11 = 1110101
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
3-55.
.
r
or ud a uc y
w cl le tr p
a) b) c) d)
e in nt ns co
D
th k ( de f i es
100111 -25 0010011 11 110001 -15 101110 -18

of or stu e o tat
+ 111001 -7 + 100110 -26 + 101110 -18 + 001001 9

ity s w g us d S
is
te f t ss th nite
100000 -32 110001 -15 011111 -33 110111 -9

e rt ss fo U
Overflow
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
3-56.+
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a) H ý D
a his
G ýC D A B C D E F G H
T
0 0 0 0 0 0 0 0
F ý BC û BD û BCD 0 0 0 1 1 1 1 1
E ý AB û ABCD û AC û AD 0 0 1 0 1 1 1 0
0 0 1 1 1 1 0 1
b) Bit Cin S Cout S ý Bit  Cin 0 1 0 0 1 1 0 0
0 1 0 1 1 0 1 1
0 0 0 0 Cout ý Bit û Cin
0 1 1 1 0 1 1 0 1 0 1 0
1 0 1 1 0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
1 1 0 1 1 0 0 1 0 1 1 1
1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1
c) Using shared inverters, XOR cost = 6. Gate input cost for a = 4 + 0 + 6 + 10 + 14 = 34 Gate input cost for
b = 4 x (2 + 6 + 2) = 40 In terms of gate cost, a is the better design.
20
lOMoARcPSD|38429838
3-57.
A3 A2 A1 A0
C4 S3 S2 S1 S0
3-58.
B0 ý 1 Cin ý 0
S0 ý A0  1  0 ý A0
C0 ý A0  1 û 0( A0 û 1)ý A0
B1 ý S
B2 ý S
B3 7 ý S
Bits 1-6 use regular full adder/subtractor logic. For bit 7, the carry logic is omitted.
)
eb
er or in ing
ed id n
W
no the iss tea s
S
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
A7 A6 A5 A4 A3 A2 A1 A0
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
B A B A B A B A B A B A B A
is
te f t ss th nite
FA Cin Cout FA Cin C out FA Cin Cout FA Cin Cout FA Cin Cout FA C in Cout FA Cin
e rt ss fo U
gr hi in e
S S S S S S S
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
S7 S6 S5 S4 S3 S2 S1 S0
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
3-59.
a his
Proceeding from MSB to LSB: A ü B if Ai ü Bi ( Ai Bi ý 1) and for all j þ i, Aj ý B j ( Aj B j û Aj B j ý 1) Based on the above,
T
X ý A3 B3 û ( A3 B3 û A3 B3 ) A2 B2 û ( A3 B3 û A3 B3 )( A2 B2 û A2 B2 ) A1B1
û( A3 B3 û A3 B3 )( A2 B2 û A2 B2 )( A1B1 û A1B1 ) A0 B0
21
lOMoARcPSD|38429838
3-60.+
B A
Cout
B Cout
Cin Cin
A3
X B3 A2
C4 B2 A1
C3 B1 A0
C2 B0
+
C1 Logic 0
3-61.
In a subtractor, the sum is replaced by the difference and the carry is replaced by the borrow. The borrow at
any given point is a 1 only if in the LSB direction from that point, A ü B.
Only borrow logic is needed to produce X, so the difference logic is discarded in contraction. The remaining
equation for borrow into the i + 1 position is: Bri û1 ý Ai Bi û Ai Bri û Bi Bri for i = 0,1,2,3. Br0 ý 0 giving
Br1 ý A0 B0 When the borrow Br4 ý 1, then A ü B. Thus, X = Br4. The resulting circuit using the borrow logic
is:
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
B3 A3 B2 A2 B1 A1 A0 B0
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
Bi Ai Bi Ai Bi Ai
of or stu e o tat
ity s w g us d S
X Bri+1 Bri Bri+1 Bri Bri+1 Bri

is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
3-62.+
ill le u vi pr
w r sa co pro is
o eir is rk
This problem requires two decisions: Is A > B? Is A = B? Two <carry= lines are required to build an iterative
th nd wo
a his
circuit, Gi and Ei. These carries are assumed to pass through the circuit from right to left with G0 = 0 and E0 = 1.
T
Each cell has inputs Ai, Bi, Gi, and Ei and outputs Gi+1 and Ei+1. Using K-maps, cell equations are:
Ei û1 ý Ai Bi Ei û Ai Bi Ei
Gi û1 ý Ai Bi Ei û ( Ai û Bi ) Ei
Using multilevel circuit techniques, the cost can be reduced by sharing terms:
Ei û1 ý ( Ai Bi û Ai Bi ) Ei B3 A3 B2 A2 B1 A1 B0 A0
Gi û1 ý ( Ai Bi û ( Ai Bi )Gi
E4 Ei+1 Bi Ai E Ei+1 Bi Ai E
i
Ei+1 Bi Ai Ei Ei+1 Bi Ai Ei E0 = 1
G4 Gi+1 Gi Gi+1 Gi Gi+1 Gi Gi+1 Gi G0 = 0
22
lOMoARcPSD|38429838
3-63.+
Circuit Diagram:
Control Logic A 3 A2 A1 A 0 B3 B2 B1 B0
Adder/Subtractor
Add/Subtract
A4 SignA Sub
B4 SignB
Sub/Add 2’s Complementer
S/A
Cout 4-bit Adder Cin 0

S3 S2 S1 S0
Control Logic
ResultCorrection
SignA
Sub Corr 2’s Complementer
Cout Sign
S4 S3 S2 S1 S0
Control Logic Truth Tables Sub ý 
S/A  SignA
  SignB
Corr ý Sub Cout
Inputs Inputs
S/A Sign A SignB Sub Sub SignA Cout Corr Sign Overflow Sign ý SignA
  Corr
0 0 0 0 0 0 0 0 0 0 Overflow ý Sub Cout
0 0 1 1 0 0 1 0 0 1
)
eb
0 1 0 1 0 1 0 0 1 0
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
0 1 1 0 0 1 1 0 1 1
e
d on g. in t la
m ld a
1 0 0 1 1 0 0 1 1 0
.
r
1 0 1 0 1 0 1 0 0 0
or ud a uc y
w cl le tr p
e in nt ns co
1 1 0 0 1 1 0 1 0 0
th k ( de f i es
1 1 1 1 1 1 1 0 1 0
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
3-64.*
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
S A B C4 S3 S2 S1 S0
de o rse de ot
ill le u vi pr
a) 0 0111 0111 0 1 1 1 0
w r sa co pro is
o eir is rk
b) 1 0100 0111 0 1 1 0 1
th nd wo
c) 1 1101 1010 1 0 0 1 1
a his
T
d) 0 0111 1010 1 0 0 0 1
e) 1 0001 1000 0 1 0 0 1
23
lOMoARcPSD|38429838
3-65.
-- Full Adder: Structural VHDL Description
-- (See Figure 4-28 for logic diagram)
library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; --X is input vector (A0, B0, C0).
entity full_adder_st is
port(X: in std_logic_vector(0 to 2);
C1, S0: out std_logic);
end;
architecture logic of full_adder_st is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component NAND2
port(in1, in2: in std_logic;
end component;
component NOR2
end component;
component AND2
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
end component;
.
r
or ud a uc y
component XOR2
w cl le tr p
e in nt ns co

th k ( de f i es
of or stu e o tat

ity s w g us d S
end component;
is
te f t ss th nite
signal S: std_logic_vector(0 to 6); -- S(0 to 6) is the vector of six gate output signals
e rt ss fo U
gr hi in e
th a a ly by
-- from upper left to lower right.

in o e r
y y p d le d
ro n an o te
--The following is the circuit netlist.

st f a s d s ec
de o rse de ot
begin
ill le u vi pr
w r sa co pro is
g0: NAND2 port map (X(1), X(0), S(0));

o eir is rk
th nd wo
g1: NOR2 port map (X(1), X(0), S(1));

a his
g2: NOT1 port map (X(2), S(2));

T
g3: AND2 port map (S(0), S(2), S(3));

g4: NOT1 port map (S(1), S(4));
g5: NOT1 port map (S(2), S(5));
g6: AND2 port map (S(0), S(4), S(6));
g7: NOR2 port map (S(1), S(3), Z(1));
g8: XOR2 port map (S(6), S(5), Z(0));
end logic;
24
lOMoARcPSD|38429838
3-66.
The solution
Thegiven is very
solution thorough
giv en is v erysince it checks
thorough each
since of the carry
it checks eachconnections between
of the carry adjacentbetween
connections cells transferring
adjac 0
and 1. In transferring 0 and
contrast a test 1. In contrast
applying C0 = 1aandtestAapplying C0 B
= 15 with = 1=and A = 15allow
0 would with B
a= 0 would
whole allowofa incorrect
variety whole connections
variety
between cells of would
that incorrect
notconnections
be detected.between cells that would not be detected.
)
eb
er or in ing
ed id n
3-67.*
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
The solution given is very thorough since it checks each of the carry connections between adjacent cells transferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
25
lOMoARcPSD|38429838
3-68.+
-- prob_4-30 adder-subtractor with overflow detection
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_unsigned.all;
entity addsubov is
port(A,B: in std_logic_vector(3 downto 0);
S: in std_logic;
SD: out std_logic_vector(3 downto 0);
C, V: out std_logic);
end addsubov;
architecture behavior of addsubov is
signal Y: std_logic_vector(3 downto 0);
signal temp4: std_logic_vector(3 downto 0);
signal temp2: std_logic_vector(4 downto 3);
signal CI: std_logic_vector(4 downto 3);
begin
with S select
Y(2 downto 0) <= B(2 downto 0) when '0',
not B(2 downto 0) when '1',
"XXX" when others;
with S select
Y(3) <= B(3) when '0',
not B(3) when '1',
)
eb
'X' when others;
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
temp4 <= ('0' & A(2 downto 0)) + ('0' & Y(2 downto 0)) + ("000" & S);
e
d on g. in t la
m ld a
CI(3) <= temp4(3);
.
r
or ud a uc y
temp2 <= ('0' & A(3)) + ('0' & Y(3)) + ('0' & CI(3));
w cl le tr p
e in nt ns co
CI(4) <= temp2(4);

th k ( de f i es
of or stu e o tat
SD <= (temp2(3) & temp4(2 downto 0));

ity s w g us d S
C <= CI(4);
is
te f t ss th nite
V <= CI(4) xor CI (3);

e rt ss fo U
gr hi in e
th a a ly by
end behavior;
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0 and 1.
In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections between cells
that would not be detected.
26
lOMoARcPSD|38429838
3-69.
// Full Adder: Structural Verilog Description
// (See Figure 4-28 for logic diagram)
module full_adder_st(C1, S0, X);
input [2:0] X; //X is the vector of inputs (A0, B0, C0).
output C1, S0;
wire [0:6] N; //N[0:6] is the six bit vector of gate
//outputs from upper left to lower right.
//The netlist for the gate types:
nand
gna(N[0],X[1],X[0]);
nor
gno1(N[1],X[1],X[0]),
gno2(C1,N[1],N[3]);
not
gn0(N[2], X[2]),
gn1(N[4], N[1]),
gn2(N[5], N[2]);
and
ga0(N[3], N[0], N[2]),
ga1(N[6], N[0], N[4]);
xor
gx(S0, N[5], N[6]);
)
eb
endmodule
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
3-70.
a his
T
27
lOMoARcPSD|38429838
3-71.*
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
3-72.
)
eb
er or in ing
ed id n
W
no the iss tea s
// Adder-Subtractor Behavioral Model
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
module addsub_4b_v (S, A, B, SD, C4);
input[3:0] A, B;
.
r
or ud a uc y
w cl le tr p
e in nt ns co
input S;
th k ( de f i es
output[3:0] SD;
of or stu e o tat
ity s w g us d S
output C4;
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
assign {C4, SD} = S?(A - B):(A + B);

in o e r
y y p d le d
ro n an o te
endmodule
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
28

Chapter 03 - Solutions

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Chapter 03 - Solutions

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디지털논리와 컴퓨터설계 (Chungnam National University)

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Problem Solutions – Chapter 3

input combinations as don’t cares:

G1G0 G1G0 G1G0 G1G0

G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10 G3G2 00 01 11 10

B0 ý G3G0 û G2G1G0 û G2G1 G0

b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30

Problem Solutions – Chapter 3

ABCD GNS YNS RNS GEW YEW REW B B

YNS = ABCD YEW = ABCD

1100 0 0 1 1 0 0 YNS ý ABCD YEW ý ABCD

RNS ý A û BCD REW ý A û BCD

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

Part b requires 6 fewer gates.

Problem Solutions – Chapter 3

b) Replacement with equiv alents

c) Manipulate inv erters d) Cancel inv erters

Problem Solutions – Chapter 3

1) Original circuit using AND, OR, Inverter

2) Mapped to Inverter, 2NAND, 3NAND, and 4NAND

two literals become available ( AB,BC )

Problem Solutions – Chapter 3

b) Mapped to 2NOR and Inverter

Problem Solutions – Chapter 3

a ý A û C û BD û BD, b ý B û CD û CD, c ý B û C û D, d ý A û CD û BC û BD û BCD,

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

3-31. (Errata: Replace <4= with <3= in <4-to-6-line decoder=)

3-32. a) The Truth Table:

Problem Solutions – Chapter 3

GE5 = C3 + C2 (C1 + C0)

Equations for output logic:

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

a) LR ý LT·BL û LT·BR û EM·BL ý BL·(LT û EM) û LT·BR

RR ý RT·BL+RT·BR û EM·BL ý BR·(RT û EM) û RT·BR

b) Maximum of four inputs on OR gates assumed.

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

ûC0 A0 A1B1 û A0 B0 A1B1 û C0 B0 A1B1

Problem Solutions – Chapter 3

100111 -25 0010011 11 110001 -15 101110 -18

+ 111001 -7 + 100110 -26 + 101110 -18 + 001001 9

100000 -32 110001 -15 011111 -33 110111 -9

Problem Solutions – Chapter 3

Problem Solutions – Chapter 3

X Bri+1 Bri Bri+1 Bri Bri+1 Bri

Problem Solutions – Chapter 3

Cout 4-bit Adder Cin 0

Problem Solutions – Chapter 3

port(in1, in2: in std_logic;

out1: out std_logic);

-- from upper left to lower right.

--The following is the circuit netlist.

g0: NAND2 port map (X(1), X(0), S(0));