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GAL16V8: Features Functional Block Diagram
GAL16V8: Features Functional Block Diagram
GAL16V8: Features Functional Block Diagram
PROGRAMMABLE
8 OLMC I/O/Q
— Reconfigurable Logic I
AND-ARRAY
— Reprogrammable Cells
— 100% Tested/100% Yields
(64 X 32)
8 OLMC I/O/Q
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention I
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. October 1998
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
16v8_06 1
Specifications GAL16V8
GAL16V8 Ordering Information
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
3.5 2.5 3.0 115 GAL16V8D-3LJ 20-Lead PLCC
XXXXXXXX _ XX X X X
2
Specifications GAL16V8
Output Logic Macrocell (OLMC)
3
Specifications GAL16V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-
registered outputs or as I/O functions. sets of the I/O function.
Architecture configurations available in this mode are similar to the Registered outputs have eight product terms per output. I/O's have
common 16R8 and 16RP4 devices with various permutations of seven product terms per output.
polarity, I/O and register placement.
The JEDEC fuse numbers, including the User Electronic Signature
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown
control pins. Any macrocell can be configured as registered or I/ on the logic diagram on the following page.
O. Up to eight registers or up to eight I/O's are possible in this mode.
CLK
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
D Q
- AC1=0 defines this output configuration.
Q - Pin 1 controls common CLK for the registered outputs.
XOR
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
OE
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
XOR - Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL16V8
Registered Mode Logic Diagram
DIP & PLCC Package Pinouts
1 2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC 19
0224
XOR-2048
2 AC1-2120
0256
OLMC 18
0480
XOR-2049
3 AC1-2121
0512
OLMC 17
0736
XOR-2050
4 AC1-2122
0768
OLMC 16
0992
XOR-2051
5 AC1-2123
1024
OLMC 15
1248
XOR-2052
6 AC1-2124
1280
OLMC 14
1504
XOR-2053
7 AC1-2125
1536
OLMC 13
1760
XOR-2054
8 AC1-2126
1792
OLMC 12
2016
XOR-2055
9 AC1-2127
OE
2191 11
SYN-2192
AC0-2193
5
Specifications GAL16V8
Complex Mode
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the
I/O functions. Registered mode.
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and
each macrocell. 11 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.
two outer most macrocells (pins 12 & 19) do not have input capa-
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR - AC1=1.
- Pin 13 through Pin 18 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR - AC1=1.
- Pin 12 and Pin 19 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL16V8
Complex Mode Logic Diagram
DIP & PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC 19
0224 XOR-2048
2 AC1-2120
0256
OLMC 18
0480 XOR-2049
3 AC1-2121
0512
OLMC 17
0736 XOR-2050
4 AC1-2122
0768
OLMC
16
0992 XOR-2051
5 AC1-2123
1024
OLMC 15
1248 XOR-2052
6 AC1-2124
1280
OLMC 14
1504 XOR-2053
7 AC1-2125
1536
OLMC 13
1760 XOR-2054
8 AC1-2126
1792
OLMC 12
2016 XOR-2055
9 AC1-2127
11
2191
SYN-2192
AC0-2193
7
Specifications GAL16V8
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs Pins 1 and 11 are always available as data inputs into the AND
or as dedicated, always active, combinatorial outputs. array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge- The JEDEC fuse numbers including the UES fuses and PTD fuses
neric output polarity or input choices. are shown on the logic diagram.
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR - AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL16V8
Simple Mode Logic Diagram
DIP & PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC
XOR-2048 19
0224 AC1-2120
2
0256
OLMC
XOR-2049 18
0480 AC1-2121
3
0512
OLMC
XOR-2050 17
0736 AC1-2122
4
0768
OLMC
XOR-2051 16
0992 AC1-2123
5
1024
OLMC
XOR-2052 15
1248 AC1-2124
6
1280
OLMC
XOR-2053 14
1504 AC1-2125
7
1536
OLMC
XOR-2054 13
1760 AC1-2126
8
1792
OLMC
XOR-2055 12
2016 AC1-2127
9 11
2191
SYN-2192
AC0-2193
9
Specifications GAL16V8D
Absolute Maximum Ratings(1) Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V Commercial Devices:
Input voltage applied .......................... –2.5 to VCC +1.0V Ambient Temperature (TA) ............................... 0 to 75°C
Off-state output voltage applied ......... –2.5 to VCC +1.0V Supply voltage (VCC)
Storage Temperature ................................ –65 to 150°C with Respect to Ground ..................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................ –55 to 125°C Industrial Devices:
1.Stresses above those listed under the “Absolute Maximum Ambient Temperature (TA) ........................... –40 to 85°C
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the with Respect to Ground ..................... +4.50 to +5.50V
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -3/-5/-7/-10 — 75 115 mA
Supply Current ftoggle = 15MHz Outputs Open L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15/-25 — 75 130 mA
Supply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
10
Specifications GAL16V8D
AC Switching Characteristics
Over Recommended Operating Conditions
TEST -3 -5 -7
PARAMETER DESCRIPTION UNITS
COND1. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Comb. Output 1 3.5 1 5 1 7.5 ns
11
Specifications
SpecificationsGAL16V8D
GAL16V8
AC Switching Characteristics
Over Recommended Operating Conditions
t B OE to Output Enabled — 10 — 15 — 18 — 20 ns
t C OE to Output Disabled — 10 — 15 — 18 — 20 ns
12
Specifications GAL16V8
Switching Waveforms
INPUT or
I/O FEEDBACK VALID INPUT
tsu th
CLK
INPUT or
I/O FEEDBACK VALID INPUT tco
REGISTERED
tpd OUTPUT
COMBINATIONAL 1/fmax
OUTPUT (external fdbk)
INPUT or
I/O FEEDBACK OE
13
Specifications GAL16V8
fmax Descriptions
CLK
LOGIC CLK
REGISTER
ARRAY
LOGIC
ARRAY
Test Condition R1 R2 CL
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
A 200Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 200Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 200Ω 390Ω 5pF
14
Specifications GAL16V8
Switching Test Conditions (Continued)
GAL16V8D-3 Output Load Conditions (see figure at right) +1.45V
Test Condition R1 CL
A 50Ω 35pF TEST POINT
R1
B High Z to Active High at 1.9V 50Ω 35pF
High Z to Active Low at 1.0V 50Ω 35pF FROM OUTPUT (O/Q)
C Active High to High Z at 1.9V 50Ω 35pF UNDER TEST Z0 = 50Ω, CL = 35pF*
Active Low to High Z at 1.0V 50Ω 35pF
*CL includes test fixture and probe capacitance.
-20
-40
-60
0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
15
Specifications GAL16V8
Power-Up Reset
Vcc (min.)
Vcc
t su
CLK t wl
t pr
INTERNAL REGISTER Internal Register
Q - OUTPUT Reset to Logic "0"
Circuitry within the GAL16V8 provides a reset signal to all reg- conditions must be met to provide a valid power-up reset of the
isters during power-up. All internal registers will have their Q device. First, the VCC rise must be monotonic. Second, the clock
outputs set low after a specified time (tpr, 1µs MAX). As a result, input must be at static TTL level as shown in the diagram during
the state on the registered output pins (if they are enabled) will power up. The registers will reset within a maximum of tpr time.
always be high on power-up, regardless of the programmed As in normal system operation, avoid clocking the device until all
polarity of the output pins. This feature can greatly simplify state input and feedback path setup times have been met. The clock
machine design by providing a known state on power-up. Be- must also meet the minimum pulse width requirements.
cause of the asynchronous nature of system power-up, some
Input/Output
INPUT/OUTPUT Equivalent Schematics
EQUIVALENT SCHEMATICS
PIN PIN
Feedback
Vcc
Active Pull-up Active Pull-up
Circuit Circuit
Vcc
Vcc Vcc Tri-State Vref
Vref
ESD Control
Protection
Circuit
PIN Data
PIN
Output
ESD
Protection
Circuit
Feedback
Typ. Vref = 3.2V Typ. Vref = 3.2V (To Input Buffer)
Typical Input Typical Output
16
Specifications GAL16V8
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams
Normalized Tsu
Normalized Tco
1.1 PT L->H 1.1 FALL 1.1 PT L->H
1 1 1
Normalized Tco
Normalized Tsu
PT L->H FALL PT L->H
1.1 1.1 1.1
1 1 1
-0.1
Delta Tco (ns)
-0.1
-0.2 -0.2
RISE
FALL
RISE
-0.3 -0.3
FALL
-0.4 -0.4
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Number of Outputs Switching Number of Outputs Switching
12 12
RISE RISE
10
Delta Tco (ns)
10
Delta Tpd (ns)
FALL FALL
8 8
6 6
4 4
2 2
0 0
-2 -2
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00
17
Specifications GAL16V8
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams
4
0.75
3
Voh (V)
Voh (V)
3
Vol (V)
0.5
2
2.75
0.25
1
0 0 2.5
0 10 20 30 40 0 10 20 30 40 50 0 1 2 3 4
1.15
1.2
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1.1
1.1
1 1.05
1
1
0.9
0.9
0.95
10
8 20
Delta Icc (mA)
30
Iik (mA)
6
40
50
4
60
2 70
80
0 90
0 0.5 1 1.5 2 2.5 3 3.5 4 -2 -1.5 -1 -0.5 0
18
Specifications GAL16V8
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams
Normalized Tco
Normalized Tsu
RISE FALL 1.1
FALL
FALL
1.05 1.05
1
1 1
0.9
0.95 0.95
Normalized Tco
Normalized Tsu
FALL FALL FALL
1.1 1.1 1.1
1 1 1
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
-0.6 -0.6
RISE RISE
-0.7 -0.7
FALL FALL
-0.8 -0.8
-0.9 -0.9
-1 -1
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Number of Outputs Switching Number of Outputs Switching
RISE RISE
8 FALL 8
Delta Tpd (ns)
FALL
4 4
0 0
-4 -4
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00
19
Specifications GAL16V8
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams
0.4
3
3.5
Voh (V)
Voh (V)
0.3
Vol (V)
2
0.2
3
1
0.1
0 0 2.5
1 6 11 16 21 26 0 5 10 15 20 25 0.00 1.00 2.00 3.00 4.00 5.00
1.1 1.1
Normalized Icc
Normalized Icc
Normalized Icc
1
1 1.05
0.9
0.9 1
8 10
7 20
Delta Icc (mA)
6 30
Iik (mA)
5 40
4 50
3 60
2 70
1 80
0 90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -3 -2.5 -2 -1.5 -1 -0.5 0
20
Specifications GAL16V8
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams
RISE
FALL
Normalized Tpd
Normalized Tsu
Normalized Tco
1.1 PT H->L 1.1 1.1 PT H->L
PT L->H PT L->H
1 1 1
Normalized Tsu
PT L->H FALL PT L->H
1.1 1.1 1.1
1 1 1
-0.2 -0.2
Delta Tpd (ns)
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
RISE RISE
-1 FALL -1 FALL
-1.2 -1.2
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
8
FALL FALL
6
6
4
4
2
2
0
0
-2
-4 -2
-6 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300
21
Specifications GAL16V8
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams
4 3.8
0.4
Voh (V)
Voh (V)
3 3.6
Vol (V)
2 3.4
0.2
1 3.2
0 0 3
0 10 20 30 40 0 10 20 30 40 50 0 1 2 3 4
1.2 1.3
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1.1 1.2
1 1 1.1
0.9 1
0.9
0.8 0.9
10
6
Delta Icc (mA)
20
Iik (mA)
4 30
40
2
50
0 60
0 0.5 1 1.5 2 2.5 3 3.5 4 -2 -1.5 -1 -0.5 0
Vin (V) Vik (V)
22