Ch10slides - Update

Chapter 10
Input Filter Design

10.1 Introduction
10.1.1 Conducted EMI
10.1.2 The Input Filter Design Problem
10.2 Effect of an Input Filter on Converter Transfer Functions
10.2.1 Discussion
10.2.2 Impedance Inequalities
10.3 Buck Converter Example
10.3.1 Effect of Undamped Input Filter
10.3.2 Damping the Input Filter
10.4 Design of a Damped Input Filter
10.4.1 Rf–Cb Parallel Damping
10.4.2 Rf–Lb Parallel Damping
10.4.3 Rf–Lb Series Damping
10.4.4 Cascading Filter Sections
10.4.5 Example: Two Stage Input Filter
10.5 Summary of Key Points
Fundamentals of Power Electronics 1 Chapter 10: Input Filter Design
10.1.1 Conducted Electromagnetic Interference
(EMI)
Input current ig(t) is pulsating: Buck converter example
ig(t) ig 1 i L
i i +
2
vg(t) + C v R
–
0
0 –
0 DTs Ts t
Approximate Fourier series of ig(t):

∞
i g(t) = DI + Σ 2I sin
k = 1 kπ
kπD cos kωt
High frequency current harmonics of substantial amplitude are injected
back into vg(t) source. These harmonics can interfere with operation of
nearby equipment. Regulations limit their amplitude, typically to values
of 10 µA to 100 µA.
Addition of Low-Pass Filter
iin Lf ig 1 L
ig(t) i
+
iin(t) 2
vg(t) + Cf C v R
–
0
0 –
0 DTs Ts t
Input filter
Magnitudes and phases of input current harmonics are modified by

input filter transfer function H(s):
∞
i in(t) = H(0)DI + Σ
k=1
H(kjω) 2I sin kπD cos kωt + ∠H(kjω)
kπ
The input filter may be required to attenuate the current harmonics by

factors of 80 dB or more.

Electromagnetic Compatibility
Ability of the device (e.g. power supply) to:

function satisfactorily in its electromagnetic environment
(susceptibility or immunity aspect)
without introducing intolerable electromagnetic disturbances (emission
aspect)
EMC
Emission Susceptibility
Radiated Conducted Radiated Conducted Electrostatic

Discharge
Harmonics EMI

Conducted EMI
Spectrum
analyzer Test result: spectrum of the voltage across a standard impedance in the LISN
AC line source ig(t) i2(t) pload(t) = VI = Pload
iac(t) + + +
i(t)
LISN EMI DC/DC
vac(t) filter vg(t) C vC(t) converter v(t) load
– – –
AC/DC rectifier Energy storage Regulated

capacitor DC output
“Earth” ground
Sample of EMC regulations that include limits on radio-

frequency emissions:
European Community Directive on EMC: Euro-Norm EN 55022 or
55081, earlier known as CISPR 22
National standards: VDE (German), FCC (US)
LISN
R1 5Ω 50µH L1 • LISN: “Line Impedance

C1
0.1µF Stabilization Network,” or
1µF
CN “artificial mains network”
Measurement points
RN • Purpose: to standardize
Device under test

AC line source
50Ω impedance of the power source

used to supply the device under
RN
test
50Ω
• Spectrum of conducted
1µF 0.1µF
CN
emissions is measured across
C1 the standard impedance (50Ω
R1 5Ω 50µH L1
above 150kHz)
LISN example

An Example of EMI Limits
EN 55022 Class B limits
70 dBµV • Frequency range:
150kHz-30MHz
Quasi-peak
• Class B: residential
60 dBµV 1mV environment
631µV • Quasi-peak/Average: two
different setups of the
Average
50 dBµV 316µV measurement device
200µV (such as narrow-band
voltmeter or spectrum
40 dBµV 100µV
analyzer)
100 kHz 1 MHz 10 MHz 100 MHz • Measurement bandwidth:
9kHz

Differential and Common-Mode EMI
Spectrum
analyzer Test result: spectrum of the voltage across a standard impedance in the LISN
AC line source pload(t) = VI = Pload
iac(t) + + +
ig(t) i2(t) i(t)
LISN EMI DC/DC
vac(t) vg(t) C vC(t) converter v(t) load
filter
– – –
Regulated
AC/DC rectifier DC output
“Earth” ground
Differential-mode EMI currents

Common-mode EMI currents
• Differential mode EMI: input current waveform of the PFC. Differential-mode

noise depends on the PFC realization and circuit parameters.
• Common-mode EMI: currents through parasitic capacitances between high
dv/dt points and earth ground (such as from transistor drain to transistor heat
sink). Common-mode noise depends on: dv/dt, circuit and mechanical layout.
10.1.2 The Input Filter Design Problem
A typical design approach:

1. Engineer designs switching regulator that meets specifications
(stability, transient response, output impedance, etc.). In
performing this design, a basic converter model is employed, such
as the one below:
Converter model
1:D i L
+
–
(no input filter) +
Vg d
(buck vg + Id C R v
–
converter
example) –

Input Filter Design Problem, p. 2
2. Later, the problem of conducted EMI is addressed. An input filter is

added, that attenuates harmonics sufficiently to meet regulations.
3. A new problem arises: the controller no longer meets dynamic
response specifications. The controller may even become unstable.
Reason: input filter changes converter transfer functions
Input filter Converter model
Converter 1:D i L
+
–
ac model is +
Lf
modified by Vg d
input filter vg + Cf Id C R v
–

Input Filter Design Problem, p. 3
40 dB
|| Gvd || ∠ Gvd Effect of L-C input
|| Gvd || filter on control-to-
30 dB
output transfer
20 dB function Gvd (s),
buck converter
10 dB example.
∠ Gvd
0 dB 0˚ Dashed lines:
original magnitude
– 10 dB
– 180˚
and phase
Solid lines: with
– 360˚ addition of input
filter
– 540˚
100 Hz 1 kHz 10 kHz
f

10.2 Effect of an Input Filter
on Converter Transfer Functions
H(s)
Input Converter
filter Zo(s) Zi(s) v
vg +
–
d T(s)
Control-to-output transfer function is Controller
v(s)
Gvd (s) =
d(s) v g(s) = 0

Determination of Gvd(s)
v(s)
Gvd (s) =
d(s) v g(s) = 0 Converter
v
Zo(s)
vg(s) source ➞ short circuit Gvd(s)
Zo(s) = output impedance of

input filter
d
We will use Middlebrook’s Extra Element Theorem to show that the input
filter modifies Gvd (s) as follows:
Z o(s)
1+
Z N (s)
Gvd (s) = Gvd (s) Z o(s) = 0
Z o(s)
1+
Z D(s)

How an input filter changes Gvd(s)
Summary of result
Z o(s)
1+
Z N (s)
Gvd (s) = Gvd (s) Z o(s) = 0
Z o(s)
1+
Z D(s)
Gvd (s) Z o(s) = 0

is the original transfer function, before addition of input filter
Z D(s) = Z i(s) is the converter input impedance, with d set to zero

d(s) = 0
Z N (s) = Z i(s) v(s) o 0 is the converter input impedance, with the output v
nulled to zero
(see Appendix C for proof using EET)

Design criteria for basic converters
Table 10.1 Input filter design criteria for basic converters
Converter ZN(s) ZD(s) Ze(s)
1 + s L + s 2LC sL
Buck – R2 R R
D D2
D2 1 + sRC
1 + s L2 + s 2 LC2
Boost – D′ R 1 – sL2
2
D′ R D′ sL
D′ R D′ 2R
1 + sRC
2 1 + s L2 + s 2 LC2
Buck–boost – D′ 2R 1 – sDL D′ 2R D′ R D′ sL
D D′ 2R D2
D2 1 + sRC

10.2.2 Impedance Inequalities
Z o(s)
1+
Z N (s)
Gvd (s) = Gvd (s) Z o(s) = 0
Z o(s)
1+
Z D(s)
The correction factor Z o(s)
1+ shows how the input filter modifies the
Z N (s)
transfer function Gvd (s).
Z o(s)
1+
Z D(s)
The correction factor has a magnitude of approximately unity provided

that the following inequalities are satisfied:
Z o < Z N , and
Zo < ZD
These provide design criteria, which are relatively easy to apply.

Effect of input filter on converter output
impedance
A similar analysis leads to the following inequalities, which guarantee

that the converter output impedance is not substantially affected by the
input filter:
Z o < Z e , and
Zo < ZD
The quantity Ze is given by:
Ze = Zi v=0
(converter input impedance when the output is shorted)

10.2.1 Discussion
H(s)
Input Converter
filter Zo(s) Zi(s) v
vg +
–
d T(s)
Controller
Z N (s) = Z i(s) v(s) o 0 is the converter input impedance, with the output v
nulled to zero
Note that this is the same as the function performed by an ideal
controller, which varies the duty cycle as necessary to maintain zero
error of the output voltage. So ZN coincides with the input impedance
when an ideal feedback loop perfectly regulates the output voltage.
When the output voltage is perfectly regulated
Closed-loop
voltage regulator
i g(t) Ts
• For a given load
+ characteristic, the output
power Pload is independent of
vg(t) + Pload + V the converter input voltage
Ts – – R
– • If losses are negligible, then

the input port i-v
vg(t) i g(t) = Pload
characteristic is a power sink
i g(t) Ts
Ts Ts
characteristic, equal to Pload:
vg(t) i g(t) = Pload
Ts Ts
Quiescent
operating • Incremental input resistance
point
is negative, and is equal to:
Ig 2
=– M
Ig slope = –
Vg R – R2
M
(same as dc asymptote of ZN)
Vg vg(t) Ts

Negative resistance oscillator
It can be shown that the closed-loop converter input impedance is

given by:
1 = 1 T(s)
+ 1 1
Z i(s) Z N (s) 1 + T(s) Z D(s) 1 + T(s)
where T(s) is the converter loop gain.

At frequencies below the loop crossover frequency, the input
impedance is approximately equal to ZN, which is a negative
resistance.
When an undamped or lightly damped input filter is connected to the
regulator input port, the input filter can interact with ZN to form a
negative resistance oscillator.

10.3 Buck Converter Example
10.3.1 Effect of undamped input filter
Input filter Converter
Lf L
Buck converter 1 i
with input filter 330 µH 100 µH +
Vg 2 R
+ Cf C
v
–
470 µF 100 µF 3Ω
30 V
–
Small-signal model D = 0.5
Input filter Converter model

Lf L
1:D i
+
–
330 µH 100 µH +
Vg d
Cf C R
vg + Id v
–
470 µF 100 µF 3Ω
Zo(s) Zi(s) –
d
Determination of ZD
1:D i L
+
Z D(s) = 12 sL + R || 1
D sC
C R
v
ZD(s)
40 dBΩ
1 fo = 1
f1 = 2π LC ωL
2πRC
30 dBΩ
R = 12 Ω 1.59 kHz D2 || ZD ||
530 Hz
D2
20 dBΩ || ZN ||
1
10 dBΩ
ωD 2C R0 /D 2
Q=R C = fo = 3 → 9.5 dB
L f1
0 dBΩ
100 Hz 1 kHz 10 kHz
f
Determination of ZN
vtest(s) io0 L
Z N (s) = 1:D
i test(s)
+
–
vo0 + + +
Vg d
itest vtest Id vs o 0 C R vo0
ZN(s)
– – –
Solution: Hence,
i test(s) = Id (s) Vg d(s)
–
D
Vg d (s) Z N (s) = = – R2
vtest(s) = – Id(s) D
D

Zo of undamped input filter
40 dBΩ
Qf → ∞
30 dBΩ
Lf
20 dBΩ
Cf
10 dBΩ || Zo ||
Zo(s)
Lf
0 dBΩ R0 f = = 0.84 Ω
Cf
ωL f
Z o(s) = sL f || 1 – 10 dBΩ 1
sC f ff = 1 = 400 Hz ωC f
2π L f C f
– 20 dBΩ
100 Hz 1 kHz
f
No resistance, hence poles are undamped (infinite Q-factor).

In practice, losses limit Q-factor; nonetheless, Qf may be very large.

Z o < Z N , and
Design criteria
Zo < ZD
40 dBΩ
f1 = 530 Hz
Qf → ∞ ωL
30 dBΩ
fo = 1.59 kHz D2 || ZD ||
12 Ω
20 dBΩ || ZN ||
1
ωD 2C R0 /D 2 Can meet
10 dBΩ
|| Zo || Q=3 inequalities
0 dBΩ R0f
everywhere
except at
ωL f
– 10 dBΩ 1 resonant
ff = 400 Hz ωC f frequency ff.
– 20 dBΩ
100 Hz 1 kHz 10 kHz Need to damp
f input filter!

Resulting correction factor
10 dB
Zo
1+
ZN 0 dB
Z
1+ o
ZD
– 10 dB
0˚
Zo
1+
ZN
– 180˚ ∠
Z
1+ o
ZD
– 360˚
100 Hz 1 kHz 10 kHz
f

Resulting transfer function
40 dB
|| Gvd || ∠ Gvd
|| Gvd ||
30 dB
Dashed lines: no
20 dB input filter
10 dB Solid lines:
including effect of
∠ Gvd
0 dB 0˚ input filter
– 10 dB
– 180˚
– 360˚
– 540˚
100 Hz 1 kHz 10 kHz
f

10.3.2 Damping the input filter
Undamped filter: Two possible approaches:

Lf
Lf
Cf Cf Rf
Zo(s)
Rf
Lf
Cf

Addition of Rf across Cf
Lf
To meet the requirement Rf < || ZN ||:
R f < R2
D Cf Rf
The power loss in Rf is Vg2/ Rf,

which is larger than the load power!
Lf
A solution: add dc blocking

capacitor Cb. Rf
Cf
Choose Cb so that its impedance is
Cb
sufficiently smaller than Rf at the
filter resonant frequency.

Damped input filter
|| Zo ||, with large Cb

Lf
Rf
Rf R0f
Cf
ωL f ff
Cb 1
ωC f

Design criteria, with damped input filter
40 dBΩ
f1 = 530 Hz ωL
30 dBΩ
fo = 1.59 kHz D2 || ZD ||
12 Ω
20 dBΩ || ZN ||
1
R0 /D 2
10 dBΩ ωD 2C
Q=3
|| Zo ||
0 dBΩ Rf = 1 Ω R0f
ωL f 1
– 10 dBΩ
ff = 400 Hz ωC f
– 20 dBΩ
100 Hz 1 kHz 10 kHz
f

Resulting transfer function
40 dB
|| Gvd || ∠ Gvd
|| Gvd ||
30 dB
Dashed lines: no
20 dB input filter
10 dB Solid lines:
∠ Gvd including effect of
0 dB 0˚ input filter
– 10 dB
– 90˚
– 180˚
100 Hz 1 kHz 10 kHz
f

10.4 Design of a Damped Input Filter
Rf –Cb Parallel Damping Rf –Lb Series Damping

Lf
Lb
+ Lf
Rf
v1 + Cf v2 +
– Rf
Cb
v1 + Cf v2
– –
–
Rf –Lb Parallel Damping
Rf Lb
• Size of Cb or Lb can become

+ very large
Lf
v1 +
–
Cf v2 • Need to optimize design

Dependence of || Zo || on Rf
Rf ÐLb Parallel Damping
30 dB
Original undamped Undamped
filter (Qf = ∞) filter (Qf = 0)
20 dB
Suboptimal damping Suboptimal damping For this
(Qf = 5Qopt ) (Qf = 0.2Qopt ) example,
10 dB
n = Lb/L = 0.516
Zo Optimal damping
0 dB (Qopt = 0.93)
R0 f
-10 dB
-20 dB
-30 dB
0.1 1 10
f
fo

10.4.1 RfÐCb Parallel Damping
Lf
• Filter is damped by Rf
+
Rf • Cb blocks dc current from
+ flowing through Rf
v1 Cf v2
–
Cb • Cb can be large in value,
and is an element to be
–
optimized

Optimal design equations
Rf ÐCb Parallel Damping
Cb
Define n=
Cf
The value of the peak output impedance for the optimum design is
2 2+n where R0f = characteristic impedance
Zo mm
= R0 f n of original undamped input filter
Given a desired value of the peak output impedance, can solve above
equation for n. The required value of damping resistance Rf can then be
found from:
Rf 2 + n 4 + 3n
Qopt = =
R0 f 2n 2 4 + n
The peak occurs at the frequency
fm = f f 2
2+n

Example
Buck converter of Section 10.3.2
2 2 + n 4 + 3n
R 20 f Zo
n= 1+ 1+4 mm
= 2.5 R f = R0 f = 0.67 Ω
2
Z o mm R 20 f 2n 2 4+n
20 dBΩ
|| Zo || Undamped
10 dBΩ
Suboptimal
damping
Comparison of designs Cb = 4700 µF
0 dBΩ Rf = 1 Ω
Optimal damping
achieves same peak – 10 dBΩ
Optimal
output impedance, with damping
Cb = 1200 µF
much smaller Cb. – 20 dBΩ Rf = 0.67 Ω
– 30 dBΩ
100 Hz 1 kHz 10 kHz
f

L
Summary +
R
+
v1 C v2
Optimal R-Cd damping –
Cd
–
Basic results • Does not degrade HF attenuation

• No limit on || Z ||mm
2 + n 4 + 3n • Cd is typically larger than C
Qopt = R =
R0 2n 2 4 + n 100
Z mm 2 2+n
= n
R0
10
with Z o mm
Cd Ro
n=
C
1
R0 = L
C
0.1
0.1 1 10
Cd
n=
C
R Ld
+
L
v1 + C v2
Optimal R-Ld damping –
30 dB
Basic results Original undamped Undamped
filter (Q = ∞) filter (Q = 0)
20 dB
n 3 + 4n 1 + 2n
Qopt = Suboptimal damping Suboptimal damping
2 1 + 4n (Q = 5Qopt ) (Q = 0.2Qopt )
10 dB
Optimal damping
Z mm Z mm 0 dB (Qopt = 0.93)
= 2n 1 + 2n R0
R0
-10 dB
with -20 dB
-30 dB
optimum value of R
Qopt = 0.1 1 10
R0 f
f0
Ld L
n= R0 =
L C

R Ld
Discussion: L
+
+
Optimal R-Ld damping v1
– C v2
30 dB
• Ld is physically very small
• A simple low-cost approach to
damping the input filter 20 dB Degradation of HF
filter attenuation
• Disadvantage: Ld degrades high- Z mm
R0
frequency attenuation of filter, by
10 dB
the factor
L =1+ 1
L||L d n
0 dB
• Basic tradeoff: peak output
impedance vs. high-frequency
attenuation
-10 dB
• Example: the choice n = 1 (Ld = L) 0.1 1 10
degrades the HF attenuation by 6 Ld
L
dB, an leads to peak output
impedance of
Z mm
= 6 R0
Ld
Optimal R-Ld +
R L
+
v1 C v2
series damping –
Basic results • Does not degrade HF attenuation
R0 2 1+n 4+n • Ld must conduct entire dc current

Qopt = = 1+
n
n
R 2 + n 4 + 3n • Peak output impedance cannot be
reduced below 2 R 0
Z mm 2 1+n 2+n 100
= n
R0
with
Z mm
L
n= d 10 R0
L
R0 = L
C Qopt
1
0.1 1 10
Ld
n=
Fundamentals of Power Electronics 41 L
Chapter 10: Input Filter Design
10.4.4 Cascading Filter Sections
• Cascade connection of multiple L-C filter sections can achieve a

given high-frequency attenuation with much smaller volume and
weight
• Need to damp each section of the filter
• One approach: add new filter section to an existing filter, using new
design criteria
• Stagger-tuning of filter sections

Addition of filter section
+
Additional Existing
vg + filter Za Zi1 filter Zo v itest
– test
section
–
How the additional filter section changes the output impedance of the
existing filter:
Z (s)
1+ a
Z N1(s)
modified Z o(s) = Z o(s) Z (s) = 0
a Z (s)
1+ a
Z D1(s)
Z N1(s) = Z i1(s) v test(s) o 0

Z D1(s) = Z i1(s) i test(s) = 0

Design criteria
+
Additional Existing
vg + filter Za Zi1 filter Zo v itest
– test
section
–
Z N1(s) = Z i1(s) v test(s) o 0

(with filter output port short-circuited)
Z D1(s) = Z i1(s) (with filter output port open-circuited)

i test(s) = 0
The presence of the additional filter section does not substantially

alter the output impedance Zo of the existing filter provided that
Z a < Z N1 and
Z a < Z D1

10.4.5 Example
Two-Stage Input Filter
Requirements: For the same R2 n2L2 R1 n1L1

buck converter example,
achieve the following: L2 L1
• 80 dB of attenuation at 250 kHz vg +

– C2 C1
Zo
• Section 1 to satisfy Zo
impedance inequalities as Section 2 Section 1
before:
40 dBΩ
1 fo = 1
f1 = 2π LC ωL
2πRC
30 dBΩ
R = 12 Ω 1.59 kHz D2 || ZD ||
530 Hz
D2
20 dBΩ || ZN ||
1
10 dBΩ
ωD 2C R0 /D 2
Q=R C = fo = 3 → 9.5 dB
L f1
0 dBΩ
100 Hz 1 kHz 10 kHz
f
Section 2 impedance inequalities
R2 n2L2 R1 n1L1
L2 L1
+
vg + C2 Za Zi1 C1 vtest itest
–
–
Section 2 Section 1
To avoid disrupting the output impedance Zo of section 1, section 2

should satisfy the following inequalities:
Z a < Z N1 = Z i1 output shorted
= R1 + sn 1L 1 ||sL 1
Z a < Z D1 = Z i1 = 1 + R + sn L ||sL
1 1 1 1
output open-circuited sC 1

Plots of ZN1 and ZD1
20 dBΩ || ZD1 ||
0 dBΩ
|| ZN1 ||
|| Za ||
–20 dBΩ
90˚
∠ZN1
45˚
0˚ ∠Za
–45˚
∠ZD1
–90˚
1 kHz 10 kHz 100 kHz 1 MHz

Section 1 output impedance inequalities
30 dBΩ
|| ZD ||
|| ZN ||
20 dBΩ
fo
Cascaded
sections 1 and 2
10 dBΩ
Section 1
alone
0 dBΩ
-10 dBΩ
-20 dBΩ
1 kHz 10 kHz 100 kHz

Resulting filter transfer function
20 dB
|| H ||
0 dB
-20 dB
-40 dB
-60 dB
-80 dB – 80 dB
at 250 kHz
-100 dB
-120 dB
1 kHz 10 kHz 100 kHz 1 MHz
f

Comparison of single-section and
two-section designs
Lf
330 µH Rf
Cf 0.67 Ω
vg +
–
470 µF Cb
1200 µF
R2 n2L2 R1 n1L1
0.65 Ω 2.9 µH 1.9 Ω 15.6 µH
L2 5.8 µH L1 31.2 µH
C2 C1
vg +
–
11.7 µF 6.9 µF

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Chapter 10

Input Filter Design

Approximate Fourier series of ig(t):

Magnitudes and phases of input current harmonics are modified by

The input filter may be required to attenuate the current harmonics by

Fundamentals of Power Electronics 3 Chapter 10: Input Filter Design

Ability of the device (e.g. power supply) to:

Radiated Conducted Radiated Conducted Electrostatic

Fundamentals of Power Electronics 4 Chapter 10: Input Filter Design

AC line source ig(t) i2(t) pload(t) = VI = Pload

AC/DC rectifier Energy storage Regulated

Sample of EMC regulations that include limits on radio-

R1 5Ω 50µH L1 • LISN: “Line Impedance

Device under test

50Ω impedance of the power source

Fundamentals of Power Electronics 6 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 7 Chapter 10: Input Filter Design

AC line source pload(t) = VI = Pload

Differential-mode EMI currents

• Differential mode EMI: input current waveform of the PFC. Differential-mode

A typical design approach:

Fundamentals of Power Electronics 9 Chapter 10: Input Filter Design

2. Later, the problem of conducted EMI is addressed. An input filter is

Fundamentals of Power Electronics 10 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 11 Chapter 10: Input Filter Design

Control-to-output transfer function is Controller

Fundamentals of Power Electronics 12 Chapter 10: Input Filter Design

Zo(s) = output impedance of

Fundamentals of Power Electronics 13 Chapter 10: Input Filter Design

Gvd (s) Z o(s) = 0

Z D(s) = Z i(s) is the converter input impedance, with d set to zero

(see Appendix C for proof using EET)

Fundamentals of Power Electronics 14 Chapter 10: Input Filter Design

Table 10.1 Input filter design criteria for basic converters

Converter ZN(s) ZD(s) Ze(s)

Fundamentals of Power Electronics 15 Chapter 10: Input Filter Design

The correction factor has a magnitude of approximately unity provided

These provide design criteria, which are relatively easy to apply.

Fundamentals of Power Electronics 16 Chapter 10: Input Filter Design

A similar analysis leads to the following inequalities, which guarantee

The quantity Ze is given by:

(converter input impedance when the output is shorted)

Fundamentals of Power Electronics 17 Chapter 10: Input Filter Design

– • If losses are negligible, then

Fundamentals of Power Electronics 19 Chapter 10: Input Filter Design

It can be shown that the closed-loop converter input impedance is

where T(s) is the converter loop gain.

Fundamentals of Power Electronics 20 Chapter 10: Input Filter Design

Small-signal model D = 0.5

Input filter Converter model

Fundamentals of Power Electronics 23 Chapter 10: Input Filter Design

No resistance, hence poles are undamped (infinite Q-factor).

Fundamentals of Power Electronics 24 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 25 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 26 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 27 Chapter 10: Input Filter Design

Undamped filter: Two possible approaches:

Fundamentals of Power Electronics 28 Chapter 10: Input Filter Design

The power loss in Rf is Vg2/ Rf,

A solution: add dc blocking

Fundamentals of Power Electronics 29 Chapter 10: Input Filter Design

|| Zo ||, with large Cb

Fundamentals of Power Electronics 30 Chapter 10: Input Filter Design

Fundamentals of Power Electronics 31 Chapter 10: Input Filter Design