University of Engineering and Department of

Technology, Taxila Computer Science, UET

Taxila

Digital Logic & Design

Dr. Farrukh Zeeshan Khan

October 11, 2017 Department of Computer Science, UET Taxila 1

 Logic Gates

• Basic Building Blocks

• Logic Gate Symbol
• Unique function
• Truth or Function Table
• Function Expression
• Timing Diagram
 AND Gate

• 1 output
• 2 inputs
• 3 inputs
• 4 inputs 0 &
0

• Multiple inputs
0
 AND Gate function

• Logical Multiplication function

Input Output
F  A B
A B F
0 0 0 F  A  B  C  ....  N
0 1 0
1 0 0
1 1 1
 AND Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
 OR Gate

• 1 output
• 2 inputs
• 3 inputs
0 >=1
• 4 inputs 0
0

• Multiple inputs
 OR Gate function

• Boolean Add function

Input Output F  A B
A B F
0 0 0
0 1 1
F  A  B  C  ..  N
1 0 1
1 1 1
 OR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
 NOT Gate

• 1 input
• 1 output
 NOT Gate function

• Invert function

Input Output
A F
0 1
1 0

FA
 NOT Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
 AND Gate Applications

• Enable/Disable Device
– Counter counts when it receives pulses

Clock Pulses U/D

Counter

B1

Reset B8

A
Carry out

B ENB

Disable
Enable
 OR Gate Applications

• Car door open alarm

Front left door

Rear left door
Alarm
Front right door
Rear right door
 NOT Gate Applications

• 1’s Complement

1 1 0 0 1 0 1 0

0 0 1 1 0 1 0 1
Alternate Representations
 NAND Gate

• 1 output
• 2 inputs
• 3 inputs
• 4 inputs 0 &
0

• Multiple inputs
0
 NAND Gate function
• NOT-AND function

Input Output
A B F F  A B
0 0 1 F  A  B  C  ....  N
0 1 1
1 0 1
1 1 0
 NAND Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
 NAND Universal Gate

Input Output
A B F
0 0 1
0 1 1
1 0 1
1 1 0
 NAND Universal Gate

Input Output Output

A B F1 F
0 0 1 0 1 2
0 1 1 0
1 0 1 0
1 1 0 1
 NAND Universal Gate

Input Output
A B F
0 0 0
0 1 1 1
3
1 0 1 2
1 1 1
 NOR Gate

• 1 output
• 2 inputs
• 3 inputs 0 >=1

• 4 inputs
0
0

• Multiple inputs
 NOR Gate function

• NOT-OR function

Input Output
A B F
F  A B
0 0 1 F  A  B  C  ....  N
0 1 0
1 0 0
1 1 0
 NOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
 NOR Universal Gate

Input Output
A B F
0 0 0
0 1 1
1 2
1 0 1
1 1 1
 NOR Universal Gate

Input Output
A B F
0 0 0
1
0 1 0
3
1 0 0 2
1 1 1
 NAND-NOR Universal Gate

1 1
3 4 3 4
2 2
 NAND Gate Applications
• Device Failure Alarm

ALARM
 NOR Gate Applications
• Washing Machine Controller

Switch
 XOR Gate

• 1 output
• 2 inputs
• Multiple inputs
0 =1
0
0
 XOR Gate function

Input Output
F  A B
A B F
0 0 0
0 1 1
1 0 1
1 1 0
 XOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
 XNOR Gate

• 1 output
• 2 inputs
• Multiple inputs
0 =
0
0
 XNOR Gate function

Input Output
A B F F  A B
0 0 1
0 1 0
1 0 0
1 1 1
XNOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
 XOR Gate Applications
• Detecting odd number of 1’s

B 1

3
C

D 2
 XNOR Gate Applications
• Detecting even number of 1’s

B 1

3
C

D 2