IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO.

2, JUNE 2015 339

A Quasi-Z-Source Direct Matrix Converter Feeding

a Vector Controlled Induction Motor Drive
Omar Ellabban, Senior Member, IEEE, Haitham Abu-Rub, Senior Member, IEEE,
and Baoming Ge, Member, IEEE

Abstract— This paper proposes a novel four-quadrant vector Dh Shoot-through duty ratio in
controlled induction motor (IM) adjustable speed drive (ASD) half carrier cycle (%).
system based on a recently proposed matrix converter topology
called quasi-Z-source direct matrix converter (QZSDMC). The DMC Direct matrix converter.
QZSDMC is formed by cascading the quasi-Z-source impedance F IM Friction coefficient (N.m.s).
network and the conventional direct matrix converter (DMC). Fs QZSDMC switching frequency (Hz).
The QZSDMC can provide buck-boost operation with voltage G QZSDMC voltage gain.
transfer ratio controlled by controlling the shoot-through duty i dr , i qr dq axes rotor current
ratio and bidirectional operation capability. The control strategy,
which is based on the indirect field oriented control algorithm, is components (A).
able to control the motor speed from zero to the rated value IFOC Indirect field oriented control.
under full load condition during motoring and regenerating IM Induction motor.
operation modes. The operating principle of the proposed system IMC Indirect matrix converter.
is presented in detail. The simulation and the real-time implemen- IMRFC Integrated matrix-reactance
tation results, using dSPACE 1103 ControlDesk, validate the high
performance of the proposed four-quadrants IM-ASD based on frequency converter.
QZSDMC system. The proposed four-quadrant vector controlled J IM Inertia (kg.m2).
IM-ASD system based on the QZSDMC topology overcomes K is Speed controller integral
the voltage gain limitation of the traditional DMC and achieves gain constant.
buck and boost condition in four-quadrant modes with reduced
K ii Current controller integral
number of switches, therefore achieving low cost, high efficiency,
and reliability, compared with back-to-back converter. gain constant.
Index Terms— Direct matrix converter (DMC), indirect field K ps Speed controller proportional
oriented control (IFOC), induction motor (IM), quasi-Z-source gain constant.
converter (QZSC), quasi-Z-source DMC (QZSDMC), Z-source K pi Current controller proportional
converter (ZSC). gain constant.
N OMENCLATURE L a1 , L a2 , L b1 , L b2 , QZS-network inductances (H).
ASD Adjustable speed drive.
L c1 , L c2 = L
BQZSDMC Boost factor for the QZSDMC.
Lf Input filter inductance (H).
BZSDMC Boost factor for the ZSDMC.
L lr IM stator inductance (H).
Ca1 , Ca2 , Cb1 , Cb2 , QZS-network capacitances (F).
L ls IM stator inductance (H).
Cc1 , Cc2 = C
Lm IM mutual inductance (H).
Cf Input filter capacitance (F).
M Modulation index (%).
CMRFC Cascade matrix-reactance
MC Matrix converter.
frequency converter.
MRFC Matrix-reactance frequency
D Shoot-through duty ratio (%).
converter.
Manuscript received September 1, 2013; revised December 12, 2013 and NST Nonshoot-through.
January 25, 2014; accepted February 19, 2014. Date of publication March 5, p IM no. of poles.
2014; date of current version April 30, 2015. This work was supported by
the National Priorities Research Program under Grant NPRP-EP X-033-2- PWM Pulsewidth modulation.
007 from the Qatar National Research Fund (a member of Qatar Foundation). QZSC Quasi-Z-source converter.
Recommended for publication by Associate Editor Luca Zarri. QZSDMC Quasi-Z-source direct matrix
O. Ellabban is with the Department of Power and Electrical Machines,
Faculty of Engineering, Helwan University, Cairo 11790, Egypt and with the converter.
Electrical and Computer Engineering Department, Texas A&M University at Rf Input filter resistance ().
Qatar, Doha 23874, Qatar (e-mail: omarellabban@hotmail.com). Rr IM rotor resistance ().
H. Abu-Rub is with the Electrical Engineering Department, Texas
A&M University at Qatar, Doha 23874, Qatar (e-mail: haitham.abu-rub@ Rs IM stator resistance ().
qatar.tamu.edu). S0 Gate signal for the switches
B. Ge is with the School of Electrical Engineering, Beijing Jiaotong Sa , Sb , Sc .
University, Beijing 100044, China, and with the Department of Electrical and
Computer Engineering, Michigan State University, East Lansing, MI 48824 S A , S B , SC Three PWM pulse sequences.
USA (e-mail: gebaoming@tsinghua.org.cn). Sa , Sb , Sc = S0 QZS-network bidirectional switches.
Color versions of one or more of the figures in this paper are available S Aa , S Ab , S Ac , S Ba , S Bb , QZSDMC nine switching signals.
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2014.2309979 S Bc , SCa , SCb , SCc
2168-6777 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
340 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO. 2, JUNE 2015

ST Shoot-through.
Sx1 , S y1 , Sz1 Top voltage envelope indicators.
Sx2 , S y2 , Sz2 Bottom voltage envelope indicators.
T∗ IM torque reference (N.m).
T0 ST time interval (s).
T1 NST time interval (s).
THD Total harmonic distortion. Fig. 1. (a) DMC and (b) IMC topology.
Ts Switching cycle (s).
v A , v B , vC QZSDMC three phase output voltage The matrix converter is an attractive alternative to the back-
references (pu). to-back converter because it can convert an ac voltage directly
va , vb , vc QZSDMC three phase input voltage into an ac output voltage of variable amplitude and frequency
references (pu). without the need for an intermediate dc-link and capacitor.
vdr , vqr dq axes stator voltage components (V). Furthermore, it provides bidirectional power flow, sinusoidal
vi Input voltage amplitude (V). input/output currents, controllable input power factor, and has
vo Output voltage amplitude (V). compact design. The volume savings of a matrix converter
VSI Voltage-source inverter. compared with a back-to-back converter has been estimated to
ymax , ymin Top and bottom envelopes of the input be a factor of three [3]. The large dc-link capacitor and large
voltages, respectively. input inductors of the back-to-back converter are replaced
ZSC Z-source converter. by small input filter with capacitors and inductors in the
ZSDMC Z-source direct matrix converter. matrix converter. Furthermore, because of a high integration
ζ Damping ratio. capability and higher reliability of the semiconductor devices,
θe IM rotor flux angle (rad). the matrix converter topology is a better solution for extreme
λdr , λqr dq axes rotor flux components (Wb). temperatures and critical volume/weight applications [5].
λr∗ IM rotor flux reference (Wb). Matrix converters can be divided into two categories: the
σ IM leakage factor. DMC and IMC, as shown in Fig. 1. The DMC performs the
ωe IM electric speed (rad/s). voltage and current conversion in one stage (direct) power
ωn System natural frequency (rad). conversion while the IMC features a two-stage (indirect)
ωr IM rotor speed (rad/s). power conversion. The DMC and IMC circuit topologies
ωsl Slip frequency (rad/s). are equivalent in their basic functionality. The difference in
the categories results from a difference in loading of the
I. I NTRODUCTION semiconductors and a different commutation scheme. The IMC

T HE use of variable speed motor drives is a growing trend

in industrial and automotive applications, guaranteeing
high efficiency, increased energy saving, and higher versa-
tility and flexibility [1]. The back-to-back converter, which
is formed by tying two VSI bridges together at their shared
dc-link, is commonly applied in many motor drive applica-
tions. One of the converters operates in the rectifying mode,
while the other converter operates in the inverting mode. The
dc-link voltage must be higher than the peak line-to-line volt-
age to achieve full control of the motor torque [2], [3]. Despite
being a well-proven topology, the back-to-back converter still
has limitations since it requires a large capacitor in the dc-link
and a heavy filter inductor at the input terminals. The dc-link
capacitor is a critical component, especially in high-power
or high-voltage applications, since it is large and expensive
component. Further, it has a limited service lifetime, and is
well known to be a primary source of failure in most of the
converters [4]. The source-side inductors are also a burden to
the system; their size is typically 20%–40% of the system size
when operating at a switching frequency of several kilohertzs.
Furthermore, the back-to-back topology is sensitive toward
electromagnetic interference and other sources of noises that
can accidentally turn ON two switches from the same phase
leg, causing a short circuit fault in turn. Thus, the drawbacks of
conventional back-to-back converters are high cost, large size,
heavy weight, relatively high energy losses, and sensitivity
toward electromagnetic interference [3].
has a simpler commutation due to its two-stage structure,
however, this is achieved at the expense of more series-
connected power devices in the current path, which results in a
higher semiconductor losses and typically a lower achievable
efficiency compared with the DMC. However, the differences
between the control performances of DMC and IMC are quite
negligible in practice. Therefore, the DMC will be investigated
within this paper as a candidate topology to achieve highest
conversion efficiency [6].
For all these attractive properties, the matrix converter has
not yet gained much attention in the industry due to its
several unsolved problems. The most critical problem is the
reduced voltage transfer ratio, which is defined as the ratio
between the output and the input voltages, and has been
constrained to 0.866 when using linear modulation [5]. Several
researches on the overmodulation have been carried out to
overcome the problem of low voltage transfer ratio. However,
the overmodulation can only be achieved at the expense of the
quality of both output voltage and input current [7].
Improving the voltage transfer ratio is an important
research topic. One easy solution is to connect a transformer
between the power supply and the MC. However, the mains
frequency transformer is bulky, expensive, and affects the
system efficiency. Other solution is to use a MRFC, which
consists of a MC and a ac chopper, and has a voltage transfer
ratio greater than one. The MRFC converter is categorized
into two groups: the integrated and cascade MRFCs, as shown
ELLABBAN et al.: QZSDMC FEEDING A VECTOR CONTROLLED IM DRIVE
Fig. 2. (a) IMRFC and (b) CMRFC topologies.
Fig. 3. (a) Basic ZSC and (b) QZSC structures.
in Fig. 2 [8]. Unfortunately, the IMRFC typology has several
disadvantages. First, the control algorithm is complicated
due to the required synchronization between the MC and
the ac chopper. Second, the voltage transfer ratio strongly
dependents on the circuit and the load parameters. Finally,
the input power factor is lower than other MCs even for a
purely resistive load. The CMRFC topology has less passive
components compared by the IMRFC topology; however, it
has limited voltage gain, complicated damping control of the
input current and disturbed output current.
The ZSC, as shown in Fig. 3(a), is an innovative power
electronics converter technology presented recently. It employs
a unique impedance network to couple the main circuit of
the converter to the power source. With proper control, the
ZSC can buck or boost voltages to a desired magnitude, which
might be greater than the available dc input voltage. The ZSC
uses the ST state, turning ON two switches from the same
phase leg, to boost the input voltage. Therefore, the ST state
now is one of the converter’s normal operating states and no
longer a potential danger for the circuit; in addition, there is no
requirement of the dead time with the ZSC, hence reliability
of the system is improved [9].
The basic ZSC topology has some significant drawbacks,
namely that the input current is discontinuous in the boost
mode and the Z-network capacitors must sustain high voltage.
Discontinuous input current is prohibited for many sources and
requires large input filters. To a great extent, this shortcoming
is avoided in the QZSC, as shown Fig. 3(b), by the presence
of an input coil in the QZSC that buffers the source current.
Moreover, voltage on one of the Z-network capacitors is
lower than in case of the basic ZSC topology. In addition,
it is also possible to develop joint grounding of the input
power source and the dc-link bus, which reduce the common-
mode noise. Hence, the QZSC topology has no disadvantages
when compared with the traditional ZSC topology. The QZSC
topology therefore can be used in any application in which the
basic ZSC topology would be used [10].
Therefore, by introducing the Z-source network to the
conventional MC, which was recently proposed as ZSDMC,
as shown in Fig. 4 [11]–[13], it is possible to overcome
the low voltage gain of the traditional MC; in addition, the
341
Fig. 4. Voltage fed ZSDMC topology.
Fig. 5. Voltage fed QZSDMC topologies with (a) discontinuous and
(b) continuous input current.
Z-source network allows the short circuit, which makes the
ZSDMC commutation easier. The ZSDMC is derived from the
traditional DMC by only adding three inductors, capacitors,
switches, and diodes. However, the ZSDMC has a limited
voltage boost ratio (voltage gain can only reach 1.15), inherited
phase shift caused by the Z-network, which makes the control
inaccurate, and also discontinuous current in the front of
Z-source network. However, for the QZSDMC, as shown in
Fig. 5, the voltage gain can go to four to five times or even
higher depending on the voltage rating of the switches, no
phase shift, which can cause less error in the control, and
lower switch voltage and current stress [14]. In addition, the
circuit in Fig. 5(b) has continuous input current [15].
Compared with traditional DMC, ZSDMC and QZSDMC
both can boost voltage higher than 0.866. The boost ratio
depends on the duty cycle of extra ST state. Also, the
QZSDMC topology can conduct less voltage/current stress on
the switch and passives, less input and output harmonics and
higher power factor than the ZSDMC. Moreover, compared
with ZSDMC topology, the QZSDMC is a component less,
size compact, high efficient, and a wide range buck-boost
matrix converter [16].
Nowadays, IM are widely used in industry due to their
reliability, robustness, high efficiency, and ability to operate
in wide torque and velocity ranges. To achieve high dynamic
performance in an IM drive application, vector control is
often applied. Vector control makes ac drives behave like dc
drives by independently controlling the flux and the torque
of the ac motor. Therefore, the field oriented control is used
in the design of IM drives in high-performance applications.
The main idea of the field oriented control is to control
of the torque and the flux separately. IFOC is one of the
most effective vector control of IMs due to the simplicity of
designing and construction [17]–[20].
In this paper, the application of the QZSDMC topology
for four-quadrant IM-ASD system is proposed. The QZSDMC
can produce the desired ac output voltage, even greater than
the input line voltage due to its boost voltage capability.
The four-quadrant speed control is implemented using the
342 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO. 2, JUNE 2015

Fig. 6. QZSDMC-based IM-ASD system.

Fig. 8. Boost factor of the ZSDMC and QZSDMC versus D.

voltage equations:
⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤
vab v La1 vCa1 vCb1 v Lb1
⎣ vbc ⎦ = ⎣ v Lb1 ⎦ + ⎣ vCb1 ⎦ − ⎣ vCc1 ⎦ − ⎣ v Lc1 ⎦ (1)
vca v Lc1 vCc1 vCa1 v La1
Fig. 7. Equivalent circuit of the QZSDMC. (a) ST state. (b) NST state.
where v denotes the voltage, and the subscript C x1 and C x2
are the capacitors 1 and 2 of phase-x; L x1 and L x2 for the
IFOC during motoring and regenerating operation modes. inductors 1 and 2 of phase-x; x = a, b, c. During the NST
The system’s configuration, equivalent circuit, analysis, and state, its equivalent circuit is shown in Fig. 7(b), and one can
control are presented in detail. Simulation and dSPACE real- get
time implementation results demonstrate the high perfor- ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤
vab v La1 vCa1 va  b  vCb1 v Lb1
mance of the proposed four-quadrants QZSDMC-IM-based ⎣vbc ⎦= ⎣v Lb1 ⎦+⎣vCb1 ⎦+⎣vb c ⎦−⎣vCc1 ⎦−⎣v Lc1 ⎦. (2)
ASD system.
vca v Lc1 vCc1 vc  a  vCa1 v La1
In steady state, the average voltage of the inductors over one
II. QZSDMC-BASED ASD switching cycle should be zero, and owing to the symmetric
voltages of three-phase capacitors, one gets [12]
A. Topology ⎡ ⎤ ⎡ ⎤
va  b  vab
The main circuit configuration of the proposed QZSDMC- ⎣ vb  c  ⎦ = 1 ⎣ vbc ⎦. (3)
based four-quadrant IM-ASD system is shown in Fig. 6.
v  1 − 2D v
ca ca
It consists of four parts, namely, input filter, QZS-network,
DMC, and IM. The QZS-network includes six inductors Define B as the boost factor and it is expressed as [12]
(L a1 , L a2 , L b1 , L b2 , L c1 , L c2 ), six capacitors (Ca1 , Ca2 , Cb1 , vo 1
Cb2 , Cc1 , Cc2 ), and three additional bidirectional switches BQZSDMC = = (4)
vi 1 − 2D
(Sa , Sb , Sc ). One gate signal can be used to control these
three switches because they have the same switching state. where vi is the amplitude of input voltage source and vo is
Therefore, the drive signal for Sa , Sb , and Sc can be denoted the output voltage amplitude of the QZS-network. However,
as S0 . the boost factor for the ZSDMC is given by [12]
vo 1
BZSDMC = = √ . (5)
vi 3D − 3D + 1
2
B. Operation and Modeling
Fig. 8 shows the boost factor for both converter topologies.
The operation principle of the QZSDMC can be divided Thus, the voltage gain G of the QZS-network in the one
into two switching states: ST and NST states. Fig. 7 shows the switching cycle, is given by
QZSDMC equivalent circuits during these states. During the
ST state, Fig. 7(a), switch S0 is off and the output of G = BM. (6)
the QZSDMC is shorted for boost operation. While, dur-
ing the NST state, Fig. 7(b), switch S0 is on for normal
DMC operation. Due to the symmetry of the system, induc- C. ST Boost Control Method
tors of QZS-network (L a1 , L a2 , L b1 , L b2 , L c1 , L c2 ) have the The principle of applying ST state for the QZSDMC is
same inductance (L), and the capacitors (Ca1 , Ca2 , Cb1 , Cb2 , to replace some of the zero state by ST state, to not affect
Cc1 , Cc2 ) also have the same capacitance (C). the output voltage. Using the carrier-based PWM, the zero
For one switching cycle, Ts , the time interval of the ST output voltage state in MC is corresponding to the switching
state is T , and the time interval of the NST state is T1 , state that all three output phases are connected to the same
hence, Ts = T + T1 , and the ST duty ratio is D = T /Ts . input phase. It happens when all three phase output voltages
From Fig. 7(a), during the ST state, one can get the following are either higher or lower than the carrier signal. Therefore,
ELLABBAN et al.: QZSDMC FEEDING A VECTOR CONTROLLED IM DRIVE 343

Fig. 9. Simple boost PWM control for the QZSDMC. Fig. 11. Voltage envelopes indicators.

according to the following logics:

S Aa = Sx1 S A + Sx2 S̄ A
S Ab = Sy1 S A + S y2 S̄ A
S Ac = Sz1 S A + Sz2 S̄ A
S Ba = Sx1 S B + Sx2 S̄ B
S Bb = Sy1 S B + Sy2 S̄ B
S Bc = Sz1 S B + Sz2 S̄ B
SCa = Sx1 SC + Sx2 S̄C
SCb = Sy1 SC + Sy2 S̄C
SCc = Sz1 SC + Sz2 S̄C . (7)
The above logical functions can be used to drive the
QZSDMC after inserting the ST states.
A simple boost control is achieved through two ST
Fig. 10. QZSDMC switching states generation. references, in which both references are related to both
envelopes by [12]
the ST reference should be either higher than the maxi- (ymax − ymin )n + ymax + ymin
vst,r = (8)
mum reference voltage or lower than the minimum reference 2
voltage [14]. where n will determine the ST duty ratio, and its value has
All the boost control methods that have been explored for a limitation that the resultant minimum value of the top ST
the traditional ZSC, such as simple boost, maximum boost, reference should be less than 0.5 p.u. and larger than M.
maximum constant boost, and modified space vector modula- Therefore, 1≥ n ≥ (1+4M)/3 for the top ST reference, and
tion [21], can be applied to the QZSDMC with a modification its negative value is (−n) for the bottom ST reference. The
of the carrier envelope. Fig. 9 shows a simple boost PWM modulation index should be less than 0.5, given that the output
control strategy for the QZSDMC. The carrier waveform has references v A , v B , and vC can be any frequency with any phase
the same envelope with the three-phase source voltages, va , angle and with no harmonic injection. ymax and ymin are the
vb , and vc . The top envelope consists of the maximum voltage top and bottom envelopes of the source voltages, respectively.
among the three input phase voltages, and the bottom envelope For the simple boost control, the ST interval from the top
consists of the minimum voltage among them. During each reference can be calculated as [12]
switching period, the modified carrier signal is compared with 1−n
the output voltage references v A , v B , and vC to produce their T0 = Tc (9)
2
PWM switching sequences (S A , S B , SC ). The ST pulses are
where T0 and Tc are the ST duration per switching cycle
generated by comparing the ST references with the modified
and switching time, respectively, and its ST duty ratio in half
carrier waveform, as shown in Fig. 10. The PWM switching
carrier cycle is [12]
sequences S A , S B , and SC should be distributed to nine
ac switches to generate the expected PWM pulses. For this 1−n
Dh = . (10)
purpose, six additional logical signals are used, as shown in 2
Fig. 11, where Sx1 , Sy1 , and Sz1 denote the indicators for their Fig. 12 shows the complete process to generate the switch-
respective phase-a, -b, and -c of the top voltage envelope. ing signals for the QZSDMC. First, the triangle carrier signal
Sx2 , Sy2 , and Sz2 denote the indicators for their respective is modulated by the input reference signals va , vb , and vc
phase-a, -b, and -c of the bottom voltage envelope. These to generate the modified carrier signal, which is bounded by
six voltage envelope indicators are combined with the three the maximum and minimum envelopes of the input reference
PWM switching sequences to generate nine switching signals signals. Second, the ST references are generated from the input
344 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO. 2, JUNE 2015

Fig. 12. Block diagram of QZSDMC PWM generation with ST insertion.

reference signals and the desired boost ratio using (8)–(10). Fig. 13. Block diagram of the IFOC controlled IM.
Then, the switching sequences S A , S B , SC , and ST pulses are
generated by comparing the output voltage references v A , v B , TABLE I
and vC and the ST references with the modified carrier signal. PI C ONTROLLERS PARAMETERS E QUATIONS
Furthermore, voltage envelopes indicators are generated from
the input reference signals va , vb , and vc . For example, Sx1 = 1
when phase-a voltage is the largest value among the three-
phase voltages and Sx2 = 1 when phase-a has the minimum
voltage among the three-phase voltages. Finally, these six
voltage envelope indicators are combined with the three PWM
switching sequences, S A , S B , SC , and the ST pulses to generate
The slip frequency, ωsl , is given by
nine switching signals.
Lm
ωsl = i qs . (14)
III. IFOC T ECHNIQUE τr λr∗
Vector control is a technique, which allows the IM to act
The rotor flux angle θe which required for coordinate trans-
like a separate excited dc machine with decoupled control
formation, is generated from the rotor speed, ωr , and the slip
of torque and flux, making it possible to operate the IM
frequency, ωsl , as given by
as a high-performance four-quadrant servo drive. The idea 
behind vector control is that the stator current of the IM is θe = (ωe + ωr )dt. (15)
decomposed into orthogonal components as a magnetization
component (flux producing) and a torque component. These The torque reference T ∗ is generated by a PI speed controller
components are controlled individually. To obtain high based on the reference speed ωr∗ and the measured rotor
dynamic performance of the IM, the magnetizing current speed ωr . The rotor flux reference λr∗ is kept constant at its
component is maintained at its rated level while the torque rated value. The feedback dq-axis stator currents i ds and i qs
should be controlled through the torque component of the ∗ and i ∗ , and the errors
are compared with their references, i ds qs
stator current. The field orientation can be generally classified are sent to the PI current controllers to generate the stator
into stator flux, air-gap flux, and rotor flux orientations. Since voltage reference components vds and v , as indicated in (16),
qs
the rotor flux orientations are extensively used in ac drives, while, the remaining terms in (6) must be added to the output
this scheme is used in this paper [17]. of each controller for voltage compensation [18]
The rotor flux orientation is achieved by aligning the d-axis
of the synchronous reference frame with the rotor flux λ̄r dids L m dλdr
vds = rs i ds + σ L s + − ωe σ L s i qs
vector. The resultant d- and q-axis rotor flux components are   dt
L r dt
 

given as 
vds comp
vds
λqr = 0 diqs Lm
vqs = rs i qs + σ L s +ωe σ L s i ds + ωe λdr (16)
λdr = λr . (11)   dt

 
Lr

.
 comp
The d-axis current i ds is referred to as flux-producing current vqs vqs
while the q-axis current i qs is the torque-producing current.
In the field-oriented control i ds , is normally kept at its rated The dq-axis voltages in the synchronous frame are then
∗ , v∗ , and v∗
transformed to the three-phase stator voltages vas
value while i qs is controlled independently. These steady-state bs cs
dq-components of the current are given as in the stationary frame for the PWM block.
Fig. 13 shows the block diagram of the IFOC controlled IM.
∗ λr∗ The parameters of the speed and current PI controllers are
i ds = (12)
Lm calculated based on Table I, where ξ, ωn are the desired
∗ 2 2 Lr T ∗ damping and dynamics response specifications, Tm = σ L s /rs ,
i qs = . (13)
3 p L m λr∗ σ = 1 − L 2m /L s L r [19].
ELLABBAN et al.: QZSDMC FEEDING A VECTOR CONTROLLED IM DRIVE
Fig. 14. Block diagram of the proposed QZSDMC-based IM-ASD.
TABLE II
S IMULATION S YSTEM PARAMETERS
IV. P ROPOSED QZSDMC-BASED IM-ASD S YSTEM
The control block diagram of the IM drive system with
QZSDMC is shown in Fig. 14. The speed encoder detects
the rotor speed to compare it with the reference speed.
The speed controller, a PI regulator, deals with the speed
error and generates the required torque reference. The IFOC
block generates the modulation signals, vabc , according to the
operating conditions during different operating modes. The ST
duty ratio, D, is designed according to (4), the corresponding
voltage gain (G) and output voltage can be obtained to
meet the desired voltage value. The carrier-based modulator
generates the gating signals for the DMC and the additional
switches in the QZS-network.
V. S IMULATION AND R EAL -T IME
I MPLEMENTATION R ESULTS
A. MATLAB Simulation Results
To verify the proposed QZSDMC-IM drive system per-
formance, simulations are carried out using MATLAB/
SIMULINK software for a 4-kW IM using the parameters in
Table II. The QZSDMC-IM ASD system simulating model is
345
Fig. 15. Motor response during motoring and regenerating operation
modes.
Fig. 16. Motor response during speed reverse.
Fig. 17. Steady-state motor current and voltage waveforms during motoring
at rated conditions.
tested during the motoring and regenerating operation modes,
as shown in Fig. 15: the acceleration mode at no load during
the time interval 0–1 s; the steady-state operation mode with
half the rated load torque and the rated speed during the
time interval 1–2 s; the steady-state operation mode with the
rated load torque and the rated speed during the time interval
2–3 s; the deceleration mode from the rated speed to negative
the rated speed with negative the rated torque during time
interval 3–4 s; and the regeneration mode with the rated load
and negative the rated speed during the time interval 4–5 s.
Fig. 15 shows the system ability to perfectly track the speed
and load torque references during different operation modes.
Also, Fig. 16 shows the motor response during speed reverse,
where, the motor speed tracks its reference and the motor
current and voltage waveforms are reversed. Fig. 17 shows
the steady-state motor response during motoring operation at
rated conditions.
The given ST duty ratio D is 0.1. According to (4) and (6),
one can get the boost factor B of 1.25 and the maximum
value of voltage gain G is 1.125. Fig. 18 shows the output line
voltage amplitude (around 670 V) of QZS-network, which is
346 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO. 2, JUNE 2015
Fig. 18. Input and output line-to-line voltage of the QZS-network.
Fig. 19. Input and output current of the QZS-network.
Fig. 20. (a) QZSDMC input current THD. (b) Motor current THD.
1.25 times of input line voltage amplitude. Fig. 19 shows the
input and output currents of the QZS-network, and Fig. 20
shows the THD factors of the input and output currents of the
QZSDMC.
Fig. 21. dSPACE real-time implementation block diagram.
Fig. 22. Real-time motor response during speed reverse with rated load
torque.
Fig. 23. Real-time motor steady-state line voltage and phase current
waveforms during motoring operation under rated conditions.
Fig. 24. Real-time waveforms of the Input and output line-to-line voltage
of the QZS-network.
B. Real-Time Implementation Results
The real-time system, as shown in Fig. 21, contains a
DS1103 PowerPC processor board, including onboard I/O
for analog-to-digital converters, digital-to-analog converters,
digital I/O, and a RS232 serial interface. Also, included in the
system is a bus interface board to connect the real-time system
to the PC. For modeling and code generation MATLAB,
SIMULINK, Real-Time Workshop by The MathWorks and the
Real–Time Interface by dSPACE are installed. ControlDesk
software from dSPACE is used for as a front-end and serves
to provide instrumentation, parameterization, measurements,
and experiment control. Fig. 22 shows the motor real-time
response during speed reverse with rated load torque and
Fig. 23 shows the real-time motor steady-state response
during motoring operations with rated conditions. Fig. 24
shows the real-time waveforms of the input and output
ELLABBAN et al.: QZSDMC FEEDING A VECTOR CONTROLLED IM DRIVE
line-to-line voltage of the QZS-network, where the required
voltage gain is achieved by inserting the ST state. There is
a good matching between MATLAB simulation and dSPACE
real-time implementation results.
VI. C ONCLUSION
This paper proposed a new four-quadrant vector controlled
IM ASD system based on the QZSDMC topology. The pro-
posed system overcomes the reduced voltage transfer ratio
limitations of traditional DMC-based ASD system, there-
fore, the proposed QZSDMC-IM-based ASD will increase
the application of the DMC in different industry fields The
proposed ASD system can operate at full load with small QZS-
network elements. The QZSDMC can achieve buck and boost
operation with reduced number of switches needed, therefore
achieving low cost, high efficiency, and reliability, compared
with the traditional DMCs, in addition, there is no requirement
of dead time with QZS-network, hence commutation of the
QZSDMC is easier than the traditional DMC The proposed
ASD system can provide a voltage gain larger than one and can
operate in motoring and regenerating operation modes with
perfect references tracking as verified by MATLAB simulation
and dSPACE real-time implementation results.
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Omar Ellabban (S’10–M’12–SM’13) was born in
Egypt in 1975. He received the B.Sc. (Hons.) degree
in Electrical Machines and Power Engineering from
Helwan University, Cairo, Egypt, and the M.Sc.
degree in Electrical Machines and Power Engi-
neering from Cairo University, Giza, Egypt, and
the Ph.D. (Hons.) degree in electrical engineering
from Vrije Universiteit Brussel, Brussel, Belgium,
in 1998, 2005, and 2011, respectively.
He joined the Research and Development Depart-
ment, Punch Powertrain, Sint-Truiden, Belgium, in
2011, where he and his team developed a next generation, high-performing
hybrid powertrain. Since 2012, he has been an Assistant Professor with
the Department of Electrical Machines and Power Engineering, Helwan
University. In 2012, he joined Texas A&M University at Qatar, Doha, Qatar,
as a Post-Doctoral Research Associate and an Assistant Research Scientist
in 2013, where he is involved in different renewable energy projects. He
has authored more than 35 journal and conference papers, one book chapter,
and one conference tutorial. He acts as a Reviewer for different IEEE journals
and conferences. In addition, he has been listed in Marquis Who’s Who in the
World (2014, 31st Edition). His current research interests include automatic
control, motor drives, power electronics, electric vehicles, switched reluctance
motor, renewable energy, and smart grid.
Haitham Abu-Rub (M’99–SM’07) received two
Ph.D. degrees in electrical engineering and human-
ities.
He is currently a Professor with Texas A&M
University at Qatar, Doha, Qatar. He has authored
more than 200 journal and conference papers, and
is leading many potential projects in electric drives,
photovoltaic, and hybrid renewable power generation
systems with different types of power electronics
converters. He is the co-author of four books, three
of which are with Wiley (one of them is in process).
He is also an author and co-author of few book chapters. His work relates to
the high-performance electric drives, renewable energy systems, multilevel
inverters, impedance source inverters and their modifications, pulse width
modulation techniques, model predictive control, and other related topics.
His current research interests include energy conversion systems, including
renewable and electromechanical systems.
Dr. Abu-Rub is the recipient of many prestigious International awards, such
as the American Fulbright Scholarship, the German Alexander von Humboldt
Fellowship, the German DAAD Scholarship, and the British Royal Society
Scholarship. He is an Editor of the IEEE T RANSACTIONS ON S USTAINABLE
E NERGY and the IEEE J OURNAL OF E MERGING AND S ELECTED T OPICS IN
P OWER E LECTRONICS .
348 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 03, NO. 2, JUNE 2015

Baoming Ge (M’11) received the Ph.D. degree

in electrical engineering from Zhejiang University,
Hangzhou, China, in 2000.
He was a Post-Doctoral Researcher with the
Department of Electrical Engineering, Tsinghua
University, Beijing, China, from 2000 to 2002, was
a Visiting Scholar with the Department of Electrical
and Computer Engineering, University of Coimbra,
Coimbra, Portugal, from 2004 to 2005, and was a
Visiting Professor with the Department of Electrical
and Computer Engineering (ECE), Michigan State
University (MSU), East Lansing, MI, USA, from 2007 to 2008, and he is
currently with the ECE Department, MSU. He has been with the School of
Electrical Engineering, Beijing Jiaotong University, Beijing, since 2002, where
he is a Professor. His current research interests include renewable energy
power generation, electrical machines and control, power electronics systems,
and control theories and applications.