mm 40 60 80 100 120

40
2: Transistors, Fabrication, Layout

J. A. Abraham

Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M.7 – VLSI I
Fall 2011
80
August 29, 2011

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 1 / 43
 Conductivity in Silicon Lattice

Look at the behavior of crystalline silicon

mm 40 close to 60
At temperatures 0 K, electrons80 in outermost
100 shell 120
tightly bound (insulator)
At higher temps., (300 K), some electrons have thermal
energy to break covalent bonds
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 1 / 43
 The Elements (Periodic Table)

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 2 / 43
 Build Systems with Information on Electrical
Characteristics of Building Blocks (Transistors)

Thismm 40 cover semiconductor

course will not 60 80
physics 100 120

Learn this from other courses in the department

We will design VLSI circuits knowing the electrical behavior of
the transistors
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 3 / 43
 Dopants
Used to selectively change the conductivity of silicon
Silicon is a semiconductor
mm 40 60 80 100 120
Pure silicon has no free carriers and conducts poorly
Adding dopants impurities to pure silicon increases the
conductivity
40
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 4 / 43
 p-n Junctions

Diodes
mm 40 60 80 100 120
A junction between p-type and n-type semiconductor forms a
diode
Current flows only in one direction
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 5 / 43
 p-n Junction, Cont’d

mm 40 60 80 100 120

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Source: Prof. Dr. Helmut Föll, University of Kiel

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 6 / 43
 nMOS Transistor

Four-Terminal device: gate, source, drain, body

mm
Gate oxide 40 60 like a capacitor
body stack looks 80 100 120
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called
40
metal oxide semiconductor (MOS) capacitor, even
though gate material changed to polysilicon
Recent gate material in nanoscale processes is back to metal

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 7 / 43
 nMOS Transistor Operation
Body (bulk) is commonly tied to Ground (0 V)
When
mmthe gate is 40
at a low voltage
60 80 100 120
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
40

When the gate is at a high voltage

Positive charge on gate of MOS
60
capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now 80electrons can flow through n-type
silicon from source through channel to
drain, transistor is ON
ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 8 / 43
 pMOS Transistor

Similar to nMOS transistor, but doping and voltages reversed

mm
Body tied to 40
high voltage60(VDD) 80 100 120
Gate low: transistor ON
Gate high: transistor OFF
Bubble
40 indicates inverted behavior

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 9 / 43
 CMOS Fabrication
Silicon technology
CMOS transistors
mm 40 are fabricated
60 on silicon
80 wafer 100 120
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section
40 wafer in a simplified manufacturing process
of

Example inverter cross-section

Typically use p-type substrate for nMOS transistors
60
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
80 n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 10 / 43
 Well and Substrate Taps
Substrate contacts are critical to correct operation of CMOS
Substrate must
mm 40 be tied to60GND, n-well 80to VDD 100 120
(reverse-biased diodes isolate regions)
Metal to lightly-doped semiconductor forms poor connection
called Schottky Diode – use heavily doped well and substrate
contacts/taps
40

A
GND VDD
Y

60
p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 11 / 43
 Inverter Masks

Transistors and wires are defined by masks

Cross-sections
mm 40shown above60 taken along
80 dashed line
100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 12 / 43
 Examples of Fabrication Steps

Start with blank

mm 40 wafer 60 80 100 120
Build inverter from the bottom up

First step is to form the n-well

40
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip
60
off SiO2

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 13 / 43
 Oxidation and Photoresist
Grow SiO2 on top of Si wafer
mm 40◦ C with H60
900 − − 1200 2 O or O2 in 80
oxidation furnace
100 120

40

Spin-on photoresist
Photoresist
60 is a light-sensitive organic polymer which softens
where exposed to light (positive resist)

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 14 / 43
 Lithography
Use light to transfer a pattern to the wafer
Expose photoresist
mm 40 through
60 n-well mask
80 (using UV light –
100 120
example 193 nm wavelength)
“Immersion lithography” used in some nanoscale processes
Strip off exposed photoresist
40

60

Interesting physics problem

How
80 can we “print” a 45 nm feature using light with a
wavelength of 193 nm?
Significant distortion of the image!
ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 15 / 43
 Trend in Integrated Circuit Feature Sizes

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 16 / 43
 Features Smaller than Wavelength of Light Used

mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 17 / 43
 Optical Proximity Correction (OPC)
What you see is NOT what you get
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 18 / 43
 Etch and Strip Photoresist
Etch oxide with Hydrofluoric acid (HF)
Only attacks 40
mm oxide where60
resist has been
80 exposed 100 120

40

Strip remaining photoresist using mixture of acids (“piranha” etch)

60
Necessary so resist does not melt in the next step

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 19 / 43
 n-Well
Formed using ion implant (used to be diffusion)
Bombard wafer with As ions, which only enter exposed Si
mm 40 60 80 100 120
(With diffusion, wafer is placed in a furnace with As gas)
Remaining oxide is then stripped off using HF, and it is back
to the bare wafer, but with an n-well
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Subsequent steps repeat the above process

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 20 / 43
 Polysilicon
Very thin layer of gate oxide is grown on wafer
mm 40
Gate oxide thickness is <60 80
20Å (few atomic layers)100 120
One of the most critical steps in fabrication process

Polysilicon deposited on top of gate oxide

40
Grown using Chemical vapor deposition (CVD)
Wafer placed in furnace with Silane (SiH) gas
Small crystals (polysilicon) formed on wafer
Heavily
60 doped to be a good conductor

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 21 / 43
 Polysilicon Patterning
Use same lithography processing to pattern polysilicon
Reactive Ion 40
mm Etch (RIE) process
60 80 100 120
Charge buildup on un-etched polysilicon can lead to “antenna
effects” and damage gate oxide

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60

Self-aligned
80 process
Polysilicon “blocks” dopants where the channel should be
formed
ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 22 / 43
 N+ Diffusion
nMOS transistors are formed
Oxide is patterned
mm 40 to form
60the n+ regions
80 100 120
N+ diffusion forms nMOS source, drain, and n-well contact

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 23 / 43
 N+ Diffusion, Cont’d
Ion implantation used to dope silicon
n+ regions are
mm 40 formed 60 80 100 120
Oxide is stripped off to complete patterning step

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 24 / 43
 P+ Diffusion

mm set of steps
A similar 40 is used to
60form the p+80 diffusion 100
regions for 120
the pMOS transistor source and drain as well as the substrate
contact

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 25 / 43
 Contacts

mmwhere the 40
Points first level of 60
metal contacts
80 the transistors
100 120
Used to wire the devices together
Wafer is covered with thick field oxide
Oxide is etched where the contact cuts are needed
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 26 / 43
 Metalization

Used to interconnect internal nodes

mm
Aluminum was 40 the traditional
60 metal 80 100 120
Switch to Copper for high performance processes
Aluminum is sputtered over the entire wafer
Patterned to remove excess metal, leaving the wires
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 27 / 43
 Layout

mm 40 60 80 100 120
Describes actual layers and geometry on the silicon substrate
to implement a function
Need to define transistors, interconnection
40 Transistor widths (for performance)
Spacing, interconnect widths, to reduce defects, satisfy power
requirements
Contacts (between poly or active and metal), and vias
(between metal layers)
60 Wells and their contacts (to power or ground)
Layout of lower-level cells constrained by higher-level
requirements: floorplanning
“design iteration”
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 28 / 43
 Layout, Cont’d

mm 40 60 80 100 120
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and
hence speed, cost, and power)
40
Feature size f = distance between source and drain
Set by minimum width of polysilicon (= minimum “drawn”
gate length)
Feature size improves 30% every 3 years or so
60
Normalize for feature size when describing design rules
Express rules in terms of λ = f /2
e.g., λ = 0.3µm in 0.6µm process

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 29 / 43
 CMOS Inverter Layout

Note: the N- and P- well are

mm 40 60 80 100 120
not shown in the layout

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 30 / 43
 Other CMOS Layouts
Using wide transistors Using even wider transistors
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 31 / 43
 Buffer with Two Inverters
Side by side Stacked
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 32 / 43
 Improving Layout Efficiency
“Flip” a cell so that power (or ground) can be shared with another
cell
mm 40 60 80 100 120

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 33 / 43
 “Stick” Diagram and Simplified Layout of NAND Gate

mm 40 60 80 100 120
Stick diagrams identify n- and p-wells are shown
actual layers (which a
schematic does not);
both can be annotated
40
with transistor sizes

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 34 / 43
 Simplified Design Rules
Based on λ (popular in academia)
Discussed
mm in the textbook
40 60 80 100 120
Rules based on λ can theoretically be migrated to a different
technology (by changing the value of λ); in practise, all the rules
do not scale in the same way, and industry typically does not use λ
rules 40

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 35 / 43
 Inverter Layout
Dimensions of pMOS and nMOS transistors
mm
Dimensions specified
40 as Width/Length
60 80( W
L) 100 120
Minimum size, 4λ/2λ, sometimes called unit-size transistor
(pMOS transistors are typically designed to be about twice the
width of nMOS transistors, because of the mobilities of holes
and electrons)
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 36 / 43
 The MOSIS Scalable CMOS Rules

mmis a prototyping
MOSIS 40 60
and small-volume 80 100
production service for 120
VLSI circuit development
MOSIS keeps costs down by combining many designs on a
single die (multi-project chips)
40 Similar facilities exist in Europe (Europractice, CMP), Taiwan,
etc.
λ-based rules
Designs using these rules are fabricated by a variety of
60
companies
Support for submicron digital CMOS, analog (buried poly
layer for capacitor), micromachines, etc.
http://www.mosis.com/Technical/Designrules/scmos/
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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 37 / 43
 Nangate 45nm Open Cell Library
Used in the laboratory exercises
This is an open-source,
mm 40 standard-cell
60 library
80 100 120
To aid university research programs and other organizations in
developing design flows, designing circuits and exercising new
algorithms
Link
40 to the wiki:
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
Example: poly rules (note: summarized here)

Rule Value
60 Description
1 50 nm Minimum width
2 140 nm Minimum spacing
3 55 nm Min. extension
4 70 nm Min. enclosure
5 80
50 nm Min. spacing
6 75 nm Min. spacing

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 38 / 43
 Example of Other Nangate 45nm Rules

mm
Active Rules 40 60 80 100 120
Rule Value Description
1 90 nm Minimum width
2 80 nm Minimum spacing
3 – Min. well-active
4 –40 active inside

Contact Rules
Rule Value Description
1 65
60nm Minimum width
2 75 nm Minimum spacing
3 – contact inside
4 5 nm Min. active around
5 5 nm Min. poly around
6 80nm
35 Min. spacing with gate
7 90 nm Min. spacing with poly

ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 39 / 43
 Trend Towards Reducing Number of Rules
Improve manufacturability
Less flexibility40for designers
mm 60 80 100 120
Intel reduced the number of poly layout rules for logic layout
in 45nm by 37% compared with the 65 nm process
Highly regular layout greatly reduces lithographic distortions
40 Limit rules, thereby limiting the number of allowed structures
and shape relationships
Move towards 1-dimensional shapes and “Gridded Design
Rules” (GDR)

60
Example layout from Tela Innovations

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 40 / 43
 Regular Layout

Lithography simulations
mm
Lithographic 40 60
distortions reduced 80
significantly with100
1-D shapes 120
and GDR
Scan D Flip-Flop, 45nm process
Source: Tela Innovations, Inc., ISPD 2009
40

2D Conven-
tional
60
Layout

80
1D GDR
Layout
ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 41 / 43
 Copper and the Damascene Process
Source: UMC
Layers of Damascene Copper (Intel)
mm 40 60 80 100 120

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Copper Damascene Interconnect (Intel)

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 42 / 43
 Advanced Metalization
IBM Technology (in Rabaey, Digital Integrated Circuits, 2nd ed.)
mm 40 60 First commercial
80 Copper
100 process 120
(0.12µ)

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ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 43 / 43