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Reconfigurable Nonvolatile Logic Operations in Resistance
Communication
Switching Crossbar Array for Large-Scale Circuits
Peng Huang, Jinfeng Kang,* Yudi Zhao, Sijie Chen, Runze Han, Zheng Zhou, Zhe Chen,
Wenjia Ma, Mu Li, Lifeng Liu, and Xiaoyan Liu*
Conventional computer systems store information in memory
units and process information in central processing unit. This
leads to huge energy-hungry data transfer between memory
and computing units, which has been the limitation of compu-
tation speed and energy efficiency—the so-called von Neumann
bottleneck.[1,2] To break the bottleneck, it is necessary to find
new materials, new devices, and new architectures to realize
computing and memory functions.[3–11] Significant scientific
progress has been made on resistance switching (RS) devices
in terms of speed, power, integration density, and reliability for
the application of memory.[12–15] Meanwhile, implication logic
in RS devices was proposed[16] and demonstrated in a row of
devices.[10,17] However, no viable method to construct large-
scale logic circuits with RS devices has been presented. Here,
we report a new computer unit built of RS crossbar array based
on resistance switching materials, where logic and memory
functions are executed in the same devices. In the new com-
puter unit, nonvolatile NAND and AND logic operations are
executed by RS devices via resistance state interaction. By syn-
thesizing NAND and AND logic operations, resistance states
stored in devices located in arbitrary positions of RS crossbar
array can perform various logic operations via logic cascading,
such as full adder. The functions can be reconfigured at run
time simply by altering trigger signals. Leveraging the unity of
logic and memory units, the huge energy-hungry data transfer
can be vastly mitigated in this new computer unit. The demand
for energy-efficient computer systems would be increasingly
larger than ever due to the information revolutions in big data
processing, Internet of Things, and wearable devices. This
reconfigurable nonvolatile logic operations in RS crossbar
array offers a technology solution to support diverse societal
applications.
RS devices have been widely studied as one of the most
promising candidates for future memory technologies by semi-
conductor research community since 2004[18–20] even though
RS phenomenon has been reported in 1960s.[21] In 2008, RS
devices were linked with memristor, which reveals that RS
devices are not just bistable switches, rather they are dynamic
devices with highly nonlinear dynamics.[22] This extends the
Dr. P. Huang, Prof. J. F. Kang, Y. D. Zhao, S. J. Chen,
R. Z. Han, Z. Zhou, Z. Chen, W. J. Ma,
M. Li, Prof. L. Liu, Prof. X. Y. Liu
Institute of Microelectronics
Peking University
No.5 Yiheyuan Road Haidian District
Beijing 100871, P. R.China
E-mail: kangjf@pku.edu.cn; xyliu@ime.pku.edu.cn
DOI: 10.1002/adma.201602418
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functionality of circuit including RS devices, such as neuromor-
phic computing and stateful logic operations.[23] Based on the
highly nonlinear dynamics nature, implication logic operation
in RS devices was proposed in 2008.[16] ‘Stateful’ logic opera-
tions were experimentally demonstrated in a row of RS devices
via material implication in 2010.[10] RS devices are a simple
metal-insulator-metal sandwich structure, and their resistances
can be switched between two digital states, low resistance state
(LRS) and high resistance state (HRS), by two different appro-
priate voltage pulses.[24–26] Leveraging the conditional toggling
property of RS devices, logic operations can also be executed.
Therefore computing and memory units can be unified with
RS devices, which may pave the way for breaking the bottleneck
of conventional computer systems.
Figure 1a shows a 16 × 8 RS crossbar array. Each junction
between the 16 top wires (WL) and 8 bottom wires (BL) is an
RS device, whose structure is shown in the inset of Figure 1b.
The typical quasi-direct-current electrical characteristic of RS
devices is shown in Figure 1b. RS devices can be switched from
HRS to LRS when the applied positive voltage across it is larger
than program voltage VSET, and opposite operation is performed
by a negative voltage with magnitude larger than erase voltage
VRESET. Here, we define HRS as logical ‘1’ and LRS as logical
‘0’. Figure 1c shows the current response of an RS device under
voltage pulses with 100 ns width, where a +1.2 V voltage pulse
is applied to switch device to LRS from HRS, while a −1.8 V
voltage pulse can switch it to HRS from LRS. Meanwhile, the
device can't be switched when the voltage pulse with magni-
tude smaller than VSET or VRESET. This conditional switching
property is critical for the design of logic operation with RS
devices. More basic electrical characteristics of our RS devices,
such as SET voltage distribution and reliability behaviors, were
measured and shown in Section S1 (Supporting Information).
NAND gate is a universal logic gate. Any binary logic func-
tion can be realized using a finite number of NAND gates.
Figure 2a shows the subcircuit used to execute NAND opera-
tion, where top electrodes of three RS devices are connected
by a common WL and BL of output device Y is grounded. A
long and low voltage pulse (VR) is assigned to the BL of input
devices (A and B) and a relatively short and high voltage pulse
(VDD) is assigned to WL through a constant reference resistor
(RC) to trigger the NAND logic operation. Inputs are the resist-
ance states of devices A and B, and the output logic state will be
stored into device Y after logic operation. The output device Y
is assigned to HRS before the logic operation. When the input
devices A and B are both in HRS (logical ‘1’), the potential of
common WL is approximate to VDD, and the output device Y
will be programmed to logical ‘0’ after logic operation. If any
input device is in LRS (logical ‘0’), the potential of common WL
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charged by the voltage pulses VDD and VR

Communication
via different paths. Thus the transient poten-
tial of the common line may be larger than
the stable potential if they are assigned at
the same time, which would lead to incor-
rect switching of the output device and the
decrease of logic operations robustness. To
avoid it, VDD should be assigned later and
ended earlier than VR. When all input devices
are in HRS, RC should be selected as low as
possible compared to RH /2 in order to guar-
antee that the potential of common WL is
close to VDD (RH is the abbreviation of resist-
ance of HRS). RC should be selected as high
as possible compared to the resistance of LRS
(RL) to ensure that the potential of common
WL is close to VR when any input device is
in logical ‘0’. A further detailed discussion
about the selection of RC is presented in the
Section S2 (Supporting Information).
To synthesize other logic operations,
NAND is enough but it may cost many oper-
ation steps and RS devices. To simplify it,
another frequently used logic operation AND
is introduced. The circuit of AND operation
Figure 1.  RS crossbar array. a) Microscope micrograph of an integrated 16 × 8 array with a TiN/ is the same as the NAND operation except
HfOX/AlOY/Pt RS device at each crosspoint. b) Typical measured current voltage characteristics the exchange of VDD and VR as shown in
of an RS device. c) Transient current response under voltage pulse. Resistance of the device Figure 2b. So the potential of common WL is
can be switched between low resistance state (logical ‘0’) and high resistance state (logical ‘1’) opposite to the condition of NAND operation
with 100 ns width voltage pulses VP (programming to logical ‘0’) and VC (erasing to logical
under the same logic inputs. Therefore, the
‘1’). The amplitude of VP and VC is +1.2 and −1.8 V, respectively. State of the device cannot be
turned with voltage pulse when the amplitude is lower than VP or VC. The inset in b shows the logic operation results are contrary and the
device cross-section schematically. logic function is AND Y′ = AB. The states of
input devices are nondestructive in these two
logic operations, which is important to miti-
is close to VR thus the output device will be in logical ‘1’ after the gate data transfer.
logic operation. That means a NAND logic operation Y ′ = AB Various logic operations can be performed via resistance
is performed via the resistance state interaction between input state interaction among the common WL devices based on the
and output devices. The state interaction is triggered by the previously presented method. However, this method cannot
pulse signals VDD and VR. Output device can retain its state for be used in the common BL devices due to their different con-
more than 105 s under 150 °C temperature stress, which can figurations as shown in Figure 2a and Figure S3a (Supporting
be seen in Figure S1c (Supporting Information). Therefore, the Information). It will greatly decrease the computing capability
logic function is nonvolatile, which means static power dissipa- of RS crossbar array as well as hinder the design of large-scale
tion of this logic operation can be zero and the latches used in logic circuit with RS crossbar array. To overcome this obstacle,
conventional computer systems are not necessary. the method of logic executed in the common BL devices is
To correctly perform a NAND logic operation with RS introduced. The trigger signal VDD is directly applied to the
devices, the selections of VDD, VR, and RC are critical. To switch WL of output device Y and the WL of input devices A and B is
the device to LRS, the magnitude of VDD should be larger directly connected to VR as shown in Figure S3a (Supporting
than VSET due to the voltage drop across RC. Bias stress across Information). The common BL is connected to the ground
output device Y is about VR when any input device is in LRS. through RC. Y is initialized to HRS before logic operation. If
The output device Y should not be switched according to logic the devices for input are all in logical ‘1’, the electrical poten-
function of NAND, so VR should be selected as small as pos- tial of BL will be close to the ground. The voltage drop across
sible. However, VR should be selected as close as possible to output device is about VDD, which leads the transition of output
VDD to ensure unchanged logic inputs during the operation. device to LRS. If any one of the input devices is in logical ‘0’,
VR is chosen to VDD/2 based on synthetical consideration of the electrical potential of the common BL will be approximate
the robustness of this logic operation. Generally, there is a to VR. Therefore, the voltage drop across output device is about
certain variation of VSET,[27] which makes the choice of VDD VDD-VR and the output device remains in HRS. It implies that
and VR more delicate. Therefore, the selection of VDD and VR the logic operation NAND is executed under the control of
should base on the distribution of VSET, which is presented trigger signals with the resistance interaction between the input
in Figure S1a (Supporting Information). The common line is and output devices. The AND logic operation can be performed

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Communication

Figure 2.  NAND and AND logic operations. a) sub-circuit of NAND and b) AND logic operations executed by the common WL devices. Logic inputs
are stored in devices A and B, and Y will store logic output depending on the states of the devices A and B. Voltage pulses VDD and VR are applied to
trigger the resistance interaction between the input and output devices. c) States of output after NAND and d) AND logic operations versus the state
combinations of inputs A and B. States are read by a small voltage pulse of 0.25 V and the measured results verify the feasibility of nonvolatile NAND
and AND logic operations in RS devices.

by changing the WL of input devices to be directly connected to
the ground and applying VR to the common BL through RC as
shown in Figure S3b (Supporting Information).
The fabricated RS crossbar array was used to experimentally
demonstrate the NAND and AND logic operations. Logic inputs
are initialized to desired states by applying appropriate positive or
negative voltage pulse across devices. Then the resistance states
are read by a small pulse voltage Vread (+0.25 V, 200 ns) to verify
the initialized results. To mitigate the impact of charging and
discharging current on the read signal, long rise and fall time of
applied pulses are used. To perform the NAND and AND logic
operations, trigger pulse signals VDD (+1.4V, 100 ns) and VR
(+0.7 V, 1 μs) are applied to corresponding nodes to stimulate
the resistance state interaction among devices. After that, Vread is
applied to device Y to read out the results of logic operations. The
logic operations executed in the common WL devices were meas-
ured and summarized as a truth table in Figure 2c,d. The meas-
ured results demonstrate that the logic operations of Y ′ = AB
and Y ′ = AB are successfully executed. The measured VSET dis-
tribution and disturbance behaviors of RS devices (Figure S1a,b
in Supporting Information) indicate that the logic operations
executed by RS devices are robust with the selected voltage
pulses. The demonstrations of NAND and AND logic opera-
tions executed in the common BL devices are presented in the
Section S3 (Supporting Information). It should be noted that the
initialization and readout processes employed in the experimental
demonstrations are only used to verify the correctness of opera-
tions, which are not necessary in the practical logic operations.
If the states of output device of NAND and AND logic opera-
tions are logical ‘0’ before operation, the output states are always
logical ‘0’ no matter what the logic inputs are. Hence, if the state
of Y is treated as an input, the logic functions of circuits shown
in Figure 2a,b should be revised as Y ′ = ABY and Y′ = ABY,
respectively. These two logic operations can be experimentally
demonstrated as shown in Section S4 (Supporting Informa-
tion). Even though the input states may be destructive, these
two logic operations are suitable for conditions that the input
state Y would not be used in the subsequent logic operations
anymore, such as the intermediate variable in compound logic
operations. Up to now, we have achieved four basic logic opera-
tions: AB, AB, ABY and ABY. Other frequently used logic oper-
ations such as INV, OR, transfer, and XOR can be executed by
synthesizing the four basic logic operations and are experimen-
tally demonstrated in the Section S5 (Supporting Information).
It can be found that the circuits of NAND and AND logic opera-
tions, transfer, and INV logic operations (Figures S5 and S6 in
the Supporting Information), and OR and XOR logic opera-
tions (Figures S7 and S8 in the Supporting Information) are the
same except the applied voltage pulses, which means that the
logic functions of the circuits constructed by RS devices can be
reconfigured simply by altering the trigger signals without any
other additional circuit change. This results from the fact that

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Communication

Figure 3.  Full adder. a) Array configuration of one-bit full adder circuits, where four assisted RS devices (AS1–AS4) are used to perform the logic func-
tions of full adder. b) Computation procedure of one-bit full adder. Here formula ‘NAND(A,B) →Y’ is used to represent that states of devices A and B
are executed the NAND logic operation and the logic output is stored into device Y. c) The time sequence of the applied trigger signals to achieve the
logic operation of full adder. d) Experimental demonstration of logic operation of full adder for all eight input combinations. The states of the input
devices before and output and assisted devices after operations are read out as resistance values shown by the grayscale maps.

the logic functions of circuits constructed by RS devices depend processes of OR and XOR logic operations, we can find that the
on not only the structure and layout of circuit but also the time four basic logic operations executed by RS devices are arranged
sequence of trigger signals. Moreover, from the computational along the time dimension, not along a spatial dimension.[28]

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An example of logic function reconfiguration and further The logic operations were performed in ten sequential
Communication

detailed discussion about the logic function reconfiguration is
shown in the Section S6 (Supporting Information).
Adder circuits play a key role in computer system and other
complex computing tasks, such as multiply operation, can be
executed using it as basic unit. Here the functions of one-bit
full adder are experimentally demonstrated by assembling the
logic operations presented above as shown in Figure 3. For one
bit full adder, there are three inputs (addend A, summand B,
and carry-in Ci) and two outputs (summary S and carry-out Co),
the logic functions can be expressed as
S = A ⊕ B ⊕ Ci (1)
C o = ( A ⊕ B)C i + AB
This set of formulas can be disassembled to the combination
of four basic operations, which are written as the form below
S = A ⊕ BCi ⋅ ( A ⊕ B)Ci
Co = ( A ⊕ B)Ci AB (2)
A ⊕ B = ABAB
steps with nine devices including the input, output, and four
assistant devices (AS1–AS4) based on Formula (2) as shown in
Figure 3a. The computation procedure is shown in Figure 3b.
Open circuit was used as input logical ‘1’ to execute NAND (X,
1) operation. The time sequence of triggered signals applied to
each node is shown in Figure 3c. Detailed descriptions about
the computational process of one bit full adder are shown in
video SV1 (Supporting Information). The experimental results
are shown in Figure 3d for all eight possible input combina-
tions. The current responses of output devices and resistance
evolution of all nine devices during the computational process
were measured and shown in Section S7 (Supporting Informa-
tion) for the typical input combination (1 + 0 + 1). The meas-
ured results demonstrate that the functions of full adder are
successfully executed. To execute complicated compound logic
operation like full adder with four basic logic operations, the
first step is to establish the logic function equations. Then the
logic function equations are disassembled to the combination
of the four basic logic operations by logic synthesis, which can
be accomplished by circuit design software. The final is the

Figure 4.  Logic operation in devices of different rows and columns. a) Location of input devices in RS crossbar array. b) Computation procedure of logic
operation Y ′ = AB + C in RS crossbar. c) Time sequence of pulse signals applied to the different nodes of RS crossbar array to perform Y ′ = AB + C
logic operation. d) Measured truth table. States are represented by the resistance values.

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design of time sequence of the applied trigger signals for this of output devices and resistance evolution of all seven devices

logic operation based on the disassembled equations.
Devices located in arbitrary positions of RS crossbar array
can execute the user-defined computing task based on the
four basic logic operations presented above. Figure 4 shows an
example that computation ( Y ′ = AB + C ) was performed with
three inputs of different rows and columns. Figure 4a sche-
matically shows the RS crossbar used to execute logic opera-
tion. The WL1R, WL2R … WL16R (BL1U, BL2U … BL8U) are the
ends of WL (BL) with connected RC, while WL1L, WL2L … WL16L
(BL1D, BL2D … BL8D) represent the ends of WL (BL) without
connected RC. According to the subcircuits of logic operations
executed by common WL devices and common BL devices, the
voltage pulses are applied to WL via RC and directly applied to
BL when performing logic operation by common WL devices,
while the voltage pulses are directly applied to WL and applied
to BL via RC when performing logic operation by common
BL devices. Therefore, these two groups of ends must be dis-
cerned. The computation procedure is shown in Figure 4b.
The time sequence of trigger signals applied to each node
of RS crossbar array is shown in Figure 4c. Detailed illustra-
tions about the computational process are presented in video
SV2 (Supporting Information). The measured truth table is
shown in Figure 4d, in which logic states are represented by
resistance values measured at 0.25 V. The current responses
Communication
during the computational process Y ′ = 10 + 0 were measured
and shown in Section S8 (Supporting Information). To alle-
viate the impact of sneak current on the logic operations, all the
other cells that did not contribute to the actual circuit operation
were remaining in pristine state or HRS for the measurement.
The WL and BL resistance would lead to inhomogeneous logic
operation in the RS crossbar due to the voltage drop on line
resistance. The measured BL and WL resistance of our RS array
is smaller than 50 Ω due to the small array size and wide line
width (10 μm). Therefore, there is little impact of line resist-
ance on the homogeneity of logic operation (Figure S12, Sup-
porting Information). Further detailed discussion about the
impact of line resistance on the homogeneity of logic operation
is presented in Section S9 (Supporting Information).
With appropriate peripheral complementary metal oxide
semiconductor (CMOS) control circuits, RS crossbar array can
be used to construct a unit which can realize the functions of
information processing and data storage on the same physical
location. The circuit architecture of this new computer unit is
shown in Figure 5. To guarantee the correctness of logic opera-
tion, reading, and writing processes, RS devices should be inte-
grated with selective device to mitigate sneak current.[29,30] The
amplitudes of voltage pulses should be increased accordingly
to offset the voltage drop on the selective device. The type of

Figure 5.  Circuit architecture of the new computer unit. The unit is constructed by RS crossbar array together with peripheral CMOS control circuit.
The RS crossbar array size is m × n and is divided into two parts B1 and B2 as shown. Cells in B1 are the assisted devices which are programmed to ‘1’
during the power off time, while cells in B2 are used to compute and store information. Peripheral CMOS control circuits include four demultiplexers,
two pulse generator modules, and write/read module. Pulse generator modules generate four paths pulse signals controlled by the clock and enable
signals. Demultiplexers deliver the pulse signals or write/read signals to the selected ports of BL/WL and assign read feedback signals to write/read
module, which are controlled by address and enable signals.

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logic operation executed by RS crossbar is not defined, which
Communication
can be programmed according to the requirements of specific
computing task at run-time by altering the trigger signals. In
this new computer unit, logic inputs are stored in input devices
before operation and logic outputs are stored into output
devices during the logic operation process. So there is no addi-
tional data transfer operation in this new computer unit except
the data input and output, which has the potential to increase
the computation energy-efficiency.
The logic operations discussed above only consider two inputs
logic operation. Actually, N inputs NAND and AND logic opera-
tions can also be executed by the same theory. Although bipolar
metal oxide based RS devices are discussed in this study, it is
believed that the proposed method to execute logic operations
and construct large-scale logic circuit is also suitable for unipolar
RS devices[25,26] and any other devices which have conditional tog-
gling property as shown in Figure 1c. The conventional computer
system based on transistor with voltage as physical variable is
beyond its ability to keep up with recent increasing need of infor-
mation technology area. The nonvolatile logic operations in high
density integration RS crossbar array with resistance as physical
variable offer a new technology solution. This technology may be
viable for new computer system applications such as the distrib-
uted computation framework to offer an alternative architecture
for computation (Section S10, Supporting Information).
Experimental Section
Experimental Arrays: The RS crossbar arrays comprised two resistive
switching layers, HfOX and Al2O3, sandwiched between top electrodes
(WL) TiN and bottom electrodes (BL) Pt. First, a 20 nm Ti adhesion
layer and a 100 nm Pt bottom electrode were prepared on a 4 inch
silicon substrate by electron beam evaporation. Then, 3 nm HfOX was
deposited by atomic layer deposition (ALD). After that, 2 nm Al2O3 was
deposited by ALD. After a 40 nm TiN top electrode was deposited by
reactive sputtering in high vacuum and patterned with lithography, dry
etch was performed to form the square-shaped devices. Finally, 50 nm Al
metallization was used to complete the device fabrication.
Experimental Characterization: Device electrical measurements were
carried out using a Cascade Probe Station with an Agilent B1500A
semiconductor parameter analyzer. Pulse Measurements were performed
with device measurements instruments together with an Agilent 81160A
pulse function generator and an Agilent Infiniium MSO9404A Series
Oscilloscopes. Bit lines and Word lines of the array were connected
through an Agilent 34980A switching matrix to the instrument, ground, a
high impedance or an external constant reference resistor (3.1 kΩ).
Supporting Information
Supporting Information is available from the Wiley Online Library or
from the author.
Acknowledgements
This work was supported in part by NSFC (Grant Nos. 61421005 and
61334007), Beijing Municipal Science, and Technology Plan Projects. The
authors acknowledge Y. Y. Wang for guidance and fruitful discussions.
Received: May 6, 2016
Revised: August 1, 2016
Published online: September 22, 2016
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