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EEE 1201: Electrical Circuits - 1 (DC)

Network Analysis

Course Teacher: Nafiz Ahmed Chisty

Head, Department of EEE


Associate Professor, Department of EEE & CoE
Faculty of Engineering
Room# D0105, D Building
Email: chisty@aiub.edu
Website: http://engg.aiub.edu/faculties/nafiz
Website: www.nachisty.com
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Objectives
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 Become familiar with the terminal characteristics of a current source


and how to solve for the voltages and currents of a network using
current sources and/or current sources and voltage sources.

 Be able to apply branch-current analysis and mesh analysis to find the


currents of network with one or more independent paths.

 Be able to apply nodal analysis to find all the terminal voltages of any
series-parallel network with one or more independent sources.

 Become familiar with bridge network configurations and how to


perform ∆ -Y or Y-∆ conversions.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Current Sources
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 A current source determines the current in the branch in


which it is located.
 The magnitude and polarity of the voltage across a current
source are a function of the network to which it is applied.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Ex. 8-1 Find the source voltage Vs and the current I1 for the circuit of Fig. 7.2.

I1 = I = 10 mA

Vs = V1 = I1R1
= (10 mA)(20 kΩ)
= 200 V
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Ex. 8-2 Find the voltage Vs and the currents I1 and I2 for the network of
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Fig. 8.3.

FIGURE 8.3

VS = E = 12V
Applying Kirchhoff ' s current law:
VR E 12
I  I1  I 2
I2 = = = = 3A
R R 4 I1  I  I 2  7 A  3 A  4 A
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Ex. 8-3 Determine the current I1 and voltage Vs for the network of
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Fig. 8.4.

FIGURE 8.4

Using CDR:
Using KVL:
|| ×
= =2A Vs-V1-20=0
Vs= 24V
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

SOURCE CONVERSIONS
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 The equivalence between a current source and a voltage source


exists only at their external terminals.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-4 a. Convert the voltage source of Fig. 8.8 (a) to a current source, and calculate the
current through the 4-Ω load for each source.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

b. Replace the 4-Ω load with a 1-kΩ load, and calculate the current IL for the voltage source.
c. Replace the calculation of part (b) assuming that the voltage source is ideal (Rs = 0 Ω) because
RL is so much larger than Rs. Is this one of those situations where assuming that the source is
ideal is an appropriate approximation?

E 6V
a. Fig. 8.8 (a ): I L    1A
Rs  R L 2   4 
Rs I ( 2 )(3 A)
Fig. 8.8 (b): I L    1A
Rs  R L 2  4

E 6V
b. I L    5.99 A
Rs  R L 2   1 k
E 6V
c. I L    6 mA  5.99 mA
R L 1 k
Yes, R L  Rs (voltage source)

FIGURE 8.8
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-5 a. Convert the current source of Fig. 8.9(a) to a voltage source, and find the load
current for each source.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

b. Replace the 6-kΩ load with a 10-kΩ load, and calculate the current IL for the current source.
c. Replace the calculation of part (b) assuming that the vcurrent source is ideal (Rs = ∞ Ω)
because RL is so much smaller than Rs. Is this one of those situations where assuming that the
source is ideal is an appropriate approximation?
a. Fig. 8.9 (a ):
Rs I
IL 
Rs  R L
(3 k)(9 mA)

3 k  6 k
 3 mA
FIGURE 8.9
Fig. 8.9 (b):
E
IL 
Rs I (3 k)(9 mA) Rs  R L
b. I L    8.97 A
Rs  R L 3 k  10  27V

c. I L  I  9 mA  8.97 mA 3 k  6 k
Yes, Rs  R L (current source)  3 mA
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

CURRENT SOURCES IN PARALLEL


 If two or more sources are in parallel, the resultant can be found
by summing the currents in one direction and subtracting sum of
currents in the opposite direction.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Current Sources in Series


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

The current through any branch of a network can be only single-valued.

Current sources of different current ratings are not connected in series.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Ex. 8-8 Determine the current I2 in the network of Fig. 8.13.

FIGURE 8.13

E s  I 1 R1  ( 4 A)(3 )  12V
Rs  R1  3 
E s  E 2 12 V  5V
I2    3.4 A
Rs  R2 3  2 
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Introduction to Methods of Analysis

• The circuits described in the previous chapters had source(s) in series


or parallel. The Reduce and Return technique cannot be applied if
the sources are not in series or parallel.

• Methods of analysis allow us to approach a network with any


number of sources in any arrangement in a systematic manner.
• Branch-current analysis, mesh analysis, and nodal analysis will be
discussed in detail in this chapter.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Branch-Current Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Procedure:

1. Assign distinct current of arbitrary direction to each branch of the network.


2. Indicate the polarities for each resistor as determined by the assumed
current direction.
3. Apply Kirchhoff’s voltage law around each closed, independent loop of the
network.
4. Apply Kirchhoff’s current law at the minimum number of nodes that will
include all the branch currents of the network.
5. Solve the resulting simultaneous linear equations for assumed branch
currents.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Ex. 8-9 Apply the branch-current method to the network below.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

KVL at Loop 1:
E1 - VR1 - VR3 = 0
2 - 2xI1- 4x(I3) = 0
FIGURE 8.17
KVL at Loop 2:
VR3 + VR2 - E2 = 0
4x(I3) + 1xI2 - 6= 0

KCL at node a:
I1 + I2 = I3

Ans: I1 = -1A; I2 = 2A; I3 =1A


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

 EXAMPLE 8.10: Apply branch-current analysis to the network in Fig.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

8.28.

Ans: I1 = 4.77A; I2 = 2.41A; I3 =7.18A.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Mesh Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Steps:
1. Find Mesh.
2. Assign distinct current in CW direction in
each mesh.
3. Indicate the polarities.
4. Apply KVL.
5. Solve the resulting simultaneous linear
equations.

Ans:
I1 = -1A;
I2 = -2A;
I4Ω =1A.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 EXAMPLE 8.12: Find the current through each branch of the


network in Fig. 8.31.

Ans: I1=1A; I2= 2A; IR2= 1A.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Ex. 8-12 Find the branch currents of the network of Fig.8.20.

Loop 1:
- 6 - 2I1 - 4 - 4(I1-I2) = 0
6I1-4I2 = -10

Loop 2:
- 4(I2-I1) + 4 - 6I2 - 3 = 0
-4I1+10I2 = 1

FIGURE 8.20 The current in the 4Ω resistor and 4V source for


loop 1 is:
I1 – I2 = – 2.182A – (– 0.773A)
= – 1.409A
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

SuperMesh Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 Supermesh currents:
If there is a current source in the network to which the mesh analysis is
applied proceed as follows:
Using the supermesh current, start the same as before by
assigning a mesh current to each independent loop including the
current sources, as if they were resistors or voltage sources.

Mentally remove the current sources (replace with open-circuit


equivalents), and apply Kirchhoff’s voltage law to all remaining
independent paths of the network using the mesh currents just
defined.

Any resulting path, including two or more mesh currents, is said


to be the path of a supermesh current.

Then relate the chosen mesh currents of the network to the


independent current sources of the network, and solve for the
mesh currents.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Ex. 8-13 Using mesh analysis, determine the currents of the network below.

FIGURE 8.21

Ans: I1=3.3A; I2= -0.67A


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Mesh Analysis (Format Approach)


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 Format Approach to mesh analysis:


1. Assign a loop current to each independent, closed loop in a clockwise direction.
2. The number of required equations is equal to the number of chosen
independent, closed loops. Column 1 of each equation is formed by summing
the resistance values of those resistors through which the loop current of
interest passes and multiplying the result by that loop current.
3. We must now consider the mutual terms in the first column. A mutual term is
simply any resistive element having an additional loop current passing through
it. It is possible to have more than one mutual term if the loop current of
interest has an element in common with more than one other loop current.
Each term is the product of the mutual resistor and the other loop current
passing through the same element .
4. The column to the right of the equality sign is the algebraic sum of the voltage
sources through which the loop current of interest passes. Positive signs are
assigned to those sources of voltage having a polarity such that the loop current
passes from the negative terminal to the positive terminal. A negative sign is
assigned to those potentials that are reversed.
5. Solve the resulting simultaneous equations for the desired loop currents.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

 EXAMPLE 8.17: Write the mesh equations for the networks below.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Nodal Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Steps:
1. Find minimum number of nodes.
2. Label each node with voltage.
3. For each node:
a) Assume all unknown currents
leave the node.
b) Apply KCL.
c) Replace the currents in KCL with
node voltage.
FIGURE 8.22 4. Solve the resulting equations.

KCL: V1  24 V
Node 1:  1 1A  0
ƩIin = ƩIout 6 12 
2V1  48  V1  12  0
3V1  60 or V1  20V
1 = I 1 + I2 V1  24
I1   0.667 A
6
V1 − E V 1
1= + I2 
20V
 1667
. A
R1 R2 12 
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Ex. 8-15 Apply nodal analysis to the network of Fig.8.23.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

KCL: KCL:
ƩIin = ƩIout ƩIin = ƩIout
0 = I 1 + I2 + 2 2 = I2 + I3
V1 − E V1 − V2 V2 − V1 V2
0= + +2 2= +
R1 R2 R2 R3
E  V1 64 V  37.818V
I R1`    3.273 A
R1 8
V R3 V 32.727 V
I R3`   2   3.273 A
R3 R3 10 
V  V2 37.818V  32.727 V
I R2 `  1   1.273 A
R2 4
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Ex. 8-16 Determine the nodal voltages for the network below.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

KCL:
ƩIin = ƩIout
0 = I 3 + I4 + 2
V2 − V1 V2
0= + +2
R3 R2
V1  V2 6V  ( 6V )
KCL: I R3`    1A
R3 12 
ƩIin = ƩIout V R1 V1 6V
4 = I1 + I3 I R1` 
R1

R1

2
 3A
V V − V2
4= 1 + 1 V R2 V2 6V
R1 R3 I R2 ` 
R2

R2

6
 1A
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Nodal Analysis (Supernode)


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 On occasion there will be independent voltage sources in the


network to which nodal analysis is to be applied. Use the
supernode approach:

1. Assign a nodal voltage to each independent node of the


network.
2. Mentally replace independent voltage sources with short-
circuits.
3. Apply KCL to the defined nodes of the network.
4. Relate the defined nodes to the independent voltage
source of the network, and solve for the nodal voltages.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Ex. 8-17 Determine the nodal voltages V1 and V2 Fig.8.25 using the
concept of a supernode.

Ans: KCL at Supernode:


V2= -1.33V; V1= 10.67V; ƩIin = ƩIout Using KVL:
I1 ↓=2.67A; I2 ↑=0.67A; 6+I3 = I1 + I2 + I3 + 4 V1 - V2 = E
I3 → =1.2A; V V
6= 1 + 2 +4
R1 R2
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Nodal Analysis (Format Approach)


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

1. Choose a reference node and assign a subscripted voltage label to the


(N – 1) remaining nodes of the network.
1. The number of equations required for a complete solution is equal to the
number of subscripted voltages (N – 1). Column 1 of each equation is
formed by summing the conductance tied to the node of interest and
multiplying the result by that subscripted nodal voltage.
2. We must now consider the mutual terms that are always subtracted form
the first column. It is possible to have more than one mutual term if the
nodal voltage of current interest has an element in common with more
than one nodal voltage. Each mutual term is the product of the mutual
conductance and the other nodal voltage tied to that conductance.
3. The column to the right of the equality sign is the algebraic sum of the
current sources tied to the node of interest. A current source is assigned
a positive sign if it supplies current to a node and a negative sign if it
draws current from the node.
4. Solve the resulting simultaneous equations for the desired voltages.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

 EXAMPLE 8.23: Write the nodal equations for the network in Fig. 8.59.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Node 1:

Node 2:

 See Example 8.24.


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Nodal Analysis (Format Approach)


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 EXAMPLE 8.25: Using nodal analysis, determine the potential across the 4Ω resistor in
Fig. 8.63.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Wye (Y) and Delta (∆) configurations


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

 Circuit configurations are encountered in which the resistors do not


appear to be in series or parallel; it may be necessary to convert the
circuit from one form to another to solve for the unknown quantities
if mesh and nodal analysis are not applied.
 Two circuit configurations that often account for these difficulties
are the wye (Y) and delta (∆) configurations.
 They are also referred to as tee (T) and the pi (П) configurations.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

∆ -Y (П-T) Conversion
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

RC
R1 R2

RB RA
R3
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu

Y-∆ (T-П) Conversion


Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

RC
R1 R2

RB R3 RA RA=

RB=

RC=
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

EX: For the following figure, find the total resistance, RT.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE

Reference

[1] Robert L. Boylestad, “Introductory Circuit Analysis”, 12th Edition, Prentice Hall Inc
Thanks

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