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Network Analysis
Objectives
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Be able to apply nodal analysis to find all the terminal voltages of any
series-parallel network with one or more independent sources.
Current Sources
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Ex. 8-1 Find the source voltage Vs and the current I1 for the circuit of Fig. 7.2.
I1 = I = 10 mA
Vs = V1 = I1R1
= (10 mA)(20 kΩ)
= 200 V
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-2 Find the voltage Vs and the currents I1 and I2 for the network of
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Fig. 8.3.
FIGURE 8.3
VS = E = 12V
Applying Kirchhoff ' s current law:
VR E 12
I I1 I 2
I2 = = = = 3A
R R 4 I1 I I 2 7 A 3 A 4 A
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-3 Determine the current I1 and voltage Vs for the network of
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Fig. 8.4.
FIGURE 8.4
Using CDR:
Using KVL:
|| ×
= =2A Vs-V1-20=0
Vs= 24V
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
SOURCE CONVERSIONS
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
b. Replace the 4-Ω load with a 1-kΩ load, and calculate the current IL for the voltage source.
c. Replace the calculation of part (b) assuming that the voltage source is ideal (Rs = 0 Ω) because
RL is so much larger than Rs. Is this one of those situations where assuming that the source is
ideal is an appropriate approximation?
E 6V
a. Fig. 8.8 (a ): I L 1A
Rs R L 2 4
Rs I ( 2 )(3 A)
Fig. 8.8 (b): I L 1A
Rs R L 2 4
E 6V
b. I L 5.99 A
Rs R L 2 1 k
E 6V
c. I L 6 mA 5.99 mA
R L 1 k
Yes, R L Rs (voltage source)
FIGURE 8.8
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-5 a. Convert the current source of Fig. 8.9(a) to a voltage source, and find the load
current for each source.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
b. Replace the 6-kΩ load with a 10-kΩ load, and calculate the current IL for the current source.
c. Replace the calculation of part (b) assuming that the vcurrent source is ideal (Rs = ∞ Ω)
because RL is so much smaller than Rs. Is this one of those situations where assuming that the
source is ideal is an appropriate approximation?
a. Fig. 8.9 (a ):
Rs I
IL
Rs R L
(3 k)(9 mA)
3 k 6 k
3 mA
FIGURE 8.9
Fig. 8.9 (b):
E
IL
Rs I (3 k)(9 mA) Rs R L
b. I L 8.97 A
Rs R L 3 k 10 27V
c. I L I 9 mA 8.97 mA 3 k 6 k
Yes, Rs R L (current source) 3 mA
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
FIGURE 8.13
E s I 1 R1 ( 4 A)(3 ) 12V
Rs R1 3
E s E 2 12 V 5V
I2 3.4 A
Rs R2 3 2
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Branch-Current Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Procedure:
KVL at Loop 1:
E1 - VR1 - VR3 = 0
2 - 2xI1- 4x(I3) = 0
FIGURE 8.17
KVL at Loop 2:
VR3 + VR2 - E2 = 0
4x(I3) + 1xI2 - 6= 0
KCL at node a:
I1 + I2 = I3
8.28.
Mesh Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Steps:
1. Find Mesh.
2. Assign distinct current in CW direction in
each mesh.
3. Indicate the polarities.
4. Apply KVL.
5. Solve the resulting simultaneous linear
equations.
Ans:
I1 = -1A;
I2 = -2A;
I4Ω =1A.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Loop 1:
- 6 - 2I1 - 4 - 4(I1-I2) = 0
6I1-4I2 = -10
Loop 2:
- 4(I2-I1) + 4 - 6I2 - 3 = 0
-4I1+10I2 = 1
SuperMesh Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Supermesh currents:
If there is a current source in the network to which the mesh analysis is
applied proceed as follows:
Using the supermesh current, start the same as before by
assigning a mesh current to each independent loop including the
current sources, as if they were resistors or voltage sources.
Ex. 8-13 Using mesh analysis, determine the currents of the network below.
FIGURE 8.21
EXAMPLE 8.17: Write the mesh equations for the networks below.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nodal Analysis
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Steps:
1. Find minimum number of nodes.
2. Label each node with voltage.
3. For each node:
a) Assume all unknown currents
leave the node.
b) Apply KCL.
c) Replace the currents in KCL with
node voltage.
FIGURE 8.22 4. Solve the resulting equations.
KCL: V1 24 V
Node 1: 1 1A 0
ƩIin = ƩIout 6 12
2V1 48 V1 12 0
3V1 60 or V1 20V
1 = I 1 + I2 V1 24
I1 0.667 A
6
V1 − E V 1
1= + I2
20V
1667
. A
R1 R2 12
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
KCL: KCL:
ƩIin = ƩIout ƩIin = ƩIout
0 = I 1 + I2 + 2 2 = I2 + I3
V1 − E V1 − V2 V2 − V1 V2
0= + +2 2= +
R1 R2 R2 R3
E V1 64 V 37.818V
I R1` 3.273 A
R1 8
V R3 V 32.727 V
I R3` 2 3.273 A
R3 R3 10
V V2 37.818V 32.727 V
I R2 ` 1 1.273 A
R2 4
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-16 Determine the nodal voltages for the network below.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
KCL:
ƩIin = ƩIout
0 = I 3 + I4 + 2
V2 − V1 V2
0= + +2
R3 R2
V1 V2 6V ( 6V )
KCL: I R3` 1A
R3 12
ƩIin = ƩIout V R1 V1 6V
4 = I1 + I3 I R1`
R1
R1
2
3A
V V − V2
4= 1 + 1 V R2 V2 6V
R1 R3 I R2 `
R2
R2
6
1A
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Ex. 8-17 Determine the nodal voltages V1 and V2 Fig.8.25 using the
concept of a supernode.
EXAMPLE 8.23: Write the nodal equations for the network in Fig. 8.59.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Node 1:
Node 2:
EXAMPLE 8.25: Using nodal analysis, determine the potential across the 4Ω resistor in
Fig. 8.63.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
∆ -Y (П-T) Conversion
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
RC
R1 R2
RB RA
R3
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
RC
R1 R2
RB R3 RA RA=
RB=
RC=
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
EX: For the following figure, find the total resistance, RT.
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE| chisty@aiub.edu
Nafiz A. Chisty| Head, Dept of EEE; Associate Professor, Dept. of EEE & CoE, FE
Reference
[1] Robert L. Boylestad, “Introductory Circuit Analysis”, 12th Edition, Prentice Hall Inc
Thanks