EC604 - Embedded Systems - Course Materials

Introduction
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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Department of Electronics and Communication Engineering
National Institute of Technology Jamshedpur, Jharkhand, India
WHAT IS AN EMBEDDED SYSTEM?
• An embedded system is an electronic/electro-mechanical system designed to perform a

specific function and is a combination of both hardware and firmware (software).
• Every embedded system is unique, and the hardware as well as the firmware is highly
specialised to the application domain.
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• Embedded systems are becoming an inevitable part of any product or equipment in all fields
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including household appliances, telecommunications, medical equipment, industrial control,
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consumer products, etc.
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EMBEDDED SYSTEMS vs. GENERAL COMPUTING SYSTEMS
Sl. General Purpose Computing Embedded System
No. System
1. A system which is a combination of a A system which is a combination of special
generic hardware and a General purpose hardware .and embedded OS for
Purpose Operating System for executing a specific set of applications
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executing a variety of applications
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2. Contains a General Purpose May or may hot contain an operating system
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Operating System (GPOS) for functioning
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3. Applications are already The firmware of the embedded system is
programmable by the user (It is pre-programmed and it is non-alterable by
possible for the en user to reinstall the end-usre (There may be exceptions for
the operating system and also add or systems supporting OS kernel image
remove user application) flashing through special hardware settings)
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EMBEDDED SYSTEMS vs. GENERAL COMPUTING SYSTEMS
Sl. General Purpose Computing Embedded System
No. System
1. Performance is the key deciding Application-specific requirements (like
factor in the selection of the syste.
performance, power requirements, memory
Always Faster is better usage, etc.) are the key deciding factors
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2. Less/Not at all tailored towards Highly tailored to take advantage of the
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reduced operating power power saving modes supported by the
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requirements, options for different hardware and the operating system
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levels of power management.
3. Response requirements are not time- For certain category of embedded systems
critical like mission critical systems, the response
time requirements is highly critical
4 Need not be deterministic in Execution behavior is deterministic for
execution behavior certain types of embedded systems like
‘Hard Real Time’ systems 4
WHAT IS AN EMBEDDED SYSTEM?
• However, the demarcation between desktop systems and embedded systems in certain areas
of embedded applications are shrinking in certain contexts.
• Smart phones are typical examples of this.
• Nowadays smart phones are available with RAM up to 256 MB and users can extend most of
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their desktop applications to the smart phones and it waives the clause “Embedded systems
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are designed for a specific application” from the characteristics of the embedded system for
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the mobile embedded device category.
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• However, smart phones come with a built-in operating system and it is not modifiable by the
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end user.
• It makes the clause: “The firmware of the embedded system is unalterable by the end user”,
still a valid clause in the mobile embedded device category.
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HISTORY OF EMBEDDED SYSTEM
• Embedded systems were in existence even before the IT revolution.
• The first recognized modem embedded system is the Apollo Guidance Computer (AGC)
developed by the MIT Instrumentation Laboratory for the lunar expedition.
• They ran the inertial guidance systems of both the Command Module (CM) and the Lunar
Excursion Module (LEM).
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• The Command Module was designed to encircle the moon while the Lunar Module and its
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crew were designed to go down to the moon surface and land there safely.
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• The Lunar Module featured in total 18 engines.
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• There were 16 reaction control thrusters, a descent engine and an ascent engine.
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• The descent engine was ‘designed to’ provide thrust to the lunar module out of the lunar
orbit and land it safely on the moon.
• MIT’s original design was based on 4K words of fixed memory (Read Only Memory) and 256
words of erasable memory (Random Access Memory).
• By June 1963, the figures reached 10K of fixed and IK of erasable memory.
• The final configuration was 36K words of fixed memory and 2K words of erasable memory.
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Classification of Embedded System
• The clock frequency of the. first microchip proto model used in AGC was 1.024 MHz and it
was derived from a 2.048 MHz crystal clock.
• The computing unit of AGC consisted of approximately 11 instructions and 16 bit word logic.
• Around 5000 ICs (3-input NOR gates, RTL logic) supplied by Fairchild Semiconductor were
used in this design.
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• The user interface unit of AGC is known as DSKY (display/keyboard) and looked like a
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calculator type keypad with an array of numerals, which was used for inputting the
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commands to the module numerically.
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• The first mass-produced embedded system was the guidance computer for the Minuteman-I
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missile in 1961.
• It was the ‘Autonetics D-l7 guidance computer, built using discrete transistor logic and a
hard-disk for main memory.
• The first integrated circuit was produced in September 1958 but computers using them
didn’t begin to appear until 1963.
• Some of their early uses were in embedded systems, notably used by NASA for the Apollo
Guidance Computer and by the US military in the Minuteman-II intercontinental ballistic 7
HISTORY OF EMBEDDED SYSTEM
• It is possible to have a multitude of classifications for embedded systems, based on different
criteria. Some of the criteria used in the classification of embedded systems are:
 Based on generation
 Complexity and performance requirements
 Based on deterministic behavior
 Based on triggering.
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• The classification based on deterministic system behavior is applicable for ‘Real Time’
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systems.
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• The application/task execution behavior for an embedded system can be either deterministic
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or non-deterministic.
• Based on the execution behavior, Real Time embedded systems are classified into Hard and
Soft.
• Embedded Systems which are ‘Reactive’ in nature (Like process control systems in industrial
control applications) can be classified based on the trigger.
• Reactive systems can be either event triggered or time triggered.
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Classification Based on Generation
• First Generation
 The early embedded systems were built around 8bit microprocessors like 8085 and Z80, and 4bit
microcontrollers.
 Simple in hardware circuits with firmware developed in Assembly code. Digital telephone keypads,
stepper motor control units etc. are examples of this.
• Second Generation
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 These are embedded systems built around 16bit microprocessors and 8 or 16 bit microcontrollers,
following the first generation embedded systems.
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 The instruction set for the second generation processors/controllers were much more complex and
powerful than the first generation processors/ controllers.
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 Some of the second generation embedded systems contained embedded operating systems for their
operation.
 Data Acquisition Systems, SCADA systems, etc. are examples of second generation embedded
systems.
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• Third Generation
 With advances in processor technology, embedded system developers started making use of
powerful 32bit processors and 16bit microcontrollers for their design.
 A new con cept of application and domain specific processors/controllers like Digital Signal
Processors (DSP) and Application Specific Integrated Circuits (ASICs) came into the picture.
 The instruction set of processors became more complex and powerful and the concept of instruction
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pipelining also evolved.
 The processor market was flooded with different types of processors from different vendors.
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 Processors like Intel Pentium, Motorola 68K, etc. gained attention in high performance embedded
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requirements.
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 Dedicated embedded real time and general purpose operating systems entered into the embedded
market.
 Embedded systems spread its ground to areas like robotics, media, industrial process control,
networking, etc.
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• Fourth Generation
 The advent of System on Chips (SoC), reconfigurable processors and multicore processors are
bringing high performance, tight integration and miniaturization into the embedded device market.
 The SoC technique implements a total system on a chip by integrating different functionalities with a
processor core on an integrated circuit.
 SoCs will be discussed later.
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 The fourth generation embedded systems are making use of high performance real time embedded
operating systems for their functioning.
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 Smart phone devices, mobile internet devices (MIDs), etc. are examples of fourth generation
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embedded systems.
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• What Next?
 The processor and embedded market is highly dynamic and demanding. So ‘what will be the next
smart move in the next embedded generation?’
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Classification Based on Complexity and Performance
• Small-Scale Embedded Systems
 Embedded systems which are simple in application needs and where the performance requirements
are not time critical fall under this category.
 An electronic toy is a typical example of a small-scale embedded system. Small-scale embedded
systems are usually built around low performance and low cost 8 or 16 bit microprocessors/
microcontrollers.
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 A small-scale embedded system may or may not contain an operating system for its functioning.
• Medium-Scale Embedded Systems
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 Embedded systems which are slightly complex in hardware and firmware (software) requirements
fall under this category.
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 Medium-scale embedded systems are usually built around medium performance, low cost 16 or 32
bit microprocessors/microcontrollers or digital signal processors.
 They usually contain an embedded operating system (either general, purpose or real time operating
system) for functioning.
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Classification Based on Complexity and Performance
• Large-Scale Embedded Systems/Complex Systems
 Embedded systems which involve highly complex hardware and firmware requirements fall under
this category.
 They are employed in mission critical applications demanding high performance.
 Such systems are commonly built around high performance 32 or 64 bit RISC processors/controllers
or Reconfigurable System on Chip (RSoC) or multi-core processors and programmable logic devices.
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 They may contain multiple processors/controllers and co-units/hardware accelerators for
offloading the processing requirements from the main processor of the system.
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 Decoding/encoding of media, cryptographic function implementation, etc. are examples for
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processing requirements which can be implemented using a co-processor/hard-ware accelerator.
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 Complex embedded systems usually contain a-high performance Real Time Operating System
(RTOS) for task scheduling, prioritization and management:
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Major Application Aareas of Embedded Systems
A few of the important domains and products are listed below:
 Consumer electronics: Camcorders, cameras, etc.
 Household appliances: Television, DVD players, washing machine, fridge, microwave oven, etc.
 Home automation and security systems: Air conditioners, sprinklers, intruder detection alarms,
closed circuit television cameras, fire alarms, etc.
 Automotive industry: Anti-lock breaking systems (ABS), engine control, ignition systems, automatic
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navigation systems, etc.
 Telecom: Cellular telephones, telephone switches, handset multimedia applications, etc.
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 Computer peripherals: Printers, scanners, fax machines, etc.
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 Computer networking systems: Network routers, switches, hubs, firewalls, etc.
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 Healthcare: Different kinds of scanners, EEG, ECG'machines etc.
 Measurement & Instrumentation: Digital multi meters, digital CROs, logic analyzers PLC systems,
etc.
 Banking & Retail: Automatic teller machines (ATM) and currency counters, point of sales (POS)
 Card Readers: Barcode, smart card readers, hand held devices, etc.
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Purpose of Embedded Systems
Each embedded system is designed to serve-the purpose of any one or a combination of the
following tasks:
 Data collection/Storage/Representation
 Data communication
 Data (signal) processing
 Monitoring
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 Control
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 Application specific user interface
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Data collection/Storage/Representation
• Data collection is usually done for storage, analysis, manipulation and transmission.
• The term “data” refers all kinds of information, viz. text, voice, image, video, electrical signals and any
other measurable quantities.
• Data can be either analog (continuous) or digital (discrete).
• Embedded systems with analog data capturing techniques collect data directly in the form of analog
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signals whereas embedded systems with digital data collection mechanism converts the analog signal to
corresponding digital signal using analog to digital (A/D) converters and then collects the binary
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equivalent of the analog data.
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• If the data is digital, it can be directly captured without any additional interface by digital embedded
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systems.
• The collected data may be stored directly in the system or maybe transmitted to some other systems or it
may be processed by the system or it may be deleted instantly after giving a meaningful representation.
• These actions are purely dependent on the purpose for which the embedded system is designed.
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Data collection/Storage/Representation
• Some embedded systems store the collected data for processing and analysis.
• Such systems incorporate a built-in/plug-in storage memory for storing the captured data.
• Some of them give the user a meaningful representation of the collected data by visual (graphical/
quantitative) or audible means using display units [Liquid Crystal Display (LCD), Light Emitting Diode
(LED), etc.] buzzers, alarms, etc.
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• Examples are: measuring instruments with storage memory and monitoring instruments with storage
memory used in medical applications.
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• Certain embedded systems store the data and will not give a representation of the same to the user,
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whereas the data is used for internal processing.
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• A digital camera is a typical example of an embedded system with data collection/storage/representation
of data.
• Images are captured and the captured image may be stored within the memory of the camera.
• The captured image can also be presented to the user through a graphic LCD unit.
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Data Communication
• Embedded data communication systems are deployed in applications ranging from complex satellite
communication systems to simple home networking systems.
• As mentioned earlier in this chapter, the data collected by an embedded terminal may require transferring
of the same to some other system located remotely.
• The transmission is achieved either by a wire-line medium or by a wireless medium.
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• Wire-line medium was the most common choice in all olden days embedded systems.
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• As technology is changing, wireless medium is becoming the de-facto standard for data communication in
embedded systems.
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• A wireless medium offers cheaper connectivity solutions and make the communication link free
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• from the hassle of wire bundles.
• Data can either be transmitted by analog means or by digital means.
• Modem industry trends are settling towards digital communication.
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Data Communication
• The data collecting embedded terminal itself can incorporate data communication units like wireless
modules (Bluetooth, ZigBee, Wi-Fi, EDGE, GPRS, etc.) or wire-line modules (RS-232C, USB, TCP/IP, PS2,
etc.).
• Certain embedded systems act as a dedicated transmission unit between the sending and receiving
terminal's, offering sophisticated functionalities like data packetizing, encrypting and decrypting.
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• Network hubs, routers, switches, etc. are typical examples of dedicated data transmission embedded
systems.
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• They act as mediators in data communication and provide various features like data security, monitoring
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etc.
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• As mentioned earlier, the data (voice, image, video, electrical signals and other measurable quantities)
collected by embedded systems may be used for various kinds of data processing.
• Embedded systems with signal processing functionalities are employed in applications demanding signal
processing like speech coding, synthesis, audio video codec, transmission applications, etc.
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Monitoring
• Embedded systems falling under this category are specifically designed for monitoring purpose.
• Almost all embedded products coming under the medical domain are with monitoring functions only.
• They are used for determining the state of some variables using input sensors.
• They cannot impose control over variables.
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• A very good example is the electrocardiogram (ECG) machine for monitoring the heartbeat of a patient.
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• The machine is intended to do the monitoring of the heartbeat.
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• It cannot impose control over the heartbeat.
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• The sensors used in ECG are the different electrodes connected to the patient’s body.
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• Some other examples of embedded systems with monitoring function are measuring instruments like
digital CRO, digital multimeters, logic analyzers, etc. used in Control & Instrumentation applications.
• They are used for knowing (monitoring) the status of some variables like current, voltage, etc. They cannot
control the variables in turn.
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Control
• Embedded systems with control functionalities impose control over some variables according to the
changes in input variables.
• A system with control functionality contains both sensors and actuators.
• Sensors are connected to the input port for capturing the changes in environmental variable or measuring
variable.
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• The actuators connected to the output port are controlled according to the changes in input variable to put
an impact on the controlling variable to bring the controlled variable to the specified range.
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• Air conditioner system used in our home to control the room temperature to a specified limit is a typical
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example for embedded system for control purpose.
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• An air conditioner contains a room temperature-sensing element (sensor) which may be a thermistor and
a handheld unit for setting up (feeding) the desired temperature.
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Application Specific User Interface
• These are embedded systems with application-specific user interfaces like buttons, switches,
keypad, lights, bells, display units, etc.
• Mobile phone is an example for this. In mobile phone the user interface is provided through
the keypad, graphic LCD module, system speaker, vibration alert, etc
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SMART RUNNING SHOES FROM ADIDAS—THE INNOVATIVE BONDING OF LIFESTYLE
WITH EMBEDDED TECHNOLOGY
• After three years of extensive research work, Adidas launched the “Smart” running shoes in
the market in April 2005.
• The term “Smart Shoe” may sound gimmicky.
• But adaptive cushioning provided by the shoe makes sense, and the design engineering
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behind the shoes is very impressive.
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• The shoe constantly adapts its shock-absorbing characterizes to customize its value/ to the
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individual runner, depending oh the running style, pace, body weight, and running surface.
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• The shoe uses a magnetic sensing system to measure cushioning level, which is adjusted via a
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digital signal processing unit that controls a motor-driven cable system.
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• A hall effect sensor is positioned at the top of the “cushioning element”, and the magnet is
placed at the bottom of the element.
• As the cushioning compresses on each impact, the sensor measures the distance from top to
bottom of mid-sole (accurate to 0.1 mm).
• About 1000 readings per second are taken and relayed to the shoe’s microprocessor.
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• The Microprocessor (MPU) is positioned under the arch of the shoe.
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• It runs an algorithm that compares the compression messages received from the sensor to a
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preset range of proper cushioning levels, so it understands if the shoe is too soft or too firm.
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• Then the MPU sends a command to a micro motor, housed in the mid-foot.
• The micro motor turns a lead screw to lengthen or shorten a cable secured to the walls of a
plastic-cushioning element.
• When the cable is shortened, the cushioning element is pulled taut and compresses very
little.
• A longer cable allows for a more cushioned feel.
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• A replaceable 3-V battery powers the motor and lasts for about 100 hours of running.
• Adaptations in the cushioning element account for the change of running surface and pace of
the runner, and they’re made gradually over an average of four running steps.
• The goal is for the runner not to feel any sudden changes.
• Adaptations are made during the “swing” phase rather than the “stance” phase of the stride
(i.e. when the foot is off the ground).
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• If the shoe’s owner prefers a more cushioned or a firmer “ride,” adjustments can be made via
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“+” and buttons that also activate the intelligent functions of the shoe.
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• LED indicators confirm when the electronics are turned on (The lights do not remain on
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when the shoes are in use).
• If the shoes aren’t turned on, they operate like old-fashioned “manual” running shoes.
• The shoes turn off if their owner is either inactive or at a walking pace for 10 minutes.
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Thank you
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Characteristics and Quality Attributes of
Embedded Systems
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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CHARACTERISTICS OF AN EMBEDDED SYSTEM?
• Unlike general purpose computing systems, embedded systems possess certain specific
characteristics and these characteristics are unique to each embedded system.
• Some of the important characteristics of an embedded system are as follows:
 Application and domain specific
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 Reactive and Real Time
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 Operates in harsh environments
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 Distributed
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 Small size and weight
 Power concerns
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Application and Domain Specific
• If you closely observe any embedded system, you will find that each embedded system is
having certain functions to perform and they are developed in such a manner to do the
intended functions only.
• They cannot be used for any other purpose.
• It is the major criterion which distinguishes an embedded system from a general purpose
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system.
• For example, you cannot replace the embedded control unit of your microwave oven with
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your air conditioner’s embedded control unit, because the embedded control units of
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microwave oven and air conditioner are specifically designed to perform certain specific
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tasks.
• Also you cannot replace an embedded control unit developed for a particular domain say
telecom with another control unit designed to serve another domain like consumer
electronics.
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Reactive and Real Time
• As mentioned earlier, embedded systems are in constant interaction with the Real world
through sensors and user-defined input devices which are connected to the input port of the
system.
• Any changes happening in the Real world (which is called an Event) are captured by the
sensors or input devices in Real Time and the control algorithm running inside the unit
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reacts in a designed manner to bring the controlled output variables to the desired level.
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• The event may be a periodic one or an unpredicted one.
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• If the event is an unpredicted one then such systems should be designed in such a way that it
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should be scheduled to capture the events without missing them.
• Embedded systems produce changes in output in response to the changes in the input.
• So they are generally referred as Reactive Systems.
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Reactive and Real Time
• Real Time System operation means the timing behaviour of the system should be
deterministic; meaning the system should respond to requests or tasks.in a known amount of
time.
• A Real Time system should not miss any deadlines for tasks or operations.
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It is not necessary that all embedded systems should be Real Time in operations.
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• Embedded applications or systems which are mission critical, like flight control systems,
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Antilock Brake Systems (ABS), etc. are examples of Real Time systems.
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• The design of an embedded Real time system should take the Worst case scenario into
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consideration.
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Operates in Harsh Environment
• It is not necessary that all embedded systems should be deployed in controlled environments.
• The environment in which the embedded system deployed may be a dusty one or a high
temperature zone or an area subject to vibrations and shock.
• Systems placed in such areas should be capable to withstand all these adverse operating
conditions.
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• The design should take care of the operating conditions of the area where the system is going to
implement.
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• For example, if the system needs to be deployed in a high temperature zone, then all the
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components used in the system should be of high temperature grade.
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• Here we cannot go for a compromise in cost.
• Also proper shock absorption techniques should be provided to systems which are going to be
commissioned in places subject to high shock.
• Power supply fluctuations, corrosion and component aging, etc. are the other factors that need
to be taken into consideration for embedded systems to work in harsh environments.
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Distributed
• The term distributed means that embedded systems may be a part of larger systems.
• Many numbers of such distributed embedded systems form a single large embedded control
unit. An automatic vending machine is a typical example for this.
• The vending machine contains a card reader (for pre-paid vending systems), a vending unit, etc.
Each of them are independent embedded units but they work together to perform the overall
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vending function.
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• Another example is the Automatic Teller Machine (ATM).
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• An ATM contains a card reader embedded unit, responsible for reading and validating the
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user’s ATM card, transaction unit for performing transactions, a currency counter for
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dispatching/vending currency to the authorized person and a printer unit for printing the
transaction details.
• We can visualize their as independent embedded systems. But they work together to achieve a
common goal.
• Another typical example of a distributed embedded system is the Supervisory Control And Data
Acquisition (SCADA) system used in Control & Instrumentation applications, which contains
physically distributed individual embedded control units connected to a supervisory module.7
Small Size and Weight
• Product aesthetics is an important factor in choosing a product.
• For example, when you plan to buy a new mobile phone, you may make a comparative study on
the pros and corns of the products available in the market.
• Definitely the product aesthetics (size, weight, shape, style, etc.) will be one of the deciding
factors to choose a product.
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• People believe in the phrase “Small is beautiful”.
• Moreover it is convenient to handle a compact device than a bulky product.
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• In embedded domain also compactness is a significant deciding factor.
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• Most of the application demands small sized and low weight products.
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Power Concerns
• Power management is another important factor that needs to be considered in designing
embedded systems.
• Embedded systems should be designed in such a way as to minimize the heat dissipation by the
system.
• The production of high amount of heat demands cooling requirements like cooling fans which
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in turn occupies additional space and make the system bulky.
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• Nowadays ultra low power components are available in the market.
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• Select the design according to the low power components like low dropout regulators, and
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controllers/processors with power saving modes.
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• Also power management is a critical constraint in battery operated application.
• The more the power consumption the less is the battery life.
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QUALITY ATTRIBUTES OF EMBEDDED SYSTEMS
• Quality attributes are the non-functional requirements that need to be documented properly in
any system design.
• If the quality attributes are more concrete and measurable it will give a positive impact on the
system development process and the end product.
• The various quality attributes that needs to be addressed in any embedded system
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development are broadly classified into two, namely
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 ‘Operational Quality Attributes’
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 ‘Non-Operational Quality Attributes’.
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Operational Quality Attributes
• The operational quality attributes represent the relevant quality attributes related to the
embedded system when it is in the operational mode or ‘online’ mode.
• The important quality attributes coming under this category are listed below:
 Response
 Throughput
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 Reliability
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 Maintainability
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 Security
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 Safety
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Response
• Response is a measure of quickness of the system.
• It gives you an idea about how fast your system is tracking the changes in input variables.
• Most of the embedded systems demand fast response which should be almost Real Time.
• For example, an embedded system deployed in flight control application should respond in a
Real Time manner.
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• Any response delay in the system will create potential damages to the safety of the flight as well
as the passengers.
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• It is not necessary that all embedded systems should be Real Time in response.
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• For example, the response time requirement for an electronic toy is not at all time-critical.
• There is no specific deadline that this system should respond within this particular timeline.
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Throughput
• Throughput deals with the efficiency of a system. In general it can be defined as the rate of
production or operation of a defined process over a stated period of time.
• The rates can be expressed in terms of units of products, batches produced, or any other
meaningful measurements.
• In the case of a Card Reader, throughput means how many transactions the Reader can perform
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in a minute or in an hour or in a day.
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• Throughput is generally measured in terms of ‘Benchmark’.
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• A ‘Benchmark’ is a reference point by which something can be measured.
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• Benchmark can be a set of performance criteria that a product is expected to meet or a
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standard product that can be used for comparing other products of the same product line.
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Reliability
• Reliability is a measure of how much % you can rely upon the proper functioning of the system
or what is the % susceptibility of the system to failures.
• Mean Time Between Failures (MTBF) and Mean Time To Repair (MTTR) are the terms used in
defining system reliability.
• MTBF gives the frequency of failures in hours/weeks/months. MTTR specifies how long the
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system is allowed to be out of order following a failure.
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• For an embedded system with critical application need, it should be of the order of minutes.
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Maintainability
• Maintainability deals with support and maintenance to the end user or client in case of
technical issues and product failures or on the basis of a routine system checkup.
• Reliability and maintainability are considered as two complementary disciplines.
• A more reliable system means a system with less corrective maintainability requirements and
vice versa.
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• As the reliability of the system increases, the chances of failure and non-functioning also
reduces, thereby the need for maintainability is also reduced.
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• Maintainability is closely related to the system availability.
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• Maintainability can be broadly classified into two categories, namely, ‘Scheduled or Periodic
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Maintenance (preventive maintenance)’ and ‘Maintenance to unexpected failures (corrective
maintenance)’.
• Some embedded products may use consumable components or may contain components which
are subject to wear and tear and they should be replaced on a periodic basis.
• The period may be based on the total hours of the system usage or the total output the system
delivered.
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Maintainability
• A printer is a typical example for illustrating the two types of maintainability.
• An inkjet printer uses ink cartridges, which are consumable components and as per the printer
manufacturer the end user should replace the cartridge after each V number of printouts to get
quality prints. This is an example for ‘Scheduled or Periodic maintenance’.
• If the paper feeding part of the printer fails the printer fails to print and it requires immediate
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repairs to rectify this problem.
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• This is an example of ‘Maintenance to unexpected failure’.
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• In both of the maintenances (scheduled and repair), the printer needs to be brought offline and
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during this time it will not be available for the user.
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• Hence it is obvious that maintainability is simply an indication of the availability of the product
for use.
• In any embedded system design, the ideal value for availability is expressed as
A { = MTBF/(MTBF + MTTR)
where A { = Availability in the ideal condition, MTBF = Mean Time Between Failures, and MTTR =
Mean Time To Repair 16
Security
• Confidentiality, ‘Integrity’, and ‘Availability’ (The tenn ‘Availability’ mentioned here is not
related to the term ‘Availability’ mentioned under the ‘Maintainability’ section) are the three
major measures of information security.
• Confidentiality deals with the protection of data and application from unauthorised disclosure.
• Integrity deals with the protection of data and application from unautho rised modification.
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• Availability deals with protection of data and application from- unauthorized users.
• A very good example of the ‘Security’ aspect in an embedded product is a Personal Digital
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Assistant (PDA).
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• The PDA can be either a shared resource (e.g. PDAs used in LAB setups) or an individual one.
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• If it is a shared one there should be some mechanism in the form of a user name and password
to access into a particular person’s profile-This is an example of ‘Availability’.
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Security
• Also all data and applications present in the PDA need not be accessible to all users.
• Some of them are specifically accessible to administrators only.
• For achieving this, Administrator and user levels of security should be implemented -An
example of Confidentiality.
• Some data present in the PDA may be visible to all users but there may not be necessary
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permissions to alter the data by the users.
• That is Read Only access is allocated to all users-An example of Integrity.
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Safety
• ‘Safety’ and ‘Security’ are two confusing tenns.
• Sometimes you may feel both of them as a single attribute.
• But they represent two unique aspects in quality attributes.
• Safety deals with the possible damages that can happen to the operators, public and the
environment due to the breakdown of an embedded system or due to the emission of
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radioactive or hazardous materials from‘ the embedded products.
• The breakdown of an embedded system may occur due to a hardware failure or a firmware
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failure.
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• Safety analysis is a must in product engineering to evaluate the anticipated damages and
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determine the best course of action to bring down the consequences of the damages to an
acceptable level.
• As stated before, some of the safety threats are sudden (like product breakdown) and some of
them are gradual (like hazardous emissions from the product).
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Non-Operational Quality Attributes
• The quality attributes that needs to be addressed for the product ‘not 5 on the basis of
operational aspects are grouped under this category.
• The important quality attributes coming under this category are listed below.
 Testability & Debug-ability
 Evolvability
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 Portability
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 Time to prototype and market
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 Per unit and total cost.
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Testability & Debug-ability
• Testability deals with how easily one can test his/her design, application and by which means
he/she can test it.
• For an embedded product, testability is applicable to both the embedded hardware and
firmware.
• Embedded hardware testing ensures that the peripherals and the total hardware functions in
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the desired mamier, whereas firmware testing ensures that the firmware is functioning in the
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expected way.
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• Debug-ability is a means of debugging the product as such for figuring out the probable sources
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that create unexpected behaviour in the total system.
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• Debug-ability has two aspects in the embedded system development context, namely, hardware
level debugging and firmware level debugging.
• Hardware debugging is used for figuring out the issues created by hardware problems whereas
firmware debugging is employed to figure out the probable errors that appear as a result of
flaws in the firmware.
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Evolvability
• Evolvability is a term which is closely related to Biology.
• '-Evolvability is referred as the non-heritable variation.
• For an embedded system, .the quality attribute ‘Evolvability’ refers to the ease with which the
embedded product (including firmware and hardware) can be modified to take advantage of
new firmware or hardware technologies.
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Portability
• Portability is a measure of‘ system independence’.
• An embedded product is said to be portable if the product is capable of functioning ‘as such’ in
various environments, target processors/ controllers and embedded operating systems.
• The ease with which an embedded product can' be ported on to a new platform is a direct
measure of the re-work required.
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• A standard embedded product should always be flexible and portable. In embedded products,
the term ‘porting’ represents the migration of the embedded firmware written for one target
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processor (e.g. Intel x86) to a different target processor (say Hitachi SH3 processor).
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• If the firmware is written in a high level language like ‘C’ with little target processor-specific
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functions (operating system extensions or compiler specific utilities), it is very easy to port the
firmware for the new processor by replacing those ‘target processor-specific functions’ with the
ones for the new target processor and re-compiling the program for the new target processor-
specific settings.
• Re-compiling the program for the new target processor generates the new target processor-
specific machine codes.
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Portability
• If the firmware is written in Assembly Language for a particular family of processor (say x86
family), it will be very difficult to translate the assembly language instructions to the new target
processor specific language and so the portability is poor.
• If you look into various programming languages for application development for desktop
applications, you will see that certain applications developed on certain languages run only on
specific operating systems and some of them run independent of the desktop operating
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systems.
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• For example, applications developed using Microsoft technologies (e.g. Microsoft Visual C++
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using Visual studio) is capable of running only on Microsoft platforms and will not function on
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other operating systems; whereas applications developed using ‘Java’ from Sun Microsystems
works on any operating system that supports Java standards.
24
Time-to-Prototype and Market
• Time-to-market is the time elapsed between the conceptualization of a product and the time at
which the product is ready for selling (for commercial product) or use (for non-commercial
products).
• The commercial embedded product market is highly competitive and time to market the
product is a critical factor in the success of a commercial embedded product.
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• There may be multiple players in the embedded industry who develop products of the same
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category (like mobile phone, portable media players, etc.).
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• If you come up with a new design and if it takes long time to develop and market it, the
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competitor product may take advantage of it with their product.
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• Also, embedded technology is one where rapid technology change is happening.
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Time-to-Prototype and Market
• If you start your design by making use of a new technology and if it takes long time to develop
and market the product, by the time you market the product, the technology might have
superseded with a new technology.
• Product prototyping helps a lot in reducing time-to-market. Whenever you have a product idea,
you may not be certain about the feasibility of the idea.
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• Prototyping is an informal kind of rapid product development in which the important features
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of the product under consideration are developed.
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• The time to prototype is also another critical factor.
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• If the prototype is developed faster, the actual estimated development time can be brought
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down significantly.
• In order to shorten the time to prototype, make use of all possible options like the use of off-
the-shelf components, re-usable assets, etc.
26
Per Unit Cost and Revenue
• Cost is a factor which is closely monitored by both end user (those who buy the product) and
product manufacturer (those who build the product).
• Cost is a highly sensitive factor for commercial products. Any failure to position the cost of a
commercial product at a nominal rate, may lead to the failure of the product in the market.
• Proper market study and cost benefit analysis should be carried out before taking a decision on
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the per-unit cost of the embedded product:
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• From a designer/ product development company perspective the ultimate aim of a product is to
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generate marginal profit.
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• So the budget and total system cost should be properly balanced to provide a marginal profit.
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27
The Product life cycle (PLC)
• Every embedded product has a product life cycle which starts with the design and development
phase.
• The product idea generation, prototyping, Roadmap definition, actual product design and
development are the activities carried out during this phase.
• During the design and development phase there is only investment and no returns. Once the
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product is ready to sell, it is introduced to the market.
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• This stage is known as the Product Introduction stage. During the initial period the sale£ and
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revenue will be low.
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• There won’t be much competition and the product sales and revenue increases with time. In the
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growth phase, the product grabs high market share.
• During the maturity phase, the growth and sales will be steady and the revenue reaches at its
peak.
• The Product Retirement/Decline phase starts with the drop in sales volume, market share and
revenue.
• The decline happens due to various reasons like competition from similar product with
enhanced features or technology changes, etc. 28
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• At some point of the decline stage, the manufacturer announces discontinuing of the product.
• The different stages of the embedded products life cycle-revenue, unit cost and profit in each
stage-are represented in the following Product Life-cycle graph (Fig.3.1).
• From the graph, it is clear that the total revenue increases from the product introduction stage
to the product maturity stage.
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• The revenue peaks at the maturity stage and starts falling in the decline/retirement stage.
• The unit cost is very high during the introductory stage (a typical example is cell phone; if you
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buy a new model of cell phone during its launch time, the price will be high and you will get the
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same model with a very reduced price after three or four months of its launching).
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• The profit increases with increase in sales and attains a steady value and then falls with a dip in
sales.
• You can see a negative value for profit during the initial period.
• It is because during the product development phase there is only investment and no returns.
• Profit occurs only when the total returns exceed the investment and operating cost.
30
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Thank you
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Application and Domain-Specific
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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Application and domain based embedded system
• Embedded systems are application and domain specific, meaning; they are specifically built
for certain applications in certain domains like consumer electronics, telecom, automotive,
industrial control, etc.
• In general purpose computing, it is possible to replace a system with another system which is
closely matching with the existing system, whereas it is not the case with embedded systems.
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• Embedded systems are highly specialized in functioning and are dedicated for a specific
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application.
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• Hence it is not possible to replace an embedded system developed for a specific application
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in a specific domain with another embedded system designed for some other application in
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some other domain.
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Washing Machine—Application-Specific Embedded System
• People experience the power of embedded systems and enjoy the features and comfort
provided by them, but they are totally unaware or ignorant of the intelligent embedded
players working behind the products providing enhanced features and comfort.
• Washing machine is a typical example of an embedded system providing extensive support in
home automation applications.
• An embedded system contains sensors, actuators, control unit and application-specific user
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interfaces like keyboards, display units, etc.
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• Some of them are visible and some of them may be invisible to you.
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• The actuator part of the washing machine consists of a motorized agitator, tumble tub, water
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drawing pump and inlet valve to control the flow of water into the unit.
• The sensor part consists of the water temperature sensor, level sensor, etc.
• The control part contains a microprocessor/controller based board with interfaces to the
sensors and actuators.
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• The sensor data is fed back to the control unit and the-control unit generates the necessary
actuator outputs.
• The control unit also provides connectivity to user interfaces like keypad for setting the
washing time, selecting the type of material to be washed like light, medium, heavy duty, etc.
• User feedback is reflected through the display unit and LEDs connected to the control board.
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• The functional block diagram of a washing machine is shown in Fig. 4.2.
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• Washing machine comes in two models, namely, top loading and front loading machines.
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• In top loading models the agitator of the machine twists back and forth and pulls the cloth
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down to the bottom of the tub.
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• On reaching the bottom of the tub the clothes work their way back up to the top of the tub
where the agitator grabs them again and repeats the mechanism.
• In the front loading machines, the clothes are tumbled and plunged into the water over and
over again. This is the first phase of washing.
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• In the second phase of washing, water is pumped out from the tub and the inner tub uses
centrifugal force to wring out more water from the clothes by spinning at several hundred
Rotations Per Minute (RPM). This is called a ‘Spin Phase’.
• If you look into the keyboard panel of your washing machine you can see three buttons
namely* Wash, Spin and Rinse.
• You can use these buttons to configure the washing stages.
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• As you can see from the picture, the inner tub of the machine contains a number of holes and
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during the spin cycle the inner tub spins, and forces the water out through these holes to the
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stationary outer tub from which it is drained off through the outlet pipe.
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• It is to be noted that the design of washing machines may vary from manufacturer to
manufacturer, but the general principle underlying in the working of the washing machine
remains the same.
• The basic controls consist of a timer, cycle selector mechanism, water temperature selector,
load size selector and start button.
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• The mechanism includes the motor, transmission, clutch, pump, agitator, inner tub, outer tub
and water inlet valve.
• Water inlet valve connects to the water supply line using at home and regulates the flow of
water into the tub.
• The integrated control panel consists of a microprocessor/controller based board with I/O
interfaces and a control algorithm running in it.
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• Input interface includes the keyboard which consists of wash type selector namely* Wash,
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Spin and Rinse, cloth type selector namely* Light, Medium, Heavy duty and washing time
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setting, etc.
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• The output interface consists of LED/LCD displays, status indication LEDs, etc. connected to
the I/O bus of the controller.
• It is to be noted that this interface may vary from manufacturer to manufacturer and model
to model.
• The other types of I/O interfaces which are invisible to the end user are different kinds of
sensor interfaces, namely, water temperature sensor, water level sensor, etc. and actuator
interface including motor control for agitator and tub movement control, inlet water flow
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control, etc.
Automotive Embedded Systems
• Automotive embedded systems are the one where electronics take control over the mechanical
systems.
• The presence of automotive embedded system in a vehicle varies from simple mirror and
wiper controls to complex air bag controller and antilock brake systems (ABS).
• Automotive embedded systems are normally built around microcontrollers or DSPs or a hybrid
of the two and are generally known as Electronic Control Units (ECUs).
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• The number of embedded controllers in an ordinary vehicle varies from 20 to 40 whereas a
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luxury vehicle like Mercedes S and BMW 7 may contain 75 to 100 numbers of embedded
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controllers.
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• Government regulations on fuel economy, environmental factors and emission standards and
increasing customer demands on safety, comfort and infotainment forces the automotive
manufactures to opt for sophisticated embedded control units within the vehicle.
• The first embedded system used in automotive application was the microprocessor based fuel
injection system introduced by Volkswagen 1600 in 1968.
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• The various types of electronic'control units (ECUs) used in the automotive embedded industry
can be broadly classified into two-High-speed embedded control units and Low-speed
embedded control units.
• High-speed Electronic Control Units (HECUs)
 High-speed electronic control units (HECUs) are deployed in critical control units
requiring fast response.
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 They include fuel injection systems, antilock brake systems, engine control, electronic
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throttle, steering controls, transmission control unit and central control unit.
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• Low-speed Electronic Control Units (LECUs)
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 Low-Speed Electronic Control Units (LECUs) are deployed in applications where response
time is not so critical.
 They generally are built around low cost microprocessors/microcontrollers and digital
signal processors.
 Audio controllers, passenger and driver door locks, door glass controls (power windows),
wiper control, mirror control, seat control systems, head lamp and tail lamp controls, sun
roof control unit etc. are examples of LECUs. 10
• Automotive Communication Buses
 Automotive applications make use of serial buses for communication, which greatly
reduces the amount of wiring required inside a vehicle.
 The following section will give you an overview of the different types of serial interface
buses deployed in automotive embedded applications.
• Controller Area Network (CAN)
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 The GAN bus was originally proposed by Robert Bosch, pioneer in the Automotive
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embedded solution providers.
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 It supports medium speed (ISOl 1519-class B with data rates up to 125 Kbps) and high
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speed (ISOl 1898 class C with data rates up to 1Mbps) data transfer.
 CAN is an event-driven protocol interface with, support for error handling in data
transmission.
 It is generally employed in safety system like airbag control; power train systems like
engine control and Antilock Brake System (ABS); and navigation systems like GPS.
 The protocol format and interface application development for CAN bus will be explained
in detail in another volume of this book series. 11
• Local Interconnect Network (LIN)
 LIN bus is a single master multiple slave (up to 16 independent slave nodes)
communication interface.
 LIN is a low speed, single wire communication interface with support for data rates up to
20 Kbps and is used for sensor/actuator interfacing.
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 LIN bus follows the master communication triggering technique to eliminate the possible
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bus arbitration problem that can occur by the simultaneous talking of different slave
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nodes connected to a single interface bus.
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 LIN bus is employed in applications like mirror controls, fan controls, seat positioning
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controls, window controls, and position controls where response time is not a critical
issue.
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• Media-Oriented System Transport (MOST)
 Bus The Media-oriented system transport (MOST) is targeted for automotive audio/video
equipment interfacing, used primarily in European cars.
 A MOST bus is a multimedia fiber-optic point-to-point network implemented in a star, ring
or daisy- chained topology over optical fiber cables.
 The MOST bus-specifications define the physical (electrical and optical parameters) layer
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as well as the application layer, network layer, and media access control.
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 MOST bus is an optical fiber cable connected between the Electrical Optical Converter
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(EOC) and Optical Electrical Converter (OEC), which would translate into the optical cable
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MOST bus.
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Key Players of the Automotive Embedded Market
• The key players of the automotive embedded market can be visualized in three verticals
namely, silicon providers, solution providers and tools and platform providers.
• Silicon Providers
 Silicon providers are responsible for providing the necessary chips which are used in the
control application development.
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 The chip may be a standard product like microcontroller or DSP or ADC/D AC chips.
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 Some applications may require specific chips and they are manufactured as Application
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Specific Integrated Chip (ASIC).
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 The leading silicon providers in the automotive industry are:
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• Analog Devices (www.analog.com):
 Provider of world class digital signal processing chips, precision analog microcontrollers,
programmable inclinometer/accelerometer, LED drivers, etc. for automotive signal
processing applications, driver assistance systems, audio system, GPS/Navigation system,
etc.
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• Xilinx (www.xilinx.com):
 Supplier of high performance FPGAs, CPLDs and automotive specific IP cores for GPS
navigation systems, driver information systems, distance control, collision avoidance,
rear, shat entertainment, adaptive cruise control, voice recognition, etc.
• Atmel (www.atmel.com):
 Supplier of cost-effective high-density Flash controllers and memories.
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 Atmel provides a series of high performance microcontrollers, namely, ARM® 1, AVR®
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2 , and 80C51.
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 A wide range of Application Specific Standard Products (ASSPs) for chassis, body
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electronics, security, safety and car infotainment and automotive networking products
for CAN, LIN and FlexRay are also supplied by Atmel.
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• Maxim/Dallas (www.maxim-ic.com):
 Supplier of world class analog, digital and mixed signal products (Microcontrollers,
ADC/DAC, amplifiers, comparators, regulators, etc), RF components, etc. for all kinds of
automotive solutions.
• NXP semiconductor (www.nxp.com):
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 Supplier of 8/16/32 Flash microcontrollers.
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• Renesas (www.renesas.com):
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 Provider of high speed microcontrollers and Large Scale Integration (LSI) technology for
car navigation systems accommodating three transfer speeds: high, medium and low.
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• Texas Instruments (www.ti.com):
 Supplier of microcontrollers, digital signal processors and automotive communication
control chips for Local Inter Connect (LIN) bus products.
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• Fujitsu (www.fmal.fujitsu.com):
 Supplier of fingerprint sensors for security applications, graphic display controller for
instmmentation application, AGPS/GPS for vehicle navigation system and different types
of microcontrollers for automotive control applications.
• Infineon (www.infineon.com):
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 Supplier of high performance microcontrollers and customised application specific chips.
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• NEC (www.nec.co.jp):
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 Provider of high performance microcontrollers.
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• There are lots of other silicon manufactures which provides various automotive support
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systems like power supply, sensors/actuators, optoelectronics, etc.
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Tools and Platform Providers
• Tools and platform providers are manufacturers and suppliers of various kinds of development
tools and Real Time Embedded Operating Systems for developing and debugging different
control unit related applications.
• Tools fall into two categories, namely embedded software application development tools and
embedded hardware development tools.
• Sometimes the silicon suppliers provide the development suite for application development
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using their chip. Some third party suppliers may also provide development kits and libraries.
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• Some of the leading suppliers of tools and platforms in automotive embedded applications are
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listed below.
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• ENEA (www.enea.com):
 Enea Embedded Technology is the developer of the OSE Real-Time operating system.
 The OSE RTOS supports both CPU and DSP and has also been specially developed to
support multi-core and fault-tolerant system development.
• The Math Works (www.mathworks.com):
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 It is the world’s leading developer and supplier of technical software.
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 It offers a wide range of tools, consultancy and training for numeric computation,
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visualisation, modelling and simulation across many different industries.
 MathWork’s breakthrough product is MATLAB- a high-level programming language and
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environment for technical computation and numerical analysis.
 Together MATLAB, SIMULINK, Stateflow and Real-Time Workshop provide top quality
tools for data analysis, test & measurement, application development and deployment,
image processing and development of dynamic and reactive systems for DSP and control
applications.
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• Keil Software (www.keil.com):
 The Integrated Development Environment Keil Microvision from Keil software is a
powerful embedded software design tool for 8051 & Cl66 family of microcontrollers.
• Lauterbach (http://www.lauterbach.com/):
 It is the world’s number one supplier of debug tools, providing support for processors
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from multiple silicon vendors in the automotive market.
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• ARTiSAN (www.artisansw.com):
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 Is the leading supplier of collaborative modelling tools for requirement analysis,
specification, design and development of complex applications.
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• Microsoft (www.microsoft.com):
 It is a platform provider for automotive embedded applications.
 Microsoft’s WindowsCE is a powerful RTOS platform for automotive applications.
 Automotive features are included in the new WinCE Version for providing support for
automotive application developers.
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Solution Providers
• Solution providers supply OEM and complete solution for automotive applications making use
of the chips, platforms and different development tools. The major players of this domain are
listed below.
• Bosch Automotive (www.boschindia.com):
 Bosch is providing complete automotive solution ranging from body electronics, diesel engine control,
gasoline engine control, powertrain systems, safety systems, in-car navigation systems and
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infotainment systems.
• DENSO Automotive (www.globaldensoproducts.com):
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 Denso is an Original Equipment Manufacturer(OEM) and solution provider for engine management,
climate control, body electronics, driving control & safety, hybrid vehicles, embedded infotainment and
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communications.
• Infosys Technologies (www.infosys.com):
 Infosys is a solution provider for automotive embedded hardware and software.
 Infosys provides the competitive edge in integrating technology change through cost-effective solutions.
• Delphi (www.delphi.com):
 Delphi is the complete solution provider for engine control, safety, infotainment, etc., and OEM for
spark plugs, bearings, etc. 21
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Thank you
8051 Microcontroller Architecture
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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Overview
• Introduction to 8051
• Microprocessor Vs Microcontroller
• The Architecture of 8051
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• Pin Configuration of 8051
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•Memory Configuration
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Introduction
• Microcontroller are single chip microcomputers
• Consists of Central processing Unit
• Memory
• I/O ports
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• Timers and counters
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• Analog-to-Digital converter (ADC)
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• Digital-to-Analog converter (DAC)
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• Serial Port, Interrupt Logic
• Oscillatory circuitry and many more functional blocks on chip
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Difference
MICRO PROCESSER MICRO CONTROLLER
• It is a CPU • It is a single chip
• Memory, I/O Ports to be connected externally • Consists Memory, I/o ports
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Difference
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8051 Basic Component
 4K bytes internal ROM
 128 bytes internal RAM
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
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 One serial interface
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 8 bit cpu
A single chip
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 64k Program memory (4k on chip)
64k Data memory
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
 32 I/O


Full duplex UART
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6 Source/5 Vector interrupts with
two level priority levels- On chip clock Oscillator. CPU RAM ROM
Microcontroller
I/O Serial
Timer COM
Port
Port 6
Block Diagram
External Interrupts
Interrupt 4k 128 bytes Timer 1 Counter I/P

Control ROM RAM Timer 2
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CPU
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Bus
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OSC 4 I/O Ports Serial
Control
PSEN ALE P0 P2 P1 P3 TXD RXD

Addr/Data
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Other 8051 featurs
 only 1 On chip oscillator (external crystal)

 6 interrupt sources (2 external , 3 internal, Reset)
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 64K external code (program) memory(only read) PSEN
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 64K external data memory(can be read and write) by RD, WR
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Code memory is selectable by EA (internal or external)
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
We may have External memory as data and code

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
8
Comparison of the 8051 Family Members
 ROM type
◦ 8031 no ROM
◦ 80xx mask ROM
◦ 87xx EPROM
◦ 89xx Flash EEPROM
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 89xx
◦ 8951
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◦ 8952
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◦ 8953
◦ 8955
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◦ 898252
◦ 891051
◦ 892051
 Example (AT89C51,AT89LV51,AT89S51)
◦ AT= ATMEL(Manufacture)
◦ C = CMOS technology
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◦ LV= Low Power(3.0v)
On-Chip Memory Internal RAM
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8051 Internal Block Diagram
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8051 Architecture
 ALU
◦ Performs Arithmetic and logical operation on 8-bit operand.
◦ It also performs multiplication and subtraction operation
◦ Each logical operation involves AND, OR, NOT, XOR
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 Boolean Processor
◦ It has own instruction set , accumulator and bit addressable RAM
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◦ Carry flag serves as accumulator
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◦ Instructions allow complement bit, set bit, and clear bit
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◦ Conditional branch like jump if bit set etc
◦ Logical bit wise AND,OR
◦ The result of bitwise logical operation are stored into the carry bit, which works as an
accumulator
12
8051 Architecture
 Program and Data Memory
◦ There are two separate Program and Data Memories
◦ Code is stored in ROM/EPROM
◦ 8051 is having 4K ROM while 8052 is 8K ROM
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◦ Data memory can be internal RAM and off-chip external data RAM
◦ Some internal on-chip RAM locations are also used for controlling the operations of the
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peripherals such as timers/counters, serial port, interrupts. etc. called as special function
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registers (SFRs)
◦ To access off-chip data RAM, 16-bit address is used.
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◦ The address (Port 0) and address-data (Port 2) buses holds this address
◦ Lower order byte of the address – data bus is time multiplexed
◦ Multiplexing reduces pin counts also reduces speed of the memory
13
8051 Architecture
 The Oscillator
◦ It use an external crystal for oscillator function
◦ 8051 operates at 12 MHz frequency
◦ The baud rate is the rate at which information is transferred in a communication
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channel. In the serial port context, "9600 baud" means that the serial port is capable of
transferring a maximum of 9600 bits per second
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◦ It is necessary to connect the quartz crystal externally and all other oscillator circuit is
-D
on-chip
 Timing and Control
BB
◦ The whole operation of 8051 is synchronous with clock
◦ Apart from the internal timings, there are control signals ALE, PSEN, and RD, WR are
generated by timing and control unit, for accessing the off-chip devices.
14
8051 CPU Registers
A (Accumulator)
B
Used in assembler
PSW (Program Status Word)
instructions
SP (Stack Pointer)
PC (Program Counter)
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DPTR (Data Pointer)
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-D
BB
15
8051 Registers
 There are general purpose or working registers, Stack Pointer, Program counter and in
addition to these CPU registers, and SFRs.
 Accumulator
◦ 8-bit accumulator
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◦ Accumulator is used by all ALU instructions
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◦ Access to accumulator is faster than access to main memory
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◦ Accumulator has direct path to ALU and can immediately store the intermediate result of operation
B- register
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
◦ 8-bit register
BB
◦ It is available as general purpose register when it is not used by multiplication or division operation.
◦ While Multiplying, It holds one of the 8-bit operands
◦ And after the execution of the multiplication operation, it stores higher byte of the result.
◦ While division, It holds as 8-bit divisor
◦ And after the execution of division instruction, the reminder is stored in B-register
16
8051 Registers
 Register R0 through R7
◦ These 8 registers are used as scratch pad registers (high-speed internal memory used for temporary
storage of calculations, data, and other work in progress) .
◦ There are 4-register banks containing R0 through R7 registers.
◦ Each of these registers are 8-bit wide.
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◦ At a time only one bank can be selected by appropriate setting of bits in the program status word (PSW).
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◦ These are located in the on-chip RAM
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◦ Certain instructions can access these registers in RAM directly.
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◦ Power-up-reset causes bank 0 to be selected by default.
◦ If a byte is written in R4 then it would stored at RAM location 04H.
BB
◦ If in another case, the programmer is selecting bank 1 and writing a byte in R4, it will store the byte at
RAM location 0CH.
17
8051 Registers
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BB
18
8051 Registers
 Stack Pointer
◦ SP is 8-bit wide.
◦ It is incremented during push or call operations
◦ It is decremented during pop or return operation.
◦ After RESET operation, the stack pointer in initialized to 07H, causing the stack to begin at 08H.
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 Program Counter
◦ Instruction opcode bytes are fetched from the program memory locations addressed by the program
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counter.
-D
◦ PC in 16-bit wide, and it can address 64K code byte.
◦ PC always points to the instruction to be fetched and is automatically incremented after fetching the
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instruction.
◦ PC is affected by call and jump instruction.
◦ Only PC has no on-chip RAM address.
19
8051 Registers
 Special Function Registers (SFR)
◦ The 128 bytes of on-chip additional RAM location from 80H to 0FFH are reserved for the special function
and therefore these are called as SFR.
◦ These SFRs are used for control or to show the status of various function done by 8051 microcontroller.
◦ All SFRs are directly addressable and can be read or written to as well.
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◦ SFR space is only reserved for the special functions and cannot be used for any other purpose.
◦ Some SFRs are bit addressable and allow their individual bits to be set or cleared by instructions.
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Example
-D
◦ One can set the port 1 bit P1.1 using an instruction
SETB P1.0
BB
◦ One can cleat the port 1 bit P1.1 using an instruction
CLR P1.0
◦ The address of P1.1 is 91H.
◦ Port 1 has 90H as its byte address and it is byte addressable too.
◦ By writing a byte to address 90H, all the 8-bit of Port 1 can be changed in on stroke
20
8051 Special Function Registers
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BB
21
BB
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8051 Registers
 Program status word
◦ PSW is 8-bit wide.
◦ It consists of carry, auxiliary carry, overflow, and parity flags
◦ There are bits RS1 and RS0 for register bank selection
◦ PSW is bit addressable register
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◦ Each PSW bit a is reffered as PSW.X
◦ PSW.0 is LSB, which is parity flag
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◦ And MSB PSW.7 is carry flag.
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BB
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8051 Registers
 Carry Flag (PSW.7)
◦ Carry flag is set when a carry is generated out of 7th bit of result.
Example
11000010 B (0C2H)
+
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10101010 B (0AAH)
101101100 B (6CH)
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 Auxiliary Carry Flag (PSW.6)
-D
◦ Auxiliary Carry flag is set when a carry is generated out of 3rd bit, during an operation.
BB
 F0 (PSW.5)
◦ F0 will be available to user as general purpose flag.
◦ This can be set/Reset by Flag.
24
8051 Registers
 Register bank select bits RS1 and RS0 (PSW.4 and PSW.3)
◦ These are bits for selecting one of the four register banks.
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 Overflow Flag (PSW.2)
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◦ Overflow flag is set as a result of an arithmetic operation, provided there is a carry out of bit 6, but not
BB
out of bit 7 or a carry out of bit 7 but not out of bit 6.
 Parity Flag (PSW.0)
◦ This indicates the number of 1 s in accumulator.
◦ If there are odd number of 1s this will be set.
◦ If even number of 1s then it will be cleared.
25
8051 Registers
 Data Pointer (DPTR)
◦ DPTR is 16-bit register of two bytes.
◦ Higher bytes is DPH and lower is DPL.
◦ The DPTR is used for addressing the off-chip data and code with the MOVX and MOVC command.
◦ With 16-bit pointer DPTR , a maximum of 64K of off-chip data memory and maximum of 64K of off-chip
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program memory can be addressed.
 Timer Registers
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◦ Register pairs (TH0, TL0) (TH1, TL1) (TH2, TL2) form 16-bit timer/counter registers 0,1,2, respectively.
-D
◦ The operation may be timing or counting.
BB
 Port 0 to 3
◦ P0, P1, P2, P3 are the SFRs corresponding to four I/O ports.
◦ Each of these ports are bit/byte addressable.
26
8051 Registers
 Control Registers
◦ TCON, TMOD, IE, IP, SCON, PCON contain the control and
status for interrupts, serial I/O and timer/counters.
 Capture Registers
◦ Register pairs (RCAP2H-RCAP2L) are the capture
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registers for the timer 2.
◦ In capture mode , a transition at the 8052 T2EX pin
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causes TH2 and TL@ to be copied into RCAP2H and Addresses 80h – FFh
RCAP2L .
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Direct Addressing used to access SPRs
BB
27
8051 Pin Configuration
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
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P1.5 6 35 P0.4(AD4)
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P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
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(RXD)P3.0 10 8051 31
EA/VPP
(TXD)P3.1 11 30
-D
ALE/PROG
(INT0)P3.2 12 29
PSEN
(INT1)P3.3 13 28 P2.7(A15)
BB
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
28
8051 Schematic Pin out 8051 Foot Print
Important Pins
 PSEN (out): Program Store Enable, the read signal for external program memory (active low).
 ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2
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 EA (in): External Access Enable, active low to access external program memory locations 0 to 4K
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 RXD,TXD: UART (Universal Asynchronous Receiver/Transmitter) pins for serial I/O on Port 3
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 XTAL1 & XTAL2: Crystal inputs for internal oscillator.
BB
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Pins of 8051
 Vcc（pin 40）：
◦ Vcc provides supply voltage to the chip.
◦ The voltage source is +5V.
◦ Power supply current for 8051 is 125 mA.
◦ Maximum power dissipation rating is 1 W.
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 GND（pin 20）：ground
 XTAL1 and XTAL2（pins 19,18）：These 2 pins provide external clock.
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◦ Way 1：using a quartz crystal oscillator
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◦ Way 2：using a TTL oscillator
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 XTAL1 XTAL2 (18):
• Output of the inverting amplifier that forms a part of the oscillator and input to the internal clock
generator.
 XTAL1 (19):
• is the input to the inverting amplifier that forms part of the oscillator circuit.
• In case of external clock, this pin must be connected to ground.
30
XTAL Connection to 8051
C2
XTAL2
 Using a quartz crystal oscillator 30pF
 We can observe the frequency on the XTAL2 pin. C1
XTAL1
30pF
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GND
XTAL Connection to an External Clock Source
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NC XTAL2
External
Oscillator
Signal
XTAL1
BB 

Using a TTL oscillator
XTAL2 is unconnected.
GND
31
Machine Cycle
 Find the machine cycle for

 (a) XTAL = 11.0592 MHz
 (b) XTAL = 16 MHz.
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 Solution:
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(a) 11.0592 MHz / 12 = 921.6 kHz;
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
 machine cycle = 1 / 921.6 kHz = 1.085 s
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 (b) 16 MHz / 12 = 1.333 MHz;
 machine cycle = 1 / 1.333 MHz = 0.75 s
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Pins of 8051
 RST（pin 9）：reset
◦ input pin and active high. Vcc
 The high pulse must be high at least 2
machine cycles.
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◦ power-on reset.
10 uF
 Upon applying a high pulse to RST, the
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microcontroller will reset and all values in
RST
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registers will be lost. 9
 Reset values of some 8051 registers 8.2 K
BB
X1
30 pF
◦ power-on reset circuit
X2
Power-On RESET
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Pins of 8051
 /EA（pin 31）：external access
◦ There is no on-chip ROM in 8031 and 8032 .
◦ The /EA pin is connected to GND to indicate the code is stored externally.
◦ /PSEN ＆ ALE are used for external ROM.
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◦ For 8051, /EA pin is connected to Vcc.
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◦ “/” means active low.
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 /PSEN（pin 29）：program store enable
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◦ This is an output pin and is connected to the OE pin of the ROM.
ALE（pin 30）：address latch enable
BB

◦ It is an output pin and is active high.

◦ 8051 port 0 provides both address and data.
◦ The ALE pin is used for de-multiplexing the address and data by connecting to the G
pin of the 74LS373 latch.
34
IMPORTANT PINS (IO Ports)
 One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3)
 Port 0 （pins 32-39）：P0（P0.0～P0.7）
◦ 8-bit R/W - General Purpose I/O
◦ Or acts as a multiplexed low byte address and data bus for external memory design
 Port 1 （pins 1-8）：P1（P1.0～P1.7）
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◦ Only 8-bit R/W - General Purpose I/O
 Port 2 （pins 21-28）：P2（P2.0～P2.7）
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◦ 8-bit R/W - General Purpose I/O
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◦ Or high byte of the address bus for external memory design
Port 3 （pins 10-17）：P3（P3.0～P3.7）
BB

◦ General Purpose I/O

◦ if not using any of the internal peripherals (timers) or
◦ external interrupts.
 Each port can be used as input or output (bi-direction)
35
Hardware Structure of I/O Pin
 Each pin of I/O ports
◦ Internally connected to CPU bus
◦ A D latch store the value of this pin
Read V
 Write to latch＝1：write data into the D latch TB
cc
latch 2 Load(L1)
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◦ 2 Tri-state buffer：
Internal P1.X pin
D Q
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 TB1: controlled by “Read pin” CPU bus
 Read pin＝1：really read the data Clk Q
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Write to M1
present at the pin latch
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 TB2: controlled by “Read latch”
 Read latch＝1：read value from TB
internal latch Read pin 1
◦ A transistor M1 gate
 Gate=0: open
 Gate=1: close 36
Address Multiplexing for External Memory
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Accessing external code memory Multiplexing the address (low-byte) and data bus
37
External code memory
WR
RD
PSEN OE
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ALE 74LS373 CS
G
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P0.0 A0
D
P0.7 A7
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D0
D7
BB
EA
P2.0 A8
P2.7 A15
8051 ROM
38
External data memory
WR WR
RD RD
PSEN
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ALE 74LS37 CS
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G
P0.0 3 A0
D
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P0.7 A7
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D0
BB
D7
EA
P2.0 A8
P2.7 A15
8051 RAM
Interface to 1K RAM
39
Overlapping External Code and Data Spaces
WR WR
RD
PSEN RD
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ALE 74LS373 CS
G
P0.0 A0
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D
P0.7 A7
-D
BB
D0
D7
EA
P2.0 A8
P2.7 A15
8051 RAM
40
Timing for MOVX Instruction
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BB
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Overlapping External Code and Data Spaces
Allows the RAM to be
 written as data memory, and
 read as data memory as well as
code memory.
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This allows a program to be
downloaded from outside into the
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RAM as data, and
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 executed from RAM as code.
BB
42
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Interrupts
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BB
43
Inside Architecture of 8051
External interrupts
On-chip ROM Timer/Counter
Interrupt for program
On-chip Timer 1 Counter
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Control code
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RAM Timer 0 Inputs
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CPU
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Serial
BB
Bus Control 4 I/O Ports
OSC Port
P0 P1 P2 P3 TxD RxD
Address/Data
8051 Microcontroller Block Diagram 44

I/O Services
• A single microcontroller can serve several devices.
• Two ways:
 Interrupt method
 An interrupt is an external or internal event that interrupts the microcontroller to inform it that
a device needs its service.
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 Whenever any device needs its service, the device notifies the microcontroller by sending it an
interrupt signal.
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 Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and
serves the device.
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 The program which is associated with the interrupt is called the interrupt service routine (ISR)
BB
or interrupt handler.
 Polling method
 The microcontroller continuously monitors the status of a given device.
 When the condition is met, it performs the device.
 After that, it moves on to monitor the next device until every one is serviced.
 The microcontroller check all devices in a round-robin fashion.
45
Interrupt Service Routine
• For every interrupt, there is a fixed location in memory that holds the address of its ISR.
• The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table
The advantage of Interrupts

• The microcontroller can serve many devices.
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• Each device can get service based on the priority assigned to it.
• The microcontroller can ignore (mask) a device request.
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• The use of microcontroller is more efficient.
-D
– Ex: in polling system, HERE: JNB TI, HERE wastes much of the microcontroller’s time.
•
BB
Steps in Enabling an Interrupt
To enable an interrupt, we take the following steps:
– Set EA=1. Enables all interrupts.
• If EA=0, no interrupt will be responded to, even if the associated bit in the IE is high.
– Enable each interrupt by setting its corresponding bit in IE.
46
Six Interrupts in the 8051
• Reset
• Two interrupt for the timers
– TF0, TF1
• Two interrupt for external hardware interrupts
– INT0, INT1
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• Serial communication
– TI or RI
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• There is a limited number of bytes for each interrupt.
-D
– 3 bytes for reset
– 8 bytes for timers and external hardware interrupts
•
–
BB
If the service routine is too short to fit the ISR, an LJMP instruction is placed in the vector table to
point to the address of the ISR.
Programmers must enable these interrupts before using them.
Note: that there are only 8 memory locations between vectors.
47
Interrupt Vectors
• Each interrupt has a specific place in code memory where program execution (interrupt service
routine) begins.
Interrupt ROM Location (Hex) Pin
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Reset 0000 9
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External hardware interrupt 0 (INT0) 0003 P3.2 (12)
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Timer 0 interrupt (TF0) 000B
-D
BB
External hardware interrupt 1 (INT1) 0013 P3.3 (13)
Timer 1 interrupt (TF1) 001B
Serial COM interrupt (RI and TI) 0023
48
IE (Interrupt Enable) Register
EA IE.7 Disables all interrupts.

If EA=0, no interrupt is acknowledged.
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If EA=1, each interrupt source is individually enabled of
disabled by setting or clearing its enable bit.
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--- IE.6 Not implemented, reserved for future use. *
-D
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952).
BB
ES IE.4 Enables or disables the serial port interrupt. RI or TI
ET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1
EX1 IE.2 Enables or disables external interrupt 1. INT1
ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0
EX0 IE.0 Enables or disables external interrupt 0. INT0
49
External Hardware Interrupts
• The 8051 has two external hardware interrupts:
– EX0: INT0, Pin 12 (P3.2)
– EX1: INT1, Pin 13 (P3.3)
• These two pins are used in timer/counter.
– INT is a trigger for hardware control (GATE=1).
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– Timer/counter is enabled only while the INT pin is high and the TR control pin is set.
• They are enabled and disabled using the IE register.
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– EX0 by IE.0
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– EX1 by IE.1
• Upon activation of these pins, the 8051 gets interrupted and jumps to the vector table to perform the ISR.
•
BB
There are two activation levels for the external hardware interrupts:
– Low level triggered
– Falling edge triggered
• This is chosen by IT0/IT1 in TCON.
– On Reset, IT0 and IT1 are both low, making external interrupts low level-triggered.
50
Interrupt Process
• If interrupt event occurs AND interrupt flag for that event is enabled, AND interrupts are
enabled, then:
 Current PC is pushed on stack.
 Program execution continues at the interrupt vector address for that interrupt.
 When a RETI instruction is encountered, the PC is popped from the stack and program execution resumes
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where it left off.
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Interrupt Priorities
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• What if two interrupt sources interrupt at the same time?
BB
• The interrupt with the highest PRIORITY gets serviced first.
• All interrupts have a default priority order.
• Priority can also be set to “high” or “low”.
51
Interrupt SFRs
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Interrupt enables for the 5 original 8051 interrupts:
Timer 2
BB
Serial (UART0)
Timer 1
Global Interrupt Enable – must
External 1
be set to 1 for any interrupt to
1 = Enable Timer 0
be enabled
0 = Disable External 0
52
Interrupts
…
mov a, #2
mov b, #16
mul ab
Program Execution
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mov R0, a
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mov R1, b interrupt
mov a, #12 ISR: inc r7
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mov b, #20 mov a,r7
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mul ab jnz NEXT
add a, R0 cpl P1.6
BB
mov R0, a NEXT: reti
mov a, R1
addc a, b return
mov R1, a
end
53
Timer and Counter
• The 8051 has two counters/timers which can be used either as timer to generate a time delay
or as counter to count events happening outside the microcontroller.
• They can be used either as timers or as counters.
• The Timer :Used as a time delay generator.
– The clock source is the internal crystal frequency of the 8051.
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• An event counter.
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– External input from input pin to count the number of events on registers.
– These clock pulses cold represent the number of people passing through an entrance, or the
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number of wheel rotations, or any other event that can be converted to pulses.
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• The 8051 has 2 timers/counters:
 Timer/Counter 0
•
•
 Timer/Counter 1
Both timers are 16 bits wide. BB
Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low byte and
high byte.
• Timer0 registers is a 16 bits register and accessed as low byte and high byte.
• The low byte is referred as a TL0 and the high byte is referred as TH0. These registers can be accessed like
any other registers. 54
Timer
• Set the initial value of registers
• Start the timer and then the 8051 counts up.
• Input from internal system clock (machine cycle)
• When the registers equal to 0 and the 8051 sets a bit to denote time out
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8051
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P2 P1
To LCD
BB
Set Timer 0
TH0
TL0
55
Counter
• Count the number of events
– Show the number of events on registers
– External input from T0 input pin (P3.4) for Counter 0
– External input from T1 input pin (P3.5) for Counter 1
– External input from Tx input pin.
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– We use Tx to denote T0 or T1.
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8051
-D
TH0
P1
BB
to
TL0 LCD
P3.4
a switch T0
56
Registers Used in Timer/Counter
• 8051 has two 16-bit Timer registers ,Timer 0 & Timer 1.
• As 8051 has 8-bit architecture , each Timer register is treated as two 8-bit registers namely
TH0, TL0, TH1, TL1.
• One 8-bit mode register -TMOD.
• One 8-bit control register-TCON.
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Edge-Triggered Interrupt
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• To make INT0 and INT1 edge-triggered interrupts, we must program the bits of the TCON
-D
register
BB
– The TCON register holds the IT0 and IT1 flag bits that determine level- or edge-
triggered mode of the hardware interrupt
• IT0 and IT1 are bits D0 and D2 of TCON
– They are also referred to as TCON.0 and TCON.2 since the TCON register is
bit-addressable
57
Timer and Counter
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-D
BB
58
TCON Register
• Timer control register TMOD is a 8-bit register which is bit addressable and in which Upper
nibble is for timer/counter, lower nibble is for interrupts
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• TR (Timer run control bit)
TR0 for Timer/counter 0; TR1 for Timer/counter 1.
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TR is set by programmer to turn timer/counter on/off.
-D
TR=0 : off (stop)
TR=1 : on (start)
• TF (timer flag, control flag)
BB
TF0 for timer/counter 0; TF1 for timer/counter 1.
TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is set to 1.
TF=0 : not reach
TF=1: reach
If we enable interrupt, TF=1 will trigger ISR. 59
TCON Register
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-D
BB
60
TCON Register
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-D
BB
61
Equivalent Instructions for the Timer Control Register
For timer 0
SETB TR0 = SETB TCON.4
CLR TR0 = CLR TCON.4
SETB TF0 = SETB TCON.5
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CLR TF0 = CLR TCON.5
For timer 1
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SETB TR1 = SETB TCON.6
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CLR TR1 = CLR TCON.6
BB
SETB TF1 = SETB TCON.7
CLR TF1 = CLR TCON.7
TCON: Timer/Counter Control Register

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD Register
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TMOD Register
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
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 Both Timer 0 &Timer 1 use the same Mode register TMOD.
• It is an-8-bit register .The lower 4-bits are meant for Timer 0 &the user 4-bits are
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meant for Timer 1
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• It is not bit addressable.
BB
• It is used similar to any other register of 8051 . For ex:
MOV TMOD,#21H
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TMOD Register
GATE
• Every timer has a mean of starting and stopping.
– GATE=0
• Internal control
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• The start and stop of the timer are controlled by way of software.
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• Set/clear the TR for start/stop timer.
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SETB TR0
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CLR TR0
– GATE=1
• External control
BB
• The hardware way of starting and stopping the timer by software and an external
source.
• Timer/counter is enabled only while the INT pin is high and the TR control pin is
set (TR).
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TMOD Register
C/T : Timer or counter selected cleared for timer operation (input from internal system
clock). Set for counter operation (input from Tx input pin).
M1,M0 : Used for mode selection. Because the Timers of 8051 can be set in 4-different modes.
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M1 M0 Mode Operation
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0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1)
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0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx
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1 0 2 8-bit auto reload 8-bit auto reload timer/counter;
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THx holds a value which is to be reloaded into
TLx each time it overflows.
1 1 3 Split timer mode
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TMOD Register
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Working of Timer Mode 1
• For this , let us consider timer 0 as an example.
• 16-bit timer (TH0 and TL0)
• TH0-TL0 is incremented continuously when TR0 is set to 1. And the 8051 stops to increment
TH0-TL0 when TR0 is cleared.
• The timer works with the internal system clock. In other words, the timer counts up each
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machine cycle.
• When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and TF0 is
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raised.
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• Programmer should check TF0 and stop the timer 0.
BB
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Steps of Mode 1
1. Choose mode 1 timer 0
– MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
– MOV TH0,#FFH
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– MOV TL0,#FCH
3. You better to clear the TF: TF0=0.
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– CLR TF0
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4. Start the timer.
BB
– SETB TR0
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Steps of Mode 1
5. The 8051 starts to count up by incrementing the TH0-TL0.

– TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H
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TR0=1
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TR0=0
TH0 TL0
Start timer
Stop timer
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FFFC FFFD FFFE FFFF 0000
TF = 0 TF = 0
BB TF = 0 TF = 0 TF = 1
TF Monitor TF until TF=1
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Steps of Mode 1
6. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1.
TH0-TL0= FFFE H, FFFF H, 0000 H (Now TF0=1)
7. Keep monitoring the timer flag (TF) to see if it is raised.
AGAIN: JNB TF0, AGAIN
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8. Clear TR0 to stop the process.
CLR TR0
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9. Clear the TF flag for the next round.
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CLR TF0
BB
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BB
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BB
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BB
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74
BB
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Basics of serial communication
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RxD and TxD pins in the 8051
• The 8051 has two pins for transferring and receiving data by serial communication. These two
pins are part of the Port3(P3.0 &P3.1)
• These pins are TTL compatible and hence they require a line driver to make them RS232
compatible
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• Max232 chip is one such line driver in use.
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• Serial communication is controlled by an 8-bit register called SCON register, it is a bit
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addressable register.
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Interfacing to PC
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SCON (Serial control) register
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BB
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SM0 , SM1, REN, TI, RI
• These two bits of SCON register determine the framing of data by specifying the number of
bits per character and start bit and stop bits. There are 4 serial modes.
SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8 bit data, 1 stop bit, 1 start bit
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1 0 Serial Mode 2
1 1 Serial Mode 3
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• REN (Receive Enable) also referred as SCON.4.
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• When it is high,it allows the 8051 to receive data on the RxD pin.
•
• BB
So to receive and transfer data REN must be set to 1.
When REN=0,the receiver is disabled.
• This is achieved as below
SETB SCON.4 & CLR SCON.4
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Contd…
TI (Transmit interrupt) is the D1 bit of SCON register.
• When 8051 finishes the transfer of 8-bit character, it raises the TI flag to indicate that it is
ready to transfer another byte.
• The TI bit is raised at the beginning of the stop bit.
RI (Receive interrupt) is the D0 bit of the SCON register.
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• When the 8051 receives data serially ,via RxD, it gets rid of the start and stop bits and places
the byte in the SBUF register.
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• Then it raises the RI flag bit to indicate that a byte has been received and should be picked up
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before it is lost.
BB
• RI is raised halfway through the stop bit.
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BB
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BB
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BB
Thank you
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Programming the 8051 Microcontroller
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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Contents
• Addressing modes
• Instruction sets
• Interrupts
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•
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Timer and Counter
• Serial Communication
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2
Addressing Modes
• Direct Addressing Mode

• Indirect Addressing Mode
• Register Addressing
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• Immediate Mode
• Register Indexed Mode
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BB
3
Addressing Modes
Direct Mode
• The direct address of the operand is specified in the instruction itself.
• Lower 128 bytes of internal RAM and the SFRs used
• specify data by its 8-bit address
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Usually for 30h-7Fh of RAM
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Opcode Byte 8-bit Direct Address
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Mov A, 70H ; copy contents of RAM at 70h to A
Mov R0,40H
Mov 56H, A BB
; copy contents of RAM at 40h to R0
; put contents of at A to 56H
Mov 0D0H, A ; put contents of A into PSW
4
Addressing Modes
Direct Mode
play with R0-R7 by direct address
MOV A,4  MOV A,R4
MOV A,7  MOV A,R7
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MOV 7,2  MOV R7,R6
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MOV R2, #5 ;Put 5 in R2
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MOV R2, 5 ;Put content of RAM at 5 in R2
BB
5
Addressing Modes
Register Indirect
• It uses any one of the registers R0-R7, of the register bank, as a pointer to the locations in the 256 bytes
of data memory block.
• It may point in the lower 128 bytes of the internal RAM, or the lower 256 bytes of the external data
memory.
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• the address of the source or destination is specified in registers
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Uses registers R0 or R1 for 8-bit address:
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mov psw, #0 ; use register bank 0
mov r0, #0x3C
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mov @r0, #3 ; memory at 3C gets #3 ; M[3C]  3
BB
Uses DPTR register for 16-bit addresses:
mov dptr, #0x9000 ; dptr  9000h
movx a, @dptr ; a  M[9000]
Note that 9000 is an address in external memory
SFRs are not addressed by this mode.
6
EXTERNAL ADDRESSING USING MOVX AND MOVC
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Addressing Modes
Register Addressing
 Registers R0 through R7 from the selected register bank, accumulator, B-register, and
DPTR are used.
 Either source or destination is one of CPU register
 The LSB of the opcode indicates which register is used
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MOV R0,A
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MOV A,R7
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ADD A,R4
ADD A,R7
MOV DPTR,#25F5H
MOV R5,DPL
BB
MOV R,DPH
Note that MOV R4,R7 is incorrect
8
Addressing Modes
Immediate Mode
• It allows using immediate data as part of the instruction.
• specify data by its value
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mov A, #0 ;put 0 in the accumulator
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;A = 00000000
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mov R4, #11h ;put 11hex in the R4 register
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;R4 = 00010001
mov B, #11 ;put 11 decimal in b register
mov DPTR,#7521h BB
;B = 00001011
;put 7521 hex in DPTR
;DPTR = 0111010100100001
9
Addressing Modes
Base Register Plus Index Register Indirect Mode
• This mode allows a byte to be accessed from the program memory, whose address is calculated as the
sum of a base register (DPTR/ PC) and the index register (accumulator)
• MOVC A, @A+DPTR, it will fetch a byte from the program memory, whose address is calculated by
adding the original 8-bit unsigned contents of the accumulator and the 16-bit contents of the DPTR.
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• Base address can be DPTR or PC
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mov DPTR, #4000h
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mov A, #5
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movc A, @A + DPTR ;a  M[4005]
• Base address can be DPTR or PC
ORG 1000h
1000 mov a, #5 BB
1002 movc a, @a + PC ;a  M[1008]
1003 Nop
• Table Lookup
• MOVC only can read internal code memory 10
The 8051 Instruction Set
 The following are the Instruction set of 8051
• Data Transfer Instruction
• Arithmetic Instructions
• Logical Instructions
• Boolean Variable Manipulation Instructions
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• Control Transfer Instructions.
 8051 has 111 instructions.
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 Instructions are classified as single byte, two-byte and three-byte.
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 45 single byte
BB
 45 two-byte
 17 three byte
11
Data Transfer Instructions
• There are MOV, MOVX, MOVC, PUSH, POP, and exchange XCG, XCH instructions.
• Data transfer instructions do not affect any of the PSW flags.
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• Exchange instructions
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XCH a, byte ;exchange accumulator and byte
BB
XCHD a, byte ;exchange low nibbles of accumulator and byte
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• MOV dest, source ;dest  source
• Stack instructions
PUSH direct ;increment stack pointer, ;move direct byte on stack
POP direct ;move direct byte from stack, ;decrement stack pointer
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pop
push
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stack pointer
BB stack
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STACKS
• Stack-oriented data transfer
– Only one operand (direct addressing)
– SP is other operand – register indirect - implied
• Direct addressing mode must be used in Push and Pop
mov sp, #0x40 ; Initialize SP
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push 0x55 ; SP  SP+1, M[SP]  M[55]
; M[41]  M[55]
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pop b ; b  M[55]
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Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore, to push/pop the
accumulator, must use acc, not a
BB
14
BB
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15
Logical Instructions
• Bitwise logical AND, OR, Exclusive-OR is possible in 8051.
• These instructions accept two 8-bit operands and the result is stored at the destination.
• No flags are affected by ANL,OR, and XOR.
• There are single instructions like CLR, SETB, and CPL
•
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Rotate instructions RR, RRC,RL,RLC
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• RLC instruction moves bit-7 of the accumulator into CY position.
• Swap instructions SWAP.
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• SWAP A instruction simply interchanges the lower and higher nibbles of the accumulator and no flags are
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affected.
BB
16
Logical Instructions
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17
Byte-level Logical Instructions
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BB
18
BYTE-LEVEL LOGICAL INSTRUCTIONS
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BB
19
BYTE-LEVEL LOGICAL INSTRUCTIONS
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20
Byte level logical instructions
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21
Bit Level Logical Instructions
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BB
22
Bit Level Logical Instructions
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23
Bit addressable control registers
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BB
24
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BB
25
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BB
26
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BB
27
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28
Rotate and swap operation
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BB
29
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BB
30
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BB
31
Arithmetic Instructions
• It is possible to carryout both signed
and unsigned addition by using the OV
flag.
• There are unsigned multiplication and
division operations directly supported
by the instructions
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Instructions Affecting Flags
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Incrementing and Decrementing
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BB
32
Incrementing and Decrementing
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ADDITION
ADDITION WITH CARRY
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BB
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SUBTRACTION
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MULTIPLE BYTE SUBTRACTION
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BB
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MULTIPLICATION
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BB
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DIVISION
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BB
37
Decimal Arithmetic
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BB
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Jump and Call Opcodes
 Jumps and calls are the decision codes that alter the flow of the program by examining the results of action
codes and changing the contents of the program counter.
 A jump permanently changes the contents of the program counter if certain program conditions exist.
 A call temporarily changes the program counter to allow another part of the program to run.
 A jump or call instruction can replace the contents of the program counter with a new program address
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number that causes program execution to begin at the code located at the new address.
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 Jump or call has 3 ranges
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 Short jump (SJMP):
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 A short jump trnasfers control within 256 byte range, from -128 to +127 bytew raltive to the first byte
of the following instruction.
BB
 Absolute jump (AJMP):
 AJMP allows 11-bit address to be specified in the instruction. The destination must be within 2K block
of the program memory from the next instruction followed by AJMP instruction.
 Long Jump (LJMP):
 LJMP, a 16 bit address is specified in the instruction and a jump to anywhere within 64 K block of
program memory is possible that is 0000H to FFFFH.
39
Jump and Call Opcodes
Relative Jump:
 Jumps that replace the program counter content with a new address that is greater than
the address of the instruction following the jump by 127d or less than the address of the
instruction following the jump by 128d are called relative jump.
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BB
40
BB
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41
BB
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Program Flow Control
• Unconditional jumps (“go to”)
• Conditional jumps
• Call and return
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Unconditional Jumps
• SJMP <rel addr> ; Short jump, relative address is 8-bit 2’s complement number, so jump can be
up to 127 locations forward, or 128 locations back.
• LJMP <address 16> ; Long jump
• AJMP <address 11> ; Absolute jump to anywhere within 2K block of program memory
• JMP @A + DPTR ; Long indexed jump
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BB
44
Unconditional Jumps
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BB
45
Unconditional Jumps
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BB
46
Infinite Loops
Start: mov C, p3.7

mov p1.6, C
sjmp Start
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Microcontroller application programs are almost always infinite loops!
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BB
47
Re-locatable Code
Memory specific NOT Re-locatable (machine code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
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ljmp Start
end
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Re-locatable (machine code)
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org 8000h
Start: mov C, p1.6
mov p3.7, C BB
sjmp Start
end
48
Jump table
Mov dptr,#jump_table
Mov a,#index_number
Rl a
Jmp @a+dptr
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...
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Jump_table: ajmp case0
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ajmp case1
ajmp case2
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ajmp case3
BB
49
Conditional Jumps
• These instructions cause a jump to occur only if a condition is true. Otherwise, program
execution continues with the next instruction.
loop: mov a, P1
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Jz loop ; if a=0, goto loop, ; else goto next instruction
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mov b, a
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• There is no zero flag (z)
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• Content of A checked for zero on time
BB
50
Bit Jumps
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Byte Jumps
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52
Byte Jumps
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Conditional Jumps
Mnemonic Description
JZ <rel addr> Jump if a = 0
JNZ <rel addr> Jump if a != 0
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JC <rel addr> Jump if C = 1
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JNC <rel addr> Jump if C != 1
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JB <bit>, <rel addr> Jump if bit = 1
JNB <bit>,<rel addr> Jump if bit != 1
JBC <bir>, <rel addr>
BB Jump if bit =1, &clear bit
CJNE A, direct, <rel addr> Compare A and memory, jump if not equal
Conditional Jumps
Mnemonic Description
CJNE A, #data <rel addr> Compare A and data, jump if not equal
CJNE Rn, #data <rel addr> Compare Rn and data, jump if not equal
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CJNE @Rn, #data <rel addr> Compare Rn and memory, jump if not equal
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DJNZ Rn, <rel addr> Decrement Rn and then jump if not zero
DJNZ direct, <rel addr>

BB Decrement memory and then jump if not zero
Call and Return
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• Call is similar to a jump, but
– Call pushes PC on stack before branching
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acall <address ll> ; stack  PC ; PC  address 11 bit
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lcall <address 16> ; stack  PC ; PC  address 16 bit
• BB
Return is also similar to a jump, but
– Return instruction pops PC from stack to get address to jump to
Ret ; PC  stack
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Calls and Returns
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BB
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Subroutines
call to the subroutine
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Main: ...
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acall sublabel
...
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...
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sublabel: ...
BB
...
the subroutine
ret
• Subroutines allow us to have "structured" assembly language programs.

• This is useful for breaking a large design into manageable parts.
• It saves code space when subroutines can be called many times in the same program.
58
Calls and Stack
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• SP is initialized to 07 after reset.(Same address as R7)
•
• BB
With each push operation 1st , pc is increased
When using subroutines, the stack will be used to store
the PC, so it is very important to initialize the stack
pointer. Location 2Fh is often used.
mov SP, #2Fh
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Subroutine –example
; Program to compute square root of value on Port 3
; (bits 3-0) and output on Port 1.
org 0
ljmp Main
reset service
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Main: mov P3, #0xFF ; Port 3 is an input
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loop: mov a, P3
anl a, #0x0F ; Clear bits 7..4 of A
lcall sqrt
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mov P1, a
main program
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sjmp loop
sqrt: inc a
BB
movc a, @a + PC
ret
Sqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3 subroutine

end
data
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Interrupts and Returns
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Problem
BB
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Thank You
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63
ARM Processor Architecture
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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What is ARM?
• Advanced RISC Machine

• First RISC microprocessor for commercial use
• Market-leader for low-power and cost-sensitive embedded applications
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The History of ARM
• The architectural ideas that that have evolved into this ARM class of microcontrollers were
developed long back in 1983.
• There was a company called Acorn computers that was the first to develop and evolve such ideas.
• Now these ideas were little different because they started to develop architectural ideas based on
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the RISC architecture concept.
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• And at that time there was a very popular microprocessor called 6502 from a company called
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Mostek that was used in one of the very popular microcomputers called BBC micro.
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• The first attempt of these people was to replace that processor by a more powerful processor,
which will make the BBC micro faster and more powerful.
•
BB
This resulted in the first commercial RISC implementation.
• It was not called ARM during that time, but it evolved into the ARM architecture.
• There was a company that finally got founded in 1990.
• The name ARM is the acronym for Advanced RISC Machine. So, you see in the name itself the word
RISC is embedded.
3
The History of ARM
• Developed at Acorn Computers Limited, of Cambridge, England, between 1983 and 1985
• Problems with CISC:
 Slower then memory parts
 Clock cycles per instruction
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• Solution – the Berkeley RISC I:
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 Competitive
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 Easy to develop (less than a year)
 Cheap
BB
 Pointing the way to the future
4
ARM Processors
• What is it?
 Family of 32-bit microcontroller processors
• Who makes it?
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ARM has changed their name several times:
 Acorn RISC Machines (1985)
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 Advanced RISC Machines (1990)
 ARM Holdings (1998)
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• What is its niche?


BB
Mid-high level complexity hand-held consumer electronics
PDA’s (1980’s)
 Cell phones (1990’s)
 Handheld game devices (2000’s)
5
• Now what is so interesting about ARM?
• The reason is ARM has been increasingly used in many applications, they are the most popular
category of microcontrollers that are seriously used in embedded system applications.
• The iPods from Apple through which you can listen to music, there was an ARM processor inside.
• Benq, Sony Ericsson these are very well known companies who manufacture TV sets and many
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audio visual equipments, there are ARM processors inside each of these equipment's.
• Typically they started to use ARM 9, but subsequently they upgraded them to the later version of
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ARM processors.
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• The Apple iPhone all of us are familiar with and some of the very popular Nokia phones all have
BB
ARM11 processor inside them.
• Till 2010, 90% of all serious embedded applications had this kind of ARM processors inside them.
• When you talk about embedded system application, depending on the application you decide how
much power you need from the processor.
• If it is a very simple application you do not need a processor as powerful as ARM.
• You can use 8-bit PIC microcontrollers. 6
Example Consumer Products
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TASC ChessMachine Nintendo DS Apple Ipod
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BB
Gameboy advance Apple Iphone
Apple Newton PDA
7
Processor design, not a chip
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Core design
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Chip design & fabrication
BB
 ARM licenses core designs to other companies
 OEMs can customize chips
 ARM provides compilers, development tools, and
debugging tools for chip development and product
development
Nintendo DS
8
ARM chips (examples)
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9
• ARM processors are typically 32 bit and above.
• So, ARM processor is required when you need reasonably powerful computation capability
that will make the heart of your embedded system.
• Now another thing is that ARM processors have very low power consumption and of course,
reasonably good performance.
• Because of this low power consumption, they are very widely used in battery operated devices.
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• There are many battery operated devices like the mobile phones
• First thing is that, ARM is essentially a RISC based architecture.
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• RISC architecture borrows some advanced architectural ideas in contrast to conventional
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microcontrollers that had very primitive kind of designs.
BB
• 8051 that was a very popular microcontroller, but architecture wise it was pretty primitive, it
did not use any kind of architectural enhancement or advanced features.
• ARM processor is not just one, but a whole family of processors and the most important thing
is that in order to maintain backward compatibility, all these share essentially a common
instruction set.
10
• The later generations some additional instructions have been added, but the older instructions
are also carried through, such that a program that was developed for a older generation would
run pretty well for the next generation also.
• Now the design philosophy here was of course we need a small processor so that we can have
lower power consumption and can be used for embedded systems application. So,
 the size of the processor should be small,
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 it should consume low power,
 high code density.
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• In microcontrollers, the program memory and data memory are all inside the chip.
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• There is a scarcity of real estate; you cannot put very large memory inside.
BB
• So, there is a maximum limit to the size of the program that you can run.
• Let us say the program memory size is 100 kilobytes.
• Whatever we write must fit within this 100 kilobytes.
• So, if the instruction set supports that in this 100 kilobytes, It can pack a code very nicely, so that
it can implement more functionality as compared with some kind of competing architecture
where a much more memory would be required to implement the same thing. 11
• Suppose an application X that need to implement in a conventional architecture maybe it will be
requiring 120 kilobytes but in RISC ARM Architecture it can fit within 100 kilobytes.
• This is something called high code density.
• There are some instruction features that allows us to reduce the number of instructions required.
• This can take advantage of limited memory and physical size restrictions.
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•
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And of course, here there is lot of flexibility in the interface.
ig
• We can interface with a wide variety of memory systems, very
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slow or also relatively.
• And of course, reduced die size means when you are actually
BB
fabricating the chip the size of that silicon is very small, so that
when you develop that ASIC it would occupy a very small portion
of it.
• So, you can use the remaining space to put in much more; with
additional functionality to make the ASIC very powerful.
12
ARM processor features
 ARM1 (1985) to ARM11 and Cortex lines, most having 5+ flavors
 ARM7 cores
 Small number of transistors (~35,000)
 No microcode, all instructions hard-wired (no flexibility in ISA)
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 3-stage pipeline (simple fetch-decode-execute)
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 4-8 KB cache memory, typically unified (data/instruction)
ig
 32-bit ISA (not used for simple control stuff)
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 18-56 MHz clock speed
 ARM extensions
 BB
 “Thumb” instruction set – 16 bit ISA packed into 32-bit code
“Jazelle” instruction set – java code executed in hardware (instead of JVM)
• Architectural simplicity, which allows
• Very small implementations, which result in
• Very low power consumption
13
• In ARM 7 instruction and data were both in the same memory.
• So, it was like a von Neumann architecture, but from ARM 9 onwards the architecture started a shift
towards Harvard architecture.
• Moving to ARM 10, the main difference was the pipeline was further enhanced by adding another
stage called issue.
• In this way the basic architecture started evolving making the processor more powerful and faster
by adding novel architectural concepts.
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BB
14
ARM chip pricing
• Core licensing – $200,000 to $10,000,000 depending
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• Some chip examples:
 Atmel AT91SAM family -- $3/unit qty 10,000 (2005)
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 NXP LPC24xx family -- $8-14/unit qty 1 (2009)
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 Texas Instruments MS470 family - $10-22/unit qty 1 (2009)
BB
15
ARM Architecture
• Typical RISC architecture:
 Large uniform register file
 Load/store architecture
 Simple addressing modes
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 Uniform and fixed-length instruction fields
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• Enhancements:
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 Each instruction controls the ALU and shifter
 Auto-increment and auto-decrement addressing modes
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 Multiple Load/Store
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 Conditional execution
• Results:
 High performance
 Low code size
 Low power consumption
 Low silicon area 16
Pipelining
• pipeline features of the ARM processor.
• Then we discuss how the pipeline in the
ARM processor looks like, and what is
expected to be gained out of it, why do use
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pipeline, what are the advantages that you
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have out of it.
ig
• What is pipelining?
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• Basically pipelining is a mechanism for
overlapped execution.
BB
• When you say we are caring out certain tasks, normally we do a task, complete it and then start
with the next task.
• In pipelining the concept is that even before you finish the first task, we start with the second
task, even before we finish the second task we start the third task.
• So, different parts of the tasks can be carried out in parallel in an overlapped fashion. 17
Pipelining
• We partition a computation that is being carried out into k number of sub-computations or
stages.
• Then it is possible to have very significant speed up, we shall see maximum up to k.
• But the very interesting thing is that we are not increasing the cost by a factor of k.
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• Well, we can have k number of processors naturally we will be getting k times speed up.
ita
• By very nominal increase in cost we are achieving close to k speed up.
ig
• In the present context we are talking about instruction execution, but pipelining can be used
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very effectively in other domains of processing also, during arithmetic operations, during
BB
memory access of a vector of data, etc.
• But in the present context, since instruction execution is the only thing we are concerned
about, we shall not be going to too much detail about the other ones.
18
Pipelining
• If we want to wash some cloths.
• Suppose I have built a machine M that
can do three things one by one, wash,
dry and iron.
• I give the machine a cloth, it will wash
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it, dry it, iron it, and output that cloth in
the ironed form.
ig
• Let me assume that the total time
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required for the whole thing is T.
BB
• I have my machine that does washing, drying and ironing, the total time taken is T. So, if I have a N
number of clothes, then the total time required will be N x T.
• Now let us assume that instead of a single very complex machine that can do everything, let me
divide this machine into three smaller pieces.
• Three simple machines one which can only wash, one can only dry, and one can only iron. 19
• Let us make another assumption; the total time early was T, let us say for each of these time is
T/3, T/3 and T/3, so that the total time still remains T.
• We shall be seeing in the next slide that for processing N number of clothes the total time
required will be only (2 + N) T / 3. If N is very large, then this 2 can be neglected, and you can
approximate it to NT/3.
• So, I have got a 3 time speed up, but I have not paid 3 times more, I am using simpler
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machines. This is the concept of pipeline.
• The first cloth comes for washing, this will
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be taking T/3 time. After it is finished with
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washing, this cloth can go for drying.
BB
• And when cloth-1 has come for drying,
machine W is free again.
• W can start with cloth-2.
• Next step, cloth-1 is coming for ironing,
cloth-2 is coming for drying, cloth-3 for
20
washing and so on.
Pipelining
• So, you see after all the machines are
all filled up, every T/3 time one cloth
will be coming out.
• Earlier one cloth was coming out every
time T.
• So, I am getting a 3 times speed up
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effectively. This is the essential idea
behind pipelining.
ig
• Extending the concept to processor
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pipeline, we want to increase the speed
of a processor now.
BB
• Suppose, I have a CPU and I want to make it k times faster. I have two alternatives.
• I can buy k copies of this CPU, and run k instructions in parallel.
• Alternatively, I can divide the execution into k-stages of pipeline.
• The instructions will be executing in a pipeline fashion just like that washing, drying, ironing.
• There also you can expect a k times speedup.
21
• In alternative 1 the cost will also go up k time, because you have to buy k copies of this CPU.
Pipelining
• Alternative 2 is to split the computation into k-stages; here you are not multiplying the hardware
by k, rather the you are splitting it into k pieces resulting in very nominal increase in cost.
• But in order do this, you need some buffering. Take the earlier example of clothes.
• When the first cloth washing is finished, you want to give it for drying.
l
• You must keep it somewhere in between, so that you can accept the next cloth for washing.
ita
• There must be a buffer or a tray between the machines, these are something called buffering
ig
requirements.
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• For a instruction pipeline also we need some registers or latches in between the stages, which
BB
will be temporary storing the result of the previous stage, which will be used by the next stage
for processing.
• If you do not use this registers, then the previous stage can go and modify this value, so the next
stage might carry out some wrong computation because of that.
22
Pipelining
• A k-stage pipeline in general looks like this.
• There are k numbers of stages S1, S2 up to Sk with
a latch or register in between every pair of stages.
• Whenever a stage completes its calculation, it will
store the data into this latch, and it will take the
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data from the next competition into its input latch.
ig
• If this latch was not there, then while the next
calculation is going on this input will go on
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changing.
BB
• Let us carry out a quick calculation of the speedup and efficiency of a pipeline in the general sense.
• Earlier we showed the calculation for the washing example.
• Let us say tau is the clock period of the pipeline, which means, every tau time data moves from
one stage to the other.
• And ti is the time delay for the circuit that is there in stage Si. And the latches delay will be dL.
23
Pipelining
• What will be the maximum stage delay, see this is t1,
this is t2, this is t3. So, the slowest stage in the
pipeline will determine what is the maximum speed
with which we can shift the data, because this
slowest stage will be become the bottleneck.
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• So, maxt{ti}, let us call it taum, is the maximum delay.
And to it we have to also add the latch delay dL. So,
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taum + dL will be your clock period tau.
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• Now, the pipeline frequency will be 1 / tau.
BB
• f will also be the maximum throughput of the
pipeline if you are expecting one result to come out
every clock.
• With this assumption let us try to make a quick calculation.
24
Pipelining
• We calculate the total time to process N sets of
data. tau is my clock period.
• Now, k – 1 clocks are required to fill up the
pipeline.
• There are k-stages, so I need k - 1 clocks to reach
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a stage where all the k-stages are working on
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something.
• After that every tau time there will be one new
ig
result being generated.
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• So, (k – 1) x tau will be the initial time for the pipe to fill up, and then this N x tau for the outputs
BB
to be generated. This will be the total time to process N data sets.
• Now, if we have an equivalent non-pipelined processor, if you ignore the latch delays for the time
being, then the total time can be estimated as N x k x tau.
• So, in a pipeline the speedup Sk we are getting is this.
• As N becomes very large this Sk approaches k. So, for a large number of data that you are
processing the pipeline, your speedup will be close to number of stages k. This is an important
25
result.
Pipelining
• Now, there is another term we define called pipeline efficiency;
how much is the performance close to the ideal value.
• Well, this Sk we just calculated will tend to k, so that is when the
pipeline is operated at maximum efficiency.
l
• If I divided by that, k, k can cancels out, so I get a factor.
ita
• This I can define as the actual pipeline efficiency. So, it will
ig
never be 100%, maybe it is working in 90% efficiency.
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• And another term which is of course is not that important in the present context is called
BB
pipeline throughput; the number of operations completed per unit time.
• Total number of operation is N. And the time taken is Tk.
• If you divide it, you get an expression, this is pipeline throughput.
• This is a very typical plot I am showing, number of task N versus speedup for various values of k.
• Let us say k = 4; you see as the number of tasks increases, the speedup increases increase and
levels to very close to 4. For k = 8, it levels to very close to 8; and so on. 26
Pipelining
l
ita
ig
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BB
• Now, coming to ARM I am not going into the details because this is not a course where I am
teaching computer architecture rather I am trying to tell you that ARM uses instruction
pipelining.
• If I have a k-stage pipeline, I can expect to have k times speedup.
• In ARM7 architecture this is one particular processor TDMI.
• There are three stages, fetch, decode and execute. 27
Pipelining
• If everything else is fine, we are expected to get about 3 times speedup in terms of instruction
execution.
• Similarly ARM9 has a 5 stage pipeline, fetch, decode, execute, memory, write.
• Within the decode, the register values are also read whatever registers are required.
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• During execute the barrel shifter is also working, ALU operations also carried out, memory
ita
access are carried out here; during write, the results written back into the register bank, so it
ig
is done here.
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• And for ARM7 all of these were done during execute.
• The register read, shift, ALU, register write everything was done in execute. But in ARM 9, you
BB
are making the pipeline more elaborate and more flexible.
• So, here the speedup can be maximum 5.
28
Pipelining
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ig
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BB
29
Pipelining
• Just one thing I want to mention here is that this speedup of k that I am talking about is an ideal
speed up.
• It is the speedup you can get when the pipeline is operating in its full speed, but sometimes due
to some reason, you cannot operate the pipeline at full speed.
• In those cases, the speedup will become less than k. I am giving one example.
l
• Suppose, there are some instructions that are executed and let us say these are all ADD
ita
instructions, and there is one complex multi register store instruction.
ig
• So, it will need multiple clock cycles.
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• The idea is that normally everything finishes in one clock.
• But for STR instruction what might happen that this pink colored box can actually require
multiple cycles.
BB
• Multiple cycle means here you cannot decode this next instruction, unless this execute is over
you cannot decode it.
• So, there will be some delay here because it is requiring multiple cycles.
• Such delays are referred to as stalls; we call them stall cycles.
30
Pipelining
• Stall cycle means some cycles are wasted.
• You see here first instruction is finished;
second instruction was finished here,
third instruction here, fourth instruction
here.
• But because of this delay this instruction
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was supposed to finish here, but it got
delayed.
ig
• Not only this, all subsequent instructions got delayed and there can be many such instructions
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like this in between. So, for every such instruction there will be some stall cycle inserted.
• And once a stall is there this stall will be carried by all subsequent instructions until that
BB
instruction exits the pipe. Such cases can slow down the maximum operational speed of a
pipeline.
• There are something called pipeline hazards.
• There can be data dependency whether you can feed the next instruction or not.
• There are a lot of architectural issues that can prevent the pipeline from operating at its
maximum speed. 31
Pipelining
• Stall instructions can occur due to this, one
example I gave because of a complex
instructions, but there can be other reasons.
• There are situations called data hazards, there
can be structural hazards, there can be control
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hazards. Because of various sequence of
operations that are being carried out, and some
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instructions like jumps and branches you may
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have to insert stall cycles.
BB
• All of these prevent the pipeline from operating at the maximum clock frequency.
• Just another thing let me tell you, in this ARM7 kind of architecture a 3-stage pipeline is there.
Let us say when an instruction reaches the execute phase, one thing you remember I told you all
instructions are 32-bit instructions. And your memory is byte addressable.
• So, if the first instruction is stored in memory location 100 the next instruction will be stored in
memory location 104, next location will be stored in location 108, because each instruction will
32
be requiring 4 bytes.
Pipelining
• The point is that when some instruction is executed the PC will always be 8 bytes ahead.
• You add 4 to it because you will be fetching this. Each instruction will be adding 4 to the
memory address. And PC is a special register which always stores the address of the next
instruction to be fetched.
• When you are fetching this instruction, this will be the PC of the current instruction plus 8,
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because current instruction is here.
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• If we add 4 to it, we will be getting the next instruction; if we add 8 to it, we will be the next to
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next instruction.
• Here you are always fetching the next to next instruction because there are three stages that is
BB
why the PC is always 8 bytes ahead.
• Because when you are executing here already incremented PC two times it is always 8 bytes
ahead, so that when you are fetching you should accordingly adjust and fetch accordingly.
33
ARM Registers
• There are some special registers, we shall be trying to tell you the necessity and roles of these
special register; something about exception handling and there is something called thumb
mode of execution also very briefly about that.
• Again we shall not be going into very much detail of this because this course is primarily meant
for a hands on demonstration for designing various systems, but learning some basic concepts
l
on the architectural issues will always help you in becoming a better designer.
ita
• This is the main purpose of trying to give you with some of the initial backgrounds of
embedded system design in the architectural concepts.
ig
• Let us start with the processor modes.
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• The ARM processor during execution at a given time, can be in one of 7 modes. This table
BB
summarizes these 7 processor modes.
• The user mode is the normal mode during execution of a program.
• When a program is executed normally, we say that the system is in user mode.
34
ARM Registers
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BB
35
ARM Registers
• This user mode acronym is usr. Now you know in processors, we can have interrupts coming
from external devices. If it comes, the program that is executing will be suspended, we will have
to go to some interrupt handling routine, run that routine and then again come back and resume
the interrupted program.
• In ARM two different levels of interrupt processing are permissible or allowed, one is called high
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priority or other is called normal priority.
• This FIQ is the high priority mode. The FIQ mode is entered when a high priority interrupt is
ig
activated and is acknowledged.
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• The point to note is that when a high priority interrupt is being processed, if some lower priority
BB
interrupt comes in the meantime; they will not be acknowledged, they will be ignored.
• So, higher priority interrupt will be having real higher priority over the lower priority ones.
• And IRQ is the low priority or the normal priority interrupts.
• There is a supervisory mode which most of the modern processors have, there are some
instructions like supervisory call or trap or SWI software interrupt.
36
ARM Registers
• There are various names, but the purpose of this instructions is that, these instructions allow
to transfer control to the operating system.
• Well in a computer where there is an operating system, these instructions allow the processor
mode to be changed from user mode to supervisor mode and then just like a subroutine call
control will jump to the supervisor or the operating system.
• Now, the supervisory mode is svc.
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• This is a protected mode and this mode is required only when there is an operating system in
your implementation.
ig
• In all embedded system application you will not require this, but in system where there is
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really an operating system and you need some protection you need to have this mode of
execution.
BB
• And abort is an optional mode for cases where you want to have memory protection.
• You want to see that when a program is executing, you are supposed to access only this region
of memory.
• If accidentally your program tries to access any memory location beyond the permissible
limits, this abort interrupt will be generated and the corresponding processor mode is called
the abort mode; for handling memory access violations the processor goes to the abort mode.37
ARM Registers
• 31 general-purpose 32-bit registers
• 16 visible, R0 – R15
• Others speed up the exception process
• Special roles:
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– Hardware
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 R14 – Link Register (LR): optionally holds return address for branch instructions
ig
 R15 – Program Counter (PC)
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– Software
 R13 - Stack Pointer (SP)
BB
38
ARM Registers
System & User FIQ Supervisor Abort IRQ Undefined

R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
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R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
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R6 R6 R6 R6 R6 R6
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R7 R7_fiq R7 R7 R7 R7
BB
R10 R10_fiq R10 R10 R10 R10
R11 R11_fiq R11 R11 R11 R11
R12 R12_fiq R12 R12 R12 R12
R13 R13_fiq R13_svc R13_abt R13_irq R13_und
R14 R14_fiq R14_svc R14_abt R14_irq R14_und
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und 39
ARM’s visible registers
• User level r0
usable in user mode
r1
– 15 GPRs, PC, CPSR r2
r3 system modes only
(current program r4
r5
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status register)
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r6
• Remaining registers are r7 r8_fiq
r8
used for system-level r9 r9_fiq
ig
r10 r10_fiq
programming and for r11 r11_fiq
r13_und
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r12 r12_fiq r13_abt r13_irq
handling exceptions r13 r13_fiq r13_svc
r14_abt r14_irq r14_und
r14_fiq r14_svc
r14
BB
r15 (PC)
SPSR_abt SPSR_irq SPSR_und

CPSR SPSR_fiq SPSR_svc
fiq svc abort irq undefi ned

user mode mode mode mode mode mode
40
ARM Registers
• Current Program Status Register (CPSR)
• Saved Program Status Register (SPSR)
• On exception, entering mod mode:
– (PC + 4)  LR
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– CPSR  SPSR_mod
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– PC  IV address
ig
– R13, R14 replaced by R13_mod, R14_mod
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– In case of FIQ mode R7 – R12 also replaced
BB
41
ARM CPSR format
• N (Negative), Z (Zero), C (Carry), V (oVerflow)
• mode – control processor mode
• T – control instruction set
– T = 1 – instruction stream is 16-bit Thumb instructions
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– T = 0 – instruction stream is 32-bit ARM instructions
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• I F – interrupt enables
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31 28 27 8 7 6 5 4 0
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NZCV unused IF T mode
BB
42
ARM memory organization
• Linear array of bytes numbered from 0 to
bit 31 bit 0
232 – 1
23 22 21 20
• Data items
19 18 17 16
– bytes (8 bits) word16
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15 14 13 12
– half-words (16 bits) – always aligned
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hal f-word14 hal f-word12
to 2-byte boundaries (start at an even 11 10 9 8
byte address) word8
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7 6 5 4
– words (32 bits) – always aligned to 4- byte6 hal f-word4
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3 2 1 0
byte
byte boundaries (start at a byte byte3 byte2 byte1 byte0 address
BB
address which is multiple of 4)
43
References
1. www.arm.com
2. ARM Limited ARM Architecture Reference Manual, Addison Wesley, June 2000
3. Trevor Martin The Insiders Guide To The Philips ARM7-Based Microcontrollers, Hitex (UK) Ltd.,
February 2005
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4. Steve Furber ARM System-On-Chip Architecture (2nd edition), Addison Wesley, March 2000.
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5. NPTEL Lectures.
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BB
44
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Thank you
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BB
45
ARM Processor Programming
(Embedded System)
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Dr. Basudeba Behera
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Assistant Professor
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ARM instruction set
• Discussion on the ARM instruction set.
• There program writing in a high level
language, but here we will discuss
about the low level features of the
ARM processor, and for that we need
to have a basic idea about the
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assembly language features that ARM
architecture provides.
ig
• various categories of ARM instructions
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and in particular the data processing
instructions that are provided by the
BB
ARM instruction set architecture.
• About the ARM instruction set, a developer need to develop or design an embedded system,
hardware platform is available, a microcontroller based system and you have to write software
for it.
ARM instruction set
• Today most of us develop the software in some high level language, either in C or in Python or in
Java, but it is always good to know the lower level features of the processor in order to have an
informed decision that which processor may be better for a particular application.
• With this motivation we are giving you a brief introduction to the assembly language features of
the ARM processor that is a reflection of the hardware features that are provided by the ARM
l
platform.
ita
• Broadly speaking any instruction set can be categorized into various groups or broad categories.
ig
• In ARM let us define these categories as data processing, data transfer and control flow. Most of
the modern microcontrollers are based on the Harvard architecture, where you will be having a
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separate program memory and a separate data memory.
BB
• The instructions that constitute the program will be stored in the program memory, while all
temporary data that will be stored in the data memory.
• Among the registers this PC is one register which will be pointing to the address of the next
instruction in the program memory.
• Whenever a new instruction is brought or fetched from memory it will be fetched from the
address which is stored in the PC.
ARM instruction set
• When talking about the data processing instructions, its about carrying out various arithmetic
and logic operations on data.
• Now, ARM is based on the RISC philosophy of architectures, most of the ARM features are RISC
based.
• Here all data processing instructions operate only on registers; that means, when I say add we
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will be adding the contents of two registers and storing the result back into another register.
ita
• So, memory is not coming into the picture here at all.
ig
• When talk about data transfer there are options.
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• We can transfer from one register to another or we can transfer from register to data memory
or data memory to register.
BB
• These options are all there, and these will constitute data transfer instructions. And, control
flow instructions are those that will alter the sequence of execution of a program.
• Normally as I said PC will be pointing to the next instruction to be executed, as the instructions
are executing the value of the PC gets incremented.
ARM instruction set
• But, whenever you have some
instructions like jump or a subroutine
call, suddenly that sequence will be
disturbed, and you will be going to some
other address and from there you will be
starting to fetch your instructions.
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• This is what is meant by change of
control flow, and such instructions are
ig
termed as control flow instructions.
-D
• Essentially control flow instructions are
those that will be altering the value of PC
BB
in some way so that the normal
sequence of instruction execution will be
altered.
ARM instruction set
• Load-store architecture
– operands are in GPRs
– load/store – only instructions that operate with memory
• Instructions
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– Data Processing – use and change only register values
– Data Transfer – copy memory values into registers (load) or copy register values
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into memory (store)
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– Control Flow
BB
• branch
• branch-and-link – save return address to resume the original sequence
• trapping into system code – supervisor calls
6
ARM instruction set
• Three-address data processing instructions
• Conditional execution of every instruction
• Powerful load/store multiple register instructions
• Ability to perform a general shift operation and a general ALU operation in a single
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instruction that executes in a single clock cycle
ita
• Open instruction set extension through coprocessor instruction set, including adding new
ig
registers and data types to the programmer’s model
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• Very dense 16-bit compressed representation of the instruction set in the Thumb
architecture
BB
7
I/O system
• I/O is memory mapped
– internal registers of peripherals (disk controllers, network interfaces, etc) are
addressable locations within the ARM’s memory map and may be read and written
using the load-store instructions
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• Peripherals may use either the normal interrupt (IRQ) or fast interrupt (FIQ) input
ita
– normally most interrupt sources share the IRQ input, while just one or two time-
critical sources are connected to the FIQ input
ig
• Some systems may include external DMA hardware to handle high-bandwidth I/O traffic
-D
BB
8
ARM Exceptions
• ARM supports a range of interrupts, traps, and supervisor calls – all are grouped under
the general heading of exceptions
• Handling exceptions
– current state is saved by copying the PC into r14_exc and CPSR into SPSR_exc (exc
stands for exception type)
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– processor operating mode is changed to the appropriate exception mode
– PC is forced to a value between 0016 and 1C16, the particular value depending on the
ig
type of exception
-D
– instruction at the location PC is forced to (the vector address) usually contains a
BB
branch to the exception handler; the exception handler will use r13_exc, which is
normally initialized to point to a dedicated stack in memory, to save some user
registers
– return: restore the user registers and then restore PC and CPSR atomically
9
ARM cross-development toolkit
• Software development C source C libraries asm source
– tools developed by ARM Limited
– public domain tools (ARM back end C compiler as sembler
for gcc C compiler) .aof
l
• Cross-development object
ita
libraries
linker
– tools run on different architecture
from one for which they produce .axf debug
ig
code
-D
ARMsd
system model
BB ARMulator development
board
10
Pipeline Organization
• Increases speed –
most instructions executed in single cycle
• Versions:
– 3-stage (ARM7TDMI and earlier)
l
– 5-stage (ARMS, ARM9TDMI)
ita
– 6-stage (ARM10TDMI)
ig
• 3-stage pipeline: Fetch – Decode - Execute
-D
• Three-cycle latency, one instruction per cycle throughput
I
BB
n
s i Fetch Decode Execute
t
r
u i+1 Fetch Decode Execute
c
t i+2 Fetch Decode Execute
i cycle
o
n 11
t t+1 t+2 t+3 t+4
Pipeline Organization
• 5-stage pipeline: • Stages:
– Reduces work per cycle =>
allows higher clock frequency
Fetch
– Separates data and instruction memory =>
l
reduction of CPI (average number of clock
ita
Decode
Cycles Per Instruction)
ig
• Pipeline flushed and refilled on branch, causing Execute
execution to slow down
-D
• Special features in instruction set eliminate small Buffer/data
pipeline BB
jumps in code to obtain the best flow through
Write-back
12
Operating Modes
• Seven operating modes:
– User
– Privileged:
l
• System (version 4 and above)
ita
• FIQ
ig
• IRQ
-D
• Abort exception modes
• Undefined
• Supervisor
BB
13
Operating Modes
User Mode: Exception Modes:

– Normal program execution mode – Entered upon exception
– System resources unavailable – Full access to system resources
l
ita
– Mode changed by exception only – Mode changed freely
ig
-D
BB
14
Exceptions
Exception Mode Priority IV Address

Reset Supervisor 1 0x00000000
Undefined instruction Undefined 6 0x00000004
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ita
Software interrupt Supervisor 6 0x00000008
ig
Prefetch Abort Abort 5 0x0000000C
-D
Data Abort Abort 2 0x00000010
BB
Interrupt IRQ 4 0x00000018
Fast interrupt FIQ 3 0x0000001C
Table 1 - Exception types, sorted by Interrupt Vector addresses
15
ARM instruction set
• Two Instruction Sets:
– ARM
• Standard 32-bit instruction set
– THUMB
l
ita
• 16-bit compressed form
• Code density better than most CISC
ig
• Dynamic decompression in pipeline
-D
BB
16
ARM instruction set
• Data Processing Instructions
• Data Transfer Instructions
• Control flow Instructions
l
ita
• Features:
– Load/Store architecture
ig
– 3-address data processing instructions
-D
– Conditional execution
BB
– Load/Store multiple registers
– Shift & ALU operation in single clock cycle
17
ARM instruction set
• Conditional execution:
– Each data processing instruction prefixed by condition code
– Result – smooth flow of instructions through pipeline
l
ita
– 16 condition codes:
ig
EQ equal MI negative HI unsigned higher GT signed greater than
-D
unsigned lower or signed less than or
BB
NE not equal PL positive or zero LS LE
same equal
unsigned higher or signed greater than

CS VS overflow GE AL always
same or equal
CC unsigned lower VC no overflow LT signed less than NV special purpose
18
ARM instruction set
ARM instruction set
Data processing
l
ita
instructions
Data transfer
instructions
ig
Block transfer
instructions
-D
Branching instructions
BB
Multiply instructions
Software interrupt
instructions
19
Data Processing Instructions
• Arithmetic and logical operations
• 3-address format:
– Two 32-bit operands (op1 is register, op2 is register or immediate)
– 32-bit result placed in a register
l
• Barrel shifter for op2 allows full 32-bit shift within instruction cycle
ita
• Arithmetic operations:
ig
– ADD, ADDC, SUB, SUBC, RSB, RSC
-D
• Bit-wise logical operations:
•
– AND, EOR, ORR, BIC
Register movement operations: BB
– MOV, MVN
• Comparison operations:
– TST, TEQ, CMP, CMN 20
if (z==1) R1=R2+(R3*4)
compiles to
EQADDS R1,R2,R3, LSL #2
( SINGLE INSTRUCTION ! )
l
ita
ig
-D
BB
21
• Classes of data processing instructions
– Arithmetic operations
– Bit-wise logical operations
– Register-movement operations
l
– Comparison operations
ita
• Operands: 32-bits wide; there are 3 ways to specify operands
ig
– come from registers
-D
– the second operand may be a constant (immediate)
– shifted register operand
•
BB
Result: 32-bits wide, placed in a register
– long multiply produces a 64-bit result
22
Arithmetic Operations Register Movement

ADD r0, r1, r2 r0 := r1 + r2 MOV r0, r2 r0 := r2
ADC r0, r1, r2 r0 := r1 + r2 + C MVN r0, r2 r0 := not r2
l
SUB r0, r1, r2 r0 := r1 - r2
ita
SBC r0, r1, r2 r0 := r1 - r2 + C - 1
ig
RSB r0, r1, r2 r0 := r2 – r1
-D
RSC r0, r1, r2 r0 := r2 – r1 + C - 1
BB
Bit-wise Logical Operations Comparison Operations
AND r0, r1, r2 r0 := r1 and r2 CMP r1, r2 set cc on r1 - r2
ORR r0, r1, r2 r0 := r1 or r2 CMN r1, r2 set cc on r1 + r2
EOR r0, r1, r2 r0 := r1 xor r2 TST r1, r2 set cc on r1 and r2
BIC r0, r1, r2 r0 := r1 and (not) r2 TEQ r1, r2 set cc on r1 xor r2
23
• Immediate operands:
Immediate = (0->255) x 22n, 0 <= n <= 12
ADD r3, r3, #3 r3 := r3 + 3
AND r8, r7, #&ff r8 := r7[7:0], & for hex
l
ita
• Shifted register operands
ig
The second operand is subject to a shift operation before it is combined with the
first operand
-D
ADD r3, r2, r1, LSL #3 r3 := r2 + 8 x r1
ADD r5, r5, r3, LSL r2
BB r5 := r5 + 2r2 x r3
24
ARM Shift Operations
31 0 31 0
• LSL – Logical Shift Left

• LSR – Logical Shift Right
00000 00000
• ASR – Arithmetic Shift Right
l
LSL #5 LSR #5
ita
• ROR – Rotate Right 31 0 31 0
0 1
• RRX – Rotate Right Extended by 1 place
ig
-D
00000 0 11111 1
ASR #5 , positive operand ASR #5 , negative operand
BB
31 0 31 0
C
C C
ROR #5 RRX
25
Setting The Condition Codes
• Any DPI can set the condition codes (N, Z, V, and C)
– for all DPIs except the comparison operations a specific request must be made
– at the assembly language level this request is indicated by adding an ‘S’ to the opcode
– Example (r3-r2 := r1-r0 + r3-r2)
l
ita
ADDS r2, r2, r0 ; carry out to C
ADC r3, r3, r1 ; ... add into high word
ig
-D
• Arithmetic operations set all the flags (N, Z, C, and V)
• Logical and move operations set N and Z
BB
– preserve V and either preserve C when there is no shift operation, or set C according to
shift operation (fall off bit)
26
Multiply Instructions
• Integer multiplication (32-bit result)
• Long integer multiplication (64-bit result)
• Built in Multiply Accumulate Unit (MAC)
• Multiply and accumulate instructions add product to running total
l
• Instructions:
ita
MUL Multiply 32-bit result
ig
MULA Multiply accumulate 32-bit result
-D
UMULL Unsigned multiply 64-bit result
BB
UMLAL Unsigned multiply accumulate 64-bit result
SMULL Signed multiply 64-bit result
SMLAL Signed multiply accumulate 64-bit result
27
Multiply Instructions
• Example (Multiply, Multiply-Accumulate)
MUL r4, r3, r2 r4 := [r3 x r2]<31:0>
MLA r4, r3, r2, r1 r4 := [r3 x r2 + r1] <31:0>
• Note
l
ita
– least significant 32-bits are placed in the result register, the rest are ignored
– immediate second operand is not supported
ig
– result register must not be the same as the first source register
-D
– if `S` bit is set the V is preserved and the C is rendered meaningless
BB
• Example (r0 = r0 x 35)
– ADD r0, r0, r0, LSL #2 ; r0’ = r0 x 5
RSB r3, r3, r1 ; r0’’ = 7 x r0’
28
• Single register load and store instructions
– transfer of a data item (byte, half-word, word) between ARM registers and memory
• Multiple register load and store instructions
– enable transfer of large quantities of data
– used for procedure entry and exit, to save/restore workspace registers, to copy blocks
l
ita
of data around memory
• Single register swap instructions
ig
– allow exchange between a register and memory in one instruction
-D
– used to implement semaphores to ensure mutual exclusion on accesses to shared data
BB
in multi
29
• Load/store instructions
• Used to move signed and unsigned Word, Half Word and Byte to and from registers
• Can be used to load PC (if target address is beyond branch instruction range)
l
ita
LDR Load Word STR Store Word
ig
LDRH Load Half Word STRH Store Half Word
-D
LDRSH Load Signed Half Word STRSH Store Signed Half Word
BB
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte STRSB Store Signed Byte
30
Block Transfer Instructions
• Load/Store Multiple instructions (LDM/STM) Mi
• Whole register bank or a subset copied to memory or LDM Mi+1
restored with single instruction R0 Mi+2
R1
l
R0
ita
R2
R1 Mi+14
ig
R2 Mi+15
R14
-D
STM
R15
R7
R8
BB 

Exchanges a word between registers
Two cycles but single atomic action
R15  Support for RT semaphores
31
Modifying the Status Registers
• Only indirectly
R0
• MSR moves contents from CPSR/SPSR to
R1
selected GPR
• MRS moves contents from selected GPR to MRS
l
CPSR/SPSR
ita
R7
• Only in privileged modes MSR R8
CPSR
ig
SPSR
-D
R14
BB
R15
32
Register-indirect addressing
Single register load and store LDR r0, [r1] r0 := mem32[r1]

STR r0, [r1] mem32[r1] := r0
l
Note: r1 keeps a word address (2 LSBs are 0)
ita
Base+offset addressing
(offset of up to 4Kbytes) LDRB r0, [r1] r0 := mem8[r1]
ig
LDR r0, [r1, #4] r0 := mem32[r1 +4] Note: no restrictions for r1
-D
Auto-indexing addressing
BB
LDR r0, [r1, #4]! r0 := mem32[r1 + 4]
r1 := r1 + 4
Post-indexed addressing
LDR r0, [r1], #4 r0 := mem32[r1]
r1 := r1 + 4
33
COPY: ADR r1, TABLE1 ; r1 points to TABLE1
ADR r2, TABLE2 ; r2 points to TABLE2
LOOP: LDR r0, [r1]
STR r0, [r2]
ADD r1, r1, #4
l
ita
ADD r2, r2, #4
...
ig
TABLE1: ...
-D
TABLE2:...
BB
COPY: ADR r1, TABLE1 ; r1 points to TABLE1
ADR r2, TABLE2 ; r2 points to TABLE2
LOOP: LDR r0, [r1], #4
STR r0, [r2], #4
...
TABLE1: ...
TABLE2:...
34
Multiple register data transfers
LDMIA r1, {r0, r2, r5} r0 := mem32[r1]

r2 := mem32[r1 + 4]
r5 := mem32[r1 + 8]
l
Note: any subset (or all) of the registers may be
ita
transferred with a single instruction
• Block copy view
ig
Note: the order of registers within the list is insignificant
– data is to be stored above or below the
-D
Note: including r15 in the list will cause a change in the the address held in the base register
control flow – address incrementing or decrementing
BB
begins before or after storing the first
 Stack organizations
value
 FA – full ascending
 EA – empty ascending
 FD – full descending
 ED – empty descending
35
Multiple register transfer addressing modes
r9’ 101816 r9’ r5 101816

r5 r1
r1 r0
r9 r0 100c 16 r9 100c 16
l
ita
100016 100016
ig
STMIA r9!, {r0,r1,r5} STMIB r9!, {r0,r1,r5}
-D
101816 101816
r9 BB
r5
r1
r0
100c 16 r9
r5
r1
100c 16
r9’ 100016 r9’ r0 100016
STMDA r9!, {r0,r1,r5} STMDB r9!, {r0,r1,r5}
36
The mapping between the stack and block copy views
As c e n di n g De s c e n di n g
l
Ful l Emp t y Ful l Emp t y
ita
B e f o re STMIB LDMIB
In c re me n t STMFA LDMED
ig
Af t e r STMIA LDMIA
STMEA LDMFD
-D
B e f o re LDMDB STMDB
De c re me n t LDMEA STMFD
BB
Af t e r LDMDA STMDA
LDMFA STMED
37
Control Flow Instructions
Branch Interpretation Normal uses
B Unconditional Always take this branch
BAL Always Always take this branch
BEQ Equal Comparison equal or zero result
BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
l
ita
BCC Carry clear Arithmetic operation did not give carry-out
BLO Lower Unsigned comparison gave lower
ig
BCS Carry set Arithmetic operation gave carry-out
BHS Higher or same Unsigned comparison gave higher or same
-D
BVC Overflow clear Signed integer operation; no overflow occurred
BVS Overflow set Signed integer operation; overflow occurred
BB
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same
38
Conditional execution
• Conditional execution to avoid branch instructions used to skip a small number of non-
branch instructions
• Example
CMP r0, #5 ;
l
BEQ BYPASS ; if (r0!=5) {
ita
ADD r1, r1, r0 ; r1:=r1+r0-r2
SUB r1, r1, r2 ; }
ig
BYPASS: ...
-D
With conditional execution
; if ((a==b) && (c==d)) e++;
BB
CMP r0, #5 ;
CMP r0, r1
ADDNE r1, r1, r0 ;
CMPEQ r2, r3
SUBNE r1, r1, r2 ;
ADDEQ r4, r4, #1
...
Note: add 2 –letter condition after the 3-letter opcode
39
Branch and link instructions
• Branch to subroutine (r14 serves as a link register)
BL SUBR ; branch to SUBR
.. ; return here
l
SUBR: .. ; SUBR entry point
ita
MOV pc, r14 ; return
ig
BL SUB1
• Nested subroutines ..
-D
SUB1: ; save work and link register
STMFD r13!, {r0-r2,r14}
BB
BL SUB2
..
LDMFD r13!, {r0-r2,pc}
SUB2: ..
MOV pc, r14 ; copy r14 into r15
40
Supervisor Calls
• Supervisor is a program which operates at a privileged level – it can do things that a
user-level program cannot do directly
– Example: send text to the display
• ARM ISA includes SWI (SoftWare Interrupt)
l
; output r0[7:0]
ita
SWI SWI_WriteC
; return from a user program back to monitor
ig
SWI SWI_Exit
-D
BB
41
Jump Tables
• Call one of a set of subroutines depending on a value computed by the program
BL JTAB
... BL JTAB
JTAB: CMP r0, #0 ...
l
BEQ SUB0 JTAB: ADR r1, SUBTAB
ita
CMP r0, #1 CMP r0, #SUBMAX ; overrun?
BEQ SUB1 LDRLS pc, [r1, r0, LSL #2]
ig
CMP r0, #2 B ERROR
-D
BEQ SUB2 SUBTAB: DCD SUB0
DCD SUB1
BB
Note: slow when the list is long, and all DCD SUB2
subroutines are equally frequent ...
42
Hello ARM World!
AREA HelloW, CODE, READONLY ; declare code area
SWI_WriteC EQU &0 ; output character in r0
SWI_Exit EQU &11 ; finish program
ENTRY ; code entry point
START: ADR r1, TEXT ; r1 <- Hello ARM World!
l
LOOP: LDRB r0, [r1], #1 ; get the next byte
ita
CMP r0, #0 ; check for text end
SWINE SWI_WriteC ; if not end of string, print
ig
BNE LOOP
-D
SWI SWI_Exit ; end of execution
TEXT = “Hello ARM World!”, &0a, &0d, 0
BB
END
43
Software Interrupt
• SWI instruction
– Forces CPU into supervisor mode
l
– Usage: SWI #n
ita
31 28 27 24 23 0
ig
Cond Opcode Ordinal
-D
Maximum 224 calls
BB
Suitable for running privileged code and making OS calls
44
Branching Instructions
• Branch (B): jumps forwards/backwards up to 32 MB
• Branch link (BL): same + saves (PC+4) in LR
• Suitable for function call/return
• Condition codes for conditional branches
l
ita
• Branch exchange (BX) and Branch link exchange (BLX):
• same as B/BL + exchange instruction set (ARM  THUMB)
ig
• Only way to swap sets
-D
BB
45
Thumb Instruction Set
• Compressed form of ARM
– Instructions stored as 16-bit,
– Decompressed into ARM instructions and
– Executed
• Lower performance (ARM 40% faster)
• Higher density (THUMB saves 30% space)
l
ita
• Optimal – “interworking” (combining two sets) – compiler supported
• More traditional:
ig
– No condition codes
-D
– Two-address data processing instructions
• Access to R0 – R8 restricted to
BB
– MOV, ADD, CMP
• PUSH/POP for stack manipulation
– Descending stack (SP hardwired to R13)
• No MSR and MRS, must change to ARM to modify CPSR (change using BX or BLX)
• ARM entered automatically after RESET or entering exception mode
• Maximum 255 SWI calls
46
Summary
• Adoption of ARM technology has increased efficiency and lowered costs
• ARM is the world’s leading architecture today
– 3 billion ARM Powered chips and counting
l
ita
ig
-D
BB
47
References
1. www.arm.com
2. ARM Limited ARM Architecture Reference Manual, Addison Wesley, June 2000
3. Trevor Martin The Insiders Guide To The Philips ARM7-Based Microcontrollers, Hitex (UK) Ltd.,
February 2005
l
4. Steve Furber ARM System-On-Chip Architecture (2nd edition), Addison Wesley, March 2000
ita
ig
-D
BB
48
l
ita
Thank you
ig
-D
BB
49
Hardware Software Co-Design and Program
Modelling
(Embedded System)
l
ita
Dr. Basudeba Behera
ig
Assistant Professor
-D
BB
INTRODUCTION
• In the traditional embedded system development approach,
 the hardware software partitioning is done at an early stage
 and engineers from the software group take care of the software architecture
development and implementation,
l
ita
 whereas engineers from the hardware group are responsible for building the hardware
required for the product.
ig
• There is less interaction between the two teams and the development happens either serially
-D
or in parallel.
• Once the hardware and software are ready, the integration is performed.
•
BB
The increasing competition in the commercial market and need for reduced ‘time-to-market’
the product calls for a novel approach for embedded system design in which the hardware and
software are co-developed instead of independently developing both.
• During the co-design process, the product requirements captured from the customer are
converted into system level needs or processing requirements.
2
INTRODUCTION
• At this point of time it is not segregated as either hardware requirement or software
requirement, instead it is specified as functional requirement.
• The system level processing requirements are then transferred into functions which can be
simulated and verified against performance and functionality.
l
• The Architecture design follows the system design.
ita
• The partition of system level processing requirements into hardware and software takes place
ig
during the architecture design phase.
-D
• Each system level processing requirement is mapped as either hardware and/or software
requirement.
•
• BB
The partitioning is performed based on the hardware-software trade-offs.
The architectural design results in the detailed behavioral description of the hardware
requirement and the definition of the software required for the hardware.
• The processing requirement behavior is usually captured using computational models and
ultimately the models representing the software processing requirements are translated into
firmware implementation using programming languages. 3
FUNDAMENTAL ISSUES IN HARDWARE SOFTWARE CO-DESIGN
• Selecting the model
• Selecting the Architecture
 controller architecture
 datapath architecture
l
ita
 Finite State Machine Datapath (FSMD)
ig
 Complex Instruction Set Computing (CISC)
-D
 Very Long Instruction Word (VLIW)
• Parallel processing architecture
• Selecting the language
BB
• Partitioning System Requirements into hardware and software
4
Selecting the model
• In hardware software co-design, models are used for capturing and describing the system
characteristics.
• A model is a formal system consisting of objects and composition rules.
l
ita
• It is hard to make a decision on which model should be followed in a particular system design.
• Most often designers switch between a variety of models from the requirements specification
ig
to the implementation aspect of the system design.
-D
• The reason being, the objective varies with each phase; for example at the specification stage,
only the functionality of the system is in focus and not the implementation information.
•
BB
When the design moves to the implementation aspect, the information about the system
components is revealed and the designer has to switch to a model capable of capturing the
system’s structure.
5
Selecting the Architecture
• A model only captures the system characteristics and does not provide information on ‘how
the system can be manufactured?’'.
• The architecture specifies how a system is going to implement in terms of the number and
l
types of different components and the interconnection among them.
ita
• Controller architecture, Datapath Architecture, Complex Instruction Set Computing (CISC),
ig
Reduced Instruction Set Computing (RISC), Very Long Instruction Word Computing (VLIW),
Single Instruction Multiple Data (SIMD), Multiple Instruction Multiple Data (MIMD), etc. are
-D
the commonly used architectures in system design.
BB
• Some of them fall into Application Specific Architecture Class (like controller architecture),
while others fall into either general purpose architecture class (CISC, RISC, etc.) or Parallel
processing class (like VLIW, SIMD, MIMD, etc.).
6
• The controller architecture implements the finite state machine model using a state register
and two combinational circuits.
• The state register holds the present state and the combinational circuits implement the logic
for next state and output.
l
• The datapath architecture is best suited for implementing the data flow graph model where
ita
the output is generated as a result of a set of predefined computations on the input data.
ig
• A datapath represents a channel between the input and output and in datapath architecture
the datapath may contain registers, counters, register files, memories and ports along with
-D
high speed arithmetic units.
BB
• Ports connect the datapath to multjple buses.
• Most of the time the arithmetic units are connected in parallel with pipelining support for
bringing high performance
7
• The Finite State Machine Datapath (FSMD) architecture combines the controller
architecture with datapath architecture. It implements a controller with datapath.
• The controller generates the control input whereas the datapath processes the data.
• The datapath contains two types of I/O ports, out of which one acts as the control port for
l
receiving/sending the control signals from/to the controller unit and the second I/O port
ita
interfaces the datapath with' external world for data input and data output.
ig
• Normally the datapath is implemented in a chip and the I/O pins of the chip acts as the data
input output ports for the chip resident data path.
-D
BB
8
• The Complex Instruction Set Computing (CISC) architecture uses an instruction set
representing complex operations.
• It is possible for a CISC instruction set to perform a large complex operation (e.g. Reading a
register value and comparing it with a given value and then transfer the program execution to
a new address location (The CJNE instruction for 8051 ISA)) with a single instruction.
l
ita
• The use of a single complex instruction in place of multiple simple instructions greatly
reduces the program memory access and program memory size requirement.
ig
• However it requires additional silicon for implementing microcode decoder for decoding the
-D
CISC instruction.
BB
• The datapath for the CISC processor is complex. On the other hand, Reduced Instruction Set
Computing (RISC) architecture uses instruction set representing simple operations and it
requires the execution of multiple RISC instructions to perform a complex operation.
• The data path of RISC architecture contains a large register file for storing the operands and
output. RISC instruction set is designed to operate on registers. RISC architecture supports
extensive pipelining.
9
• The Very Long Instruction Word (VLIW) architecture implements multiple functional units
(ALUs, multipliers, etc.) in the datapath.
• The VLIW instruction packages one standard instruction per functional unit of the datapath.
• Parallel processing architecture implements multiple concurrent Processing Elements
l
(PEs) and each processing element may associate a datapath containing register and local
ita
memory.
ig
• Single Instruction Multiple Data (SIMD) and Multiple Instruction Multiple Data (MIMD)
architectures are examples for parallel processing architecture.
-D
• In SIMD architecture, a single instruction is executed in parallel with the help of the
BB
Processing Elements.
10
• The scheduling of the instruction execution and controlling of each PE is performed through a
single controller.
• The SIMD architecture forms the basis of re-configurable processor.
• On the other hand, the processing elements of the MIMD architecture execute different
l
instructions at a given point of time.
ita
• The MIMD architecture forms the basis of multiprocessor systems.
ig
• The PEs in a multiprocessor system communicates through mechanisms like shared memory
-D
and message passing.
BB
11
• Selecting the language A programming language captures a ‘Computational Model’ and
maps it into architecture.
• There is no hard and fast rule to specify this language should be used for capturing this model.
• A model can be captured using multiple programming languages like C, C++, C#, Java, etc. for
l
software implementations and languages like VHDL, System C, Verilog, etc. for hardware
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implementations.
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• On the other hand, a single language can be used for capturing a variety of models. Certain
languages are good in capturing certain computational model.
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• For example, C++ is a good candidate for capturing an object oriented model.
•
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The only pre-requisite in selecting a programming language for capturing a model is that the
language should capture the model easily.
12
• Partitioning System Requirements into hardware and software So far discussed about the
models for capturing the system requirements and the architecture for implementing the
system.
• From an implementation perspective, it may be possible to implement the system
requirements in either hardware or software (firmware).
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• It is a tough decision making task to figure out which one to opt.
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• Various hardware software trade-offs are used for making a decision on the hardware-
software partitioning.
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13
COMPUTATIONAL MODELS IN EMBEDDED DESIGN
The commonly used computational models in embedded system design are as
follow.
 Data Flow Graph (DFG) model,
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 State Machine model,
 Concurrent Process model,
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 Sequential Program model,
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 Object Oriented model, etc.
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14
Data Flow Graph/Diagram (DFG) Model
• The Data Flow Graph (DFG) model translates the data processing requirements into a data
flow graph.
• The Data Flow Graph (DFG) model is a data driven model in which the program execution is
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determined by data.
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• This model emphasizes on the data and operations on the data which transforms the input
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data to output data.
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• Indeed Data Flow Graph (DFG) is a visual model in which the operation on the data (process)
is represented using a block (circle) and data flow is represented using arrows.
•
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An inward arrow to the process (circle) represents input data and an outward arrow from the
process (circle) represents output data in DFG notation.
15
Data Flow Graph/Diagram (DFG) Model
• Embedded applications which are computational
intensive and data driven are modeled using the
DFG model.
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• DSP applications are typical examples for it.
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• Now let’s have a look at the implementation of a
DFG.
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• Suppose one of the functions in our application
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contains the computational requirement x = a + b;
and y = x - c.
•
•
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Figure shows the implementation of a DFG model for implementing these requirements.
In a DFG model, a data path is the data flow path from input to output.
• A DFG model is said to be acyclic DFG (ADFG) if it doesn’t contain multiple values for the input
variable and multiple output values for a given set of input(s).
• Feedback inputs (Output is fed back to Input), events, etc. are examples for non-acyclic inputs.
A DFG model translates the program as a single sequential process execution. 16
Control Data Flow Graph/Diagram (CDFG)
• We have seen that the DFG model is a data driven model in
which the execution is controlled by data and it doesn’t
involve any control operations (conditionals).
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• The Control DFG (CDFG) model is used for modelling
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applications involving conditional program execution.
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• CDFG models contains both data operations and control
operations.
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• The CDFG uses Data Flow Graph (DFG) as element and
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conditional (constructs) as decision makers.
• CDFG contains both data flow nodes and decision nodes,
whereas DFG contains only data flow nodes.
• Let us have a look at the implementation of the CDFG for the following requirement.
• If flag = 1 ,x = a + b\ els ey = a-b;
• This requirement contains a decision making process. 17
Control Data Flow Graph/Diagram (CDFG)
• The control node is represented by a ‘Diamond’ block which is the decision making element
in a normal flow chart based design.
• CDFG translates the requirement, which is modeled to a concurrent process model.
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• The decision on which process is to be executed is determined by the control node.
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• A real world example for modeling the embedded application using CDFG is
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 the capturing and saving of the image to a format set by the user in a digital still camera
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where everything is data driven starting from the Analog Front End which converts the
CCD sensor generated analog signal to Digital Signal and the task which stores the data
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from ADC to a frame buffer for the use of a media processor which performs various
operations like, auto correction, white balance adjusting, etc.
• The decision on, in which format the image is stored (formats like JPEG, TIFF, BMP, etc.) is
controlled by the camera settings, configured by the user.
18
State Machine Model
• The State Machine model is used for modeling reactive or event-driven embedded systems
whose processing behavior are dependent on state transitions.
• Embedded systems used in the control and industrial applications are typical examples for
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event driven systems.
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• The State Machine model describes the system behavior with ‘States’, ‘Events’, ‘Actions’ and
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‘Transitions’.
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• State is a representation of a current situation.
• An event is an input to the state.
•
•
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The event acts as stimuli for state transition.
Transition is the movement from one state to another.
• Action is an activity to be performed by the state machine.
• A Finite State Machine (FSM) model is one in which the number of states are finite.
• In other words the system is described using a finite number of possible states. 19
State Machine Model
• As an example let us consider the design of an
embedded system for driver/ passenger ‘Seat Belt
Warning’ in an automotive using the FSM model.
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• The system requirements are captured as.
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 When the vehicle ignition is turned on and
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the seat belt is not fastened within 10
seconds of ignition ON, the system generates
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an alarm signal for 5 seconds.
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 The Alarm is turned off when the alarm time (5 seconds) expires or if the driver/
passenger fastens the belt or if the ignition switch is turned off, whichever happens
first.
• Here the states are ‘Alarm Off’, ‘Waiting’ and ‘Alarm On’ and the events are ‘Ignition Key ON’,
‘Ignition Key OFF’, ‘Timer Expire’, ‘Alarm Time Expire’ and ‘Seat Belt ON’.
• Using the FSM, the system requirements can be modeled as given in Fig. 7.3. 20
State Machine Model
• The ‘Ignition Key ON’ event triggers the 10 second timer and transitions the state to ‘Waiting’.
If a ‘Seat Belt ON’ or ‘Ignition Key OFF’ event occurs during the wait state, the state
transitions into ‘Alarm Off’.
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• When the wait timer expires in the waiting state, the event ‘Timer Expire’ is generated and it
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transitions the state to ‘Alarm On’ from the ‘Waiting’ state.
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BB
21
State Machine Model
• The ‘Alarm On’ state continues until a ‘Seat Belt ON’ or ‘Ignition Key OFF’ event or ‘Alarm
Time Expire’ event, whichever occurs first.
• The occurrence of any of these events transitions the state to ‘Alarm Off’. The wait state is
implemented using a timer.
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• The timer also has certain set of states and events for state transitions.
• As seen from the FSM, the timer state can be either ‘IDLE’ or ‘READY’ or ‘RUNNING’.
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• During the normal condition when the timer is not running, it is said to be in the ‘IDLE’ state.
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• The timer is said to be in the ‘READY’ state when the timer is loaded with the count
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corresponding to the required time delay.
• The timer remains in the ‘READY’ state until a ‘Start Timer’ event occurs.
• The timer changes its state to ‘RUNNING’ from the ‘READY’ state on receiving a ‘Start Timer’
event and remains in the ‘RUNNING’ state until the timer count expires or a ‘Stop Timer’ even
occurs.
• The timer state changes to ‘IDLE’ from ‘RUNNING’ on receiving a ‘Stop Timer’ or ‘Timer
22
Expire’ event.
Example 1
Design an automatic tea/coffee
vending machine based on
FSM model for the following
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requirement.
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• The tea/coffee vending is
initiated by user inserting a
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5 rupee coin.
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• After inserting the coin, the
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user can either select
‘Coffee’ or ‘Tea’ or press
‘Cancel’ to cancel the order
and take back the coin.
23
• In its simplest representation, it contains four states namely; ‘Wait for coin’ ‘Wait for User
Input’, ‘Dispense Tea’ and ‘Dispense Coffee’.
• The event ‘Insert Coin’ (5 rupee coin insertion), transitions the state to ‘Wait for User Input’.
• The system stays in this state until a user input is received from the buttons ‘Cancel’, ‘Tea’ or
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‘Coffee’ (Tea and Coffee are the drink select button).
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• If the event triggered in ‘Wait State’ is ‘Cancel’ button press, the coin is pushed out and the
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state transitions to ‘Wait for Coin’.
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• If the event received in the ‘Wait State’ is either ‘Tea’ button press, or ‘Coffee’ button press,
the state changes to ‘Dispense Tea’ and ‘Dispense Coffee’ respectively.
•
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Once the coffee/tea vending is over, the respective states transitions back to the ‘Wait for
Coin’ state.
24
• A few modifications like adding a timeout for the ‘Wait State’ (Currently the ‘Wait State’ is
infinite; it can be re-designed to a timeout based ‘Wait State’.
• If no user input is received within the timeout period, the coin is returned back and the state
automatically transitions to ‘Wait for Coin’ on the timeout event) and capturing another
events like, ‘Water not available’, ‘Tea/Coffee Mix not available’ and changing the state to an
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‘Error State’ can be added to enhance this design.
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Example 2
Design a coin operated public telephone unit based on FSM model for the following
requirements.
1. The calling process is initiated by lifting the receiver (off-hook) of the telephone unit
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2. After lifting the phone the user needs to insert a 1 rupee coin to make the call.
3. If the line is busy, the coin is returned on placing the receiver back on the hook (on-hook)
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4. If the line is through, the user is allowed to talk till 60 seconds and at the end of 45th second,
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prompt for inserting another 1 rupee coin for continuing the call is initiated
5. If the user doesn’t insert another 1 rupee coin, the call is terminated on completing the 60
seconds time slot.
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6. The system is ready to accept new call request when the receiver is placed back on the hook
(on-hook)
7. The system goes to the ‘Out of Order’ state when there is a line fault.
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BB
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• The FSM model is a simple representation and it doesn’t take care of scenarios like, user
doesn’t insert a coin within the specified time after lifting the receiver, user inserts coins
other than a one rupee etc.
• Handling these scenarios is left to the readers as exercise.
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• Most of the time state machine model translates the requirements into sequence driven
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program and it is difficult to implement concurrent processing with FSM.
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• This limitation is addressed by the Hierarchical/ Concurrent Finite State Machine model
(HCFSM).
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• The HCFSM is an extension of the FSM for supporting concurrency and hierarchy.
•
BB
HCFSM extends the conventional state diagrams by the AND, OR decomposition of States
together with inter level transitions and a broadcast mechanism for communicating between
concurrent processes.
28
• HCFSM uses statecharts for capturing the states, transitions, events and actions.
• The Harel Stateehart, UML State diagram, etc. are examples for popular statecharts used for
the HCFSM modelling of embedded systems.
• In statecharts, the state is usually represented using geometric shapes like rounded
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rectangle, rectangle, ellipse, circle, etc.
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• The Harel Stateehart uses a rounded rectangle for representing state.
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• Arrows are used for representing the state transition and they are marked with the event
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associated with the state transition.
• Sometimes an optional parenthesized condition is also labeled with the arrow.
•
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The condition specifies on what basis the state transition happens at the occurrence of the
specified event.
• Lots of design tools are available for state machine and statechart based system modelling.
The IAR visualSTATE
29
Sequential Program Model
• In the sequential programming Model, the functions or processing requirements are executed
in sequence.
• It is same as the conventional procedural programming.
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• Here the program instructions are iterated and executed conditionally and the data gets
transformed through a series of operations.
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• FSMs are good choice for sequential program modeling.
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• Another important tool used for modeling sequential program is Flow Charts.
BB
• The FSM approach represents the states, events, transitions and actions, whereas the Flow
Chart models the execution flow.
• The execution of functions in a sequential program model for the ‘Seat Belt Warning’ system
is illustrated below.
30
Sequential Program Model
#define ON 1
#define OFF 0
#define YES 1
#define NO 0
Void seat_belt_warn ()
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{
wait_10sec ();
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if (check_ignition_key()==ON)
{
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if (check_seat_belt () ==OFF )
{
BB
Set_timer (5);
Start_alarm();
While ((check_seat_belt () == OFF) && (check_ignition_key ()
==OFF )&& (timer_expire ()==NO));
Stop_alarm ();
}
}
} 31
Concurrent/Communicating Process Model
• The concurrent or communicating process model models concurrently executing tasks/
processes.
• It is easier to implement certain requirements in concurrent processing model than the
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conventional sequential execution.
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• Sequential execution leads to a single sequential execution of task and thereby leads to poor
ig
processor utilization, when the task involves I/O waiting, sleeping for specified duration etc.
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• If the task is split into multiple subtasks, it is possible to tackle the CPU usage effectively,
when the subtask under execution goes to a wait or sleep mode, by switching the task
BB
execution.
• However, concurrent processing model requires additional overheads in task scheduling,
task synchronization and communication.
• As an example for the concurrent processing model let us examine how we can implement
the ‘Seat Belt Warning’ system in concurrent processing model.
32
Split the tasks into:
1. Timer task for waiting 10 seconds (wait timer task)
2. Task for checking the ignition key status (ignition key status monitoring task)
3. Task for checking the seat belt status (seat belt status monitoring task)
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4. Task for starting and stopping the alarm (alarm control task)
5. Alarm timer task for waiting 5 seconds (alarm timer task)
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BB
33
• We have five tasks here and we cannot execute them randomly or sequentially.
• We need to synchronize their execution through some mechanism.
• We need to start the alarm only after the expiration of the 10 seconds wait timer and that
too only if the seat belt is OFF and the ignition key is ON. Hence the alarm control task is
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executed only when the wait timer is expired and if the ignition key is in the ON state and
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seat belt is in the OFF state.
ig
• Here we will use events to indicate these scenarios.
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• The wait timerexpire event is associated with 1 the timer task event and it will be in the
reset state initially and it is set when the timer expires.
•
BB
Similarly, events ignition on and ignition off are associated with the task ignition key status
monitoring and the events seat belt_on and seat_belt_off are associated with the task seat
belt status morning.
34
• The events ignition j)jf and ignition on are set and reset respectively when the ignition key
status is OFF and reset and set respectively when the ignition key status is ON, by the
ignition key status monitoring task.
• Similarly the events seat_belt_off and seat_belt_on are set and reset respectively when the
seat belt status is OFF and reset and set respectively when the seat belt status is ON, by the
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seat belt status monitoring task.
• The events alarm Timer start and alarm Timer_expire are associated with the alarm timer
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task.
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• The alarm Timer start event will be in the reset state initially and it is set by the alarm
BB
control task when the alarm is started.
• The alarm Timer expire event will be in these F state Initialfy-and4tisj£t when ,the alarm
timer expires.
• The alarm control task waits for the signaling of the event wait Timer expire^ and starts the
alarm timer and alarm if both the events ignition on and seat helt off are in the set state
when the event wait Jimer^expire signals.
35
• If not the alarm control task simply completes its execution and returns.
• In case the alarm is started, the alarm control task waits for the signaling of any one of the
events alarm timer expire or ignition off or seat belt on.
• Upon signaling any one of these events, the alarm is stopped and the alarm control task
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simply completes its execution and returns.
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• It should be noted that the method explained here is just one way of implementing a
ig
concurrent model for the ‘Seat Belt Warning’ system.
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• The intention is just to make the readers familiar with the concept of multi tasking and task
communication/synchronisation.
•
• BB
There may be other ways to model the same requirements.
The concurrent processing model is commonly used for the modeling of ‘Real Time’ systems.
• Various techniques like ‘Shared memory’, ‘Message Passing’, ‘Events’, etc. are used for
communication and synchronizing between concurrently executing processes.
36
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37
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38
Object-Oriented Model
• The object-oriented model is an object based model for modeling system requirements.
• It disseminates a complex software requirement into simple well defined pieces called
objects.
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• Object-oriented model brings re-usability, maintainability and productivity in system
design. In the object-oriented modeling, object is an entity used for representing or
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modeling a particular piece of the system.
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• Each object is characterized by a set of unique behavior and state.
• A class is an abstract description of a set of objects and it can be considered as a ‘blueprint’
•
of an object.
BB
A class represents the state of an object through member variables and object behavior
through member functions.
• The member variables and member functions of a class can be private, public or protected.
• Private member variables and functions are accessible only within the class, whereas public
variables and functions are accessible within the class as well as outside the class. 39
INTRODUCTION TO UNIFIED MODELLING LANGUAGE (UML)
• Unified Modelling Language (UML) is a visual modelling language for Object Oriented
Design (OOD).
• ‘Things’, ‘Relationships’ and ‘Diagrams’ are the fundamental building blocks of UML.
Things
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• A ‘Thing’ is an abstraction of the UML model. The ‘Things’ in UML are classified into:
Structural things: Represents mostly the static parts of a UML model. They are also known as
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‘classifiers’. Class, interface, use case, use case realization (collaboration), active class,
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component and node are the structural things in UML.
Behavioral things: Represents mostly the dynamic parts of a UML model. Interaction, state
BB
machine and activity are the behavioral things in UML.
Grouping things: Are the organizational parts of a UML model. Package and sub-system are the
grouping things in UML.
Annotational things: Are the explanatory parts of a UML model.
Note is the Annotational thing in UML.
40
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41
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42
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43
Relationships: As the name indicates, they express the type of relationship between UML
elements (objects, classes, etc.).
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44
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45
UML Diagrams
• UML Diagrams give a pictorial representation of the static aspects, behavioral
aspects and organization and management of different modules (classes,
packages, etc.) of the system.
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• UML diagrams are grouped into Static Diagrams and Behavioral Diagrams.
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Static Diagrams
ig
• Diagram representing the static (structural) aspects of the system.
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• Class Diagram, Object Diagram, Component Diagram, Package Diagram,
BB
Composite Structure Diagram and Deployment Diagram falls under this
category. T
46
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BB
47
Behavioral Diagrams
These are diagrams representing the dynamic (behavioral) aspects of the system.
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BB
48
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BB
49
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50
The UML Tools
The tools for building UML based models and diagrams are 1 available from different vendors.
Some of them are commercial and some of them are either free or open source. The table
given below gives a summary of the popular UML modeling tools.
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51
HARDWARE SOFTWARE TRADE-OFFS
• Certain system level processing requirements may be possible to develop in either
hardware or software.
• The decision on which one to opt is based on the trade-offs and actual system
requirement.
• For example, if the embedded system under consideration involves some multimedia
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codec! requirement.
• The media codec can be developed in either software, or using dedicated hardware chip
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(like ASIC or ASSP).
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• Here the trade-off is performance and re-configurability.
BB
• A codec developed in hardware may be much more efficient, optimized with low
processing and power requirements.
• It is possible to develop the same codec in software using algorithm.
• But the software implementation need not be optimised for performance, speed and
power efficiency.
52
• On the other hand, a codec developed in software is re-usable and re-configurable.
• With certain modification it can be configured for other codec implementations, whereas a
codec developed in a fixed hardware (like ASIC/ASSP) is fixed and it cannot be changed.
Memory size is another important hardware software trade-off.
• Evaluate how much memory is required if the system requirement under consideration is
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implemented in software (firmware).
• Embedded systems are highly memory constrained and embedded designers don’t have
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the luxury of using extravagant memory for implementing requirements.
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• On the other hand, evaluate the gate count required (Normally hardware chips are
BB
implemented using logic gates and the density of the chip is expressed in terms of the
number of gates used in the design (millions of gates ©)), if the required feature is going to
implement in hardware.
• Effort required in terms of man hours, if the required feature is going to build in either
software or custom hardware implementation using VHDL or any other hardware
description languages and the cost for each are another important hardware-software
trade-off in any embedded system development. 53
To summarise, the important hardware-software trade-offs in embedded system
design are
 Processing speed and performance
 Frequency of change (Re-configurability)
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 Memory size and gate count
 Reliability
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 Man hours (Effort) and cost
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BB
54
REFERENCES
1. Shibu K V, “Introduction to Embedded Systems, Second Edition, Mc Graw Hill
Education, 2017.
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55

EC604 - Embedded Systems - Course Materials

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Introduction

• An embedded system is an electronic/electro-mechanical system designed to perform a

Interrupt 4k 128 bytes Timer 1 Counter I/P

PSEN ALE P0 P2 P1 P3 TXD RXD

 only 1 On chip oscillator (external crystal)

We may have External memory as data and code

 Find the machine cycle for

 machine cycle = 1 / 921.6 kHz = 1.085 s

◦ It is an output pin and is active high.

◦ General Purpose I/O

8051 Microcontroller Block Diagram 44

The advantage of Interrupts

Note: that there are only 8 memory locations between vectors.

Interrupt ROM Location (Hex) Pin

Timer 1 interrupt (TF1) 001B

Serial COM interrupt (RI and TI) 0023

EA IE.7 Disables all interrupts.

SETB TF0 = SETB TCON.5

TCON: Timer/Counter Control Register

5. The 8051 starts to count up by incrementing the TH0-TL0.

TF Monitor TF until TF=1

• Direct Addressing Mode

ADDITION WITH CARRY

Start: mov C, p3.7

DJNZ direct, <rel addr>

call to the subroutine

• Subroutines allow us to have "structured" assembly language programs.

Sqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3 subroutine

• Advanced RISC Machine

• Who makes it?

• Core licensing – $200,000 to $10,000,000 depending

System & User FIQ Supervisor Abort IRQ Undefined

SPSR_abt SPSR_irq SPSR_und

fiq svc abort irq undefi ned

User Mode: Exception Modes:

Exception Mode Priority IV Address

Undefined instruction Undefined 6 0x00000004

Fast interrupt FIQ 3 0x0000001C

Table 1 - Exception types, sorted by Interrupt Vector addresses

unsigned higher or signed greater than

CC unsigned lower VC no overflow LT signed less than NV special purpose

ARM instruction set

Arithmetic Operations Register Movement

• LSL – Logical Shift Left

• ASR – Arithmetic Shift Right

ASR #5 , positive operand ASR #5 , negative operand

Single register load and store LDR r0, [r1] r0 := mem32[r1]

LDMIA r1, {r0, r2, r5} r0 := mem32[r1]

r9’ 101816 r9’ r5 101816

r9’ 100016 r9’ r0 100016

STMDA r9!, {r0,r1,r5} STMDB r9!, {r0,r1,r5}

 Data Flow Graph (DFG) model,

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