A B C D E

1 1

Compal Confidential
2
Schematics Document 2

AUBURNDALE/CLARKSFIELD with
Intel IBEX PEAK-M core logic

3
Dior DIS 3

2008-10-30
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 30, 2008 Sheet 1 of 50
A B C D E
 A B C D E

Compal Confidential
File Name : Dior DIS

Thermal Sensor
Fan Control
DP to Docking
Page 33
Dior DIS XDP Conn.
Page 4
Accelerometer

LIS302DLTR
Page 4
ADM1032 Page 23 Mobile Page 31

1 1
ATI M92S/M93S PEG CPU Dual Core DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2
LCD conn
Page 20 BANK 0, 1, 2, 3 Page 9,10

CRT Page 21,22,23,24,25 Socket-rPGA989 Dual Channel

Page 19 37.5mm*37.5mm

Page 4,5,6,7,8
CRT to Docking VRAM*4 CK505
Page 33
DMI X4 Clock Generator
HDMI conn Page 26 ICS9LPRS397
Page 23
Page 11
USB x2(Docking) Page 34

USB x2(Sub/B) Page 34

2
Express Card 54 WWAN Card Mini-Card 2

Sub-board UWB USB2.0 FingerPrinter VFM451 daughter board

Page 34 Page 29 Page 29
Intel Ibex Peak M USBx1 Page 34
Azalia
USB conn x 2(For I/O)
PCI-E BUS 1071pins BT Conn USB x 1 Page 31
25mm*27mm SATA0

USB x1(Camara)
10/100/1000 LAN WLAN Card 1394/Card Reader SATA1 Page 20
Page 12,13,14,15,16,17
Marvell Sub-board MDC V1.5 RJ11
88E8072/88E8075 Page 29 ONFI Interface Page 30 Page 30
Page 27 Page 34

Braidwood Audio CKT 92HD75 TPA6047A

Sub-board Page 34 AMP & Audio Jack Page 34
Page 18
RJ45 CONN
3
1394 port SD/MMC/ 3

Page 28
MS/XD Slot SATA ODD Connector Page. 33
Page 18 Docking CONN.
NAND card
2.5" SATA HDD Connector (2) PS/2 Interfaces
LPC BUS Page 18 (2) USB 2.channels
(2) SATA Channels
RTC CKT. (2) Display Port Channels
LED (1) Serial Port
Page 34 Page 34 (1) Parallel Port
(1) Line In
(1) Line Out
SMSC KBC Super I/O
Power OK CKT. TPM1.2 (1) RJ45 (10/100/1000)
Page 37
SLB9635TT 1098 IT8305E Page 36
(1) VGA
Page 32 page 35 (1) 2 LAN indicator LED's
(1) Power Button
COM1 LPT (1) I2C interface
4
Power On/Off CKT. Touch Pad CONN. Int.KBD ( Docking ) ( Docking )
4

Page 34 Page 33 Page 33

Page 30 Page 30

TrackPoint CONN.
Page 30
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/10/24 2009/10/24 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
Page 38 SPI ROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom LA-4891
Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4MB MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 2 of 50
A B C D E
 A

( O MEANS ON X MEANS OFF )

Voltage Rails Symbol Note :

+RTCVCC +B +5VALW +1.5V +5VS : means Digital Ground

+3VL +3VALW +0.75V +3VS
+1.5VS
power
plane +NVVDD : means Analog Ground
+VCCP
+CPU_CORE
+1.05VS
+1.8VS

State

Install below 43 level BOM structure for ver. 0.1

DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
S0
O O O O O M92@ : Install for M92 Graphic controller
S1 8072@ : Install for 8072 NIC controller
O O O O O
S3 1098@ : Install for 1098 KBC controller
O O O O X
CK32@ : Install for 32 pin CLOCK GEN
S5 S4/AC
O O O X X
Install below 45 level BOM structure for ver. 0.1
S5 S4/ Battery only
O O X X X 45@ : means just put it in the BOM of 45 level.
S5 S4/AC & Battery
don't exist
O X X X X
1 1

Reserve below BOM structure for ver. 0.1

@ : means just reserve , no build
CONN@ : means ME part.
M93@ : Install for M93 Graphic controller
8075@ : Install for 8075 NIC controller
SMBUS Control Table 1091@ : Install for 1091 KBC controller

THERMAL CK72@ : Install for 72 pin CLOCK GEN

SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR

SMB_EC_CK1
SMB_EC_DA1
SMSC1098
V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V V X V
SML0CLK
SML0DATA
Calpella X X X X X X X X X
SML1CLK
SML1DATA
Calpella X X X X X X X V X

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 3 of 50
A
 5 4 3 2 1

Layout rule：10mil width trace +VCCP

length < 0.5", spacing 20mil PM_EXTTS#0 1 2 +VCCP
JCPU1B R1 10K_0402_5%
20_0402_1% 1 R2 2COMP3 AT23 1 4 RP2 PM_EXTTS#1 1 2 XDP_TDI_R 1 2
COMP3 CLK_CPU_BCLK_P 15
A16 CLK_BCLK 2 3 R7 10K_0402_5% R8 @ 51_0402_5%
BCLK CLK_CPU_BCLK#_P 15

MISC
20_0402_1% 1 R9 2COMP2 AT24 COMP2 BCLK# B16 CLK_BCLK# 0_4P2R_5% XDP_TMS 1 2
CK32@ R10 @ 51_0402_5%
49.9_0402_1% 1 R3 2COMP1 CLK_CPU_XDP XDP_PREQ#

CLOCKS
G16 COMP1 BCLK_ITP AR30 1 2
AT30 CLK_CPU_XDP# R4 @ 51_0402_5%
49.9_0402_1% BCLK_ITP#
1 R5 2COMP0 AT26 COMP0
XDP_TDO 1 2
E16 CLK_PEG 1 4 RP4 R6 51_0402_5%
PEG_CLK CLK_EXP 13 This shall place near XDP
D16 CLK_PEG# 2 3
PEG_CLK# CLK_EXP# 13 +1.5V
PAD T1 TP_SKTOCC# AH24 R40 0_0402_5% 0_4P2R_5%
SKTOCC# CK32@ XDP_TCK
DPLL_REF_SSCLK A18 1 2 1 2
D A17 1 2 VDDPWRGOOD_R 1 2 R11 @ 51_0402_5% D
H_CATERR# DPLL_REF_SSCLK# R39 0_0402_5% R12 4.75K_0402_1%
AK14 CATERR# This shall place near CPU

THERMAL
1 2
R13 12K_0402_1%
SM_DRAMRST# F6 DRAMRST# 9,10
15 H_PECI 1 R14 2 H_PECI_ISO AT15 PECI
0_0402_5% AL1 SM_RCOMP0
SM_RCOMP[0] SM_RCOMP1
AM1

1 R15 2 H_PROCHOT#_D AN26

SM_RCOMP[1]
SM_RCOMP[2] AN1 SM_RCOMP2 XDP Connector
47 H_PROCHOT# PROCHOT#
0_0402_5% AN15 PM_EXTTS#0 T91 PAD
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1 1 2 from DDR JP1
PM_EXT_TS#[1] PM_EXTTS#1_R 9,10
R17 0_0402_5% 1 2
GND0 GND1
15 H_THERMTRIP# 1 R19 2 H_THERMTRIP#_R AK15 THERMTRIP#
XDP_PREQ# 3 OBSFN_A0 OBSFN_C0 4
0_0402_5% XDP_PRDY# 5 6
OBSFN_A1 OBSFN_C1
7 GND2 GND3 8
AT28 XDP_PRDY# XDP_BPM#0 9 10
PRDY# XDP_PREQ# XDP_BPM#1 OBSDATA_A0 OBSDATA_C0
PREQ# AP27 11 OBSDATA_A1 OBSDATA_C1 12
+VCCP 13 14 +VCCP
XDP_TCK XDP_BPM#2 GND4 GND5
TCK AN28 15 OBSDATA_A2 OBSDATA_C2 16
H_CPURST# 1 R18 2H_CPURST#_R AP26 AP28 XDP_TMS XDP_BPM#3 17 18
RESET_OBS# TMS OBSDATA_A3 OBSDATA_C3

PWR MANAGEMENT
0_0402_5% AT27 XDP_TRST# 19 20
TRST# GND6 GND7 +3VS

JTAG & BPM

21 OBSFN_B0 OBSFN_D0 22
14 H_PM_SYNC 1 R20 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI_R 1 23 OBSFN_B1 OBSFN_D1 24
0_0402_5% AR27 XDP_TDO_R 25 26
TDO XDP_TDI_M C1 XDP_BPM#4 GND8 GND9
TDI_M AR29 27 OBSDATA_B0 OBSDATA_D0 28

2
H_CPUPWRGD 1 R21 2 VCCPWRGOOD_1 AN14 AP29 XDP_TDO_M 0.1U_0402_10V6K XDP_BPM#5 29 30
0_0402_5% VCCPWRGOOD_1 TDO_M @ 2 OBSDATA_B1 OBSDATA_D1 R22
31 GND10 GND11 32
AN25 XDP_DBRESET# XDP_BPM#6 33 34 1K_0402_5%
DBR# OBSDATA_B2 OBSDATA_D2
15 H_CPUPWRGD 1 R23 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
R24 XDP_BPM#7 35 OBSDATA_B3 OBSDATA_D3 36
0_0402_5% 1K_0402_5% 37 38

1
XDP_BPM#0 H_CPUPWRGD H_CPUPWRGD_R GND12 GND13 CLK_CPU_XDP
BPM#[0] AJ22 1 2 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
C 1 R25 2 VDDPWRGOOD_R AK13 AK22 XDP_BPM#1 PM_PWRBTN#_R 41 42 CLK_CPU_XDP# C
14 PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1] 14 PM_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
0_0402_5% AK24 XDP_BPM#2 43 44 1K_0402_5%
BPM#[2] XDP_BPM#3 H_PWRGD_XDP VCC_OBS_AB VCC_OBS_CD XDP_RST#_R R27 H_CPURST#
BPM#[3] AJ24 1 2 45 HOOK2 RESET#/HOOK6 46 1 2
37 VTTPWRGOOD AM15 AJ25 XDP_BPM#4 R26 0_0402_5% 47 48 XDP_DBRESET#
VTTPWRGOOD BPM#[4] HOOK3 DBR#/HOOK7 XDP_DBRESET# 12,14
AH22 XDP_BPM#5 49 50
BPM#[5] XDP_BPM#6 GND14 GND15 XDP_TDO
BPM#[6] AK23 9,10,11,13,27,29,31,33 SMB_DATA_S3 51 SDA TD0 52
H_PWRGD_XDP 1 R29 2 H_PWRGD_XDP_R AM26 AH23 XDP_BPM#7 9,10,11,13,27,29,31,33 SMB_CLK_S3 53 54 XDP_TRST#
0_0402_5% TAPPWRGOOD BPM#[7] SCL TRST# XDP_TDI
55 TCK1 TDI 56
XDP_TCK 57 58 XDP_TMS
PLT_RST#_R +VCCP TCK0 TMS
15 BUF_PLT_RST# 1 R30 2 AL14 RSTIN# 59 GND16 GND17 60
24.9K_0402_1%
10/09 HP SAMTE_BSH-030-01-L-D-A CONN@
1

2
XDP_RST#_R 1 @ 2 PLT_RST# PLT_RST# 12,15,21,27,29,32,34
IC,AUB_CFD_rPGA,R1P0 R48 R31 0_0402_5%
R32 1K_0402_5%
12.4K_0402_1%
2

1
PM_PWRBTN#_R

Processor Pullups JTAG MAPPING

+VCCP XDP_TDI_R 1 2 XDP_TDI

R33 0_0402_5%

PWM Fan Control

H_CATERR# 1 2
R34 50_0402_1% XDP_TDO_M 1 2 XDP_TDO
H_PROCHOT#_D R35 @ 0_0402_5%

circuit
1 2
R36 68_0402_5%

2
H_CPURST#_R 1 2
R37 @ 68_0402_5% R38
B B
0_0402_5%

1
C2
XDP_TDI_M 1 2
09/24 HP 1 2 conn@ R41 @ 0_0402_5%
R42 @ 0.1U_0402_10V6K JP2 DDR3 Compensation Signals
+5VS 2 1 +5VS_FAN 1 1 XDP_TDO_R
35 FAN_PWM 2 2 G1 4 1 2
0_0603_5% 3 5 SM_RCOMP0 1 2 R43 0_0402_5%
3 G2 R44 100_0402_1%
ACES_85204-03001 SM_RCOMP1 1 2
R45 24.9_0402_1%
SM_RCOMP2 1 2
R46 130_0402_1%

Layout Note:Please these

resistors near Processor 10/09 HP
Close to XDP
XDP_TRST# 1 2
R47 51_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(1/5)-Thermal/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 4 of 50
5 4 3 2 1
 5 4 3 2 1

Layout rule：trace
length < 0.5"

JCPU1A JCPU1E
B26 EXP_ICOMPI 1 R49 2 49.9_0402_1%
PEG_ICOMPI
PEG_ICOMPO A26 RSVD32 AJ13
14 DMI_CRX_PTX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27 RSVD33 AJ12
14 DMI_CRX_PTX_N1 C23 A25 EXP_RBIAS 1 R50 2 750_0402_1%
DMI_RX#[1] PEG_RBIAS
14 DMI_CRX_PTX_N2 B22 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] 21 AP25 RSVD1
14 DMI_CRX_PTX_N3 A21 K35 PCIE_CRX_GTX_N0 AL25 AH25
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N1 RSVD2 RSVD34
PEG_RX#[1] J34 AL24 RSVD3 RSVD35 AK26
14 DMI_CRX_PTX_P0 B24 J33 PCIE_CRX_GTX_N2 AL22
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N3 V_DDR_CPU_REF0 RSVD4
14 DMI_CRX_PTX_P1 D23 DMI_RX[1] PEG_RX#[3] G35 AJ33 RSVD5 RSVD36 AL26

DMI
D B23 G32 PCIE_CRX_GTX_N4 AG9 AR2 D
14 DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] V_DDR_CPU_REF1 RSVD6 RSVD_NCTF_37
14 DMI_CRX_PTX_P3 A22 F34 PCIE_CRX_GTX_N5 M27
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N6 RSVD7
PEG_RX#[6] F31 L28 RSVD8 RSVD38 AJ26
D24 D35 PCIE_CRX_GTX_N7 J17 AJ27
14 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] SA_DIMM_VREF RSVD39
G24 E33 PCIE_CRX_GTX_N8 H17
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] SB_DIMM_VREF
F23 C33 PCIE_CRX_GTX_N9 G25
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] RSVD11
H23 D32 PCIE_CRX_GTX_N10 09/18 G17
14 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] RSVD12
B32 PCIE_CRX_GTX_N11 E31 AP1
PEG_RX#[11] PCIE_CRX_GTX_N12 RSVD13 RSVD_NCTF_40
14 DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31 E30 RSVD14 RSVD_NCTF_41 AT2
F24 B28 PCIE_CRX_GTX_N13
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_CRX_GTX_N14 AT3
14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] RSVD_NCTF_42
G23 A31 PCIE_CRX_GTX_N15 AR1
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] RSVD_NCTF_43
PCIE_CRX_GTX_P[0..15] 21
J35 PCIE_CRX_GTX_P0
PEG_RX[0] PCIE_CRX_GTX_P1
PEG_RX[1] H34
H33 PCIE_CRX_GTX_P2 AL28
PEG_RX[2] PCIE_CRX_GTX_P3 CFG0 RSVD45
E22 FDI_TX#[0] PEG_RX[3] F35 T2 PAD AM30 CFG[0] RSVD46 AL29
D21 G33 PCIE_CRX_GTX_P4 T3 PAD CFG1 AM28 AP30
FDI_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P5 CFG2 CFG[1] RSVD47
D19 FDI_TX#[2] PEG_RX[5] E34 T4 PAD AP31 CFG[2] RSVD48 AP32
D18 F32 PCIE_CRX_GTX_P6 T5 PAD CFG3 AL32 AL27
FDI_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P7 CFG4 CFG[3] RSVD49
G21 FDI_TX#[4] PEG_RX[7] D34 T6 PAD AL30 CFG[4] RSVD50 AT31
PCIE_CRX_GTX_P8 CFG5

PCI EXPRESS -- GRAPHICS

E19 FDI_TX#[5] PEG_RX[8] F33 T7 PAD AM31 CFG[5] RSVD51 AT32
F21 B33 PCIE_CRX_GTX_P9 T8 PAD CFG6 AN29 AP33
FDI_TX#[6] PEG_RX[9] CFG[6] RSVD52
Intel(R) FDI
G18 D31 PCIE_CRX_GTX_P10 T9 PAD CFG7 AM32 AR33
FDI_TX#[7] PEG_RX[10] PCIE_CRX_GTX_P11 CFG8 CFG[7] RSVD53
PEG_RX[11] A32 T10 PAD AK32 CFG[8] RSVD_NCTF_54 AT33
C30 PCIE_CRX_GTX_P12 CFG9 AK31 AT34

RESERVED
PEG_RX[12] T11 PAD CFG[9] RSVD_NCTF_55
D22 A28 PCIE_CRX_GTX_P13 T12 PAD CFG10 AK28 AP35
FDI_TX[0] PEG_RX[13] PCIE_CRX_GTX_P14 CFG11 CFG[10] RSVD_NCTF_56
C21 FDI_TX[1] PEG_RX[14] B29 T13 PAD AJ28 CFG[11] RSVD_NCTF_57 AR35
D20 A30 PCIE_CRX_GTX_P15 T14 PAD CFG12 AN30 AR32
FDI_TX[2] PEG_RX[15] CFG13 CFG[12] RSVD58
C18 FDI_TX[3] PCIE_CTX_GRX_N[0..15] 21 T15 PAD AN32 CFG[13]
G22 L33 PCIE_CTX_GRX_C_N0 C6 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N0 T16 PAD CFG14 AJ32
FDI_TX[4] PEG_TX#[0] PCIE_CTX_GRX_C_N1 C7 0.1U_0402_10V6K PCIE_CTX_GRX_N1 CFG15 CFG[14]
E20 FDI_TX[5] PEG_TX#[1] M35 1 2 T17 PAD AJ29 CFG[15] RSVD_TP_59 E15
C F20 M33 PCIE_CTX_GRX_C_N2 C8 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N2 CFG16 AJ30 F15 C
FDI_TX[6] PEG_TX#[2] T18 PAD CFG[16] RSVD_TP_60
G19 M30 PCIE_CTX_GRX_C_N3 C9 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N3 T19 PAD CFG17 AK30 A2
FDI_TX[7] PEG_TX#[3] PCIE_CTX_GRX_C_N4 C10 0.1U_0402_10V6K PCIE_CTX_GRX_N4 CFG18 CFG[17] KEY R53
PEG_TX#[4] L31 1 2 T20 PAD H16 RSVD_TP_86 RSVD62 D15
R51 2 1 1K_0402_5% F17 K32 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5 C15 @ 0_0402_5%
R52 FDI_FSYNC[0] PEG_TX#[5] PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_N6 RSVD63
2 1 1K_0402_5% E17 FDI_FSYNC[1] PEG_TX#[6] M29 C12 1 2 0.1U_0402_10V6K
RSVD64 AJ15 1 2
J31 PCIE_CTX_GRX_C_N7 C13 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N7 AH15 1 2
R55 PEG_TX#[7] RSVD65
2 1 1K_0402_5% C17 FDI_INT PEG_TX#[8] K29 PCIE_CTX_GRX_C_N8 C14 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N8 @ 0_0402_5%
H30 PCIE_CTX_GRX_C_N9 C15 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N9 B19 R54
R56 PEG_TX#[9] RSVD15
2 1 1K_0402_5% F18 FDI_LSYNC[0] PEG_TX#[10] H29 PCIE_CTX_GRX_C_N10 C16 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N10 R58 A19 RSVD16
R57 2 1 1K_0402_5% D17 F29 PCIE_CTX_GRX_C_N11 C17 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N11 @ 0_0402_5%
FDI_LSYNC[1] PEG_TX#[11] PCIE_CTX_GRX_C_N12 C18 0.1U_0402_10V6K PCIE_CTX_GRX_N12
PEG_TX#[12] E28 1 2 1 2 A20 RSVD17
D29 PCIE_CTX_GRX_C_N13 C19 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N13 1 2 B20
PEG_TX#[13] PCIE_CTX_GRX_C_N14 C20 0.1U_0402_10V6K PCIE_CTX_GRX_N14 @ 0_0402_5% RSVD18
PEG_TX#[14] D27 1 2 RSVD_TP_66 AA5
C26 PCIE_CTX_GRX_C_N15 C21 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N15 R59 U9 AA4
PEG_TX#[15] RSVD19 RSVD_TP_67
PCIE_CTX_GRX_P[0..15] 21 T9 RSVD20 RSVD_TP_68 R8
L34 PCIE_CTX_GRX_C_P0 C22 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P0 AD3
PEG_TX[0] PCIE_CTX_GRX_C_P1 C23 0.1U_0402_10V6K PCIE_CTX_GRX_P1 RSVD_TP_69
PEG_TX[1] M34 1 2 AC9 RSVD21 RSVD_TP_70 AD2
M32 PCIE_CTX_GRX_C_P2 C24 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P2 AB9 AA2
PEG_TX[2] PCIE_CTX_GRX_C_P3 C25 0.1U_0402_10V6K PCIE_CTX_GRX_P3 RSVD22 RSVD_TP_71
PEG_TX[3] L30 1 2 RSVD_TP_72 AA1
M31 PCIE_CTX_GRX_C_P4 C26 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P4 R9
PEG_TX[4] PCIE_CTX_GRX_C_P5 C27 0.1U_0402_10V6K PCIE_CTX_GRX_P5 RSVD_TP_73
PEG_TX[5] K31 1 2 RSVD_TP_74 AG7
M28 PCIE_CTX_GRX_C_P6 C28 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P6 C1 AE3
PEG_TX[6] PCIE_CTX_GRX_C_P7 C29 0.1U_0402_10V6K PCIE_CTX_GRX_P7 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[7] H31 1 2 A3 RSVD_NCTF_24
K28 PCIE_CTX_GRX_C_P8 C30 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P8
PEG_TX[8] PCIE_CTX_GRX_C_P9 C31 0.1U_0402_10V6K PCIE_CTX_GRX_P9
PEG_TX[9] G30 1 2 RSVD_TP_76 V4
G29 PCIE_CTX_GRX_C_P10 C32 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P10 V5
PEG_TX[10] PCIE_CTX_GRX_C_P11 C33 0.1U_0402_10V6K PCIE_CTX_GRX_P11 RSVD_TP_77
PEG_TX[11] F28 1 2 RSVD_TP_78 N2
E27 PCIE_CTX_GRX_C_P12 C34 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P12 J29 AD5
PEG_TX[12] PCIE_CTX_GRX_C_P13 C35 0.1U_0402_10V6K PCIE_CTX_GRX_P13 RSVD26 RSVD_TP_79
PEG_TX[13] D28 1 2 J28 RSVD27 RSVD_TP_80 AD7
C27 PCIE_CTX_GRX_C_P14 C36 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P14 W3
PEG_TX[14] PCIE_CTX_GRX_C_P15 C37 0.1U_0402_10V6K PCIE_CTX_GRX_P15 RSVD_TP_81
PEG_TX[15] C25 1 2 A34 RSVD_NCTF_28 RSVD_TP_82 W2
A33 RSVD_NCTF_29 RSVD_TP_83 N3
B AE5 B
RSVD_TP_84
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
IC,AUB_CFD_rPGA,R1P0 B35 RSVD_NCTF_31

VSS AP34

CFG Straps for PROCESSOR IC,AUB_CFD_rPGA,R1P0

CFG0 1 2 CFG7 1 2
R60 @ 3.01K_0402_1% R61 @ 3.01K_0402_1%

PCI-Express Configuration Select Only temporary for early CFD samples (rPGA/BGA)
1: Single PEG No needed by MoW41.
CFG0 0: Bifurcation enabled
Not applicable for Clarksfield Processor

10/02
CFG3 1 2
R62 3.01K_0402_1%

CFG3-PCI Express Static Lane Reversal

1: Normal Operation
CFG3 0: Lane Numbers Reversed
15 -> 0, 14 ->1, .....

R63
CFG4 1 2
A @ 3.01K_0402_1% A

CFG4-Display Port Presence

1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(2/5)-DMI/PEG/FDI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 5 of 50
5 4 3 2 1
 5 4 3 2 1

JCPU1D
JCPU1C

10 DDR_B_D[0..63] SB_CK[0] W8 M_CLK_DDR2 10

D AA6 W9 D
SA_CK[0] M_CLK_DDR0 9 SB_CK#[0] M_CLK_DDR#2 10
AA7 DDR_B_D0 B5 M3
9 DDR_A_D[0..63] SA_CK#[0] M_CLK_DDR#0 9 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB 10
P7 DDR_B_D1 A5
SA_CKE[0] DDR_CKE0_DIMMA 9 SB_DQ[1]
DDR_A_D0 A10 DDR_B_D2 C3
DDR_A_D1 SA_DQ[0] DDR_B_D3 SB_DQ[2]
C10 SA_DQ[1] B3 SB_DQ[3] SB_CK[1] V7 M_CLK_DDR3 10
DDR_A_D2 C7 DDR_B_D4 E4 V6
SA_DQ[2] SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 10
DDR_A_D3 A7 Y6 DDR_B_D5 A6 M2
SA_DQ[3] SA_CK[1] M_CLK_DDR1 9 SB_DQ[5] SB_CKE[1] DDR_CKE3_DIMMB 10
DDR_A_D4 B10 Y5 DDR_B_D6 A4
SA_DQ[4] SA_CK#[1] M_CLK_DDR#1 9 SB_DQ[6]
DDR_A_D5 D10 P6 DDR_B_D7 C4
SA_DQ[5] SA_CKE[1] DDR_CKE1_DIMMA 9 SB_DQ[7]
DDR_A_D6 E10 DDR_B_D8 D1
DDR_A_D7 SA_DQ[6] DDR_B_D9 SB_DQ[8]
A8 SA_DQ[7] D2 SB_DQ[9]
DDR_A_D8 D8 DDR_B_D10 F2 AB8
SA_DQ[8] SB_DQ[10] SB_CS#[0] DDR_CS2_DIMMB# 10
DDR_A_D9 F10 AE2 DDR_B_D11 F1 AD6
SA_DQ[9] SA_CS#[0] DDR_CS0_DIMMA# 9 SB_DQ[11] SB_CS#[1] DDR_CS3_DIMMB# 10
DDR_A_D10 E6 AE8 DDR_B_D12 C2
SA_DQ[10] SA_CS#[1] DDR_CS1_DIMMA# 9 SB_DQ[12]
DDR_A_D11 F7 DDR_B_D13 F5
DDR_A_D12 SA_DQ[11] DDR_B_D14 SB_DQ[13]
E9 SA_DQ[12] F3 SB_DQ[14]
DDR_A_D13 B7 DDR_B_D15 G4 AC7
SA_DQ[13] SB_DQ[15] SB_ODT[0] M_ODT2 10
DDR_A_D14 E7 AD8 DDR_B_D16 H6 AD1
SA_DQ[14] SA_ODT[0] M_ODT0 9 SB_DQ[16] SB_ODT[1] M_ODT3 10
DDR_A_D15 C6 AF9 DDR_B_D17 G2
SA_DQ[15] SA_ODT[1] M_ODT1 9 SB_DQ[17]
DDR_A_D16 H10 DDR_B_D18 J6
DDR_A_D17 SA_DQ[16] DDR_B_D19 SB_DQ[18]
G8 SA_DQ[17] J3 SB_DQ[19]
DDR_A_D18 K7 DDR_B_D20 G1
SA_DQ[18] SB_DQ[20] DDR_B_DM[0..7] 10
DDR_A_D19 J8 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D20 SA_DQ[19] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
G7 SA_DQ[20] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D21 G10 DDR_B_D23 J1 H3 DDR_B_DM2
SA_DQ[21] DDR_A_DM[0..7] 9 SB_DQ[23] SB_DM[2]
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
J10 SA_DQ[23] SA_DM[1] D7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M6 SA_DQ[25] SA_DM[3] M7 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D29 SB_DQ[28] SB_DM[7]
L9 SA_DQ[27] SA_DM[5] AM7 K4 SB_DQ[29]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D30 M4
C DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D31 SB_DQ[30] C
K8 SA_DQ[29] SA_DM[7] AN13 N5 SB_DQ[31]
DDR_A_D30 N8 DDR_B_D32 AF3
DDR_A_D31 SA_DQ[30] DDR_B_D33 SB_DQ[32]
P9 SA_DQ[31] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 10
DDR_A_D32 AH5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
DDR_A_D33 SA_DQ[32] DDR_B_D35 SB_DQ[34] SB_DQS#[0] DDR_B_DQS#1
AF5 SA_DQ[33] DDR_A_DQS#[0..7] 9 AK1 SB_DQ[35] SB_DQS#[1] F4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D36 AG4 J4 DDR_B_DQS#2
SA_DQ[34] SA_DQS#[0] SB_DQ[36] SB_DQS#[2]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D37 AG3 L4 DDR_B_DQS#3

DDR_A_D36 SA_DQ[35] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AF6 SA_DQ[36] SA_DQS#[2] J9 AJ4 SB_DQ[38] SB_DQS#[4] AH2

DDR SYSTEM MEMORY - B

DDR_A_D37 AG5 N9 DDR_A_DQS#3 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AM6 SB_DQ[42]
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D43 AN2
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D44 SB_DQ[43]
AL10 SA_DQ[42] AK5 SB_DQ[44]
DDR_A_D43 AK12 DDR_B_D45 AK2
DDR_A_D44 SA_DQ[43] DDR_B_D46 SB_DQ[45]
AK8 SA_DQ[44] AM4 SB_DQ[46]
DDR_A_D45 AL7 DDR_B_D47 AM3
SA_DQ[45] DDR_A_DQS[0..7] 9 SB_DQ[47] DDR_B_DQS[0..7] 10
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AL8 SA_DQ[47] SA_DQS[1] F9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AM10 SA_DQ[49] SA_DQS[3] M9 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AL11 SA_DQ[51] SA_DQS[5] AK10 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AN9 SA_DQ[53] SA_DQS[7] AR13 AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D54 AT11 DDR_B_D56 AN7
DDR_A_D55 SA_DQ[54] DDR_B_D57 SB_DQ[56]
AP12 SA_DQ[55] AP6 SB_DQ[57]
DDR_A_D56 AM12 DDR_B_D58 AP8
DDR_A_D57 SA_DQ[56] DDR_B_D59 SB_DQ[58]
AN12 SA_DQ[57] DDR_A_MA[0..15] 9 AT9 SB_DQ[59]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D60 AT7
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D61 SB_DQ[60]
AT14 SA_DQ[59] SA_MA[1] W1 AP9 SB_DQ[61]
DDR_A_D60 AT12 AA8 DDR_A_MA2 DDR_B_D62 AR10
B SA_DQ[60] SA_MA[2] SB_DQ[62] DDR_B_MA[0..15] 10 B
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_DQ[63] SB_MA[0] DDR_B_MA1
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[1] V2
DDR_A_D63 AP14 AA9 DDR_A_MA5 T5 DDR_B_MA2
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[2] DDR_B_MA3
SA_MA[6] V8 SB_MA[3] V3
T1 DDR_A_MA7 R1 DDR_B_MA4
SA_MA[7] DDR_A_MA8 SB_MA[4] DDR_B_MA5
SA_MA[8] Y9 10 DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AC3 U6 DDR_A_MA9 W5 R2 DDR_B_MA6
9 DDR_A_BS0 SA_BS[0] SA_MA[9] 10 DDR_B_BS1 SB_BS[1] SB_MA[6]
AB2 AD4 DDR_A_MA10 R7 R6 DDR_B_MA7
9 DDR_A_BS1 SA_BS[1] SA_MA[10] 10 DDR_B_BS2 SB_BS[2] SB_MA[7]
U7 T2 DDR_A_MA11 R4 DDR_B_MA8
9 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[8]
U3 DDR_A_MA12 R5 DDR_B_MA9
SA_MA[12] DDR_A_MA13 SB_MA[9] DDR_B_MA10
SA_MA[13] AG8 10 DDR_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
T3 DDR_A_MA14 Y7 P3 DDR_B_MA11
SA_MA[14] 10 DDR_B_RAS# SB_RAS# SB_MA[11]
AE1 V9 DDR_A_MA15 AC6 R3 DDR_B_MA12
9 DDR_A_CAS# SA_CAS# SA_MA[15] 10 DDR_B_WE# SB_WE# SB_MA[12]
AB3 AF7 DDR_B_MA13
9 DDR_A_RAS# SA_RAS# SB_MA[13]
AE9 P5 DDR_B_MA14
9 DDR_A_WE# SA_WE# SB_MA[14]
N1 DDR_B_MA15
SB_MA[15]

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 6 of 50
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

JCPU1F
JCPU1G

AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22
AT18 AT22

SENSE
LINES
+VCCP +VCCP VAXG3 VSSAXG_SENSE
48A 18A AT16 VAXG4 15A
AR21 VAXG5
D AG35 AH14 AR19 D
VCC1 VTT0_1 VAXG6

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
AG34 AH12 @ 47P_0402_50V8J @ 47P_0402_50V8J AR18
VCC2 VTT0_2 VAXG7
AG33 VCC3 VTT0_3 AH11 AR16 VAXG8 GFX_VID[0] AM22

1
C38

C39

C40

C41
AG32 AH10 1 1 1 1 C743 C744 C741 C742 AP21 AP22
VCC4 VTT0_4 VAXG9 GFX_VID[1]

GRAPHICS VIDs
AG31 VCC5 VTT0_5 J14 AP19 VAXG10 GFX_VID[2] AN22
AG30 J13 AP18 AP23

2
VCC6 VTT0_6 VAXG11 GFX_VID[3]
AG29 VCC7 VTT0_7 H14 AP16 VAXG12 GFX_VID[4] AM23
2 2 2 2 @ 47P_0402_50V8J @ 47P_0402_50V8J
AG28 VCC8 VTT0_8 H12 AN21 VAXG13 GFX_VID[5] AP24

GRAPHICS
AG27 VCC9 VTT0_9 G14 AN19 VAXG14 GFX_VID[6] AN24
AG26 VCC10 VTT0_10 G13 AN18 VAXG15
AF35 G12 09/24 HP AN16
VCC11 VTT0_11 VAXG16

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
AF34 VCC12 VTT0_12 G11 AM21 VAXG17 GFX_VR_EN AR25
AF33 VCC13 VTT0_13 F14 AM19 VAXG18 GFX_DPRSLPVR AT25

C42

C43

C44

C45

C46
AF32 F13 1 1 1 1 1 AM18 AM24 R64 2 1 1K_0402_5%
VCC14 VTT0_14 @ @ VAXG19 GFX_IMON
AF31 VCC15 VTT0_15 F12 AM16 VAXG20
AF30 VCC16 VTT0_16 F11 AL21 VAXG21
AF29 VCC17 VTT0_17 E14 AL19 VAXG22
2 2 2 2 2 +1.5V
AF28 VCC18 VTT0_18 E12 AL18 VAXG23
AF27 D14 +VCCP AL16
VCC19 VTT0_19 VAXG24
AF26 VCC20 VTT0_20 D13 AK21 VAXG25 VDDQ1 AJ1

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
AD35 D12 AK19 AF1
1.1V RAIL POWER

VCC21 VTT0_21 +CPU_CORE VAXG26 VDDQ2

C47

C48

C49

C50

C51
AD34 D11 AK18 AE7

- 1.5V RAILS
VCC22 VTT0_22 VAXG27 VDDQ3 1 1 1 1 1

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
AD33 VCC23 VTT0_23 C14 AK16 VAXG28 VDDQ4 AE4
AD32 VCC24 VTT0_24 C13 AJ21 VAXG29 VDDQ5 AC1

C52

C53

C54

C55
AD31 C12 1 1 1 1 @ 47P_0402_50V8J @ 47P_0402_50V8J AJ19 AB7
VCC25 VTT0_25 VAXG30 VDDQ6 2 2 2 2 2
AD30 VCC26 VTT0_26 C11 AJ18 VAXG31 VDDQ7 AB4

1
AD29 B14 C745 C746 C747 C748 AJ16 Y1
VCC27 VTT0_27 VAXG32 VDDQ8
AD28 VCC28 VTT0_28 B12 AH21 VAXG33 VDDQ9 W7
2 2 2 2

POWER
AD27 A14 AH19 3A W4

2
VCC29 VTT0_29 VAXG34 VDDQ10
AD26 VCC30 VTT0_30 A13 AH18 VAXG35 VDDQ11 U1

330U_D2_2VM_R6M

10U_0805_10V4K

10U_0805_10V4K
AC35 A12 @ 47P_0402_50V8J @ 47P_0402_50V8J AH16 T7
VCC31 VTT0_31 VAXG36 VDDQ12

C56
AC34 VCC32 VTT0_32 A11 VDDQ13 T4 1

C57

C58
C AC33 P1 C
VCC33 VDDQ14 1 1
AC32 +VCCP 09/24 HP N7 +
VCC34 +VCCP VDDQ15
AC31 VCC35 VDDQ16 N4

DDR3
AC30 VCC36 VTT0_33 AF10 VDDQ17 L1
2 2 2
10U_0805_10V4K

10U_0805_10V4K

AC29 VCC37 VTT0_34 AE10 J24 VTT1_45 VDDQ18 H1

10U_0805_10V4K

10U_0805_10V4K

FDI
AC28 VCC38 VTT0_35 AC10 J23 VTT1_46
CPU CORE SUPPLY

C59

C60

AC27 VCC39 VTT0_36 AB10 1 1 H25 VTT1_47 +VCCP

C61

C62
AC26 VCC40 VTT0_37 Y10 1 1
AA35 VCC41 VTT0_38 W10
AA34 VCC42 VTT0_39 U10 VTT0_59 P10
2 2

10U_0805_10V4K

10U_0805_10V4K
AA33 VCC43 VTT0_40 T10 VTT0_60 N10
2 2
AA32 VCC44 VTT0_41 J12 VTT0_61 L10

C63

C64
AA31 VCC45 VTT0_42 J11 VTT0_62 K10 1 1
AA30 VCC46 VTT0_43 J16
AA29 VCC47 VTT0_44 J15
AA28 VCC48 +VCCP 2 2
AA27 VCC49

1.1V
AA26 VCC50 VTT1_63 J22
Y35 K26 J20 +VCCP
VCC51 VTT1_48 VTT1_64

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
Y34 VCC52 J27 VTT1_49 VTT1_65 J18

PEG & DMI

Y33 VCC53 J26 VTT1_50 VTT1_66 H21

C65

C66

C67

C68

10U_0805_10V4K

10U_0805_10V4K
Y32 VCC54 1 1 1 1 J25 VTT1_51 VTT1_67 H20
Y31 VCC55 H27 VTT1_52 VTT1_68 H19

C69

C70
Y30 VCC56 G28 VTT1_53 1 1
Y29 VCC57 G27 VTT1_54
2 2 2 2
Y28 VCC58 G26 VTT1_55
Y27 VCC59 F26 VTT1_56 2 2
Y26 VCC60 E26 VTT1_57 VCCPLL1 L26

1.8V
V35 VCC61 PSI# AN33 PSI# 47 E25 VTT1_58 VCCPLL2 L27
+1.8VS
V34 0.6A M26
POWER

VCC62 VCCPLL3
V33 VCC63 H_VID[0..6] 47
V32 AK35 H_VID0
VCC64 VID[0]

1U_0603_10V4Z

1U_0603_10V4Z

2.2U_0603_6.3V4Z

10U_0805_10V4K

4.7U_0603_6.3V6K
B V31 AK33 H_VID1 B
VCC65 VID[1]

C71

C72

C73

C74

C75
V30 AK34 H_VID2 1 1 1 1 1
VCC66 VID[2] H_VID3
V29 VCC67 VID[3] AL35
CPU VIDS

V28 AL33 H_VID4

VCC68 VID[4] H_VID5
V27 VCC69 VID[5] AM33
2 2 2 2 2
CPU

V26 AM35 H_VID6 IC,AUB_CFD_rPGA,R1P0

VCC70 VID[6] PM_DPRSLPVR_R
U35 VCC71 PROC_DPRSLPVR AM34 1 2 PROC_DPRSLPVR 47
U34 R67 0_0402_5%
VCC72
U33 VCC73
U32 VCC74
U31 VCC75 VTT_SELECT G15 H_VTTVID1 44
U30 VCC76
U29 VCC77
U28 VCC78
H_VTTVID1 = Low, 1.1V
U27 VCC79
U26 VCC80
H_VTTVID1 = High, 1.05V
R35 VCC81
R34 VCC82
R33 VCC83
R32 VCC84 ISENSE AN35 IMVP_IMON 47
R31 VCC85
R30 VCC86
R29 0_0402_5%
VCC87
R28 AJ34 VCC_SENSE 1 R68 2 VCCSENSE
SENSE LINES

VCC88 VCC_SENSE VCCSENSE 47

R27 VCC89 VSS_SENSE AJ35 VSS_SENSE 1 2 VSSSENSE
VSSSENSE 47
R26 R69 0_0402_5%
VCC90
P35 VCC91
P34 VCC92 VTT_SENSE B15 VTT_SENSE 44
P33 VCC93 VSS_SENSE_VTT A15 VSS_SENSE_VTT 44
P32 VCC94
P31 VCC95
P30 VCC96
A P29 A
VCC97
P28 VCC98
P27 VCC99
P26 VCC100
Close to CPU
+CPU_CORE

VCCSENSE 1
R70
2
100_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
VSSSENSE 1 2
R71 100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(4/5)-PWR
IC,AUB_CFD_rPGA,R1P0 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 7 of 50
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
CPU CORE
JCPU1H JCPU1I

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
Inside cavity
AT20 VSS1 VSS81 AE34

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87
AT17 VSS2 VSS82 AE33 1 1 1 1 1 1 1 1 1 1 1 1
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163 2 2 2 2 2 2 2 2 2 2 2 2
AR24 VSS6 VSS86 AE29 K3 VSS164
AR23 VSS7 VSS87 AE28 J32 VSS165
AR20 VSS8 VSS88 AE27 J30 VSS166
D AR17 AE26 J21 D
VSS9 VSS89 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171

between Inductor and socket

C88

C89

C90

C91

C92

C93

C94

C95

C96

C97
AR3 VSS14 VSS94 AC2 H26 VSS172 1 1 1 1 1 1 1 1 1 1
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175 2 2 2 2 2 2 2 2 2 2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2VM_R6M

330U_D2_2VM_R6M

330U_D2_2VM_R6M

330U_D2_2VM_R6M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AN23 VSS24 VSS104 AB26 G34 VSS182

C108

C109

C106

C107

C104

C105
AN20 VSS25 VSS105 AB6 G31 VSS183 1 1 1 1 1 1

C98

C99

C100

C101

C102

C103

C110

C111

C112

C113
AN17 VSS26 VSS106 AA10 G20 VSS184 1 1 1 1 1 1 1 1 1 1
AM29 Y8 G9 + + + + @ + @ +
VSS27 VSS107 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190

Under cavity
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
AM2 VSS36 VSS116 W29 E35 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
C AL17 V10 E18 C
VSS41 VSS121 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 VSS_NCTF1_R
VSS46 VSS126 VSS204 VSS_NCTF1 VSS_NCTF2_R T54
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
VSS_NCTF3_R T55
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
VSS_NCTF4_R T78
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
VSS_NCTF5_R T79
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 VSS_NCTF6_R T80
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1
VSS_NCTF7_R T56
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35
T57
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
B AH9 L32 A27 B
VSS73 VSS153 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 L2 10/14 HP
VSS77 VSS157
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(5/5)-GND/Bypass
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

V_DDR_CPU_REF +1.5V +1.5V

3A@1.5V
6 DDR_A_D[0..63]
DDR3 SO-DIMM A 6 DDR_A_DM[0..7]
JDIMMA1 CONN@
6 DDR_A_DQS[0..7] +1.5V
V_DDR_CPU_REF 1 2
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4 6 DDR_A_DQS#[0..7]

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

1
C114

C115
1 1 DDR_A_D1 7 8
DQ1 VSS3 6 DDR_A_MA[0..15]
9 10 DDR_A_DQS#0 R76
DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0 1K_0402_1%
11 DM0 DQS0 12
V_DDR_CPU_REF VREFDQ
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6
15 16

2
D DDR_A_D3 DQ2 DQ6 DDR_A_D7 M1 V_DDR_CPU_REF R76, R77, R78, R81, D
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12 V_DDR_CPU_REF0
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13 M3 R104, R110
DQ9 DQ13 V_DDR_CPU_REF1
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1 R77
DDR_A_DQS1 DQS#1 DM1 DRAMRST# 1K_0402_1%
29 DQS1 RESET# 30 DRAMRST# 4,10
31 32

2
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
DDR_A_DQS#3
Layout Note:
61 VSS22 DQS#3 62
DDR_A_DM3 63 DM3 DQS3 64 DDR_A_DQS3 Place near DIMM
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

+1.5V
6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
C CKE0 CKE1 DDR_CKE1_DIMMA 6 C
75 VDD1 VDD2 76

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D2_2VM_R6M
77 78 DDR_A_MA15
NC1 A15

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C128
6 DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14 1
BA2 A14

C116

C117

C118

C119

C120

C121

C122

C123

C124

C125

C126

C127
81 VDD3 VDD4 82 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_MA12 83 84 DDR_A_MA11 +
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 88 @ @
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 2 2 2 2 2 2 2 2 2 2 2 2 2
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
6 M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 6
6 M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 6
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
6 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# Layout Note:
BA0 RAS# DDR_A_RAS# 6
111 VDD13 VDD14 112
6 DDR_A_WE# DDR_A_WE# 113 WE# S0# 114 DDR_CS0_DIMMA#
DDR_CS0_DIMMA# 6
Place near DIMM
6 DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 6
117 VDD15 VDD16 118
DDR_A_MA13 M_ODT1 V_DDR_CPU_REF
119 A13 ODT1 120 M_ODT1 6
6 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2 V_DDR_CPU_REF0 +0.75VS
123 VDD17 VDD18 124
125 126 DDR_VREF_CA_DIMMA 1 2 V_DDR_CPU_REF
NCTEST VREF_CA R78 0_0402_5%
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36 1 2
DDR_A_D33 DQ32 DQ36 DDR_A_D37 R104 @ 0_0402_5%
131 DQ33 DQ37 132

C131

1U_0603_10V4Z

C132

1U_0603_10V4Z

C133

C134

1U_0603_10V4Z

C159

10U_0603_6.3V6M
1U_0603_10V4Z
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4 09/18 as short as possible 1 1 1 1 1
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B 139 140 DDR_A_D38 B
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 DDR_VREF_CA_DIMMA 2 2 2 2 2
143 DQ35 VSS33 144
145 146 DDR_A_D44
VSS34 DQ44
0.1U_0402_10V6K

2.2U_0603_6.3V4Z

DDR_A_D40 147 148 DDR_A_D45

DQ40 DQ45
C129

C130

DDR_A_D41 149 150 1 1

DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
DDR_A_DM5 153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 DDR_A_D46 2 2
157 DQ42 DQ46 158
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R79 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#1_R
SA0 EVENT# PM_EXTTS#1_R 4,10
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 4,10,11,13,27,29,31,33
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 4,10,11,13,27,29,31,33
C135

C136

A 203 204 A
1 1 VTT1 VTT2 +0.75VS
1 10K_0402_5%
R80

205 206 0.65A@0.75V

G1 G2
2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

DDRIII-SODIMM SLOT1
TOP SLOT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size Document Number
Custom LA-4891

Date: Monday, October 27, 2008 Sheet 9 of 50

Rev
0.1

5 4 3 2 1
 5 4 3 2 1

V_DDR_CPU_REF +1.5V +1.5V

6 DDR_B_DQS#[0..7]
3A@1.5V
6 DDR_B_D[0..63]
CONN@
6 DDR_B_DM[0..7]
JDIMMB1
V_DDR_CPU_REF 1 2
VREF_DQ VSS1 6 DDR_B_DQS[0..7]
3 4 DDR_B_D4
VSS2 DQ4
2.2U_0603_6.3V4Z

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5 6 DDR_B_MA[0..15]
1 1 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
9 VSS4 DQS#0 10
C137

C138
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16
D DDR_B_D3 17 18 DDR_B_D7 D
DQ3 DQ7
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# 4,9
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB Layout Note:

C CKE0 CKE1 DDR_CKE3_DIMMB 6 C
75 VDD1 VDD2 76
77 NC1 A15 78 DDR_B_MA15 Place near DIMM
6 DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4 +1.5V
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
A3 A2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_B_MA1 97 98 DDR_B_MA0
A1 A0

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
99 VDD9 VDD10 100

C139

C140

C141

C142

C143

C144

C145

C146

C147

C148

C149

C150
6 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3 1 1 1 1 1 1 1 1 1 1 1 1
CK0 CK1 M_CLK_DDR3 6
6 M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 6
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1 @ @
A10/AP BA1 DDR_B_BS1 6 2 2 2 2 2 2 2 2 2 2 2 2
6 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# 6
111 VDD13 VDD14 112
6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB#
WE# S0# DDR_CS2_DIMMB# 6
6 DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 6
117 VDD15 VDD16 118
DDR_B_MA13 M_ODT3 V_DDR_CPU_REF
119 A13 ODT1 120 M_ODT3 6
6 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2 R81 V_DDR_CPU_REF1
123 VDD17 VDD18 124
125 126 DDR_VREF_CA_DIMMB 1 2 V_DDR_CPU_REF
NCTEST VREF_CA 0_0402_5%
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36 1 2 Layout Note:
DDR_B_D33 DQ32 DQ36 DDR_B_D37 R110 @ 0_0402_5%
131 DQ33 DQ37 132
133 VSS29 VSS30 134 Place near DIMM
DDR_B_DQS#4 135 136 DDR_B_DM4 09/18 as short as possible
DDR_B_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B 139 140 DDR_B_D38 B
DDR_B_D34 VSS32 DQ38 DDR_B_D39 DDR_VREF_CA_DIMMB
141 DQ34 DQ39 142 0.1U_0402_10V6K +0.75VS

2.2U_0603_6.3V4Z
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146
C151

C152
DDR_B_D40 147 148 DDR_B_D45 1 1
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
VSS36 DQS#5

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5 2 2

C153

C154

C155

C156
155 VSS37 VSS38 156 1 1 1 1
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 DDR_B_D52 2 2 2 2
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
1 R82 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#1_R
SA0 EVENT# PM_EXTTS#1_R 4,9
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 4,9,11,13,27,29,31,33
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 4,9,11,13,27,29,31,33
C157

C158

A 1 2 203 204 A
1 1 VTT1 VTT2 +0.75VS
R83 10K_0402_5%
205 206 0.65A@0.75V
G1 G2
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

DDRIII-SODIMM SLOT2
BOT SLOT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size

Date:
Document Number
LA-4891
Monday, October 27, 2008 Sheet 10 of 50
Rev
0.1

5 4 3 2 1
 5 4 3 2 1

+3VS_CK505 +1.05VS_CK505 +3VS_CK505 +1.05VS_CK505

14.31818MHZ_20P_1BX14318BE1A
U2

1 32 SMB_CLK_S3 CLK_XTAL_OUT
VDD_DOT SCL SMB_CLK_S3 4,9,10,13,27,29,31,33
R85 CK32@ 0_0402_5% 2 31 SMB_DATA_S3
VSS_DOT SDA SMB_DATA_S3 4,9,10,13,27,29,31,33
CLK_BUF_DOT96 1 2 L_CLK_BUF_DOT96 3 30 REF_0/CPU_SEL 2 1 R90 CLK_14M_PCH CLK_XTAL_IN
13 CLK_BUF_DOT96 DOT_96 REF_0/CPU_SEL CLK_14M_PCH 13
CLK_BUF_DOT96# 1 2 L_CLK_BUF_DOT96# 4 29 CK32@ 33_0402_1%
13 CLK_BUF_DOT96# DOT_96# VDD_REF
R87 CK32@ 0_0402_5% 5 28 CLK_XTAL_IN
27M_CLK R89 1 CK32@ 2 33_0402_5% L_27M_CLK VDD_27 XTAL_IN CLK_XTAL_OUT
23 27M_CLK 6 27MHZ XTAL_OUT 27
7 27MHZ_SS VSS_REF 26
8 25 CK_PWRGD
VSS_27 CKPWRGD/PD# Y1
R91 CK32@0_0402_5% 9 24 R94 CK32@ 0_0402_5% 2 1
CLK_BUF_CKSSCD L_CLK_BUF_CKSSCD VSS_SATA VDD_CPU R_CLK_BUF_BCLK
13 CLK_BUF_CKSSCD 1 2 10 SRC_1/SATA CPU_0 23 1 2 CLK_BUF_BCLK CLK_BUF_BCLK 13
D CLK_BUF_CKSSCD# 1 2 L_CLK_BUF_CKSSCD# 11 22 R_CLK_BUF_BCLK# 1 2 CLK_BUF_BCLK# D
13 CLK_BUF_CKSSCD# SRC_1#/SATA# CPU_0# CLK_BUF_BCLK# 13
R92 CK32@ 0_0402_5% 12 21 R96 CK32@ 0_0402_5% 2 2
CLK_DMI R93 VSS_SRC VSS_CPU
13 CLK_DMI 1 CK32@ 2 0_0402_5% L_CLK_DMI 13 SRC_2 CPU_1 20
CLK_DMI# R95 1 2 L_CLK_DMI# 14 19 CK_PWRGD R152 1 2 +3VS_CK505 C182 C183
13 CLK_DMI# SRC_2# CPU_1#
CK32@ 0_0402_5% 15 18 33P_0402_50V8J 33P_0402_50V8J
+1.05VS +1.05VS_CK505 CPU_STOP# VDD_SRC_IO VDD_CPU_IO 10K_0402_5% 1 1
16 CPU_STOP# VDD_SRC 17

TGND

1
D
Close to U2/U3
1 2 2 CLK_EN# 47
0_0603_5% R97 SLG8SP585VTR_QFN32_5X5 G

33
10U_0805_10V4K

10U_0805_10V4K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
Q13 S

3
C176

C177

C178

C179

C180

C181
1 1 1 1 1 1 2N7002_SOT23-3

2 2 2 2 2 2
+3VS_CK505 +3VS_CK505_U3 U3

14.31818MHZ_20P_1BX14318BE1A
CK72@ 6 11
STP_PCI#_R R98 VDDREF NC
1 2 10K_0402_5% 12 VDDPCI
CLK_XTAL_OUT_72 19
+3VS +3VS_CK505 CPU_STOP# R99 VDD48
1 2 10K_0402_5% +1.05VS_CK505_U3 23 VDD96_IO
CLK_XTAL_IN_72 27 10 SMB_CLK_S3
C221 2 CLK_14M_PCH VDDPLL3 SCLK SMB_DATA_S3
Close to U2/U3 1 55 VDDSRC SDATA 9
1 2 @ 10P_0402_50V8J 72
0_0603_5% R84 VDDCPU STP_PCI#_R R102 1
PCI_STOP# 54 2 @ 0_0402_5% STP_PCI# 15
10U_0805_10V4K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

Need add jump wire for debug if needed 53 CPU_STOP#

CPU_STOP#
C164

C165

C166

C167

C168

C169

C170

1 1 1 1 1 1 1 Y8
71 CLK_CPU_BCLK_C RP1 4 1
+1.05VS_CK505_U3 CPUT0_LPR_F CLK_CPU_BCLK#_C
2 1 CPUC0_LPR_F 70 3 2
C174 2 1 REF_0/CPU_SEL 0_4P2R_5%
2 2 2 2 2 2 2 @ 10P_0402_50V8J 31 VDDPLL3_IO CPUT1_LPR_F 68
C 38 67 Force SRC output with default C
2 2 VDDSRC_IO CPUC1_LPR_F
EMI Capacitor 52 VDDSRC_IO register when use 72pin CLK GEN
C642 C641 62 65
33P_0402_50V8J 33P_0402_50V8J VDDSRC_IO CR7#
66 VDDCPU_IO
1 1 R_CLK_UWB_U3 R464 1
CPUT2_ITP_LPR/SRCT8_LPR 64 2 0_0402_5%
63 R_CLK_UWB_U3# R463 1 2 0_0402_5%
CPUC2_ITP_LPR/SRCC8_LPR
61 R_CLK_PEG_U3 R103 1 2 0_0402_5%
SRCT7_LPR R_CLK_PEG_U3# R119 1
SRCC7_LPR 60 2 0_0402_5%
+VCCP 33_0402_5% 1 2 R113 13 58
PCI CR#6
PIN 30 CPU_0 CPU_1 33_0402_5% 1 2 R105 PCI2_TME 14 57 CLK_PCIE_CARD_U3 R121 1 2 0_0402_5%
REF_0/CPU_SEL PCI2/TME SRCT6_LPR CLK_PCIE_CARD_U3# R161 1
1 2 SRCC6_LPR 56 2 0_0402_5%
R100 @ 10K_0402_5% 33_0402_5% 1 2 R106 PCI_CLK3 15 PCI3
0 (Default) 133MHz 133MHz CR10# 49
1 2 Need add jump wire for debug if needed R154
R101 10K_0402_5% 50 R_CLK_PCIE_MCARD_U3 1 2 0_0402_5%
CK32@ 33_0402_5% SRCT10_LPR
1 100MHz 100MHz 1 2 R109 27_SEL 16 PCI4/27_Select SRCC10_LPR 51 R_CLK_PCIE_MCARD_U3# 1 2 0_0402_5%
R153
33_0402_5% 1 2 R108 ITP_EN 17 46
PCI_F5/ITP_EN CR#11 R193
+1.05VS_CK505_U3 +3VS_CK505_U3 48 R_CLK_PCIE_WWAN_U3 1 2 0_0402_5%
SRCT11_LPR R_CLK_PCIE_WWAN_U3#
SRCC11_LPR 47 1 2 0_0402_5%
CLK_XTAL_IN_72 5 R166
X1

0.1U_0402_10V6K

0.1U_0402_10V6K
CR#9 43

C185

C184
1 1 CLK_XTAL_OUT_72 4
X2 R_CLK_PCIE_LAN_U3 R441 1
SRCT9_LPR 44 2 0_0402_5%
45 R_CLK_PCIE_LAN_U3# R455 1 2 0_0402_5%
SRCC9_LPR
2 2

CR#4 41
B B
39 R_CLK_PCIE_EXP_U3 R456 1 2 0_0402_5%
33_0402_5% FSA SRCT4_LPR R_CLK_PCIE_EXP_U3#
1 2 R116 20 USB_48MHz/FSLA SRCC4_LPR 40 R458 1 2 0_0402_5%

CR#3 37
33_0402_5% 1 2 R151 FSB 2 FSLB/TEST_MODE R_CLK_PEG R86 1
SRCT3_LPR 35 2 0_0402_5%
36 R_CLK_PEG# R114 1 2 0_0402_5%
33_0402_5% SRCC3_LPR
FSLC FSLB FSLA CPU SRC PCI 1 2 R120 FSC 7 FSLC/TEST_SEL/REF0
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz R_CLK_BUF_CKSSCD R541 1
SRCT2_LPR/SATAT_LPR 32 2 0_0402_5%
33 R_CLK_BUF_CKSSCD# R542 1 2 0_0402_5%
SRCC2_LPR/SATAC_LPR
1 0 1 100 100 33.3
24 R_CLK_BUF_DOT96 R539 1 2 0_0402_5%
SRCT0_LPR/DOTT_96_LPR R_CLK_BUF_DOT96# R540 1
0 0 1 133 100 33.3 SRCC0_LPR/DOTC_96_LPR 25 2 0_0402_5%
59 GNDSRC
28 27M_CLK_R R543 1 2 33_0402_5%
27MHz_NonSS/SRCT1_LPR/SE1
0 1 1 166 100 33.3 18 GNDPCI 27MHz_SS/SRCC1_LPR/SE2 29

22 GND48
Need add jump wire for debug if needed
26 1 CK_PWRGD
+1.05VS_CK505_U3 +1.05VS_CK505_U3 +1.05VS_CK505_U3 GND CK_PWRGD/PD#
30 GND
+3VS +3VS +3VS
1

69 GNDCPU CR#A 21 PAD T60

R122 R123 R124
2

4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% 34

R125 R126 R127 GNDSRC
10K_0402_5% @ 10K_0402_5% 10K_0402_5% 42 8
2

A GNDSRC REF1 A
FSA FSB FSC 3
1

GNDREF
ITP_EN 27_SEL PCI2_TME ICS9LPRS397EKLFT MLF 72P
1

R129 R130
2

R128 4.7K_0402_5% 4.7K_0402_5%

@ 4.7K_0402_5% R131 R132 R133
@ 10K_0402_5% 10K_0402_5% @10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

CLOCK GENERATOR
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 11 of 50
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1 +RTCVCC +3VS

1 2 PCH_RTCX2 R135 1 2 SM_INTRUDER#

R134 10M_0402_5% 1M_0402_5% 1 2 SIRQ
R137 1 2 PCH_INTVRMEN R136 10K_0402_5%
330K_0402_5%
High = Internal VR Enabled(Default)

32.768KHZ_12.5PF_Q13MC14610002
1 2 HDA_SPKR
R138 @ 1K_0402_5%
1

4
18P_0402_50V8J

LOW=Default HIGH=No Reboot

1 1
OSC

OSC

C188 C189
D 18P_0402_50V8J D
U4A
2 2
NC

NC

Y2 +RTCVCC PCH_RTCX1 B13 D33

1 RTCX1 FWH0 / LAD0 LPC_LAD0 29,32,35,36

1
PCH_RTCX2 D13 B33 LPC_LAD1 29,32,35,36
2

C190 CLRP1 RTCX2 FWH1 / LAD1

FWH2 / LAD2 C32 LPC_LAD2 29,32,35,36
1U_0603_10V4Z SHORT PADS A32 LPC_LAD3 29,32,35,36

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 C14 RTCRST#
R139 20K_0402_1% C34
FWH4 / LFRAME# LPC_LFRAME# 29,32,35,36
1 2 PCH_SRTCRST# D17
R140 20K_0402_1% SRTCRST#
1 A34 LPC_LDRQ#0 36

RTC

LPC
LDRQ0#

1
SM_INTRUDER# A16 F34 T21 PAD
C193 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN A14 AB9 SIRQ
SIRQ 32,35,36

2
2 INTVRMEN SERIRQ

R141 1 2 33_0402_5% HDA_BIT_CLK A30

30 HDA_BIT_CLK_MDC HDA_BCLK
R142 1 2 33_0402_5% AK7 SATA_PRX_DTX_N0
34 HDA_BIT_CLK_CODEC SATA0RXN SATA_PRX_DTX_N0 18
R143 1 2 33_0402_5% HDA_SYNC D29 AK6 SATA_PRX_DTX_P0
30 HDA_SYNC_MDC HDA_SYNC SATA0RXP SATA_PRX_DTX_P0 18
R144 1 2 33_0402_5% AK11 SATA_PTX_DRX_N0
34 HDA_SYNC_CODEC SATA0TXN SATA_PTX_DRX_N0 18
HDA_SPKR P1 AK9 SATA_PTX_DRX_P0
34 HDA_SPKR SPKR SATA0TXP SATA_PTX_DRX_P0 18
R145 1 2 33_0402_5% HDA_RST# C30
30 HDA_RST#_MDC HDA_RST#
R146 1 2 33_0402_5% AH6 SATA_PRX_DTX_N1
34 HDA_RST#_CODEC SATA1RXN SATA_PRX_DTX_N1 18
AH5 SATA_PRX_DTX_P1
SATA1RXP SATA_PRX_DTX_P1 18
34 HDA_SDIN0 HDA_SDIN0 G30 AH9 SATA_PTX_DRX_N1
HDA_SDIN0 SATA1TXN SATA_PTX_DRX_N1 18
AH8 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 18
30 HDA_SDIN1 HDA_SDIN1 F30
+3VALW HDA_SDIN1
SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
C 1 2 LID_SW# F32 AF6 C
R147 10K_0402_5% HDA_SDIN3 SATA2TXP
AH3 SATA_PRX_DTX_N3
SATA3RXN SATA_PRX_DTX_N3 33
R148 1 2 33_0402_5% HDA_SDOUT B29 AH1 SATA_PRX_DTX_P3 0.01U_0402_16V7K
30 HDA_SDOUT_MDC HDA_SDO SATA3RXP SATA_PRX_DTX_P3 33
R149 1 2 33_0402_5% AF3 SATA_PTX_DRX_N3 C199 1 2 SATA_PTX_C_DRX_N3
34 HDA_SDOUT_CODEC SATA3TXN SATA_PTX_C_DRX_N3 33
AF1 SATA_PTX_DRX_P3 C201 1 2 SATA_PTX_C_DRX_P3
SATA3TXP SATA_PTX_C_DRX_P3 33
R150 1 2@ 100K_0402_5% H32 0.01U_0402_16V7K

SATA
HDA_DOCK_EN# / GPIO33 SATA_PRX_DTX_N4
SATA4RXN AD9 SATA_PRX_DTX_N4 33
10/07 HP J30 AD8 SATA_PRX_DTX_P4 0.01U_0402_16V7K
20,30,35 LID_SW# HDA_DOCK_RST# / GPIO13 SATA4RXP SATA_PRX_DTX_P4 33
AD6 SATA_PTX_DRX_N4 C202 1 2 SATA_PTX_C_DRX_N4
SATA4TXN SATA_PTX_C_DRX_N4 33
AD5 SATA_PTX_DRX_P4 C203 1 2 SATA_PTX_C_DRX_P4
SATA4TXP SATA_PTX_C_DRX_P4 33
1 2 HDA_BIT_CLK_MDC PCH_JTAG_TCK M3 JTAG_TCK SATA5RXN AD3 0.01U_0402_16V7K
C752 @ 47P_0402_50V8J AD1
SATA5RXP
1 2 HDA_BIT_CLK_CODEC PCH_JTAG_TMS K3 JTAG_TMS SATA5TXN AB3
C753 @ 47P_0402_50V8J AB1
SATA5TXP
1 2 HDA_SDOUT_MDC PCH_JTAG_TDI K1 JTAG_TDI
C754 @ 47P_0402_50V8J

JTAG
1 2 HDA_SDOUT_CODEC PCH_JTAG_TDO J2 JTAG_TDO SATAICOMPO AF16
C755 @ 47P_0402_50V8J R155
PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2 +3VS
TRST# SATAICOMPI +1.05VS
10/01 HP 37.4_0402_1%

35 KBC_SPI_CLK_R BA2 SPI_CLK

2
for SMSC EC
1 2 AV3 1 2 +3VS R159 R160
35 KBC_SPI_CS0#_R SPI_CS0#
R157 15_0402_5% R158 10K_0402_5% 10K_0402_5% 10K_0402_5%
35 PCH_SPI_CS1#_R 1 2 AY3 SPI_CS1# SATALED# T3 SATA_LED# 33,34
R165 15_0402_5%

1
AY1 Y9 SATA_DET#0 HDD_HALTLED
B 35 KBC_SPI_SI_R
notice KBC state SPI_MOSI SATA0GP / GPIO21 B
SPI

35 KBC_SPI_SO AV1 V1 HDD_HALTLED SATA_DET#0

SPI_MISO SATA1GP / GPIO19 HDD_HALTLED 34

IBEXPEAK-M_FCBGA1071

+3VALW +3VALW +3VALW +3VALW

1

R355 R358 R536 R643 CONN@

@ 200_0402_5% @ 200_0402_5% 20K_0402_1% @ 20K_0402_1% JBATT1
+3VS JP3 +RTCVCC +3VL +BATT1.1 E-T_3801-E02N-01R_2P
1
2

OBSFN_A0

1
2
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST# 2 OBSFN_A1 D38
3 GND
1

4 OBSDATA_A0 2
R354 R535 R537 R353 5 1 R748
@ 100_0402_1% @ 100_0402_1% @ 10K_0402_5% OBSDATA_A1 +BATT_D
10K_0402_5% 6 GND
W=20mils 3 1 2
7 W=20mils W=20mils
OBSDATA_A2 C208 DAN202U_SC70 1K_0402_5%
8 1
2

R162 OBSDATA_A3
9 GND
14,35,47 PM_PWROK 1 2 10 1U_0603_10V4Z
HOOK0
11 HOOK2
1K_0402_5% 2 Place near IBEX-M
12 HOOK4
13 HOOK5
1K_0402_5% 14
PCH_JTAG_TCK R163 1 VCCOBS_AB
1 2 4,15,21,27,29,32,34 PLT_RST# 2 15 HOOK6
A R156 51_0402_5% 16 A
4,14 XDP_DBRESET# HOOK7
17 GND
PCH_JTAG_TDO 18
PCH JTAG Enable PCH JTAG Disable TDO
19 TRST#
PCH Pin RefDes ES1 ES2 ES1 ES2 PCH_JTAG_TDI 20
PCH_JTAG_TDO R358 No Install 200ohm No Install No Install PCH_JTAG_TMS TDI
21 TMS
R535 No Install 100ohm No Install No Install 22
PCH_JTAG_TMS R355 200ohm 200ohm No Install No Install TCK1
23
PCH_JTAG_TDI
R354
R536
100ohm
200ohm
100ohm
200ohm
No Install
20Kohm
No Install
No Install
PCH_JTAG_TCK 24
GND
TCK0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
R537 100ohm 100ohm 10Kohm No Install
PCH_JTAG_TCK R156 51ohm 51ohm 51ohm 51ohm MOLEX_52435-2472_24P-T
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
PCH_JTAG_RST# R643 20Kohm 20Kohm No Install No Install CONN@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R353 10Kohm 10Kohm No Install No Install Custom LA-4891 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 12 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS
SMBCLK 1 2 +3VALW
SMB_CLK_S3 1 2 R167 2.2K_0402_5%
R169 10K_0402_5% SMBDATA 1 2
SMB_DATA_S3 1 2 R168 2.2K_0402_5%
R171 10K_0402_5% SML0CLK 1 2
SML1CLK_R 1 2 R170 4.7K_0402_5%
R173 10K_0402_5% SML0DATA 1 2
SML1DAT_R 1 2 R172 4.7K_0402_5%
R175 10K_0402_5% SML1CLK 1 2
R174 4.7K_0402_5%
SML1DATA 1 2
PEG_CLKREQ# 1 2 R176 4.7K_0402_5%
D R177 10K_0402_5% SMBALERT# 1 2 D
R207 10K_0402_5%
SML0ALERT# 1 2
R272 10K_0402_5%
SML1ALERT# 1 2
R771 10K_0402_5%
10/02 HP
U4B
Set it as GPI11 SMBALERT# R350 1 2 SML1ALERT#
BG30 B9 SMBALERT# @ 0_0402_5%
PERN1 SMBALERT# / GPIO11 SMBALERT# 27
BJ30 SMBCLK R351 1 2 SML1CLK_R
PERP1 SMBCLK @ 0_0402_5%
BF29 PETN1 SMBCLK H14
BH29 SMBDATA R352 1 2 SML1DAT_R
PETP1 SMBDATA @ 0_0402_5%
SMBDATA C8
34 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 AW30
PCIE_PRX_DTX_P2 BA30 PERN2
34 PCIE_PRX_DTX_P2 PERP2
EXP C210 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N2 BC30 J14 SML0ALERT# T51 PAD
34 PCIE_PTX_C_DRX_N2 PETN2 SML0ALERT# / GPIO60
C211 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P2 BD30
34 PCIE_PTX_C_DRX_P2 PETP2
C6 SML0CLK Q7A
PCIE_PRX_DTX_N3 SML0CLK 2N7002DW T/R7_SOT-363-6
34 PCIE_PRX_DTX_N3 AU30

SMBus
PCIE_PRX_DTX_P3 PERN3 SML0DATA SMBCLK SMB_CLK_S3
34 PCIE_PRX_DTX_P3 AT30 PERP3 SML0DATA G8 6 1 SMB_CLK_S3 4,9,10,11,27,29,31,33
Media Card C209 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N3 AU32
34 PCIE_PTX_C_DRX_N3 PETN3
C212 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P3 AV32
34 PCIE_PTX_C_DRX_P3 PETP3
M14 SML1ALERT#

2
PCIE_PRX_DTX_N4 SML1ALERT# / GPIO74
29 PCIE_PRX_DTX_N4 BA32 PERN4
29 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_P4 BB32 E10 SML1CLK
C213 1 PCIE_PTX_DRX_N4 PERP4 SML1CLK / GPIO58
WLAN 29 PCIE_PTX_C_DRX_N4 2 0.1U_0402_10V6K BD32 PETN4
Q7B
C214 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P4 BE32 G12 SML1DATA 2N7002DW T/R7_SOT-363-6
29 PCIE_PTX_C_DRX_P4 PETP4 SML1DATA / GPIO75 SMBDATA 3 4 SMB_DATA_S3

PCI-E*
SMB_DATA_S3 4,9,10,11,27,29,31,33
BF33 PERN5
BH33 T13 +3VS
PERP5 CL_CLK1

Controller
BG32

5
C PETN5 C
BJ32 PETP5 CL_DATA1 T11

Link
27 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_N6 BA34 T9
PCIE_PRX_DTX_P6 AW34 PERN6 CL_RST1#
27 PCIE_PRX_DTX_P6 PERP6
NIC C217 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N6 BC34
27 PCIE_PTX_C_DRX_N6 PETN6
C218 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P6 BD34
27 PCIE_PTX_C_DRX_P6 PETP6
H1 PEG_CLKREQ# Q8A
PCIE_PRX_DTX_N7 PEG_A_CLKRQ# / GPIO47 2N7002DW T/R7_SOT-363-6 R357
29 PCIE_PRX_DTX_N7 AT34 PERN7
29 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_P7 AU34 SML1CLK 6 1 SML1CLK_R 1 2 CAP_CLK 23,30,35
C219 1 PCIE_PTX_DRX_N7 PERP7
WWAN 29 PCIE_PTX_C_DRX_N7 2 0.1U_0402_10V6K AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PEG_PCH# 21
@ 0_0402_5%
C220 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P7 AV36 AD45
29 PCIE_PTX_C_DRX_P7 PETP7 CLKOUT_PEG_A_P CLK_PEG_PCH 21

2
BG34 PERN8 CLKOUT_DMI_N AN4 CLK_EXP# 4

PEG
BJ34 AN2 10/04 HP
PERP8 CLKOUT_DMI_P CLK_EXP 4
BG36 Q8B
PETN8 2N7002DW T/R7_SOT-363-6 R360
BJ36 PETP8
AT1 CLK_DP# T52 PAD SML1DATA 3 4 SML1DAT_R 1 2 CAP_DAT 23,30,35
CLKOUT_DP_N / CLKOUT_BCLK1_N CLK_DP @ 0_0402_5%
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 T53 PAD
AK48 +3VS 10/04 HP
+3VALW CLKOUT_PCIE0N
AK47

5
CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 CLK_DMI# 11
1 2 P9 PCIECLKRQ0# / GPIO73 CLKIN_DMI_P BA24 CLK_DMI 11
R676 10K_0402_5%

AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_BCLK# 11

+3VS AM45 AP1
CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK 11
1 2 U4 PCIECLKRQ1# / GPIO18
R640 10K_0402_5% F18
CLKIN_DOT_96N CLK_BUF_DOT96# 11
R180 E18
CLKIN_DOT_96P CLK_BUF_DOT96 11
34 CLK_PCIE_EXP_PCH# 1 2 0_0402_5% CLK_PCIE_EXP_PCH#_R AM47 CLKOUT_PCIE2N
EXP 34 CLK_PCIE_EXP_PCH 1 2 0_0402_5% CLK_PCIE_EXP_PCH_R AM48 CLKOUT_PCIE2P
B R181 AH13 B
CLKIN_SATA_N / CKSSCD_N CLK_BUF_CKSSCD# 11
34 CLKREQ_EXP# N4 AH12 XTAL25_IN
PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_CKSSCD 11
R183 XTAL25_OUT 1 2
34 CLK_PCIE_CARD_PCH# 1 2 0_0402_5% CLK_PCIE_CARD_PCH#_R AH42 CLKOUT_PCIE3N REFCLK14IN P41 CLK_14M_PCH 11
R182 1M_0402_5%
Media Card 34 CLK_PCIE_CARD_PCH 1 2 0_0402_5% CLK_PCIE_CARD_PCH_R AH41 CLKOUT_PCIE3P
Y3
R184
+3VALW 10K_0402_5% 2 R746 1 A8 J42 1 2
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 15
R185
29 CLK_PCIE_MCARD_PCH# 1 2 0_0402_5% CLK_PCIE_MCARD_PCH#_R AM51 CLKOUT_PCIE4N XTAL25_IN AH51 XTAL25_IN 25MHZ_20P_1BG25000CK1A

18P_0402_50V8J

18P_0402_50V8J
WLAN 29 CLK_PCIE_MCARD_PCH 1 2 0_0402_5% CLK_PCIE_MCARD_PCH_R AM53 CLKOUT_PCIE4P XTAL25_OUT AH53 XTAL25_OUT 09/22 HP
R186 1 C223 1 C224
29 CLKREQ_WLAN# M9 AF38 R187 1 2 90.9_0402_1% +1.05VS
PCIECLKRQ4# / GPIO26 XCLK_RCOMP

2 2
AJ50 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 T45
+3VALW AJ52 10/07 HP
CLKOUT_PCIE5P
1 2 H6 P43
Clock Flex

R770 10K_0402_5% PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

Note: remove 25MHz crystal
R192 for ES2 silicon.
1 2 0_0402_5% CLK_PCIE_LAN_PCH#_R AK53 T42 CLK_14M_KBC_P 1 2
27 CLK_PCIE_LAN_PCH# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 CLK_14M_KBC_PCH 35
NIC 27 CLK_PCIE_LAN_PCH 1 2 0_0402_5% CLK_PCIE_LAN_PCH_R AK51 CLKOUT_PEG_B_P
R195 47_0402_5%
R194
27 CLK_PCIE_LAN_REQ# P13 PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 N50 CLK_48M_SIO_P 2 1 CLK_48M_SIO_PCH 36
R118 47_0402_5%

IBEXPEAK-M_FCBGA1071

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 13 of 50
5 4 3 2 1

www.vinafix n
 5 4 3 2 1

U4C U4D

FDI_RXN0 BA18 T48 L_BKLTEN SDVO_TVCLKINN BJ46

5 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BH17 T47 BG46
DMI_CTX_PRX_N1 DMI0RXN FDI_RXN1 L_VDD_EN SDVO_TVCLKINP
5 DMI_CTX_PRX_N1 BJ22 DMI1RXN FDI_RXN2 BD16
5 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 AW20 BJ16 Y48 BJ48
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN3 L_BKLTCTL SDVO_STALLN
5 DMI_CTX_PRX_N3 BJ20 DMI3RXN FDI_RXN4 BA16 SDVO_STALLP BG48
FDI_RXN5 BE14 AB48 L_DDC_CLK
5 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BD24 BA14 Y45 BF45
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN6 L_DDC_DATA SDVO_INTN
5 DMI_CTX_PRX_P1 BG22 DMI1RXP FDI_RXN7 BC12 SDVO_INTP BH45
5 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BA20 AB46
DMI_CTX_PRX_P3 DMI2RXP L_CTRL_CLK
5 DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18 V48 L_CTRL_DATA
FDI_RXP1 BF17
D DMI_CRX_PTX_N0 BE22 BC16 AP39 T51 D
5 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N1 BF21 BG16 AP41 T53
5 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA
DMI_CRX_PTX_N2 BD20 AW16
5 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP4
DMI_CRX_PTX_N3 BE18 BD14 AT43
5 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP5 LVD_VREFH
FDI_RXP6 BB14 AT42 LVD_VREFL DDPB_AUXN BG44
DMI_CRX_PTX_P0 BD22 BD12 BJ44
5 DMI_CRX_PTX_P0 DMI0TXP FDI_RXP7 DDPB_AUXP
DMI_CRX_PTX_P1 BH21 AU38
5 DMI_CRX_PTX_P1 DMI1TXP DDPB_HPD

LVDS
DMI_CRX_PTX_P2 BC20 AV53
5 DMI_CRX_PTX_P2 DMI2TXP LVDSA_CLK#
DMI_CRX_PTX_P3 BD18 BJ14 1 2 AV51 BD42
5 DMI_CRX_PTX_P3 DMI3TXP FDI_INT LVDSA_CLK DDPB_0N
R262 1K_0402_5% BC42

DMI
FDI
DDPB_0P
FDI_FSYNC0 BF13 1 2 BB47 LVDSA_DATA#0 DDPB_1N BJ42
+1.05VS BH25 R263 1K_0402_5% BA52 BG42

Digital Display Interface

DMI_ZCOMP LVDSA_DATA#1 DDPB_1P
FDI_FSYNC1 BH13 1 2 AY48 LVDSA_DATA#2 DDPB_2N BB40
1 2 DMI_IRCOMP BF25 R289 1K_0402_5% AV47 BA40
R196 49.9_0402_1% DMI_IRCOMP LVDSA_DATA#3 DDPB_2P
FDI_LSYNC0 BJ12 1 2 DDPB_3N AW38
R361 1K_0402_5% BB48 BA38
LVDSA_DATA0 DDPB_3P
FDI_LSYNC1 BG14 1 2 BA50 LVDSA_DATA1
R362 1K_0402_5% AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49

AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
4,12 XDP_DBRESET# T6 J12 PCIE_WAKE# AY53 AV40
SYS_RESET# WAKE# PCIE_WAKE# 27,29,34 LVDSB_DATA#0 DDPC_HPD
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
47 VGATE M6 Y1 PM_CLKRUN# AT53 BD40
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 32,35,36 LVDSB_DATA#3 DDPC_0P
1 2 DDPC_1N BF41
R199 R227 0_0402_5% AY51 BH41
PWROK System Power Management LVDSB_DATA0 DDPC_1P
12,35,47 PM_PWROK 1 2 B17 PWROK AT48 LVDSB_DATA1 DDPC_2N BD38
@ 0_0402_5% AU50 BC38
LVDSB_DATA2 DDPC_2P
AT51 LVDSB_DATA3 DDPC_3N BB36
1 2 K5 P8 SUS_STAT# PADT110
PADT110 BA36
R198 0_0402_5% MEPWROK SUS_STAT# / GPIO61 DDPC_3P
C C

1 2 AUXPWROK A10 LAN_RST# SUSCLK / GPIO62 F3 SUS_CLK PADT109

PADT109 AA52 CRT_BLUE DDPD_CTRLCLK U50
R210 10K_0402_5% AB53 U52
CRT_GREEN DDPD_CTRLDATA
AD53 CRT_RED
PM_DRAM_PWRGD D9 E4
4 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SLP_S5# 33
R200 BC46
DDPD_AUXN
43 RPGOOD 1 2 0_0402_5% V51 CRT_DDC_CLK DDPD_AUXP BD46
35 PM_RSMRST# 1 2 C16 RSMRST# SLP_S4# H7 SLP_S4# 38,46 V53 CRT_DDC_DATA DDPD_HPD AT38
R201 10K_0402_5%
+3VALW BJ40
DDPD_0N
1 2 M1 SUS_PWR_DN_ACK / GPIO30 SLP_S3# P12 SLP_S3# 27,34,35,37,38,41,43,44,45,46,49 Y53 CRT_HSYNC DDPD_0P BG40
R639 10K_0402_5% Y51 BJ38
CRT_VSYNC DDPD_1N
4 PM_PWRBTN#_R DDPD_1P BG38

CRT
30 ON/OFFBTN# 1 2 P5 PWRBTN# SLP_M# K8 DDPD_2N BF37
R202 0_0402_5% AD48 BH37
DAC_IREF DDPD_2P

1K_0402_0.5%
AB51 CRT_IRTN DDPD_3N BE36

1
R203
23,35,38 AC_PRESENT P7 ACPRESENT / GPIO31 TP23 N2 DDPD_3P BD36

IBEXPEAK-M_FCBGA1071
35 LOW_BAT# 1 2 LOW_BAT#_R A6 BATLOW# / GPIO72 PMSYNCH BJ10 H_PM_SYNC 4
R204 0_0402_5%

2
IBEX_R# F14 F6 SLP_LAN#
RI# SLP_LAN# / GPIO29

IBEXPEAK-M_FCBGA1071

+3VS

PM_CLKRUN# 1 2 PM_RSMRST# 1 2
R205 10K_0402_5% R206 10K_0402_5%
B PWROK 1 2 B
+3VALW R747 10K_0402_5%

SLP_S3# 1 2
LOW_BAT#_R 1 2 R538 @ 10K_0402_5%
R209 10K_0402_5% SLP_S4# 1 2
SLP_LAN# 1 2 R546 @ 10K_0402_5%
R340 10K_0402_5% 10/07 HP SLP_S5# 1 2
IBEX_R# 1 2 R547 @ 10K_0402_5%
R211 10K_0402_5%
PCIE_WAKE# 1 2
R212 1K_0402_5%
AC_PRESENT 1 2
R439 10K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(3/6)-DMI/GPIO/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 14 of 50
5 4 2 1
 5 4 3 2 1

+3VS U4E U4F

H40 AD0 NV_CE#0 AY9 NV_CE0# 18
RP17 N34 BD1 +3VS R213 1 2 10K_0402_5% BMBUSY# Y3 AH45 T22 PAD
AD1 NV_CE#1 NV_CE1# 18 BMBUSY# / GPIO0 CLKOUT_PCIE6N
PCI_PIRQG# 1 8 C44 AP15 AH46 T23 PAD
AD2 NV_CE#2 NV_CE2# 18 CLKOUT_PCIE6P
PCI_PIRQC# 2 7 A38 BD8 48 OCP# OCP# C38
AD3 NV_CE#3 NV_CE3# 18 TACH1 / GPIO1
PCI_PIRQA# 3 6 C36 0_0402_5%
PCI_PIRQE# AD4 RUNSCI_EC# R214 WWAN
4 5 J34 AD5 NV_DQS0 AV9 NV_DQS0 18 35 RUNSCI_EC# D37 TACH2 / GPIO6
A40 AD6 NV_DQS1 BG8 NV_DQS1 18 CLKOUT_PCIE7N AF48 CLK_PCIE_WWAN_PCH#_R 2 1 CLK_PCIE_WWAN_PCH# 29

MISC
8.2K_0804_8P4R_5% D45 23 THERM_SCI# THERM_SCI# J32 AF47 CLK_PCIE_WWAN_PCH_R 2 1
AD7 TACH3 / GPIO7 CLKOUT_PCIE7P CLK_PCIE_WWAN_PCH 29
E36 AP7 0_0402_5% R215
AD8 NV_DQ0 / NV_IO0 NV_DQ0 18 +3VS
RP18 H48 AP6 GPIO8 F10
AD9 NV_DQ1 / NV_IO1 NV_DQ1 18 GPIO8
PCI_STOP# 1 8 E40 AT6 2 1
AD10 NV_DQ2 / NV_IO2 NV_DQ2 18
PCI_SERR# 2 7 C40 AT9 28 CB_IN# CB_IN# K9 U2 R216 10K_0402_5%
AD11 NV_DQ3 / NV_IO3 NV_DQ3 18 LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 35
PCI_IRDY# 3 6 M48 BB1
AD12 NV_DQ4 / NV_IO4 NV_DQ4 18
PCI_PIRQD# 4 5 M45 AV6 GPIO15 T7
D AD13 NV_DQ5 / NV_IO5 NV_DQ5 18 GPIO15 D
F53 AD14 NV_DQ6 / NV_IO6 BB3 NV_DQ6 18
8.2K_0804_8P4R_5% M40 BA4 GPIO16 AA2 AM3
AD15 NV_DQ7 / NV_IO7 NV_DQ7 18 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK#_P 4

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 NV_DQ8 18
RP16 J36 BB6 ALS_EN# F38 AM1
AD17 NV_DQ9 / NV_IO9 NV_DQ9 18 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK_P 4
PCI_REQ2# 1 8 K48 BD6
AD18 NV_DQ10 / NV_IO10 NV_DQ10 18
PCI_REQ1# 2 7 F40 BB7 VGA_RST# Y7 BG10 PCH_PECI_R 1 2
AD19 NV_DQ11 / NV_IO11 NV_DQ11 18 SCLOCK / GPIO22 PECI H_PECI 4

GPIO
PCI_FRAME# 3 6 C42 BC8 0_0402_5% R217
AD20 NV_DQ12 / NV_IO12 NV_DQ12 18
PCI_TRDY# 4 5 K46 BJ8 GPIO24 H10 T1 KB_RST#
AD21 NV_DQ13 / NV_IO13 NV_DQ13 18 GPIO24 RCIN# KB_RST# 35
M51 AD22 NV_DQ14 / NV_IO14 BJ6 NV_DQ14 18
8.2K_0804_8P4R_5% J52 BG6 WWAN_TRANSMIT_OFF# AB12 BE10
AD23 NV_DQ15 / NV_IO15 NV_DQ15 18 29 WWAN_TRANSMIT_OFF# GPIO27 PROCPWRGD H_CPUPWRGD 4

CPU
K51 AD24
L34 BD3 NV_ALE LAN_DIS# V13 BD10 H_THERMTRIP#_L 1 2
AD25 NV_ALE NV_ALE 18 27 LAN_DIS# GPIO28 THRMTRIP# H_THERMTRIP# 4
F42 AY6 NV_CLE 54.9_0402_1%
AD26 NV_CLE NV_CLE 18

1
PCI_GNT3# 1 2 J40 STP_PCI# M11 R218
AD27 11 STP_PCI# STP_PCI# / GPIO34
R257 @ 1K_0402_5% G46 R219
AD28 SATA_CLKREQ# 56_0402_1%
F44 AD29 NV_RCOMP AU2 1 2 V6 SATACLKREQ# / GPIO35
A16 swap overide Strap/Top-Block M47 R220 32.4_0402_1%
Swap Override jumper AD30 NPCI_RST#

PCI
H36 AV7 NV_RB# 18 35,36 NPCI_RST# AB7 BA22 T24 PAD

2
Low=A16 swap AD31 NV_RB# SATA2GP / GPIO36 TP1
+VCCP
PCI_GNT3# override/Top-Block J50 AY8 GPIO37 AB13 AW22
C/BE0# NV_WR#0_RE# NV_RE#_WR#0 18 SATA3GP / GPIO37 TP2 T25 PAD
Swap Override enabled G42 AY5
C/BE1# NV_WR#1_RE# NV_RE#_WR#1 18
High=Default H47 GPIO38 V3 BB22 T26 PAD
C/BE2# SLOAD / GPIO38 TP3
G34 C/BE3# NV_WE#_CK0 AV11 NV_WE#_CK0 18
BF5 GPIO39 P3 AY45 T27 PAD
NV_WE#_CK1 NV_WE#_CK1 18 SDATAOUT0 / GPIO39 TP4
PCI_PIRQA# G38
PCI_PIRQB# PIRQA# GPIO45
H51 PIRQB# H3 PCIECLKRQ6# / GPIO45 TP5 AY46 T28 PAD
PCI_PIRQC# B37 H18 USB20_N0
PIRQC# USBP0N USB20_N0 31
PCI_PIRQD# A44 J18 USB20_P0 CONN CLKREQ_WWAN# F1 AV43 T29 PAD
PIRQD# USBP0P USB20_P0 31 29 CLKREQ_WWAN# PCIECLKRQ7# / GPIO46 TP6
A18 USB20_N1
USBP1N USB20_N1 31
PCI_REQ0# F51 C18 USB20_P1 CONN GPIO48 AB6 AV45 T30 PAD
REQ0# USBP1P USB20_P1 31 SDATAOUT1 / GPIO48 TP7
PCI_REQ1# A46 N20 USB20_N2
REQ1# / GPIO50 USBP2N USB20_N2 34
PCI_REQ2# B45 P20 USB20_P2 CONN GPIO49 AA4 AF13 T31 PAD
C REQ2# / GPIO52 USBP2P USB20_P2 34 SATA5GP / GPIO49 TP8 C
PCI_REQ3# M53 J20 USB20_N3
REQ3# / GPIO54 USBP3N USB20_N3 34
L20 USB20_P3 CONN WLAN_TRANSMIT_OFF# F8 M18 T32 PAD
USBP3P USB20_P3 34 29 WLAN_TRANSMIT_OFF# GPIO57 TP9
PCI_GNT0# F48 F20 USB20_N4
GNT0# USBP4N USB20_N4 34
MODEM_DISABLE# K45 G20 USB20_P4 EXPRESS N18 T33 PAD
30 MODEM_DISABLE# GNT1# / GPIO51 USBP4P USB20_P4 34 TP10
T113PAD PCI_GNT2# F36 A20 USB20_N5
GNT2# / GPIO53 USBP5N USB20_N5 27
PCI_GNT3# H53 C20 USB20_P5 GLAN (8075) A4 AJ24 T34 PAD
GNT3# / GPIO55 USBP5P USB20_P5 27 VSS_NCTF_1 TP11
M22 USB20_N6 A49

NCTF
USBP6N USB20_N6 29 VSS_NCTF_2

RSVD
PCI_PIRQE# B41 N22 USB20_P6 WLAN A5 AK41 T35 PAD
PIRQE# / GPIO2 USBP6P USB20_P6 29 VSS_NCTF_3 TP12
18 ODD_DET# ODD_DET# K53 B21 A50
PCI_PIRQG# PIRQF# / GPIO3 USBP7N VSS_NCTF_4
A36 PIRQG# / GPIO4 USBP7P D21 A52 VSS_NCTF_5 TP13 AK42 T36 PAD
ACCEL_INT# A48 H22 USB20_N8 A53
31 ACCEL_INT# PIRQH# / GPIO5 USBP8N USB20_N8 31 17 PCH_NCTF6 VSS_NCTF_6
J22 USB20_P8 Bluetooth B2 M32 T37 PAD
USBP8P USB20_P8 31 17 PCH_NCTF7 VSS_NCTF_7 TP14
USB

K6 E22 USB20_N9 B4
29 PCI_RST# PCIRST# USBP9N USB20_N9 29 VSS_NCTF_8
F22 USB20_P9 WWAN B52 N32 T38 PAD
USBP9P USB20_P9 29 VSS_NCTF_9 TP15
PCI_SERR# E44 A22 USB20_N10 B53
32,35 PCI_SERR# SERR# USBP10N USB20_N10 32 VSS_NCTF_10
PCI_PERR# E50 C22 USB20_P10 Fingerprint BE1 M30 T39 PAD
PERR# USBP10P USB20_P10 32 VSS_NCTF_11 TP16
G24 USB20_N11 BE53
USBP11N USB20_N11 33 VSS_NCTF_12
H24 USB20_P11 DOCK BF1 N30 T40 PAD
USBP11P USB20_P11 33 VSS_NCTF_13 TP17
PCI_IRDY# A42 L24 USB20_N12 BF53
IRDY# USBP12N USB20_N12 20 VSS_NCTF_14
H44 M24 USB20_P12 USB Camera BH1 H12 T41 PAD
PAR USBP12P USB20_P12 20 VSS_NCTF_15 TP18
PCI_DEVSEL# F46 A24 USB20_N13 BH2
DEVSEL# USBP13N USB20_N13 33 VSS_NCTF_16
PCI_FRAME# C46 C24 USB20_P13 DOCK BH52 AA23 T42 PAD
FRAME# USBP13P USB20_P13 33 VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
PCI_LOCK# D49 BJ1 AB45 T43 PAD
PLOCK# 17 PCH_NCTF19 VSS_NCTF_19 NC_1
B25 USBRBIAS 1 2 BJ2
PCI_STOP# USBRBIAS# R221 22.6_0402_1% VSS_NCTF_20

Within
D41 STOP# BJ4 VSS_NCTF_21 NC_2 AB38 T44 PAD
PCI_TRDY# C48 D25 BJ49
TRDY# USBRBIAS VSS_NCTF_22
500 mils
BJ5 VSS_NCTF_23 NC_3 AB42 T45 PAD
M7 PME# BJ50 VSS_NCTF_24
N16 USB_OC0# BJ52 AB41 T46 PAD
OC0# / GPIO59 BT_OFF VSS_NCTF_25 NC_4
4,12,21,27,29,32,34 PLT_RST# D5 PLTRST# OC1# / GPIO40 J16 BT_OFF 31 17 PCH_NCTF26 BJ53 VSS_NCTF_26
F16 WEBCAM_OFF D1 T39 T47 PAD
B OC2# / GPIO41 WEBCAM_OFF 20 VSS_NCTF_27 NC_5 B
CLK_PCI_KBC_R N52 L16 FPR_OFF D2
CLKOUT_PCI0 OC3# / GPIO42 FPR_OFF 32 VSS_NCTF_28
CLK_PCI_FB_R P53 E14 USB_OC4# D53
CLK_PCI_TPM_R CLKOUT_PCI1 OC4# / GPIO43 ISO_PREP# VSS_NCTF_29
P46 CLKOUT_PCI2 OC5# / GPIO9 G16 ISO_PREP# 33 E1 VSS_NCTF_30 INIT3_3V# P6 T48 PAD
P51 F12 LANLINK_STATUS# LANLINK_STATUS# 27,28,33,35 E53
CLK_PCI_DB_P CLKOUT_PCI3 OC6# / GPIO10 USB_OC#7 VSS_NCTF_31
P48 CLKOUT_PCI4 OC7# / GPIO14 T15 TP24 C10 T49 PAD
IBEXPEAK-M_FCBGA1071
IBEXPEAK-M_FCBGA1071
+3VS
R223 1 2 39_0402_5%
36 CLK_PCI_SIO_PCH
KB_RST# R259 1 2 10K_0402_5%
R225 1 2 39_0402_5% CLK_PCI_KBC_R +3VALW
35 CLK_PCI_KBC_PCH
PCI_GNT0# 1 2 NPCI_RST# R222 1 2 10K_0402_5%
R191 2 1 39_0402_5% R236 @ 1K_0402_5% WLAN_TRANSMIT_OFF# R231 1 2 10K_0402_5%
29 CLK_PCI_DEBUG_PCH Danbury Technology Enable
MODEM_DISABLE# 1 2 SATA_CLKREQ# R435 1 2 10K_0402_5%
R189 2 1 39_0402_5% CLK_PCI_DB_P R238 @ 1K_0402_5% NV_ALE High=Endabled GPIO24 R235 1 2 10K_0402_5%
32 CLK_PCI_DB_PCH Low=Disable (@) GPIO49 R243 1 2 10K_0402_5%
GPIO15 R246 1 2 1K_0402_5%
R224 1 2 51_0402_5% CLK_PCI_FB_R Boot BIOS Strap VGA_RST# R240 1 2 10K_0402_5%
13 CLK_PCI_FB PCI_GNT0# MODEM_DISABLE# Boot BIOS Location +V_NVRAM_VCCQ ISO_PREP# R239 1 2 10K_0402_5%
R228 1 2 47_0402_5% CLK_PCI_TPM_R 0 0 LPC ALS_EN# R237 1 2 10K_0402_5%
32 CLK_PCI_TPM_PCH 0 1 Reserved(NAND) NV_ALE 1 R245 2 GPIO45 R663 1 2 10K_0402_5%
1 0 PCI @ 1K_0402_5% RUNSCI_EC# R247 1 2 10K_0402_5%
10/07 HP 1 1 SPI* USB_OC0# R284 1 2 10K_0402_5%
GPIO37 R248 1 2 10K_0402_5%
USB_OC4# R226 1 2 10K_0402_5%
DMI Termination Voltage GPIO16 R251 1 2 10K_0402_5%
+3VS 1 2 NV_CLE Set to Vss when LOW USB_OC#7 R229 1 2 10K_0402_5%
R250 0_0402_5% Set to Vcc when HIGH GPIO38 R252 1 2 10K_0402_5%
RP19 GPIO8 R230 1 2 10K_0402_5%
ACCEL_INT# 1 8 +3VS +3VS GPIO39 R256 1 2 10K_0402_5%
PCI_LOCK# 2 7 CB_IN# R253 1 2 10K_0402_5%
A PCI_DEVSEL# 3 6 NV_CLE 1 2 GPIO48 R255 1 2 10K_0402_5% A
PCI_PERR# 4 5 R254 @ 1K_0402_5% WWAN_TRANSMIT_OFF# R233 1 2@ 10K_0402_5%
5

U5 THERM_SCI# R283 1 2 10K_0402_5%

8.2K_0804_8P4R_5% 1 PLT_RST# on-die VR:
P

IN1 *Enable: 1 (internal PU) STP_PCI# R527 1

4 BUF_PLT_RST# 4 O 2 10K_0402_5%
RP20 2 Disable: 0 (install R233)
IN2
G

PCI_REQ0# 1 8
1

PCI_PIRQB# 2 7 @ SN74AHC1G08DCKR_SC70-5
Security Classification Compal Secret Data Compal Electronics, Inc.
3

ODD_DET# 3 6
PCI_REQ3# 4 5 R258 2008/10/24 2009/10/24 Title
100K_0402_5%
Issued Date Deciphered Date
8.2K_0804_8P4R_5% IBEX-M(4/6)-PCI/USB/RSVD
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 30, 2008 Sheet 15 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

+1.05VS +VCCP_VCCA_CLK
L1
1 2 +3VS
+1.05VS

10U_0603_6.3V6M

1U_0402_6.3V4Z
@ 10UH_LB2012T100MR_20%_0805 L45

+1.05VS U4J POWER

+1.05VS U4G POWER 2 1

C225

C228
1 1 AB24 AE50 MURATA_BLM18AG601SN1D_0603
VCCCORE[1] VCCADAC[1]

1U_0603_10V4Z

10U_0805_10V4K

0.01U_0402_16V7K

10U_0805_10V4K

0.1U_0402_10V6K
AB26 VCCCORE[2]

C226

C227

C229

C230

C231
10/13 Intel
AP51 VCCACLK[1] VCCIO[5] V24 1 1 AB28 VCCCORE[3] 0.069A VCCADAC[2] AE52 1 1 1

1U_0402_6.3V4Z
@ @ 0.052A
1 2 2 VCCIO[6] V26 AD26 VCCCORE[4] 1.524A

CRT
AP53 VCCACLK[2] VCCIO[7] Y24 1 AD28 VCCCORE[5] VSSA_DAC[1] AF53
Y26 C232 AF26
VCCIO[8] 2 2 VCCCORE[6] 2 2 2

C234
1U_0402_6.3V4Z

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
2
AF23 VCCLAN[1] VCCSUS3_3[1] V28 AF30 VCCCORE[8]
2
D
0.344A VCCSUS3_3[2] U28 AF31 VCCCORE[9] D
AF24 VCCLAN[2] VCCSUS3_3[3] U26 AH26 VCCCORE[10]
PAD T50 VCCSUS3_3[4] U24 AH28 VCCCORE[11]
VCCSUS3_3[5] P28 AH30 VCCCORE[12]
1 2 Y20 DCPSUSBYP VCCSUS3_3[6] P26 AH31 VCCCORE[13] 0.030A VCCALVDS AH38 1 R260 2
C233 0.1U_0402_10V6K N28 AJ30 0_0603_5%
VCCSUS3_3[7] VCCCORE[14]
VCCSUS3_3[8] N26 AJ31 VCCCORE[15] VSSA_LVDS AH39 Remove it if no problem found
AD38 VCCME[1] VCCSUS3_3[9] M28
M26 +3VALW
VCCSUS3_3[10] +1.05VS
AD39 L28 AP43 1 2

USB
+1.05VS VCCME[2] VCCSUS3_3[11] VCCTX_LVDS[1] 0_0603_5% R261
VCCSUS3_3[12] L26 0.059A VCCTX_LVDS[2] AP45

0.1U_0402_10V6K

0.1U_0402_10V6K
AD41 J28 AT46

LVDS
VCCME[3] VCCSUS3_3[13] VCCTX_LVDS[3]

C236

C237
VCCSUS3_3[14] J26 1 1 AK24 VCCIO[24] VCCTX_LVDS[4] AT45
+1.05VS_APLL
10U_0805_10V4K

10U_0805_10V4K

1U_0402_6.3V4Z
AF43 VCCME[4] VCCSUS3_3[15] H28
C235
1 H26 L2
VCCSUS3_3[16]
C240

C241

1 1 AF41 VCCME[5] 0.163AVCCSUS3_3[17] G28

2 2
1 2 BJ24 VCCAPLLEXP0.042A

10U_0805_10V4K
G26 @ 10UH_LB2012T100MR_20%_0805 AB34
VCCSUS3_3[18] VCC3_3[2]
AF42 VCCME[6] VCCSUS3_3[19] F28
2 +3VS

C238
2 2 1.998A VCCSUS3_3[20] F26 1 AN20 VCCIO[25] VCC3_3[3] AB35
V39 E28 AN22

HVCMOS
VCCME[7] VCCSUS3_3[21] VCCIO[26]
E26 AN23 AD35 1 2

Clock and Miscellaneous

VCCSUS3_3[22] @ VCCIO[27] VCC3_3[4] C239 0.1U_0402_10V6K
V41 VCCME[8] VCCSUS3_3[23] C28 AN24 VCCIO[28]
2
1U_0402_6.3V4Z

VCCSUS3_3[24] C26 AN26 VCCIO[29]

V42 VCCME[9] VCCSUS3_3[25] B27 AN28 VCCIO[30]
C242

1 VCCSUS3_3[26] A28 BJ26 VCCIO[31]

Y39 VCCME[10] VCCSUS3_3[27] A26 BJ28 VCCIO[32]
AT26 VCCIO[33]
Y41 U23 +1.05VS AT28
2 VCCME[11] VCCSUS3_3[28] VCCIO[34]
AU26 VCCIO[35]
Y42 V23 AU28 +1.8VS
VCCME[12] VCCIO[56] +1.05VS VCCIO[36]

1U_0402_6.3V4Z

1U_0402_6.3V4Z
AV26 VCCIO[37]

C244

C245
>1mA F24 ICH_V5REF_SUS 1 1 AV28 AT24 1 2
C243 V5REF_SUS VCCIO[38] VCCVRM[2] R349 0_0402_5%
AW26 VCCIO[39]
C 1 2 +VCCRTCEXT V9 AW28 C
DCPRTC VCCIO[40] +VCCP

DMI
0.1U_0402_10V6K BA26 AT16
2 2 VCCIO[41] VCCDMI[1]
ICH_V5REF_RUN
BA28 VCCIO[42] 0.061A
0.035A >1mA V5REF K49 BB26 VCCIO[43] VCCDMI[2] AU16
C246
1 2
1U_0603_10V4Z
+1.8VS AU24 VCCVRM[3] BB28 VCCIO[44]
PCI/GPIO/LPC

BC26 VCCIO[45]
+3VS

PCI E*
0.072A VCC3_3[8] J38 BC28 VCCIO[46] +V_NVRAM_VCCQ

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0603_6.3V6M
BB51 VCCADPLLA[1] BD26 VCCIO[47]
+V1.05S_VCCA_A_DPL BB53 L38 BD28
VCCADPLLA[2] VCC3_3[9] VCCIO[48]

C248

C249

C250
1 1 1 1 BE26 VCCIO[49] VCCPNAND[1] AM16

0.1U_0402_10V6K
0.073A M36 C247 BE28 AK16
VCC3_3[10] VCCIO[50] VCCPNAND[2]

C251
+V1.05S_VCCA_B_DPL BD51 0.357A 0.1U_0402_10V6K BG26 AK20 1
VCCADPLLB[1] VCCIO[51] VCCPNAND[3]
BD53 VCCADPLLB[2] VCC3_3[11] N36 BG28 VCCIO[52] VCCPNAND[4] AK19
+1.05VS 2 2 2 2
BH27 VCCIO[53] 0.156A VCCPNAND[5] AK15
AH23 VCCIO[21] VCC3_3[12] P36 VCCPNAND[6] AK13
2
AJ35 VCCIO[22] AN30 VCCIO[54] VCCPNAND[7] AM12
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

NAND / SPI
AH35 VCCIO[23] VCC3_3[13] U35 AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS
C252

C253

C254

1 1 1 VCCPNAND[9] AM15
AF34 VCCIO[2] 3.208A
VCC3_3[14] AD13 1 2 +3VS AN35 VCC3_3[1]
AH34 C255 0.1U_0402_10V6K
2 2 2 VCCIO[3]
+3VS
AF32 VCCIO[4] +1.05VS_VCCAPLL +1.05VS +1.8VS 1
R341
2
0_0402_5%
AT22 VCCVRM[1] 0.035A
VCCSATAPLL[1] AK3
1 2 +VCCSST V12 0.032A AK1 L3 +1.05VS_VCCFDIPLL BJ18 6mA AM8
DCPSST VCCSATAPLL[2] VCCFDIPLL VCCME3_3[1]

0.1U_0402_10V6K
0.1U_0402_10V6K 1 2 AM9
1U_0402_6.3V4Z VCCME3_3[2]

10U_0603_6.3V6M

C260
FDI
C256 +1.05VS AM23 0.085A AP11 1
VCCIO[1] VCCME3_3[3]
C258

C259
1 1 @ 10UH_LB2012T100MR_20%_0805 AP9
+V1.1A_INT_VCCSUS VCCME3_3[4]
1 2 Y22 DCPSUS
0.1U_0402_10V6K AH22
C257 VCCIO[9] @ @ 2
2 2 IBEXPEAK-M_FCBGA1071
B +3VALW P18 AT20 B
VCCSUS3_3[29] VCCVRM[4] +1.8VS
1 2 0.2A@3.3V U19
SATA

0.1U_0402_10V6K VCCSUS3_3[30] +1.05VS

PCI/GPIO/LPC

VCCIO[10] AH19
C261 U20 VCCSUS3_3[31]
VCCIO[11] AD20
1U_0402_6.3V4Z

U22 VCCSUS3_3[32]
C263

VCCIO[12] AF22 1
+3VS L4
AD19 +1.05VS L5 1 2 +1.05VS_VCCFDIPLL
VCCIO[13] +1.05VS
1 2 0.4A@3.3V V15 AF20 1 2 +V1.05S_VCCA_A_DPL @ 10UH_LB2012T100MR_20%_0805
0.1U_0402_10V6K VCC3_3[5] VCCIO[14] 2 10UH_LB2012T100MR_20%_0805
VCCIO[15] AF19 1
C262 V16 AH20 1 1
VCC3_3[6] VCCIO[16] + C265 C266

1
Y16 AB19 1U_0402_6.3V4Z 220U_D2_4VM_R15 10U_0603_6.3V6M
VCC3_3[7] VCCIO[17] C264 R264 @ @
VCCIO[18] AB20
+VCCP 2 2 2
VCCIO[19] AB22 0_0603_5%
AD22 +1.05VS
0.1A@1.1V VCCIO[20]
AT18

2
V_CPU_IO[1]
4.7U_0603_6.3V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

AA34 +PCH_VCC1_1_20 1 R265 2

CPU

VCCME[13] +5VALW +3VALW +5VS +3VS

C267

C268

C269

1 1 1 >1mA Y34 +PCH_VCC1_1_21 1 R266 2 0_0402_5% L6

VCCME[14] +PCH_VCC1_1_22 R267
AU18 V_CPU_IO[2] VCCME[15] Y35 1 2 0_0402_5% 1 2 +V1.05S_VCCA_B_DPL
AA35 +PCH_VCC1_1_23 1 R268 2 0_0402_5%
VCCME[16]

2
0_0402_5% 10UH_LB2012T100MR_20%_0805 1
2 2 2 R270 D4 R271 D5
1
RTC

C271 + C270 10_0402_5% 10_0402_5%

+RTCVCC
A12 VCCRTC 2mA 6mA VCCSUSHDA L30 1 2 +3VALW
HDA

1 R269 0_0402_5% 1U_0402_6.3V4Z 220U_D2_4VM_R15 CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2

1
2mA@3.3V IBEXPEAK-M_FCBGA1071 C272 2 2
0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V4Z ICH_V5REF_SUS ICH_V5REF_RUN

20 mils 20 mils
2
C275

C276

1 1
1 1
A C273 C274 A
0.1U_0402_10V6K_X5R 1U_0402_6.3V4Z_X5R
2 2
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(5/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 16 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

U4I U4H
AY7 VSS[159] VSS[259] H49 AB16 VSS[0]
B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 VSS[164] VSS[264] K47 AM19 VSS[4] VSS[83] AK34
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 VSS[166] VSS[266] L14 AA26 VSS[6] VSS[85] AK38
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 VSS[168] VSS[268] L2 AA30 VSS[8] VSS[87] AK46
D B7 L22 AA31 AK49 D
VSS[169] VSS[269] VSS[9] VSS[88]
BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 VSS[172] VSS[272] L40 AB15 VSS[12] VSS[91] AL2
BB20 VSS[173] VSS[273] L52 AB23 VSS[13] VSS[92] AL52
BB24 VSS[174] VSS[274] M12 AB30 VSS[14] VSS[93] AM11
BB30 VSS[175] VSS[275] M16 AB31 VSS[15] VSS[94] BB44
BB34 VSS[176] VSS[276] M20 AB32 VSS[16] VSS[95] AD24
BB38 VSS[177] VSS[277] N38 AB39 VSS[17] VSS[96] AM20
BB42 VSS[178] VSS[278] M34 AB43 VSS[18] VSS[97] AM22
BB49 VSS[179] VSS[279] M38 AB47 VSS[19] VSS[98] AM24
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 VSS[181] VSS[281] M46 AB8 VSS[21] VSS[100] AM28
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 VSS[184] VSS[284] M8 AD11 VSS[24] VSS[103] AM31
BC22 VSS[185] VSS[285] N24 AD12 VSS[25] VSS[104] AM32
BC32 VSS[186] VSS[286] P11 AD16 VSS[26] VSS[105] AM34
BC36 VSS[187] VSS[287] AD15 AD23 VSS[27] VSS[106] AM35
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 VSS[189] VSS[289] P30 AD31 VSS[29] VSS[108] AM39
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 P34 AD34 AU20 +3VS
VSS[191] VSS[291] VSS[31] VSS[110]
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 VSS[194] VSS[294] P47 AD46 VSS[34] VSS[113] AM49

1
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7
BE16 R52 AD7 AA50 R179
VSS[196] VSS[296] VSS[36] VSS[115] CRACK_BGA 25,35
BE20 VSS[197] VSS[297] T12 AE2 VSS[37] VSS[116] BB10

6
BE24 T41 AE4 AN32 100K_0402_5%
VSS[198] VSS[298] VSS[38] VSS[117] Q4A
BE30 T46 AF12 AN50

2
VSS[199] VSS[299] VSS[39] VSS[118]
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52 2N7002DW T/R7_SOT-363-6
C BE38 T5 AH49 AP12 2 C
VSS[201] VSS[301] VSS[41] VSS[120] 15 PCH_NCTF6
BE42 VSS[202] VSS[302] T8 AU4 VSS[42] VSS[121] AP42
BE46 U30 AF35 AP46

1
VSS[203] VSS[303] VSS[43] VSS[122]
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49
BE50 U32 AN34 AP5 +3VS
VSS[205] VSS[305] VSS[45] VSS[124]
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2
BF3 VSS[208] VSS[308] V11 AF49 VSS[48] VSS[127] AR52

1
BF49 P16 AF5 AT11 CRACK_BGA
VSS[209] VSS[309] VSS[49] VSS[128] R178
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48

3
BG24 V22 AG52 AT32 100K_0402_5%
VSS[212] VSS[312] VSS[52] VSS[131] Q4B
BG4 V30 AH11 AT36

2
VSS[213] VSS[313] VSS[53] VSS[132]
BG50 VSS[214] VSS[314] V31 AH15 VSS[54] VSS[133] AT41 2N7002DW T/R7_SOT-363-6
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47 15 PCH_NCTF7 5
BH15 VSS[216] VSS[316] V34 AH24 VSS[56] VSS[135] AT7
BH19 V35 AH32 AV12

4
VSS[217] VSS[317] VSS[57] VSS[136]
BH23 VSS[218] VSS[318] V38 AV18 VSS[58] VSS[137] AV16
BH31 V43 AH43 AV20 +3VS
VSS[219] VSS[319] VSS[59] VSS[138]
BH35 VSS[220] VSS[320] V45 AH47 VSS[60] VSS[139] AV24
BH39 VSS[221] VSS[321] V46 AH7 VSS[61] VSS[140] AV30
BH43 VSS[222] VSS[322] V47 AJ19 VSS[62] VSS[141] AV34

1
BH47 V49 AJ2 AV38 CRACK_BGA
VSS[223] VSS[323] VSS[63] VSS[142] R234
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46

6
C50 V8 AJ23 AV49 100K_0402_5%
VSS[226] VSS[326] VSS[66] VSS[145] Q5A
D51 W2 AJ26 AV5

2
VSS[227] VSS[327] VSS[67] VSS[146]
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8 2N7002DW T/R7_SOT-363-6
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14 15 PCH_NCTF19 2
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 Y15 AT5 AW2

1
VSS[231] VSS[331] VSS[71] VSS[150] +3VS
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
B E34 Y23 AK12 AW32 B
VSS[233] VSS[333] VSS[73] VSS[152]
E38 VSS[234] VSS[334] Y28 AM41 VSS[74] VSS[153] AW36
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40

1
E46 Y31 AK26 AW52 CRACK_BGA
VSS[236] VSS[336] VSS[76] VSS[155] R88
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43

3
E8 Y43 AK28 AY47 100K_0402_5%
VSS[239] VSS[339] VSS[79] VSS[158] Q5B
F49 Y46

2
VSS[240] VSS[340] IBEXPEAK-M_FCBGA1071
F5 VSS[241] VSS[341] P49 2N7002DW T/R7_SOT-363-6
G10 VSS[242] VSS[342] Y5 15 PCH_NCTF26 5
G14 VSS[243] VSS[343] Y6
G18 Y8

4
VSS[244] VSS[344]
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 AD51

BGA Ball Cracking Prevention and Detection

VSS[247] VSS[347]
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

IBEXPEAK-M_FCBGA1071

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(6/6)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 17 of 50
5 4 3 2 1

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 5 4 3 2 1

SATA HDD CONN.

Place caps.
near HDD
JHDD2

2CONN.
GND 1
2 SATA_PTX_C_DRX_P0 0.01U_0402_16V7K_X7R 1 C733 SATA_PTX_DRX_P0
A+ SATA_PTX_DRX_P0 12
3 SATA_PTX_C_DRX_N0 0.01U_0402_16V7K_X7R 1 2 C734 SATA_PTX_DRX_N0
A- SATA_PTX_DRX_N0 12
GND 4
5 SATA_PRX_C_DTX_N0 0.01U_0402_16V7K_X7R 1 2 C737 SATA_PRX_DTX_N0
D B- SATA_PRX_DTX_N0 12 D
6 SATA_PRX_C_DTX_P0 0.01U_0402_16V7K_X7R 1 2 C397 SATA_PRX_DTX_P0
B+ SATA_PRX_DTX_P0 12
GND 7

V33 8
V33 9
V33 10
GND 11
12 +5VS
GND
GND 13
V5 14

0.1U_0402_10V6K

1U_0603_10V4Z

10U_0805_10V4K

10U_0805_10V4K
V5 15

C383

C398

C738

C384
V5 16 +5VS 1 1 1 1
GND 17
+V_NVRAM_VCCQ 18
+3VS +3.3V_NVRAM Reserved
2 1 +3VS 19
NAND 0_0603_5%
R685

R684
2
@ 0_0603_5%
1
0_0603_5%
+1.8VS
GND
V12
V12
20
21
2 2 2 2

2 1 V12 22
R686 10U_0805_10V4K 0.33U_0603_16V4Z

Placea caps. near

1 1 1 1 1
0.01U_0402_16V7K 0.33U_0603_16V4Z 47U_B2_6.3V-M C729 C725 C722 C727 C721 SUYIN_127043FR022G528_22P_NR-T

HDD CONN.
1 CONN@
1 1 1 1 0.01U_0402_16V7K
C723 C726 C728 C720 + C724 2 2 2 2 2
1U_0603_10V4Z 0.033U_0402_16V4Z

40
41
42

38
39
78
1
2
3
JP14
2 2 2 2 2

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6

VCCQ_1
VCCQ_2
VCCQ_3
0.033U_0402_16V4Z 1U_0603_10V4Z

6 9 TP_NV_DOS_0# PAD T119

C 15 NV_DQ0 DQ0 DOS_0# C
15 NV_DQ1 7 DQ1 DOS_0 10 NV_DQS0 15
45 31 TP_NV_DOS_1# PAD T114
15 NV_DQ2 DQ2 DOS_1#
15 NV_DQ3 46 DQ3 DOS_1 32 NV_DQS1 15
15 NV_DQ4 12 DQ4
13 15 TP_NV_RFU_1 PAD T117
15 NV_DQ5 DQ5 RFU_1
51 16 TP_NV_RFU_2 PAD T120
15 NV_DQ6 DQ6 RFU_2 TP_NV_RFU_3
Place caps.
52 63
15 NV_DQ7
15 NV_DQ8 28
DQ7
DQ8
RFU_3
RFU_4 64 TP_NV_RFU_4
PAD
PAD
T112
T115
SATA ODD CONN.
near ODD
29 CONN@
15 NV_DQ9 DQ9
67 24 JODD2
CONN.
15 NV_DQ10 DQ10 CE_0#
68 25 NV_CE0#
15 NV_DQ11 DQ11 CE_2# NV_CE0# 15
15 NV_DQ12 34 DQ12 CE_1# 22 GND 1
35 61 NV_CE1# 2 SATA_PTX_C_DRX_P1 0.01U_0402_16V7K_X7R 1 2 C377 SATA_PTX_DRX_P1
15 NV_DQ13 DQ13 CE_3# NV_CE1# 15 A+ SATA_PTX_DRX_P1 12
73 4 3 SATA_PTX_C_DRX_N1 0.01U_0402_16V7K_X7R 1 2 C730 SATA_PTX_DRX_N1
15 NV_DQ14 DQ14 CE_4# A- SATA_PTX_DRX_N1 12
74 43 NV_CE2# 4
15 NV_DQ15 DQ15 CE_6# NV_CE2# 15 GND
37 5 SATA_PRX_C_DTX_N1 0.01U_0402_16V7K_X7R 1 2 C732 SATA_PRX_DTX_N1
CE_5# B- SATA_PRX_DTX_N1 12
76 NV_CE3# 6 SATA_PRX_C_DTX_P1 0.01U_0402_16V7K_X7R 1 2 C385 SATA_PRX_DTX_P1
CE_7# NV_CE3# 15 B+ SATA_PRX_DTX_P1 12
18 48 TP_NV_CK_0# PAD T118 09/23 HP
NV_CLE CLE_0 CK_0#
15 NV_CLE 57 CLE_1 CK_0/WE_0# 49 NV_WE#_CK0 15 GND 7
19 70 TP_NV_CK_1# PAD T111 8 R302 1 2 @ 0_0402_5%
ALE_0 CK_1# DP ODD_DET# 15
NV_ALE 58 71 9
15 NV_ALE ALE_1 CK_1/WE_1# NV_WE#_CK1 15 V5
V5 10 +5VS 09/28 HP 1
54 11 C757
R/B# NV_RB# 15 MD
60 55 TP_NV_WP0# PAD T116 12
15 NV_RE#_WR#1 W/R_1#/RE_1# WP# GND
21 13 @ 0.1U_0402_10V6K
15 NV_RE#_WR#0 W/R_0#/RE_0# GND 2
77 TP_NV_VREF PAD T121
VREF
FOX_LN21133-D005-9F_13P_NR
5 VSS_1 VSS_13 44
8 VSS_2 VSS_14 47
11 50 +5VS
B VSS_3 VSS_15 B
14 VSS_4 VSS_16 53
17 VSS_5 VSS_17 56

10U_0805_10V4K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
20 VSS_6 VSS_18 59
23 VSS_7 VSS_19 62

C376

C735

C736

C731
26 VSS_8 VSS_20 65 1 1 1 1
27 VSS_9 VSS_21 66
30 VSS_10 VSS_22 69
33 VSS_11 VSS_23 72
2 2 2 2
36 VSS_12 VSS_24 75

NVRAM Connector

Placea caps. near

ODD CONN.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 18 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 A B C D E

VGA_BLU
VGA_GRN
CRT Connector VGA_RED
D_HSYNC
D_VSYNC

+5VS +RCRT_VCC +CRTVDD

PJDLC05_SOT23-3

PJDLC05_SOT23-3

PJDLC05_SOT23-3

PJDLC05_SOT23-3

PJDLC05_SOT23-3
D7

D8

D9

D10

D11
F1 D6

1
1.1A_6VDC_FUSE CH491D_SC59
1 2 2 1
W=40mils
1 +CRTVDD
C277 @ @ @ @ @

3
1 1
0.1U_0402_10V6K
10/17 HP 2 suyin_070912fr015s207cr_15p
JP4
09/30 HP 6
11
R294 1 2 VGA_RE R472 1 2 0_0805_5% VGA_R 1
33 VGA_RED
0_0805_5% 7
D_DDCDATA 12
R304 1 2 VGA_GR R473 1 2 0_0805_5% VGA_G 2
33 VGA_GRN
0_0805_5% 8
13
R318 1 2 VGA_BL R565 1 2 0_0805_5% VGA_B 3
33 VGA_BLU

@ 10P_0402_50V8J

@ 10P_0402_50V8J

@ 10P_0402_50V8J
0_0805_5% 9
14 16

2
R334
150_0402_1%

R323
150_0402_1%

R322
150_0402_1%

C350

C343

C342
1 1 1 4 17
10
+5VS +5VS 10/17 HP D_DDCCLK 15 CONN@
5
C284 C285 2 2 2

1
0.1U_0402_10V6K 0.1U_0402_10V6K
1 2 1 2

+CRTVDD +3VS_VGA
5

U6
D_HSYNC 33
74AHCT1G125GW_SOT353-5
P

OE#

2 4 HSYNC R276 1 2 33_0402_5% D_HSYNC

23 CRT_HSYNC A Y

R279

R280

R281

R277
G

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
U7
D_VSYNC 33
P

OE#
3

2 2 4 VSYNC R278 1 2 33_0402_5% D_VSYNC 2

23 CRT_VSYNC A Y
G

2
2
74AHCT1G125GW_SOT353-5 Q9

G
1 1
3

C286 C287
33 D_DDCDATA 1 2 1 3 CRT_DDC_DATA 23
5P_0402_50V8C 5P_0402_50V8C R688 0_0402_5%

S
2 2
L Place cloce to U8

2
2N7002_SOT23-3 Q10

G
33 D_DDCCLK 1 2 1 3 CRT_DDC_CLK 23
R689 0_0402_5%

S
D_HSYNC & D_VSYNC 2N7002_SOT23-3
09/23 ATI L should be routed to
docking connector then L Place cloce to U8
to VGA connector

Place cloce to U8 need update P/N

3 L 3

L7 L8
0805CS-390XJLC_0805 0805CS-111XJLC_0805
23 DAC_RED DAC_RED 1 2 DAC_RE 1 2 RED_R 33
L9 L10
0805CS-390XJLC_0805 0805CS-111XJLC_0805
23 DAC_GRN DAC_GRN 1 2 DAC_GR 1 2 GREEN_R 33
L11 L12
0805CS-390XJLC_0805 0805CS-111XJLC_0805
23 DAC_BLU DAC_BLU 1 2 DAC_BL 1 2 BLUE_R 33
18P_0402_50V8J

18P_0402_50V8J

18P_0402_50V8J
C281

C282

C283
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1
R273 1

R274 1

R275 1

10/17 HP 10/17 HP
2 2 2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 19 of 50
A B C D E

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

+3VS

LCD/PANEL BD. CONN.

1
R293
10/03 HP 10K_0402_5%

2
D30
JLVDS1
DISP_OFF# 2 1 ENABLT ENABLT 23

1
1 1
D 2 R286 D
2 LVDS_ACLKP 21
3 CH751H-40PT_SOD323-2 100K_0402_5%
3 LVDS_ACLKN 21
4 4
5 LVDS_A0P 21

2
5
6 6 LVDS_A0N 21 D31
7 7 LVDS_A1P 21
8 LVDS_A1N 21 2 1 LID_SW# LID_SW# 12,30,35
8
9 9 LVDS_A2P 21
10 10 LVDS_A2N 21
11 CH751H-40PT_SOD323-2
11
12 12 LVDS_BCLKP 21
13 13 LVDS_BCLKN 21
14 14
15 15 LVDS_B0P 21
16 16 LVDS_B0N 21
17 17 LVDS_B1P 21
18 18 LVDS_B1N 21
19 19 LVDS_B2P 21
20 20 LVDS_B2N 21
21 21
22 USB20_P12_R 0_0402_5% 2 1 R287 +5VS +5VS Q15 +5V_WEBCAM
22 USB20_P12 15
23 USB20_N12_R 0_0402_5% 2 1 R288 SI2301BDS_SOT23
23 USB20_N12 15
24 D12
24

D
25 EDID_CLK 4 2 USB20_P12_R 3 1 09/24 HP
25 EDID_CLK 23 VIN IO1
26 EDID_DATA
26 EDID_DATA 23

1U_0603_10V4Z

100K_0402_5%

0.01U_0402_16V7K

0.1U_0402_10V6K

4.7U_0805_10V4Z
27 INV_PWM USB20_N12_R 3 1
27 INV_PWM 21 IO2 GND

1
C292

R290
DISP_OFF#

G
28 1

2
28

@ 47P_0402_50V8J

C293

C294

C295
29 DAC_BRIG PJLCR05_SOT143-4 1 1 1
29

1
+3VALW

C751
30 30 1

2
31 R691 680P_0402_50V7K
31 C297 2
32

2
32 1K_0402_5% 2 2 2
33 33

1
C 2 C
34 34 +5V_WEBCAM
35 +3VS R291 1 2
+3VS

1
35 10K_0402_5% R292 47K_0402_5%
36 36 +LCDVDD
37 37
38

2
38

6
39 +5VS
39 INVPWR_B+ 1
40 C298
40

1
41 C291 0.1U_0402_10V6K
41 680P_0402_50V7K
42 42 2
Q16A 2

2
09/30 HP R249 1 2 2N7002DW T/R7_SOT-363-6
+3VALW

1
ACES 20415-4006 22P
CONN@ 15 WEBCAM_OFF 100K_0402_5%

10/01 Change the footprint

+LCDVDD INVPWR_B+ B+
09/24 HP 09/24 HP
1 2
R285 0_0805_5%
680P_0402_50V7K

680P_0402_50V7K
@ 47P_0402_50V8J

C289

@ 47P_0402_50V8J

C290

1 1
1

1
C749

C750
2

2 2

LCD POWER CIRCUIT

+LCDVDD +LCDVDD
B B

1
Q17
R295 3 SI2301BDS_SOT23

S
1 +3VS
100_0402_1%

G
3 2

2
R296 1 2 150K_0402_1%

5 R297 1 2 47K_0402_5% C299 1 2 0.1U_0402_10V6K

2N7002DW T/R7_SOT-363-6 1 1 1

4
Q16B C300 C301 C302
0.1U_0402_10V6K 4.7U_0805_10V4Z 4.7U_0805_10V4Z

1
@
2 2 2

OUT
21 ENAVDD 2 IN Q19

GND
DTC124EKAT146_SC59-3

1
R298

3
100K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN & Q-Switch & GPIO Ext.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 20 of 50
5 4 3 2 1

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 A B C D E

1 1

PEG Interface
U8A

AF30 AH30 PCIE_CRX_GTX_G_P15 0.1U_0402_10V6K 2 1 C333 PCIE_CRX_GTX_P15 5

5 PCIE_CTX_GRX_P15 PCIE_RX0P PCIE_TX0P
AE31 AG31 PCIE_CRX_GTX_G_N15 0.1U_0402_10V6K 2 1 C334 PCIE_CRX_GTX_N15 5
5 PCIE_CTX_GRX_N15 PCIE_RX0N PCIE_TX0N

AE29 AG29 PCIE_CRX_GTX_G_P14 0.1U_0402_10V6K 2 1 C331 PCIE_CRX_GTX_P14 5

5 PCIE_CTX_GRX_P14 PCIE_RX1P PCIE_TX1P
AD28 AF28 PCIE_CRX_GTX_G_N14 0.1U_0402_10V6K 2 1 C332 PCIE_CRX_GTX_N14 5
5 PCIE_CTX_GRX_N14 PCIE_RX1N PCIE_TX1N

LVDS Interface 5 PCIE_CTX_GRX_P13

5 PCIE_CTX_GRX_N13
AD30
AC31
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
AF27
AF26
PCIE_CRX_GTX_G_P13
PCIE_CRX_GTX_G_N13
0.1U_0402_10V6K
0.1U_0402_10V6K
2
2
1
1
C329
C330
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
5
5

AC29 AD27 PCIE_CRX_GTX_G_P12 0.1U_0402_10V6K 2 1 C327 PCIE_CRX_GTX_P12 5

5 PCIE_CTX_GRX_P12 PCIE_RX3P PCIE_TX3P
AB28 AD26 PCIE_CRX_GTX_G_N12 0.1U_0402_10V6K 2 1 C328 PCIE_CRX_GTX_N12 5
5 PCIE_CTX_GRX_N12 PCIE_RX3N PCIE_TX3N
U8F

AB30 AC25 PCIE_CRX_GTX_G_P11 0.1U_0402_10V6K 2 1 C325 PCIE_CRX_GTX_P11 5

5 PCIE_CTX_GRX_P11 PCIE_RX4P PCIE_TX4P

PCI EXPRESS INTERFACE

R300 1 2 10K_0402_5% AA31 AB25 PCIE_CRX_GTX_G_N11 0.1U_0402_10V6K 2 1 C326 PCIE_CRX_GTX_N11 5
5 PCIE_CTX_GRX_N11 PCIE_RX4N PCIE_TX4N
LVDS CONTROL AB11 R299 1 2 0_0402_5% INV_PWM 20
VARY_BL R301 1 0_0402_5%
DIGON AB12 2 ENAVDD 20
AA29 Y23 PCIE_CRX_GTX_G_P10 0.1U_0402_10V6K 2 1 C323 PCIE_CRX_GTX_P10 5
5 PCIE_CTX_GRX_P10 PCIE_RX5P PCIE_TX5P
Y28 Y24 PCIE_CRX_GTX_G_N10 0.1U_0402_10V6K 2 1 C324 PCIE_CRX_GTX_N10 5
5 PCIE_CTX_GRX_N10 PCIE_RX5N PCIE_TX5N
2 2

AH20 Y30 AB27 PCIE_CRX_GTX_G_P9 0.1U_0402_10V6K 2 1 C321 PCIE_CRX_GTX_P9 5

TXCLK_UP_DPF3P LVDS_BCLKP 20 5 PCIE_CTX_GRX_P9 PCIE_RX6P PCIE_TX6P
AJ19 W31 AB26 PCIE_CRX_GTX_G_N9 0.1U_0402_10V6K 2 1 C322 PCIE_CRX_GTX_N9 5
TXCLK_UN_DPF3N LVDS_BCLKN 20 5 PCIE_CTX_GRX_N9 PCIE_RX6N PCIE_TX6N

TXOUT_U0P_DPF2P AL21 LVDS_B0P 20

AK20 LVDS_B0N 20 W29 Y27 PCIE_CRX_GTX_G_P8 0.1U_0402_10V6K 2 1 C319 PCIE_CRX_GTX_P8 5
TXOUT_U0N_DPF2N 5 PCIE_CTX_GRX_P8 PCIE_RX7P PCIE_TX7P
V28 Y26 PCIE_CRX_GTX_G_N8 0.1U_0402_10V6K 2 1 C320 PCIE_CRX_GTX_N8 5
5 PCIE_CTX_GRX_N8 PCIE_RX7N PCIE_TX7N
AH22 LVDS_B1P 20
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N AJ21 LVDS_B1N 20
V30 W24 PCIE_CRX_GTX_G_P7 0.1U_0402_10V6K 2 1 C317 PCIE_CRX_GTX_P7 5
5 PCIE_CTX_GRX_P7 PCIE_RX8P PCIE_TX8P
AL23 LVDS_B2P 20 U31 W23 PCIE_CRX_GTX_G_N7 0.1U_0402_10V6K 2 1 C318 PCIE_CRX_GTX_N7 5
TXOUT_U2P_DPF0P 5 PCIE_CTX_GRX_N7 PCIE_RX8N PCIE_TX8N
AK22 LVDS_B2N 20
TXOUT_U2N_DPF0N
AK24 U29 V27 PCIE_CRX_GTX_G_P6 0.1U_0402_10V6K 2 1 C315 PCIE_CRX_GTX_P6 5
TXOUT_U3P 5 PCIE_CTX_GRX_P6 PCIE_RX9P PCIE_TX9P
AJ23 T28 U26 PCIE_CRX_GTX_G_N6 0.1U_0402_10V6K 2 1 C316 PCIE_CRX_GTX_N6 5
TXOUT_U3N 5 PCIE_CTX_GRX_N6 PCIE_RX9N PCIE_TX9N

LVTMDP T30 U24 PCIE_CRX_GTX_G_P5 0.1U_0402_10V6K 2 1 C313 PCIE_CRX_GTX_P5 5

5 PCIE_CTX_GRX_P5 PCIE_RX10P PCIE_TX10P
R31 U23 PCIE_CRX_GTX_G_N5 0.1U_0402_10V6K 2 1 C314 PCIE_CRX_GTX_N5 5
5 PCIE_CTX_GRX_N5 PCIE_RX10N PCIE_TX10N
AL15 LVDS_ACLKP 20
TXCLK_LP_DPE3P
AK14 LVDS_ACLKN 20
TXCLK_LN_DPE3N PCIE_CRX_GTX_G_P4 0.1U_0402_10V6K C311
5 PCIE_CTX_GRX_P4 R29 T26 2 1 PCIE_CRX_GTX_P4 5
PCIE_RX11P PCIE_TX11P PCIE_CRX_GTX_G_N4 0.1U_0402_10V6K C312
TXOUT_L0P_DPE2P AH16 LVDS_A0P 20 5 PCIE_CTX_GRX_N4 P28 PCIE_RX11N PCIE_TX11N T27 2 1 PCIE_CRX_GTX_N4 5
AJ15 LVDS_A0N 20
TXOUT_L0N_DPE2N
AL17 LVDS_A1P 20 P30 T24 PCIE_CRX_GTX_G_P3 0.1U_0402_10V6K 2 1 C310 PCIE_CRX_GTX_P3 5
TXOUT_L1P_DPE1P 5 PCIE_CTX_GRX_P3 PCIE_RX12P PCIE_TX12P
AK16 LVDS_A1N 20 N31 T23 PCIE_CRX_GTX_G_N3 0.1U_0402_10V6K 2 1 C303 PCIE_CRX_GTX_N3 5
TXOUT_L1N_DPE1N 5 PCIE_CTX_GRX_N3 PCIE_RX12N PCIE_TX12N
AH18 LVDS_A2P 20
TXOUT_L2P_DPE0P PCIE_CRX_GTX_G_P2 0.1U_0402_10V6K C308
AJ17 LVDS_A2N 20 5 PCIE_CTX_GRX_P2 N29 P27 2 1 PCIE_CRX_GTX_P2 5
TXOUT_L2N_DPE0N PCIE_RX13P PCIE_TX13P PCIE_CRX_GTX_G_N2 0.1U_0402_10V6K C309
5 PCIE_CTX_GRX_N2 M28 P26 2 1 PCIE_CRX_GTX_N2 5
PCIE_RX13N PCIE_TX13N
AL19
TXOUT_L3P
AK18
TXOUT_L3N PCIE_CRX_GTX_G_P1 0.1U_0402_10V6K C306
5 PCIE_CTX_GRX_P1 M30 P24 2 1 PCIE_CRX_GTX_P1 5
PCIE_RX14P PCIE_TX14P PCIE_CRX_GTX_G_N1 0.1U_0402_10V6K C307
5 PCIE_CTX_GRX_N1 L31 P23 2 1 PCIE_CRX_GTX_N1 5
PCIE_RX14N PCIE_TX14N

216-0728002 A11 M92-S2_FCBGA631 L29 M27 PCIE_CRX_GTX_G_P0 0.1U_0402_10V6K 2 1 C304 PCIE_CRX_GTX_P0 5

5 PCIE_CTX_GRX_P0 PCIE_RX15P PCIE_TX15P
K30 N26 PCIE_CRX_GTX_G_N0 0.1U_0402_10V6K 2 1 C305 PCIE_CRX_GTX_N0 5
3 5 PCIE_CTX_GRX_N0 PCIE_RX15N PCIE_TX15N 3

CLOCK
13 CLK_PEG_PCH 1 4 RP6 CLK_PEG_VGA AK30 PCIE_REFCLKP
2 3 CLK_PEG_VGA# AK32
13 CLK_PEG_PCH# PCIE_REFCLKN
0_4P2R_5%
CK32@
CALIBRATION
Y22 R303 1 2 1.27K_0402_1%
Remove after DB2 PCIE_CALRP
N10 AA22 R305 1 2 2K_0402_1% +1.1VS
NC_PWRGOOD PCIE_CALRN

4,12,15,27,29,32,34 PLT_RST# AL27 PERSTB

216-0728002 A11 M92-S2_FCBGA631

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PEG & LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 21 of 50
A B C D E

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

D D

U8C

MDA0 K27 K17 MAA0

MDA[0..63] MDA1 DQA_0 MAA_0 MAA1
J29 DQA_1 MAA_1 J20
26 MDA[0..63] MDA2 MAA2
H30 DQA_2 MAA_2 H23
MDA3 H32 G23 MAA3
MDA4 DQA_3 MAA_3 MAA4
G29 G24

MEMORY INTERFACE
MDA5 DQA_4 MAA_4 MAA5
F28 DQA_5 MAA_5 H24
MDA6 F32 J19 MAA6 MAA[12..0]
+1.5VS DQA_6 MAA_6 MAA[12..0] 26
MDA7 F30 K19 MAA7
MDA8 DQA_7 MAA_7 MAA8 A_BA[2..0]
C30 DQA_8 MAA_8 J14 A_BA[2..0] 26
MDA9 F27 K14 MAA9
DQA_9 MAA_9

1
MDA10 A28 J11 MAA10
R306 MDA11 DQA_10 MAA_10 MAA11
C28 DQA_11 MAA_11 J13
40.2_0402_1% MDA12 E27 H11 MAA12
MDA13 DQA_12 MAA_12 A_BA2
G26 DQA_13 MAA_13/BA2 G11
MDA14 D26 J16 A_BA0

2
MDA15 DQA_14 MAA_14/BA0 A_BA1
F25 DQA_15 MAA_15/BA1 L15
+VDD_MEM15_REFD MDA16 A25 DQA_16 DQMA#[7..0] 26
MDA17 C25 E32 DQMA#0
MDA18 DQA_17 DQMA_0 DQMA#1
1 E25 DQA_18 DQMA_1 E30

1
C335 MDA19 D24 A21 DQMA#2
R307 0.1U_0402_10V6K MDA20 DQA_19 DQMA_2 DQMA#3
E23 DQA_20 DQMA_3 C21
100_0402_1% MDA21 F23 E13 DQMA#4
2 MDA22 DQA_21 DQMA_4 DQMA#5
D22 DQA_22 DQMA_5 D12
MDA23 F21 E3 DQMA#6

2
C MDA24 DQA_23 DQMA_6 DQMA#7 C
E21 DQA_24 DQMA_7 F4
MDA25 D20 DQA_25 QSA[7..0] 26
MDA26 F19 H28 QSA0
MDA27 DQA_26 RDQSA_0 QSA1
A19 DQA_27 RDQSA_1 C27
MDA28 D18 A23 QSA2
MDA29 DQA_28 RDQSA_2 QSA3
F17 DQA_29 RDQSA_3 E19
+1.5VS MDA30 A17 E15 QSA4
MDA31 DQA_30 RDQSA_4 QSA5
C17 DQA_31 RDQSA_5 D10
MDA32 E17 D6 QSA6
DQA_32 RDQSA_6
1

MDA33 D16 G5 QSA7

DQA_33 RDQSA_7 QSA#[7..0] 26
R308 MDA34 F15
40.2_0402_1% MDA35 DQA_34 QSA#0
A15 DQA_35 W DQSA_0 H27
MDA36 D14 A27 QSA#1
MDA37 DQA_36 W DQSA_1 QSA#2
F13 C23
2

MDA38 DQA_37 W DQSA_2 QSA#3

A13 DQA_38 W DQSA_3 C19
+VDD_MEM15_REF1 MDA39 C13 C15 QSA#4
MDA40 DQA_39 W DQSA_4 QSA#5
E11 DQA_40 W DQSA_5 E9
1 MDA41 A11 C5 QSA#6
DQA_41 W DQSA_6
1

C336 MDA42 C11 H4 QSA#7

R309 0.1U_0402_10V6K MDA43 DQA_42 W DQSA_7
F11 DQA_43
100_0402_1% MDA44 A9 L18 ODTA0
2 DQA_44 ODTA0 ODTA0 26
MDA45 C9 K16 ODTA1
DQA_45 ODTA1 ODTA1 26
MDA46 F9
2

MDA47 DQA_46 CLKA0

D8 DQA_47 CLKA0 H26 CLKA0 26
MDA48 E7 H25 CLKA0#
DQA_48 CLKA0B CLKA0# 26
MDA49 A7
MDA50 DQA_49 CLKA1
C7 DQA_50 CLKA1 G9 CLKA1 26
MDA51 F7 H9 CLKA1#
DQA_51 CLKA1B CLKA1# 26
MDA52 A5
B MDA53 DQA_52 RASA0# B
E5 DQA_53 RASA0B G22 RASA0# 26
MDA54 C3 G17 RASA1#
DQA_54 RASA1B RASA1# 26
MDA55 E1
MDA56 DQA_55 CASA0#
G7 DQA_56 CASA0B G19 CASA0# 26
MDA57 G6 G16 CASA1#
DQA_57 CASA1B CASA1# 26
MDA58 G1
MDA59 DQA_58 CSA0#_0
G3 DQA_59 CSA0B_0 H22 CSA0#_0 26
MDA60 J6 J22
MDA61 DQA_60 CSA0B_1
J1 DQA_61
MDA62 J3 G13 CSA1#_0
+1.5VS +1.5VS DQA_62 CSA1B_0 CSA1#_0 26
MDA63 J5 K13
DQA_63 CSA1B_1
+VDD_MEM15_REFD K26 K20 CKEA0
MVREFDA CKEA0 CKEA0 26
+VDD_MEM15_REF1 J26 J17 CKEA1
MVREFSA CKEA1 CKEA1 26
1

R310 1 2 @ 243_0402_1% J25 G25 WEA0#

NC_MEM_CALRN0 W EA0B WEA0# 26
R311 R312 1 2 @ 243_0402_1% K7 H10 WEA1#
NC_MEM_CALRN1 W EA1B WEA1# 26
4.7K_0402_5%
R313 1 2 243_0402_1% J8 AB16 R745 1 2 0_0402_5%
MEM_CALRP1 RSVD#1 HDMI_CEC 23
R314 1 2 @ 243_0402_1% K25 G14 R751 1 2 0_0402_5%
2

NC_MEM_CALRP0 RSVD#2 DP_CEC 33

G20 R752 1 2 0_0402_5%
RSVD#3 DP_CEC2 33
L10 DRAM_RST
26 DRAM_RST#
1U_0402_6.3V4Z
R315

K8 CLKTESTA
L7 CLKTESTB
2

C337

1
216-0728002 A11 M92-S2_FCBGA631
1

A 2 A
R316 R317
1
@ 4.7K_0402_5%

4.7K_0402_5% 4.7K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Memory Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 22 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

U8B
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 10K RESISTOR
M93-S3/M92-S2 AF2 HDMI_CLK+_VGA X = DESIGN DEPENDANT
L44 TXCAP_DPA3P HDMI_CLK-_VGA THEY MUST NOT CONFLICT DURING RESET
AE9 AF4 NA = NOT APPLICABLE
+DPC_PVDD DVCNTL_0/ DVPDATA_18 TXCAM_DPA3N
+1.8VS 2 1 L9 DVCNTL_1 / NC
BLM18PG121SN1D_0603 N9 AG3 HDMI_TX0+_VGA
M93@ DVCNTL_2 / NC TX0P_DPA2P STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS

C643

C469

C520
1 1 1 AE8 DPA AG5 HDMI_TX0-_VGA RECOMMENDED SETTINGS

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
DVDATA_12 / DVPDATA_16 TX0M_DPA2N
AD9 DVDATA_11 / DVPDATA_20
AC10 AH3 HDMI_TX1+_VGA +3VS_VGA
2 2 2
AD7
DVDATA_10 / DVPDATA_22
DVDATA_9 / DVPDATA_12
TX1P_DPA1P
TX1M_DPA1N AH1 HDMI_TX1-_VGA STRAPS TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0
AC8 DVDATA_8 / DVPDATA_14

M93@

M93@

M93@
AC7 AK3 HDMI_TX2+_VGA
DVDATA_7 / DVPCNTL_0 TX2P_DPA0P HDMI_TX2-_VGA TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
AB9 AK1
DVDATA_6 / DVPDATA_8 TX2M_DPA0N @ R333
AB8 DVDATA_5 / DVPDATA_6
GPU_GPIO0 2 1 10K_0402_5%
AB7 AK5 GPU_GPIO1 @ R321 2 1 10K_0402_5%
DVDATA_4 DVPDATA_4 TXCBP_DPB3P DPB_TXP3 33
AB4 AM3 GPU_GPIO2 @ R335 2 1 10K_0402_5% BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 0
DVDATA_3 / DVPDATA_19 TXCBM_DPB3N DPB_TXN3 33
D
AB2 DVDATA_2 / DVPDATA_21 D
L28 Y8 AK6 GPU_GPIO8 @ R336 2 1 10K_0402_5%
DVDATA_1 / DVPDATA_2 TX3P_DPB2P DPB_TXP2 33
+1.8VS 2 1 +DPC_VDD18 Y7 AM5 GPU_GPIO9 @ R337 2 1 10K_0402_5% GPIO8 0
DVDATA_0 / DVPDATA_0 TX3M_DPB2N DPB_TXN2 33
BLM18PG121SN1D_0603 DPB GPU_GPIO21 @ R339 2 1 10K_0402_5%
M93@
C381

C378

C380
1
10U_0603_6.3V6M 1 1 AJ7

0.1U_0402_10V6K
1U_0402_6.3V4Z
TX4P_DPB1P DPB_TXP1 33
DVO AH6 GPU_GPIO11 R338 2 1 10K_0402_5% BIF_VGA DIS GPIO9 VGA ENABLED 0
TX4M_DPB1N DPB_TXN1 33
GPU_GPIO12 @ R342 2 1 10K_0402_5%
AK8 GPU_GPIO13 @ R343 2 1 10K_0402_5%
2 2 2 TX5P_DPB0P DPB_TXP0 33
AL7 GPIO21 0
TX5M_DPB0N DPB_TXN0 33
M93@

M93@

M93@
M93-S3/M92-S2 CRT_VSYNC R345 2 1 10K_0402_5%
+DPC_PVDD W6 CRT_HSYNC R346 2 1 10K_0402_5% BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
DPC_PVDD / DVPDATA_11 VSYNC_DAC2 @ R347 10K_0402_5%
V6
DPC_PVSS / GND M92-S2/M93-S3 2 1
V4 HSYNC_DAC2 @ R348 2 1 10K_0402_5%
DVPDATA_3/TXCCP_DPC3P DPC_TXP3 33
+DPC_VDD18 AC6 U5 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 001
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N DPC_TXN3 33
L29 1 2 M93@ 0_0402_5% AC5
+DPC_VDD10 R666 DPC_VDD18#2/DVPDAT23
+1.1VS 2 1 DVPDATA_7 / TX0P_DPC2P W3 DPC_TXP2 33
BLM18PG121SN1D_0603 +DPC_VDD10 AA5 V2 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
DPC_VDD10#1/DVPDAT15 DVPDATA_1 / TX0M_DPC2N DPC_TXN2 33
M93@ 2 M93@ 0_0402_5%
C457

C379

C382

1 1 1 1 AA6
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

R667 DPC_VDD10#2/DVPDAT17
Y4 DPC_TXP1 33
DVPCNTL_MV1 / TX1P_DPC1P H2SYNC 0
W5 DPC_TXN1 33
DVPDATA_9 / TX1M_DPC1N
2 2 2
1 2 M93@ 0_0402_5% U1 DPC_VSSR#1 / DVPCLK DVPDATA_13 / TX2P_DPC0P AA3 DPC_TXP0 33
M93@

M93@

M93@

R661 1 2 M93@ 0_0402_5% W1 Y2 GENERICC 0

DPC_VSSR#2 / DVPDAT5 DVPCNTL_1 / TX2M_DPC0N DPC_TXN0 33
R662 U3
+3VS_VGA DPC_VSSR#3 / GND AUD[1] AUD[0]
Y6 AA12 1 2 +VDDR4
R332 1 DPC_VSSR#4 / GND VDDR4 / DPCD_CALR
2 M93@ 0_0402_5% AA1 DPC_VSSR#5/ DVPCNTL_MV0
R544 M92@ 0_0402_5% AUD[1] HSYNC 0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
1 2 AUD[0] VSYNC 1 0 Audio for DisplayPort only
DPC R545 M93@ 150_0402_1% 1 1 Audio for both DisplayPort and HDMI
1

R324 R344
4.7K_0402_5% 4.7K_0402_5% EDID_CLK R1
20 EDID_CLK
20 EDID_DATA
EDID_DATA R3
SCL
I2C AMD RESERVED CONFIGURATION STRAPS
2

SDA
EDID_CLK AM26 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
R DAC_RED 19
EDID_DATA GENERAL PURPOSE I/O AK26
+3VS_VGA GPU_GPIO0 RB THEY MUST NOT CONFLICT DURING RESET
U6
GPU_GPIO1 GPIO_0
U10 AL25 DAC_GRN 19
GPU_GPIO2 GPIO_1 G
C T10 GPIO_2 GB AJ25 C
THERM_DAT U8 H2SYNC GENERICC
R325 1 GPIO_3_SMBDATA
2@ 10K_0402_5% VGA_PWRSEL THERM_CLK U7 AH24 DAC_BLU 19
R326 1 GPIO_4_SMBCLK B
2@ 10K_0402_5% GPIO23_CLKREQB
14,35,38 AC_PRESENT T9 AG25
GPIO_5_AC_BATT BB
R327 T75
T8
GPIO_6 DAC1 PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
1 2@ 10K_0402_5% GPIO24_TRSTB
20 ENABLT T7 GPIO_7_BLON HSYNC AH26 CRT_HSYNC CRT_HSYNC 19
R328 1 2@ 10K_0402_5% GPIO25_TDI GPU_GPIO8 P10 AJ27 CRT_VSYNC
CRT_VSYNC 19
THEY MUST NOT CONFLICT DURING RESET
R329 GPIO_8_ROMSO VSYNC
1 2@ 10K_0402_5% GPIO26_TCK GPU_GPIO9 P4
R319 GPIO_9_ROMSI
1 2@ 10K_0402_5% GPIO27_TMS P2
R330 T76 GPIO_10_ROMSCK
1 2@ 10K_0402_5% GPIO28_TDO GPU_GPIO11 N6 GPIO_11 RSET AD22 R356 1 2 499_0402_1% GPIO21_BB_EN
R320 1 2@ 5.11K_0402_1% TESTEN R331 1 2 1K_0402_5% GPU_GPIO12 N5 (1.8V@70mA AVDD) L13
GPU_GPIO13 GPIO_12 +AVDD
N3 AG24 1 2 +1.8VS
GPIO_13 AVDD +HDMI_5V_OUT +5VS
33 DPB_HPD Y9 AE22 R401 1 2 0_0402_5% BLM18PG121SN1D_0603
GPIO_14_HPD2 AVSSQ L14

C338

C339
VGA_PWRSEL N1

0.1U_0402_10V6K

1U_0402_6.3V4Z
49 VGA_PWRSEL GPIO_15_PWRCNTL_0

C695
M4 AE23 +VDD1DI (1.8V@45mA VDD1DI) 1 2 1 1 1

10U_0603_6.3V6M
GPIO_16_SSIN VDD1DI +1.8VS

2
THERM_INT R6 AD23 BLM18PG121SN1D_0603
GPIO_17_THERMAL_INT VSS1DI D13
33 DPC_HPD W10
L16 GPIO_18_HPD3

C341

C340
1 2GPU_CTF M2 M92-S2/M93-S3 RB491D_SOT23
300mA

0.1U_0402_10V6K

1U_0402_6.3V4Z
R359 @ 10K_0402_5% GPIO_19_CTF 2 2 2

C696
2 1 +DPLL_PVDD P8 AM12 1 1 1

10U_0603_6.3V6M
+1.8VS T77 GPIO_20_PWRCNTL_1 R2 / NC
BLM18PG121SN1D_0603 GPU_GPIO21 P7 AK12

1
GPIO_21_BB_EN R2B / NC
C344

C345

C346

1 1 1 N8
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

GPIO23_CLKREQB GPIO_22_ROMCSB
N7 AL11
GPIO_23_CLKREQB G2 / NC 2 2 2
T11 AJ11 1
GPIO_29 G2B / NC 09/24 ATI
10/24 ATI change R11/T11 to VSS R11

HDMI Connector
2 2 2 GPIO_30 0.1U_0402_10V6K
AK10
GPIO24_TRSTB B2 / NC C347
L6 JTAG_TRSTB B2B / NC AL9
GPIO25_TDI 2
L5 JTAG_TDI 09/22 HP
GPIO26_TCK L3
GPIO27_TMS JTAG_TCK +3VS_VGA
L1 AH12 22 HDMI_CEC
GPIO28_TDO JTAG_TMS C / NC
K4
JTAG_TDO DAC2 Y / NC
AM10
TESTEN AF24 AJ9
TESTEN COMP / NC JHDMI1
AB13 18
L19 GENERICA HSYNC_DAC2 HDMI_SDATA +5V
W8 AL13 16 13
300mA GENERICB H2SYNC SDA CEC

1
+1.1VS 2 1 +DPLL_VDDC +1.8VS W9 AJ13 VSYNC_DAC2 C HDMI_SCLK 15 14
BLM18PG121SN1D_0603 GENERICC V2SYNC Q20 SCL Reserved
W7 2 1 2 19
GENERICD R365 150K_0402_5% HP_DET
C352

C353

C354

1 1 1 AD10 MMBT3904_SOT323 B 2
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

GENERICE_HPD4 +VDD2DI E HDMI_R_CK- GND

AD19 +1.8VS 12 5

3
VDD2DI / NC CK- GND
1

HDMI_HPD AC14 AC19 HDMI_R_CK+ 10 8

R363 HPD1 VSS2DI / NC HDMI_HPD HDMI_R_D0- CK+ GND

@ 365K_0603_1%
1 2 9 11
D0- GND

1
B 2 2 2 499_0402_1% R367 0_0402_5% HDMI_R_D0+ B
7 20
D0+ GND

1
AE20 +3VS_VGA 09/22 HP HDMI_R_D1- 6 21
A2VDD / NC R368 HDMI_R_D1+ D1- GND
4 22
2

10K_0402_5% HDMI_R_D2- D1+ GND

A2VDDQ / NC AE17 +1.8VS 3 D2- GND 23

R369
AC16 HDMI_R_D2+ 1 17

2
VREFG R402 1 D2+ DDC/CEC_GND
AE19 2 0_0402_5%

2
A2VSSQ
C355

1
0.1U_0402_10V6K
1

TAITW_PDVBR0-19FLBS4NN4N_19P-T
R366 AG13 R364 1 2 715_0402_1% CONN@
XTALIN 249_0402_1% R2SET / NC
2
R381 2 1 @ 1M_0402_5% XTALOUT DDC/AUX CRT
2

AE6 CRT_DDC_CLK 19
Y4 PLL/CLOCK DDC1CLK
DDC1DATA AE5 CRT_DDC_DATA 19
@ 27MHz_16PF_6P27000126 +DPLL_PVDD AF14 HDMI_TX0-_VGA 1 2 HDMI_TX0- 1 2 HDMI_R_D0-
DPLL_PVDD C356 0.1U_0402_10V6K R372 0_0402_5%
4 3 AE14 AD2
GND OUT DPLL_PVSS AUX1P
AD4
1
IN GND
2 1
AUX1N HDMI 1
1 2
2 HDMI_R_CK+ 1 2
1 C363 +DPLL_VDDC AD14 AC11 HDMICLK L20 R373 499_0402_1%
C365 @ 22P_0402_50V8J DPLL_VDDC DDC2CLK HDMIDAT @ WCM-2012-900T_0805 HDMI_R_CK-
AC13 1 2
@ 22P_0402_50V8J DDC2DATA HDMI_CLK-_VGA HDMI_CLK- R395 0_0402_5% HDMI_R_CK- R374 499_0402_1%
1 2 1 2 4 3
2 R370 2 4 3
11 27M_CLK 1 82.5_0402_1% XTALIN AM28 AD13 DPB_AUX 33
C367 0.1U_0402_10V6K HDMI_R_D1- 1 2
2 XTALOUT XTALIN AUX2P R375 499_0402_1%
AK28 AD11 DPB_AUX# 33
XTALOUT AUX2N
1

1 2 HDMI_TX0+_VGA 1 2 HDMI_TX0+ R376 1 2 0_0402_5% HDMI_R_D0+ HDMI_R_D1+ 1 2

R371 1 2 L24 C359 0.1U_0402_10V6K R377 499_0402_1%
AE16
100_0402_1% DDCCLK_AUX5P @ WCM-2012-900T_0805 HDMI_R_D0-
AD16 1 2
DDCDATA_AUX5N HDMI_TX1-_VGA HDMI_TX1- R378 0_0402_5% HDMI_R_D1- R379 499_0402_1%
4 3 1 2 1 2
4 3 C360 0.1U_0402_10V6K HDMI_R_D0+
AC1 1 2
External VGA Thermal Sensor
2

GPU_THERMAL_D+ DDC6CLK R380 499_0402_1%

T4 DPLUS DDC6DATA AC3
GPU_THERMAL_D- T2 THERMAL HDMI_CLK+_VGA 1 2 HDMI_CLK+ R396 1 2 0_0402_5% HDMI_R_CK+ 1 2 HDMI_R_D2+ 1 2
DMINUS C369 0.1U_0402_10V6K 1 2 L22 R382 499_0402_1%
AD20 DPC_AUX 33
+3VS +3VS DDCCLK_AUX3P @ WCM-2012-900T_0805 HDMI_R_D2-
AC20 DPC_AUX# 33 1 2
L21 DDCDATA_AUX3N R383 499_0402_1%
R5 TS_FDO 4 4 3 3
2 1+TSVDD AD17 AB22 +3VS_VGA +HDMI_5V_OUT
+1.8VS TSVDD NC#1
BLM18PG121SN1D_0603 AC17 AC22
TSVSS NC#2 R386 0_0402_5% 2N7002_SOT23-3
C357

C358

C697

1 1 1 HDMI_TX1+_VGA 1 2 HDMI_TX1+ 1 2 HDMI_R_D1+

10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z

1
C362 0.1U_0402_10V6K D
1

2 +5VS 2
1

2
C361 R384 R385 +3VS HDMI_TX2-_VGA 1 2 HDMI_TX2- R387 1 2 0_0402_5% HDMI_R_D2- G

1
A @ 4.7K_0402_5% @ 4.7K_0402_5% 2 2 2 R389 R388 R390 R391 C364 0.1U_0402_10V6K Q21 S A

3
0.1U_0402_10V6K 10K_0402_5% 10K_0402_5% 2K_0402_1% 2K_0402_1% R392
1 216-0728002 A11 M92-S2_FCBGA631 100K_0402_5%
1 2
2

1 2
5

L23
2

U9 Q67A 1 @ WCM-2012-900T_0805

2
1 8 THERM_CLK 2N7002DW T/R7_SOT-363-6 HDMIDAT 4 3 HDMI_SDATA 4 3
C368 2200P_0402_50V7K VDD SCLK THERM_CLK 4 3
6 1 CAP_CLK 13,30,35
1 2 GPU_THERMAL_D+ 2 7 THERM_DAT Q22B
D+ SDATA 2N7002DW T/R7_SOT-363-6 HDMI_TX2+_VGA HDMI_TX2+ R394 0_0402_5% HDMI_R_D2+
1 2 1 2
GPU_THERMAL_D- 3 6 +3VS C366 0.1U_0402_10V6K
THERM_SCI# 15
2

D- ALERT#
2

1 2 THERM_INT 4 5 1 2
+3VS_VGA
R393 10K_0402_5% THERM# GND R431 10K_0402_5%
+3VS
Q67B
2N7002DW T/R7_SOT-363-6 HDMICLK HDMI_SCLK
Security Classification Compal Secret Data Compal Electronics, Inc.
1 6 Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
ADM1032ARMZ REEL_MSOP8 THERM_DAT 3 4
+3VS
CAP_DAT 13,30,35
Q22A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI, MSIC & Thermal
Put the sensor colse to CPU 2N7002DW T/R7_SOT-363-6 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891 0.1
5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 23 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

For Future S3 GPUs

+DPB_VDD18 +1.8VS

0.11A

10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K
C391

C392

C393
1 1 1

D D

@2 @2 @2

U8G
+1.8VS
+DPE_VDD18 DP E/F POWER DP A/B POWER +DPA_VDD18
0.11A AG15 AE11
DPE_VDD18#1 NC_DPA_VDD18#1
AG16 DPE_VDD18#2 NC_DPA_VDD18#2 AF11

0.1U_0402_10V6K
C700

C370

C371
+1.1VS +DPA_VDD18 +1.8VS
10U_0603_6.3V6M
1 1 1
1U_0402_6.3V4Z
+DPF_VDD10
0.11A
0.2A

@ 0.1U_0402_10V6K
AG20 AF6 +DPA_VDD10
2 2 2 0.17A AG21
DPE_VDD10#1 DPA_VDD10#1
AF7

@1U_0402_6.3V4Z
DPE_VDD10#2 DPA_VDD10#2

0.1U_0402_10V6K
C372

C373

C374

C708

C707

C706
10U_0603_6.3V6M

@ 10U_0603_6.3V6M
1 1 1 1 1 1

1U_0402_6.3V4Z
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
AH14 AE3
DPE_VSSR#2 DPA_VSSR#2 2 2 2 2 2 2
AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
AM16 AG6
DPE_VSSR#4 DPA_VSSR#4
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5

+1.1VS +DPB_VDD18
+DPE_VDD18

+DPF_VDD10
0.11A AF16
AG17
DPF_VDD18#1 NC_DPB_VDD18#1
AE13
AF13
DPF_VDD18#2 NC_DPB_VDD18#2
0.1U_0402_10V6K
1U_0402_6.3V4Z
C399

C400

C709

+DPF_VDD10
10U_0603_6.3V6M

1 1 1
+VPB_VDD10
C
0.17A AF22
AG22
DPF_VDD10#1 DPB_VDD10#1 AF8
AF9 C
DPF_VDD10#2 DPB_VDD10#2 0.2A
2 2 2
AF23 DPF_VSSR#1 DPB_VSSR#1 AF10
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 AH8
DPF_VSSR#3 DPB_VSSR#3
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8

+DPE_PVDD 1 2 AF17 AE10 R398 1 2 150_0402_1%

+1.8VS R397 150_0402_1% DPEF_CALR DPAB_CALR +1.8VS

L31 L32
2 1
0.02A AG18 DP PLL POWER AG8 +DPA_PVDD
0.02A 2 1
BLM18PG121SN1D_0603 DPE_PVDD DPA_PVDD BLM18PG121SN1D_0603
AF19 AG7
0.1U_0402_10V6K

DPE_PVSS DPA_PVSS
C386

C387

C701

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1
1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_10V6K
C388

C389

C390
216-0728002 A11 M92-S2_FCBGA631 1 1 1

AG19 AG10
2 2 2 NC_DPF_PVDD DPB_PVDD
AF20 AG11
NC_DPF_PVSS DPB_PVSS 2 2 2

+1.8VS

L34
B +DPB_PVDD
0.02A 2 1
B
BLM18PG121SN1D_0603

0.1U_0402_10V6K
C394

C395

C396
10U_0603_6.3V6M
1 1 1

1U_0402_6.3V4Z
2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

DPX POWER

wWw.Laptopfix.vn
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 24 of 50
5 4 3 2 1
 5 4 3 2 1

+1.5VS

2A
U8E
C710

C711

C712

C713

C413

C401

C402

C403

C404

C652

C405

C414

C415

C416
10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1

AA27 PCIE_VSS#1 GND#1 A3

2 2 2 2 2 2 2 2 2 2 2 2 2 2 AB24 A30
+1.8VS PCIE_VSS#2 GND#2
AB32 PCIE_VSS#3 GND#3 AA13
0.5A AC24
AC26
PCIE_VSS#4 GND#4
AA16
AB10
D U8D +PCIE_GDDR PCIE_VSS#5 GND#5 D
AC27 PCIE_VSS#6 GND#6 AB15
+1.5VS AD25 AB6
PCIE_VSS#7 GND#7

C406

C407

C420

C408

C409

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
MEM I/O 1 1 1 1 1 AD32 AC9
PCIE PCIE_VSS#8 GND#8
AE27 AD6
PCIE_VSS#9 GND#9
H13 AB23 AF32 AD8
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#10 GND#10
H16 VDDR1#2 PCIE_VDDR#2 AC23 AG27 PCIE_VSS#11 GND#11 AE7
+VDDC_CT 2 2 2 2 2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
C421

C410

C411

C412
1 1 1 1 H19 AD24 AH32 AG12
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#12 GND#12
J10 VDDR1#4 PCIE_VDDR#4 AE24 K28 PCIE_VSS#13 GND#13 AH10
0.11A J23
J24
VDDR1#5 PCIE_VDDR#5 AE25
AE26
K32
L27
PCIE_VSS#14 GND#14 AH28
B10
+1.8VS 2 2 2 2 VDDR1#6 PCIE_VDDR#6 PCIE_VSS#15 GND#15
J9 VDDR1#7 PCIE_VDDR#7 AF25 M32 PCIE_VSS#16 GND#16 B12
10U_0603_6.3V6M
C417

C418

C419

C422

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 1 K10 AG26 N25 B14
VDDR1#8 PCIE_VDDR#8 +1.1VS PCIE_VSS#17 GND#17
K23
K24
VDDR1#9 2A N27
P25
PCIE_VSS#18 GND#18 B16
B18
VDDR1#10 +PCIE_VDDC PCIE_VSS#19 GND#19
K9 L23 P32 B20
2 2 2 2 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#20 GND#20
L11 L24 R27 B22
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#21 GND#21

10U_0603_6.3V6M
C423

C424

C425

C426

C427
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
L12 VDDR1#13 PCIE_VDDC#3 L25 1 1 1 1 1 T25 PCIE_VSS#22 GND#22 B24
L13 L26 T32 B26
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#23 GND#23
L20 VDDR1#15 PCIE_VDDC#5 M22 U25 PCIE_VSS#24 GND#24 B6
L21 N22 U27 B8
+3VS_VGA VDDR1#16 PCIE_VDDC#6 2 2 2 2 2 PCIE_VSS#25 GND#25
L22 N23 V32 C1
VDDR1#17 PCIE_VDDC#7 PCIE_VSS#26 GND#26
N24 W25 C32
PCIE_VDDC#8 PCIE_VSS#27 GND#27
PCIE_VDDC#9 R22 W26 PCIE_VSS#28 GND#28 E28
PCIE_VDDC#10 T22 W27 PCIE_VSS#29 GND#29 F10
+VDDC_CT LEVEL U22 Y25 F12
+1.8VS TRANSLATION PCIE_VDDC#11 +NVVDD PCIE_VSS#30 GND#30
PCIE_VDDC#12 V22 Y32 PCIE_VSS#31 GND#31 F14
10U_0603_6.3V6M
C428

C429

C430

C431
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 1 AA20 F16
+VDDR5 VDD_CT#1 GND#32
AA21 F18
VDD_CT#2 GND#33
AB20 VDD_CT#3 VDDC#1 AA15 GND#34 F2
C442

C443

C444
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1 1 1 AB21 CORE N15 F20

2 2 2 2 VDD_CT#4 VDDC#2 GND#35

C432

C433

C434

C435

C436

C437

C718

C439

C440

C717
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
N17 1 1 1 1 1 1 1 1 1 1 M6 F22
VDDC#3 GND#56 GND#36
M93-S3/M92-S2 VDDC#4
R13 N11
GND#57 GND#37
F24

POWER
C C
VDDC#5 R16 N12 GND#58 GND#38 F26
2 2 2 AA17 R18 N13 F6
VDDR3#1 VDDC#6 2 2 2 2 2 2 2 2 2 2 GND#59 GND#39
AA18 I/O R21 N16 F8

M92@
AB17
AB18
VDDR3#2
VDDR3#3
VDDR3#4
VDDC#7
VDDC#8
VDDC#9
T12
T15
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
R665 0_0402_5% T17 P6 G31
+VDDR5 VDDC#10 GND#63 GND#43
1 2 V12 VDDR4#1 / VDDR5 VDDC#11 T20 P9 GND#64 GND#44 G8
+VDDR4 Y12 U13 +NVVDD R12 H14
+VDDR4 VDDR4#2 VDDC#12 GND#65 GND#45
+1.8VS 1 2 U12 VDDR4#3 / VDDR5 VDDC#13 U16 R15 GND#66 GND#46 H17
R664 0_0402_5% U18 R17 H2
VDDC#14 GND#67 GND#47
0.1U_0402_10V6K
1U_0402_6.3V4Z

M93@ AA11 U21 R20 H20

NC#1 / VDDR4 VDDC#15 GND#68 GND#48
C471

C472

C473

C445

C446

C447

C448

C449

C450

C451

C453

C454

C716
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 Y11 V15 1 1 1 1 1 1 1 1 1 1 T13 H6
DVCLK / VDDR4 VDDC#16 GND#69 GND#49
VDDC#17 V17 T16 GND#70 GND#50 J27
V11 V20 T18 J31
NC#3 / VDDR5 VDDC#18 GND#71 GND#51
U11 V21 T21 K11
2 2 2 NC#4 / VDDR5 VDDC#19 2 2 2 2 2 2 2 2 2 2 GND#72 GND#52
Y13 T6 K2
VDDC#20 GND#73 GND#53
Y16 U15 K22
VDDC#21 GND#74 GND#54
Y18 U17 K6
+1.5VS VDDC#22 GND#75 GND#55
L46
0.04A MEM CLK VDDC#23
Y21 U20
U9
GND#76
+VDDRHA GND#77
2 1 L17 V13
BLM18PG121SN1D_0603 VDDRHA GND#78
V16
ISOLATED GND#79
2 1
C470
L16
VSSRHA CORE I/O 2A V18
Y10
GND#80
+1.8VS 1U_0402_6.3V4Z +VDDCI GND#81
M13 +NVVDD Y15
VDDCI#1 GND#82
L42 PLL M15 Y17 A32 MECH#1
VDDCI#2 GND#83 VSS_MECH#1

C460

C455

C456

C461

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 1 +PCIE_PVDD AM30 M16 1 1 1 1 Y20 AM1 MECH#2
PCIE_PVDD VDDCI#3 GND#84 VSS_MECH#2
BLM18PG121SN1D_0603 M17 AM32 MECH#3
VDDCI#4 VSS_MECH#3
C458

C459

C462
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1 1 1 M18
+MPV18 VDDCI#5
L8 M20
NC_MPV18 VDDCI#6 2 2 2 2
M21
VDDCI#7
N20
B 2 2 2 +SPV18 VDDCI#8 B
H7 NC_SPV18 216-0728002 A11 M92-S2_FCBGA631
+SPV10 H8
+NVVDD SPV10

L43
0.035A J7
SPVSS
1 2
MCK1608471YZF 0603
C463

C464

C465

+3VS
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1 1 1 BACK BIAS
M11 +3VS_VGA +3VS
BBP#1 SI2301BDS_SOT23
+NVVDD M12 BBP#2

1
2 2 2
C466

C467

0.1U_0402_10V6K
1U_0402_6.3V4Z

R241 1 3

S
1 1

D
CRACK_BGA 17,35

6
216-0728002 A11 M92-S2_FCBGA631 100K_0402_5% Q23

2
Q61A

G
2

2
2 2 +3VS R403
2N7002DW T/R7_SOT-363-6

BGA Ball Cracking Prevention and Detection

MECH#1 2 100K_0402_5%

1 R646

1
2 1 1 2
0.1U_0402_10V6K C688 09/17 soft start by HP
+3VS +3VS 47K_0402_5%

6
09/22 HP
Q62A
1

+1.8VS 2N7002DW T/R7_SOT-363-6

L49 R244 CRACK_BGA R242 CRACK_BGA R404 2 1 @ 330K_0402_5% 2
+MPV18 37,45 1.1VS_POK
1 2
3

MCK1608471YZF 0603 1 1 100K_0402_5% 100K_0402_5% +3VS 1 2 R406 1 2 0_0402_5%

1
C702 C703 Q62B Q61B R405 4.7K_0402_5%
2

2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6 C468

1U_0402_6.3V4Z 0.1U_0402_10V6K MECH#3 5 MECH#2 5 1 2
A 2 2 @ 0.01U_0402_16V7K A
4

L51
1 2 +SPV18
MCK1608471YZF 0603 1 1
C705 C704

1U_0402_6.3V4Z
2 2
0.1U_0402_10V6K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Main Power

wWw.Laptopfix.vn
www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 25 of 50
5 4 3 2 1
 5 4 3 2 1

U10 U11 U12 U13

VREFC_A1 M9 E4 MDA20 VREFC_A2 M9 E4 MDA26 VREFC_A3 M9 E4 MDA38 VREFC_A4 M9 E4 MDA52

VREFD_Q1 VREFCA DQL0 MDA19 VREFD_Q2 VREFCA DQL0 MDA27 VREFD_Q3 VREFCA DQL0 MDA34 VREFD_Q4 VREFCA DQL0 MDA50
H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
F3 MDA23 F3 MDA25 F3 MDA32 F3 MDA54
MAA0 DQL2 MDA18 MAA0 DQL2 MDA24 MAA0 DQL2 MDA39 MAA0 DQL2 MDA49
N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9
MAA1 P8 H4 MDA17 MAA1 P8 H4 MDA29 MAA1 P8 H4 MDA33 MAA1 P8 H4 MDA53
MAA2 A1 DQL4 MDA21 MAA2 A1 DQL4 MDA30 MAA2 A1 DQL4 MDA37 MAA2 A1 DQL4 MDA51
P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9
MAA3 N3 G3 MDA22 MAA3 N3 G3 MDA28 MAA3 N3 G3 MDA35 MAA3 N3 G3 MDA55
MAA4 A3 DQL6 MDA16 MAA4 A3 DQL6 MDA31 MAA4 A3 DQL6 MDA36 MAA4 A3 DQL6 MDA48
P9 H8 P9 H8 P9 H8 P9 H8
MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
P3 A5 P3 A5 P3 A5 P3 A5
MAA6 R9 MAA6 R9 MAA6 R9 MAA6 R9
MAA7 A6 MDA0 MAA7 A6 MDA15 MAA7 A6 MDA44 MAA7 A6 MDA56
R3 A7 DQU0 D8 R3 A7 DQU0 D8 R3 A7 DQU0 D8 R3 A7 DQU0 D8
MAA8 T9 C4 MDA4 MAA8 T9 C4 MDA10 MAA8 T9 C4 MDA42 MAA8 T9 C4 MDA58
MAA9 A8 DQU1 MDA1 MAA9 A8 DQU1 MDA14 MAA9 A8 DQU1 MDA47 MAA9 A8 DQU1 MDA60
R4 A9 DQU2 C9 R4 A9 DQU2 C9 R4 A9 DQU2 C9 R4 A9 DQU2 C9
D MAA10 MDA6 MAA10 MDA11 MAA10 MDA40 MAA10 MDA61 D
L8 A10/AP DQU3 C3 L8 A10/AP DQU3 C3 L8 A10/AP DQU3 C3 L8 A10/AP DQU3 C3
MAA11 R8 A8 MDA3 MAA11 R8 A8 MDA12 MAA11 R8 A8 MDA45 MAA11 R8 A8 MDA63
MAA12 A11 DQU4 MDA7 MAA12 A11 DQU4 MDA8 MAA12 A11 DQU4 MDA43 MAA12 A11 DQU4 MDA62
N8 A12 DQU5 A3 N8 A12 DQU5 A3 N8 A12 DQU5 A3 N8 A12 DQU5 A3
MDA[0..63] T4 B9 MDA2 T4 B9 MDA13 T4 B9 MDA46 T4 B9 MDA57
22 MDA[0..63] A13 DQU6 MDA5 A13 DQU6 MDA9 A13 DQU6 MDA41 A13 DQU6 MDA59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 A15/BA3 M8 A15/BA3 M8 A15/BA3 M8 A15/BA3
+1.5VS +1.5VS +1.5VS +1.5VS

M3 B3 A_BA0 M3 B3 A_BA0 M3 B3 A_BA0 M3 B3

MAA[12..0] 22 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N9 D10 A_BA1 N9 D10 A_BA1 N9 D10 A_BA1 N9 D10
22 MAA[12..0] 22 A_BA1 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD
22 A_BA2 M4 BA2 VDD G8 M4 BA2 VDD G8 M4 BA2 VDD G8 M4 BA2 VDD G8
K3 K3 K3 K3
VDD VDD VDD VDD
VDD K9 VDD K9 VDD K9 VDD K9
N2 N2 N2 N2
VDD CLKA0 VDD VDD CLKA1 VDD
22 CLKA0 J8 N10 J8 N10 22 CLKA1 J8 N10 J8 N10
CK VDD CLKA0# CK VDD CK VDD CLKA1# CK VDD
22 CLKA0# K8 R2 K8 R2 22 CLKA1# K8 R2 K8 R2
DQMA#[7..0] CK VDD CKEA0 CK VDD CK VDD CKEA1 CK VDD
22 DQMA#[7..0] 22 CKEA0 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10 22 CKEA1 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10
+1.5VS +1.5VS +1.5VS +1.5VS

K2 A2 ODTA0 K2 A2 K2 A2 ODTA1 K2 A2
22 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 22 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L3 A9 CSA0#_0 L3 A9 L3 A9 CSA1#_0 L3 A9
22 CSA0#_0 CS VDDQ RASA0# CS VDDQ 22 CSA1#_0 CS VDDQ RASA1# CS VDDQ
22 RASA0# J4 C2 J4 C2 22 RASA1# J4 C2 J4 C2
QSA[7..0] RAS VDDQ CASA0# RAS VDDQ RAS VDDQ CASA1# RAS VDDQ
22 QSA[7..0] 22 CASA0# K4 CAS VDDQ C10 K4 CAS VDDQ C10 22 CASA1# K4 CAS VDDQ C10 K4 CAS VDDQ C10
L4 D3 WEA0# L4 D3 L4 D3 WEA1# L4 D3
22 WEA0# WE VDDQ WE VDDQ 22 WEA1# WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ F2
QSA2 F4 H3 QSA3 F4 H3 QSA4 F4 H3 QSA6 F4 H3
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C8 H10 C8 H10 C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
QSA#[7..0]
22 QSA#[7..0] DQMA#2 DQMA#3 DQMA#4 DQMA#6
E8 A10 E8 A10 E8 A10 E8 A10
DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
C DMU VSS DMU VSS DMU VSS DMU VSS C
VSS E2 VSS E2 VSS E2 VSS E2
G9 G9 G9 G9
QSA#2 VSS QSA#3 VSS QSA#4 VSS QSA#6 VSS
G4 J3 G4 J3 G4 J3 G4 J3
QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B8 DQSU VSS J9 B8 DQSU VSS J9 B8 DQSU VSS J9 B8 DQSU VSS J9
VSS M2 VSS M2 VSS M2 VSS M2
M10 M10 M10 M10
VSS VSS VSS VSS
VSS P2 VSS P2 VSS P2 VSS P2
T3 P10 DRAM_RST# T3 P10 DRAM_RST# T3 P10 DRAM_RST# T3 P10
22 DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T2 VSS T2 VSS T2 VSS T2
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2
R407 L2 B10 R408 L2 B10 R409 L2 B10 R410 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 NC VSSQ G2 T1 NC VSSQ G2 T1 NC VSSQ G2 T1 NC VSSQ G2
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100

B +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS B

1

1
R411 R412 R413 R414 R415 R416 R417 R418
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2

2
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C474

C475

C476

C477

C478

C479

C480

C481
1 1 1 1 1 1 1 1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R419 R420 R421 R422 R423 R424 R425 R426
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
2

2
+1.5VS
+1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C495

C496

C497

C498

C499

C500

C501

C502

C518

C519
1 1 1 1 1 1 1 1 1 1
C487

C488

C489

C490

C491

C492

C493

C494

C517

C516
CLKA0 1 2 C483 C484 C485 C486 C482 C515
R427 56_0402_1% CLKA1 1 2
A R428 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A
10U_0603_6.3V6M 10U_0603_6.3V6M
10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKA0# 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R429 56_0402_1% CLKA1# 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 R430 56_0402_1% 1
C503 C504
0.01U_0402_16V7K 0.01U_0402_16V7K
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92-S VRAM

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 26 of 50
5 4 3 2 1
 5 4 3 2 1

+3V_LAN +3VALW
Q54A +3V_LAN

D
3 1

1
+3VALW +3V_LAN 2N7002DW T/R7_SOT-363-6 Q55

1
R555 35,41,42,48 ADP_PRES 2 SI2301BDS_SOT23

G
2
10K_0402_5% R586 +3V_LAN

1
R556 47K_0402_5%
R432 0.1U_0402_10V6K 0.1U_0402_10V6K V1.8_LAN
09/22 HP

2 2

6
10K_0402_5% 10K_0402_5% R588 1 1 1 1 1

2
C512 C507 C510 C511 0.1U_0402_10V6K

G
2 1
47K_0402_5% C508 1 1

3
1 3 CLK_LAN_REQ# 0.1U_0402_10V6K
D 13 CLK_PCIE_LAN_REQ# 2 2 2 2 2 D
Q54B C513 C514

S
0.1U_0402_10V6K 0.1U_0402_10V6K
2N7002_SOT23-3 5 2 2
14,34,35,37,38,41,43,44,45,46,49 SLP_S3#
Q60 0.1U_0402_10V6K
2N7002DW T/R7_SOT-363-6

4
1 4 RP8 CLK_PCIE_LAN
13 CLK_PCIE_LAN_PCH CLK_PCIE_LAN#
13 CLK_PCIE_LAN_PCH# 2 3
0_4P2R_5%
CK32@
Remove after DB2

V1.2_LAN
U15
0.1U_0402_10V6K
CLK_LAN_REQ# 42 LED 59 LAN_ACT# LAN_ACT# 28,33 1 1 1 1
CLKREQn LED_ACTn
13 PCIE_PRX_DTX_P6 0.1U_0402_10V6K 2 1 C506 PCIE_RXP2_LAN49 60
TX_P LED_LINK10/100n
13 PCIE_PRX_DTX_N6 0.1U_0402_10V6K 2 1 C509 PCIE_RXN2_LAN50 62 R465 1 2 10K_0402_5% +3V_LAN C523 C524 C525 C526
TX_N LED_LINK1000n LANLINK_STATUS# 0.1U_0402_10V6K
13 PCIE_PTX_C_DRX_P6 54 RX_P PCI-E LED_DUPLEXn 63 LANLINK_STATUS# 15,28,33,35 2 2 2 2
13 PCIE_PTX_C_DRX_N6 53 RX_N
PCIE_WAKE# 6 46 0.1U_0402_10V6K 0.1U_0402_10V6K
14,29,34 PCIE_WAKE# WAKEn TEST TESTMODE +3V_LAN
CLK_PCIE_LAN 55
CLK_PCIE_LAN# REFCLKP
56 8
R436 REFCLKN AVDDH V1.8_LAN
4,12,15,21,29,32,34 PLT_RST# 1 2 0_0402_5% 5
PERSTn
AVDD 19
28 LAN_MDI0P 17 MDIP0 POWER NC 22
28 LAN_MDI0N 18 23
MDIN0 NC
C 28 LAN_MDI1P 20
MDIP1 & AVDD
28
+3V_LAN C
28 LAN_MDI1N 21 MDIN1
28 LAN_MDI2P 26
MDIP2 Media GROUND VDDO_TTL
1
V1.2_LAN
28 LAN_MDI2N 27 40
MDIN2 VDDO_TTL
28 LAN_MDI3P 30 MDIP3 VDDO_TTL 45
28 LAN_MDI3N 31 61 0.1U_0402_10V6K
MDIN3 VDDO_TTL V1.2_LAN
1 1 1 1
LAN_EE_CLK 38 2
LAN_EE_DATA VPD_CLK VDD C527 C528 C529 C530
41 EEPROM 7
VPD_DATA VDD 0.1U_0402_10V6K
VDD 13
SPI_DO_LAN 34 33 2 2 2 2
SPI_DI_LAN SPI_DO VDD 0.1U_0402_10V6K 0.1U_0402_10V6K
35 SPI_DI VDD 39
SPI_CLK_LAN 37 FLASH 44
SPI_CS_LAN SPI_CLK MEMORY VDD
36 SPI_CS VDD 48
8072@ R653 0_0402_5% 58 2 1
LAN_DIS# LAN_X1 VDD R652 0_0402_5%
1 2 15 65
XTALI EAPD
LAN_X2 14
XTALO
CLOCK 8075@
8075@R654
8075@ R654 0_0402_5% 51
USB20_N5_L NC
15 USB20_N5 1 2 10 52
USB20_P5_L LOM_DISABLEn(USB_DM-) NC 8075@
15 USB20_P5 1 2 9 32
8075@R655
8075@ R655 0_0402_5% 8075@ R657 0_0402_5% SWITCH_VAUX(USB_DP+) (PD18LDO)NC R656 2 +3V_LAN
SMALERTn 57 1 0_0402_5% SMBALERT# 13
LAN_DIS# 1 2 11 64 R658 2 1
15 LAN_DIS# SWITCH_VCC(LOM_DISABLEn) SMCLK SMB_CLK_S3 4,9,10,11,13,29,31,33
+3V_LAN 12 0_0402_5%
VAUX_AVLBL 8075@ 4.7U_0805_10V4Z C531 R438 4.7K_0402_5%
+3VS 47
VMAIN_AVLBL No Connect
27P_0402_50V8J C521 24 2 1 2 1
CTRL18 Reserved
2 1 4 25
CTRL18 Reserved

3
CTRL12 3 29 Q26
CTRL12 Reserved
2

1 2 4.99K_0402_1% 16 Analog 43 1 2
RSET SMDATA SMB_DATA_S3 4,9,10,11,13,29,31,33
R659 0_0402_5% 1 CTRL12
Y5 R437 88E8072-NNC1C000_QFN64 8075@
25MHZ_20P_1BG25000CK1A
09/17 HP 2SB1188T100R_SC62-3
V1.2_LAN

2
27P_0402_50V8J C522 LAN_X1
1

B LAN_X2 10U_0805_10V4K C532 B

2 1
2 1

+3V_LAN +3V_LAN

R232 1 2 10K_0402_5% LAN_DIS#

4.7U_0805_10V4Z C533 8072@ R440 4.7K_0402_5%
+3V_LAN 2 1 2 1
C505 +3V_LAN 8072@

3
2 1 Q28
2SB1188T100R_SC62-3
0.1U_0402_10V6K 1 8072@ 1 CTRL18
1

R433 R434 C694

4.7K_0402_5% 4.7K_0402_5% U36 0.1U_0402_10V6K V1.8_LAN 1 2

2
SPI_CS_LAN 2
1 8 8075@
U14 SPI_DI_LAN CS# VCC 10U_0805_10V4K C534 R660 0_0402_5%
2 7
2

SO HOLD# SPI_CLK_LAN 8075@

1 8 3 6 2 1
CS# VCC WP# SCK SPI_DO_LAN
2 7 4 5
SO HOLD# LAN_EE_CLK GND SI
3 6
WP# SCK LAN_EE_DATA AT25F1024AN-10SU-2.7 SOIC 8P
4 GND SI 5
8075@
CAT24C08WI-GT3 SO 8P
88E8072 88E8075

R653 R654 ROM size will update

after check with vendor
C533 R655
R440 U36
A A
Q28 C694
Insert

R659
R658
R656
R652
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
R660
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 27 of 50
5 4 3 2 1
 5 4 3 2 1

D D

10/15 HP

C LAN_MDI0P C
27 LAN_MDI0P
LAN_MDI0N
27 LAN_MDI0N
LAN_MDI1P +V_3P3_LAN_LED
27 LAN_MDI1P
LAN_MDI1N
27 LAN_MDI1N
LAN_MDI2P +3V_LAN
27 LAN_MDI2P

1 10K_0402_5%
R457
LAN_MDI2N
27 LAN_MDI2N
LAN_MDI3P
27 LAN_MDI3P

1 10K_0402_5%
R519
LAN_MDI3N
27 LAN_MDI3N
JP5

2
+V_3P3_LAN_LED 13 Yellow LED+
LAN_ACT# R442 1 2 300_0603_5% 14
27,33 LAN_ACT#

2
Yellow LED-
SHLD1 16
MDO3- 8 PR4-
1 2 DETECT PIN1 9 CB_IN# 15
V1.8_LAN @ 680P_0402_50V7K C539 MDO3+ 7 PR4+ 2
MDO1- C719
09/28 HP 6 PR2- @ 0.1U_0402_10V6K
2

MDO2- 1
5 PR3-
R282 U35 +V_3P3_LAN_LED
0_0603_5% LAN_MDI0P 12 13 MDO0+ MDO2+ 4
TD4- MX4- MDO0+ 33 PR3+
10/02 HP

@ 10K_0402_5%
MDO1+ 3
1

PR2+

1
R443
MDO0- 2
LAN_MDI0N MDO0- R444 PR1-
11 TD4+ 1:1 MX4+ 14 MDO0- 33 DETCET PIN2 10
75_0402_1% MDO0+ 1
TRM_CT MCT0 C541 1 PR1+
1 2 10 15 2 0.01U_0402_16V7K 1 2 15

2
B C540 TCT4 MCT4 SHLD1 B
+V_3P3_LAN_LED 11 Green LED+
0.1U_0402_10V6K LAN_MDI1P 9 16 MDO1+
TD3- MX3- MDO1+ 33
LANLINK_STATUS# R445 1 2 300_0603_5% 12
15,27,33,35 LANLINK_STATUS# Green LED-
FOX_JM36113-P1123-7F

LAN_MDI1N 8 17 MDO1- R446 1 2

TD3+ 1:1 MX3+ MDO1- 33
75_0402_1% @ 680P_0402_50V7K C542
1 2 TRM_CT 7 18 MCT1 C544 1 2 0.01U_0402_16V7K 1 2
C543 TCT3 MCT3
0.1U_0402_10V6K LAN_MDI2P 6 19 MDO2+
TD2- MX2- MDO2+ 33
20 mil
+3V_LAN +V_3P3_LAN_LED
LAN_MDI2N 5 20 MDO2- R447
TD21+ 1:1 MX2+ MDO2- 33
75_0402_1%
1 2 TRM_CT 4 21 MCT2 C546 1 2 0.01U_0402_16V7K 1 2
TCT2 MCT2

D
C545 20 mil 3 1
0.1U_0402_10V6K LAN_MDI3P 3 22 MDO3+
TD1- MX1- MDO3+ 33

1
Q29
AP2301GN 1P_SOT23

G
2
R471
100K_0402_5%
LAN_MDI3N 2 23 MDO3- R448
MDO3- 33

2
TD1+ 1:1 MX1+ 75_0402_1%
1 2 TRM_CT 1 24 MCT3 C548 1 2 0.01U_0402_16V7K 1 2 C549 1 2
TCT1 MCT1

1
C547 D
0.1U_0402_10V6K NS892402 1G 1000P_1808_3KV7K 33 DOCK_ID 2 Q30
G 2N7002_SOT23-3
S

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 30, 2008 Sheet 28 of 50
5 4 3 2 1

wWw.Laptopfix.vn
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 A B C D E

WWAN JP6 CONN@

+3V_WWAN R767
@ 0_0805_5%
+3VS
09/28 HP
+3V_WWAN

PCIE_WAKE# 1 1 2 2 1 2
WLAN +3V_WLAN +1.5VS

@ 39P_0402_50V8J

@ 39P_0402_50V8J

@ 39P_0402_50V8J
09/24 HP 3 4
3 4 Reserve for port80 card use for FCS in factory side. 10/17

C550

C551

C552
+3VALW R460 1 2 5 6
5 6

@ 0.01U_0402_16V7K

@ 0.1U_0402_10V6K

@ 4.7U_0805_10V4Z
10K_0402_5% 7 8 UIM_PWR 1 1 1
15 CLKREQ_WWAN# 7 8

0.01U_0402_16V7K

0.1U_0402_10V6K

4.7U_0805_10V4Z
9 10 UIM_DATA DEG_FRAME# R449 1 2 0_0402_5% LPC_LFRAME# 12,32,35,36
9 10

C557

C558

C554

C555

C553

C556
CLK_PCIE_WWAN# 11 12 UIM_CLK 1 1 1 1 1 1 DEBUG_AD3 R450 1 2 0_0402_5% LPC_LAD3
CLK_PCIE_WWAN 11 12 UIM_RST DEBUG_AD2 R452 0_0402_5% LPC_LAD2
13 13 14 14 1 2
UIM_VPP 2 2 2 DEBUG_AD1 R451 0_0402_5% LPC_LAD1
15 15 16 16 1 2
T92 PAD 17 18 DEBUG_AD0 R453 1 2 0_0402_5% LPC_LAD0
17 18 M_WXMIT_OFF# 2 2 2 2 2 2
T93 PAD 19 19 20 20 LPC_LAD[0..3] 12,32,35,36
21 22 PLT_RST# PCI_RST#_R R454 1 2 0_0402_5%
21 22 PCI_RST# 15
13 PCIE_PRX_DTX_N7 23 23 24 24
1 25 26 1
13 PCIE_PRX_DTX_P7 25 26
27 27 28 28
29 30 SMB_CLK_S3
29 30 SMB_CLK_S3 4,9,10,11,13,27,31,33 +3V_WWAN
13 PCIE_PTX_C_DRX_N7 31 32 SMB_DATA_S3 CLK_PCI_DEBUG R754 1 2CK32@ 0_0402_5%
31 32 SMB_DATA_S3 4,9,10,11,13,27,31,33 CLK_PCI_DEBUG_PCH 15
13 PCIE_PTX_C_DRX_P7 33 33 34 34
35 36 Remove after DB2 +3V_WLAN
35 36 USB20_N9 15
37 37 38 38 USB20_P9 15

0.01U_0402_16V7K

0.1U_0402_10V6K

4.7U_0805_10V4Z
39 39 40 40 14,27,34 PCIE_WAKE#

C559

C560

C561
+3V_WWAN 41 42 WW_LED# 1 1 1 JP7
41 42 WW_LED# 34
43 44 PCIE_WAKE#
1 2
43 44 09/23 HP R750 1 1 2
45 45 46 46 2 @ 10K_0402_5% 3 3 4 4
47 48 +3VALW 2 R459 1
5 6 +1.5VS
47 48 2 2 2 10K_0402_5% 5 6 DEG_FRAME#
49 49 50 50 13 CLKREQ_WLAN# 7 7 8 8
T94 PAD 51 52 9 10 DEBUG_AD3
51 52 CLK_PCIE_MCARD# 9 10 DEBUG_AD2
11 11 12 12
53 54 CLK_PCIE_MCARD 13 14 DEBUG_AD1
GND1 GND2 13 14 DEBUG_AD0
15 15 16 16
FOXCONN AS0B226-S40N-7F 52P PCI_RST#_R 17 18
CLK_PCI_DEBUG 17 18 XMIT_D_OFF#
19 19 20 20
U17 1 4 RP10 CLK_PCIE_WWAN 21 22
15 CLK_PCIE_WWAN_PCH 21 22 PLT_RST# 4,12,15,21,27,32,34
1 6 2 3 CLK_PCIE_WWAN# R461 1 2 0_0402_5% PCIE_C_RXN4 23 24
CH1 CH4 15 CLK_PCIE_WWAN_PCH# 13 PCIE_PRX_DTX_N4 23 24
0_4P2R_5%
13 PCIE_PRX_DTX_P4
R462 1 2 0_0402_5% PCIE_C_RXP4 25 25 26 26
2 5 CK32@ Remove after DB2 27 28
Vn Vp +3V_WWAN 27 28
29 29 30 30
3 4 31 32 09/24 HP
CH2 CH3 13 PCIE_PTX_C_DRX_N4 31 32
D14 13 PCIE_PTX_C_DRX_P4 33 34
+3V_WWAN 33 34
@ S DIO(BR) NUP4301MR6T1 TSOP-6 15 WWAN_TRANSMIT_OFF# 1 2 M_WXMIT_OFF# 35 35 36 36 USB20_N6 15
+3V_WLAN 37 38
37 38 USB20_P6 15
D15 CH751H-40PT_SOD323-2 39 40
@ DAN217T146_SC59-3 39 40
41 41 42 42
JP8 3 +3VALW 43 44 WL_LED#
43 44 WL_LED# 34
4 1 UIM_PWR 1 45 46
2 UIM_VPP GND VCC UIM_RST 45 46 2
5 VPP RST 2 2 47 47 48 48
UIM_DATA 6 3 UIM_CLK 49 50
I/O CLK 49 50

1 10K_0402_5%
R466
7 1 C645 1 10/22 HP 51 52
DET +3VALW T95 PAD 51 52
18P_0402_50V8J
C562

@ 53 54
GND1 GND2
4.7U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K SI2305DS-T1-E3_SOT23-3
2 2
C563

C564

8 1 1

2
GND

1 10K_0402_5%
9 Q31 FOXCONN AS0B226-S40N-7F 52P
GND
1

R469
35 MC1_DISABLE 1 R468 2 2 CONN@
13 CLK_PCIE_MCARD_PCH 1 4 RP12 CLK_PCIE_MCARD
R467 220K_0402_1% +3V_WWAN 2 3 CLK_PCIE_MCARD#
2 2 13 CLK_PCIE_MCARD_PCH#
@ 47K_0402_5% @ 0_4P2R_5%
CK32@ Remove after DB2

3
R470
7W
2

1
CONN@ TAITW_PMPAT6-06GLBS7N14N0 35 MC2_DISABLE 1 2 2
220K_0402_1% +3V_WLAN
UIM_PWR XMIT_D_OFF# 2 1 WLAN_TRANSMIT_OFF# 15
Q32 D16 CH751H-40PT_SOD323-2
SI2305DS-T1-E3_SOT23-3 Add to prevent leakage issue.
5W

1
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WWAN/NAND mini
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 29, 2008 Sheet 29 of 50
A B C D E

wWw.Laptopfix.vn
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 CAP SWITCH BOARD. INT_KBD CONN.
+3VL +3VS +3VL +3VL +3VS KSO[0..13]
35 KSO[0..13]
KSI[0..7]
35 KSI[0..7]

R479

R480
1

1
JP12 CP2 @

5.1K_0402_5%

5.1K_0402_5%
JP11 1 2 CP1 @ KSI_D_10 1 8
KSO13 1 2 KSO13 KSO12 KSI7
1 1 2 2 3 3 4 4 1 8 2 7
3 4 KSO12 5 6 KSO12 KSO9 2 7 KSI_D_6 3 6
3 4 CAP_RST_EC KSO9 5 6 KSO9 KSI_D_9 KSI_D_5
35 CAP_RST_EC 5 6 7 8 3 6 4 5

2
5 6 WL/BT_LED# KSI_D_9 7 8 KSI_D_9 KSI_D_11
34 WL/BT_LED# 7 7 8 8 9 9 10 10 4 5
9 10 KSI_D_11 11 12 KSI_D_11 100P_1206_8P4C_50V8K
R681 2 0_0402_5% CAP_CLK_R 9 10 CAP_CLK_R KSI_D_13 11 12 KSI_D_13 100P_1206_8P4C_50V8K
13,23,35 CAP_CLK 1 11 11 12 12 13 13 14 14
13,23,35 CAP_DAT 1 R682 2 0_0402_5% CAP_DAT_R 13 14 CAP_DAT_R KSI7 15 16 KSI7
R683 2 0_0402_5% CAP_INT_R 13 14 CAP_INT_R KSI_D_6 15 16 KSI_D_6 CP3 @ CP4 @
35 CAP_INT 1 15 15 16 16 17 17 18 18
17 18 KSI_D_5 19 20 KSI_D_5 KSI_D_13 1 8 KSO1 1 8
STB_LED# 17 18 STB_LED# KSO1 19 20 KSO1 KSO10 KSO8
19 20 21 22 2 7 2 7

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
33,34 STB_LED# 19 20 21 22
2 2 2 ON/OFF# 21 22 ON/OFF# KSO10 23 24 KSO10 KSO6 3 6 KSO3 3 6
33 ON/OFF# 21 22 23 24
1 10K_0402_5%
R481

LID_SW# 23 24 LID_SW# KSO6 25 26 KSO6 KSO7 4 5 KSI_D_3 4 5

12,20,35 LID_SW# 23 24 25 26
10/09 EMI KSO7 KSO7

@ C644

@ C588

@ C587
27 27 28 28
ACES 85203-12021 12P P1.0 KSO4 29 30 KSO4 100P_1206_8P4C_50V8K 100P_1206_8P4C_50V8K
1 1 1 CONN@ KSO8 29 30 KSO8
31 31 32 32
KSO3 33 34 KSO3 CP5 @ CP6 @
2

KSI_D_3 33 34 KSI_D_3 KSO4 KSI_D_1

35 35 36 36 1 8 1 8
KSI_D_1 37 38 KSI_D_1 KSI_D_2 2 7 KSI_D_12 2 7
KSI_D_2 37 38 KSI_D_2 KSI_D_4 KSI_D_8
39 39 40 40 3 6 3 6
KSI_D_4 41 42 KSI_D_4 KSI_D_0 4 5 KSI_D_14 4 5
KSI_D_0 41 42 KSI_D_0
43 43 44 44
KSI_D_10 45 46 KSI_D_10 100P_1206_8P4C_50V8K 100P_1206_8P4C_50V8K
KSI_D_12 45 46 KSI_D_12
47 47 48 48
KSI_D_8 49 50 KSI_D_8 KSO13 1 2 CP7 @

MDC 1.5 Conn. +3VS

+3VS KSI_D_14
KSO5
KSO2
51
53
55
49
51
53
55
50
52
54
56
52
54
56
KSI_D_14
KSO5
KSO2
C756
@ 100P_0402_50V8J
KSO5
KSO2
KSO0
1
2
3
8
7
6
KSO0 57 58 KSO0 KSO11 4 5
57 58

C583

1000P_0402_50V7K

C584

0.1U_0402_10V6K

C585

4.7U_0805_10V4Z
JP13 KSO11 59 60 KSO11
CONN@ ACES_88020-12101_12P 59 60 100P_1206_8P4C_50V8K
1 1 1
1 1 2 2 61 GND1 GND3 63
HDA_SDOUT_MDC 3 3
12 HDA_SDOUT_MDC 4 4 62 GND2 GND4 64
5 5 6 6
HDA_SYNC_MDC 2 2 2 CONN@ HIROSE FH12HP-30S-1SV 55 30P
12 HDA_SYNC_MDC 7 7 8 8
12 HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 9 10 10
R482 33_0402_5% 11 11 R483 2 0_0402_5%
12 12 1 HDA_BIT_CLK_MDC 12
@
+3VALW 1 2
GND
GND
GND
GND
GND
GND
C586 D18
@ 10P_0402_50V8J D17 2 KSI_D_3
5

U18 2 KSI_D_0 KSI3 1

13
14
15
16
17
18
1 KSI0 1 3 KSI_D_11
P

12 HDA_RST#_MDC IN1
4 3 KSI_D_8
O DAP202U_SOT323-3
15 MODEM_DISABLE# 2 IN2
G

DAP202U_SOT323-3 D20
MC74AHC1G08DFT2G SC70 5P D19 2 KSI_D_4
3

2 KSI_D_1 KSI4 1
KSI1 1 3 KSI_D_12
3 KSI_D_9
DAP202U_SOT323-3
DAP202U_SOT323-3 D22
D21 2 KSI_D_5
2 KSI_D_2 KSI5 1
KSI2 1 3 KSI_D_13
3 KSI_D_10
DAP202U_SOT323-3
DAP202U_SOT323-3 D23
2 KSI_D_6
KSI6 1
3 KSI_D_14

DAP202U_SOT323-3

Power button +3VL +3VL +3VL

TrackPoint CONN.
1
100K_0402_5%

R484
1
R485

100K_0402_5% JP16
1 2 +5VS
1 2
3 4
2

3 4
ON/OFFBTN_KBC# 35 5 5 6 6 1
5

U19 7 8 SP_CLK C589

35 SP_CLK
2

7 8
1

SN74LVC1G14DCKR_SC70-5 D +3VALW SP_DATA

9 10
V

35 SP_DATA 9 10
ON/OFF# 2 4 1 2 2 11 12 0.1U_0402_10V6K
A Y R486 11 12 2
NC

G 13 14
13 14
G

1 100K_0402_5% 1 S Q34 1 2 +5VS 15 16 +5VS

3

2N7002_SOT23-3 R487 @ 100K_0402_5% 15 16

1
3

C590 C591 D25 ACES_87153-08011_8P

1U_0603_10V4Z 1U_0603_10V4Z 1 2 CONN@
2 2 ON/OFFBTN# 14
CH751H-40PT_SOD323-2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 30 of 50

wWw.Laptopfix.vn
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 5 4 3 2 1

+5VALW USB_VCCA

2
R488
+5VALW 10K_0402_5%

U20
BT Connector

1
1 8 W=100mils JP17
GND OUT
2 IN OUT 7 1 1

150U_B2_6.3VM_R35M
3 IN OUT 6 15 USB20_N0 2 2
34,38 SLP_S4 SLP_S4 4 5 3 JP18
EN# OC# 15 USB20_P0 3

0.1U_0402_10V6K

1000P_0402_50V7K
1 1 4 4 1 +3VAUX_BT
D C593 G548A2P8U_MSOP8 5 D
1 1 GND 2
+ 6 USB20_P8_R R489 1 2 0_0402_5%
GND 3 USB20_P8 15
4.7U_0805_10V4Z (2A,100mils ,Via NO.=4) 7 USB20_N8_R R490 1 2 0_0402_5%
2 GND 4 USB20_N8 15

C594

C595
C592 8
2 2 2 GND 5 BT_LED 34
CONN@ SUYIN_020167MR004S511ZR_4P
ACES_87212-05G0_5P
CONN@

USB_VCCA
D26
4 2 USB20_P0
USB_VCCA USB_VCCB VIN IO1
USB20_N0 3 1
R769 IO2 GND +3VALW +3VAUX_BT
0_0805_5% PJLCR05_SOT143-4
1 2 Q35

D
3 1

C596

C597
+5VALW USB_VCCB SI2301BDS_SOT23

G
2
1
R492 1 1
10K_0402_5%

2
R491

2
+5VALW @ 10K_0402_5% 2 2

0.1U_0402_10V6K

10U_0805_10V4K
U21 R493

1
1 8 W=100mils JP19 15 BT_OFF 1 2
GND OUT
2 IN OUT 7 1 1

150U_B2_6.3VM_R35M
C 3 6 2 220K_0402_1% C
IN OUT 15 USB20_N1 2

@ 0.1U_0402_10V6K

@ 1000P_0402_50V7K
SLP_S4 4 5 3
EN# OC# 15 USB20_P1 3
1 1 4 4
C598 @ G548A2P8U_MSOP8 1 1 5
+ GND
6 GND
@ 4.7U_0805_10V4Z (2A,100mils ,Via NO.=4) 7
2 GND

C600

C601
@ C599 8
2 2 2 GND
CONN@ SUYIN_020167MR004S511ZR_4P
USB_VCCB
D27
4 2 USB20_P1
VIN IO1
USB20_N1 3 1
IO2 GND
PJLCR05_SOT143-4

ACCELEROMETER
+3VS_ACL

B B

0.1U_0402_10V6K

10U_0805_10V4K
+3VS +3VS_ACL +3VS_ACL_IO

C602

C603
1 1
D28 R518
CH751H-40PT_SOD323-2 0_0603_5%
2 1 1 2
2 2

U22
LIS302DL
+3VS_ACL_IO 1 VDD_IO
+3VS_ACL 6 VDD GND 2
GND 4
15 ACCEL_INT# 8 INT 1 GND 5
9 INT 2 GND 10

12 SDO
4,9,10,11,13,27,29,33 SMB_DATA_S3 13 SDA / SDI / SDO
4,9,10,11,13,27,29,33 SMB_CLK_S3 14 SCL / SPC
RSVD 3 +3VS_ACL
+3VS_ACL R494 2 1 10K_0402_5% 7 11
CS RSVD
HP302DLTR8_LGA14_3X5

L Must be placed in the center of the system.

Change U22 part description from

A LIS302DLTR LGA to HP302DLTR8 as HP A
change list. 12/03

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB & BT Connector & Acclerometer
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 31 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

+3VS +3VALW

Finger printer TPM1.2 on board

C604

0.1U_0402_10V6K

C605

0.1U_0402_10V6K

C606

0.1U_0402_10V6K

C607

0.1U_0402_10V6K
1 2 TPM_XTALI 1 1 1 1
C611 22P_0402_50V8J

Y6

1
2 2 2 2
2 1 R504
D NC IN 10M_0402_5% D
3 NC OUT 4

2
32.768KHZ 1TJS125DJ4A420P
+3VALW

24
19
10
Need update symbol

5
1 2 TPM_XTALO U23
C612 22P_0402_50V8J

VSB
VDD
VDD
VDD
LPC_LAD0 26
Q36 SI2301BDS_SOT23 LPC_LAD1 LAD0
23 LAD1
JP20 LPC_LAD2 20
S
USB20_N1_PWR +3VS LPC_LAD3 LAD2 TPM_GPIO +3VS

D
3 1 1 1 17 LAD3 GPIO 6 PAD T106
2 LPC_LFRAME# 22 2 TPM_GPIO2 PAD T107
15 USB20_N10 2 LFRAME# GPIO2

C608

C609
3 PLT_RST# 16 Base I/O Address
15 USB20_P10 3 LRESET#

1
R495 1 2 10K_0402_5% LPC_PD# 0 = 02Eh
G

1 1 4 28
2

4 SIRQ LPCPD#
27 SERIRQ
1 =* 04Eh
2

CONN@ CLK_PCI_TPM 21 R497

LCLK

0.1U_0402_10V6K

10U_0805_10V4K
R496 ACES 85203-04021 4P R498 4.7K_0402_5%
10K_0402_5% 2 2 @ SLB 9635 TT 1.2 0_0402_5%
1 2 1 2

2
+3VS @ C610 R499 10_0402_5% 15 8 1 2 1 2
10P_0402_50V8J CLKRUN# TEST1 R500 @
9
1

TESTB1/BADD 4.7K_0402_5%
14,35,36 PM_CLKRUN#

1
R501 7
220K_0402_1% +5VALW PP

15 FPR_OFF 1 2 D29 R502 3

USB20_P10 @ 4.7K_0402_5% TPM_XTALO NC
4 VIN IO1 2 14 XTALO NC 12
1

2
USB20_N10 TPM_XTALI NC
3 IO2 GND 1 13 XTALI/32K IN

1
PJLCR05_SOT143-4

GND
GND
GND
GND
R503
0_0402_5% SLB 9635 TT 1.2_TSSOP28

25
18
11
4
C C

2
Remove after DB2

CK32@ 0_0402_5% 2 1 R756 CLK_PCI_TPM

15 CLK_PCI_TPM_PCH

Add SIRQ and connect to

pin5. 10/08
+3VL
LPC Debug Port
BIOS ROM(4MB)

1
+3VL
R505 B+
100K_0402_5% 10/14 HP
1 SPI ROM Socket SPI ROM
20mils

2
C613 U24 &U1
0.1U_0402_10V6K 8 4
B 2 VCC VSS 8051_RECOVER# JP21 B
SPI_WP# 3 1
W CLK_PCI_DB Ground
2 LPC_PCI_CLK
20mils 1 2 SPI_HOLD#_1 7 3
+3VL HOLD Ground
R506 3.3K_0402_5% 45@ SST25VF032B-66_SO8 4
12,29,35,36 LPC_LFRAME# LPC_FRAME#
35 SPI_CS0# SPI_CS0# 1 12,35,36 SIRQ SIRQ 5
S +V3S
4,12,15,21,27,29,34 PLT_RST# 6 LPC_RESET#
35 SPI_CLK SPI_CLK 6 7
C 15,35 PCI_SERR# +V3S
12,29,35,36 LPC_LAD0 8 LPC_AD0
35 SPI_SI SPI_SI 5 2 SPI_SO_R 1 2 12,29,35,36 LPC_LAD1 9
D Q SPI_SO 35 LPC_AD1
R507 15_0402_5% 12,29,35,36 LPC_LAD2 10
WIESO_G6179-100000_8P LPC_AD2
12,29,35,36 LPC_LAD3 11 LPC_AD3
12 VCC_3VA
35 8051TX 13 PWR_LED#
35 8051RX 14 CAPS_LED#
35 8051_RECOVER# 8051_RECOVER# 15 NUM_LED#
43 DEBUG_KBCRST 16 VCC1_PWRGD
+3VL
20mils 1 2 SPI_WP# 1 2 SPI_CLK_JP 17
R508 3.3K_0402_5% R509 @ 0_0402_5% SPI_CS0#_JP SPI_CLK
18 SPI_CS#
SPI_SI_JP 19
SPI_SO_JP SPI_SI
20 SPI_SO
SPI_HOLD#_0 21 SPI_HOLD#
35 KBC_SPI_CS1#_R 22 Reserved
23 Reserved
SPI_HOLD#_1 2 1 SPI_HOLD#_0 24
0_0402_5% R510 Reserved
SPI_CLK 2 1 SPI_CLK_JP
0_0402_5% R511 ACES_87216-2404_24P
SPI_SI 2 1 SPI_SI_JP CONN@
0_0402_5% R512
SPI_CS0# 2 1 SPI_CS0#_JP
0_0402_5% R513
A SPI_SO_R 2 1 SPI_SO_JP A
0_0402_5% R514
Remove after DB2

CK32@ 0_0402_5% 2 1 R758 CLK_PCI_DB

15 CLK_PCI_DB_PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/SW LPC DEBUG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 28, 2008 Sheet 32 of 50
5 4 3 2 1

wWw.Laptopfix.vn
www.vinafix.vn
 ADPIN
DOCK CONN. 190PIN DOCKING CONNECTOR VA_ON#
1

1
+3VS

C615

C616
(2) PS/2 Interfaces C614
(2) USB 2.channels R516 0.1U_0402_10V6K
(2) SATA Channels +5VS DOCK_ID 1 R515 2 1K_0402_5%
1 1 2
(2) Display Port Channels 10K_0402_5%
(1) Serial Port

2
(1) Parallel Port
(1) Line In 2 2

C617

C618

C619

C620
(1) Line Out

0.1U_0402_10V6K

0.1U_0402_10V6K

10U_0805_10V4K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
(1) RJ45 (10/100/1000)
(1) VGA 1 1 1 1
(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface 2 2 2 2
JP22B

PAD T58 DCAD 143 46 DCAD2 T59 PAD

DP_CEC 143 46 DP_CEC2
22 DP_CEC 142 142 47 47 DP_CEC2 22
23 DPB_HPD 141 141 48 48 DPC_HPD 23
JP22A 14 SLP_S5# 2 1 R517 140 49 ON/OFF#
ADPIN 140 49 ON/OFF# 30
12A ADP_SIGNAL ADP_SIGNAL 1K_0402_5% 139 50 VA_ON#
139 50
190 P1 G1 189 138 138 51 51
137 137 52 52
136 136 53 53
135 135 54 54
188 188 1 1 134 134 55 55
MDO3+ 187 2 MDO1+ 133 56
28 MDO3+ 187 2 MDO1+ 28 133 56
MDO3- 186 3 MDO1- 132 57
28 MDO3- 186 3 MDO1- 28 132 57
185 4 36LPTSTB# LPTSTB# 131 58
185 4 131 58 D_DDCDATA 19
MDO2+ 184 5 MDO0+ 36LPTAFD# LPTAFD# 130 59
28 MDO2+ 184 5 MDO0+ 28 130 59 D_DDCCLK 19
MDO2- 183 6 MDO0- 36LPTERR# LPTERR# 129 60 D_VSYNC 19
28 MDO2- 183 6 MDO0- 28 129 60
182 7 36LPTACK# LPTACK# 128 61 D_HSYNC 19
182 7 LPTBUSY 128 61
36LPTBUSY 127 127 62 62
36 LPTPE LPTPE 126 63 R_DOCK_RED 1 R524 2 0_0402_5% DOCK_RED
DETECT LPTSLCT 126 63
181 181 8 8 LANLINK_STATUS# 15,27,28,35 36 LPTSLCT 125 125 64 64
180 9 LAN_ACT# 27,28 LPD7 124 65 R_DOCK_GRN 1 R525 2 0_0402_5% DOCK_GRN
180 9 36 LPD7 124 65
179 10 +5VS LPD6 123 66 R_DOCK_BLU 1 R526 2 0_0402_5% DOCK_BLU
179 10 36 LPD6 123 66
178 11 LPD5 122 67
178 11 36 LPD5 122 67
177 12 LPD4 121 68 DCD#1
177 12 36 LPD4 121 68 DCD#1 34,36
176 13 LPD3 120 69 RI#1 RI#1 34,36
176 13 36 LPD3 120 69
175 14 LPD2 119 70 DTR#1 DTR#1 34,36
175 14 36 LPD2 119 70
174 15 LPD1 118 71 CTS#1
09/25 HP 174 15 36 LPD1 118 71 CTS#1 34,36
173 16 LPD0 117 72 RTS#1
173 16 36 LPD0 117 72 RTS#1 34,36
172 17 LPTSLCTIN# 116 73 DSR#1
172 17 36 LPTSLCTIN# 116 73 DSR#1 34,36
171 18 LPTINIT# 115 74 TXD1
171 18 36 LPTINIT# 115 74 TXD1 34,36
170 19 30,34 STB_LED# 114 75 RXD1 RXD1 34,36
170 19 USB20_N11 15 114 75
169 20 113 76 SER_SHD SER_SHD 34,36
169 20 USB20_P11 15 12,34 SATA_LED# 09/25 HP 113 76
168 21 DOCK_ID 112 77 SMB_CLK_S3 4,9,10,11,13,27,29,31
168 21 28 DOCK_ID 112 77
167 22 ISO_PREP# 111 78
167 22 15 ISO_PREP# 111 78 09/25 HP SMB_DATA_S3 4,9,10,11,13,27,29,31
166 166 23 23 110 110 79 79
165 165 24 24 12 SATA_PTX_C_DRX_P4 109 109 80 80
164 25 12 SATA_PTX_C_DRX_N4 108 81 KBD_DATA
164 25 108 81 KBD_DATA 35
163 26 R521 0_0402_5% 107 82 KBD_CLK
163 26 107 82 KBD_CLK 35
162 162 27 27 12 SATA_PRX_DTX_P4 1 2 SATA_PRX_DTX_P4_R 106 106 83 83 PS2_DATA
PS2_DATA 35
161 161 28 28 12 SATA_PRX_DTX_N4 1 2 SATA_PRX_DTX_N4_R 105 105 84 84 PS2_CLK
PS2_CLK 35
160 29 R520 0_0402_5% 104 85
160 29 104 85 LINE_IN_SENSE 34
159 30 103 86 DOCK_HPS#
159 30 15 USB20_N13 103 86 DOCK_HPS# 34
0.1U_0402_10V6K 2 1 C621 R_DPB_TXP0 158 31 R_DPC_TXP0 C622 1 2 0.1U_0402_10V6K 102 87
23 DPB_TXP0 158 31 DPC_TXP0 23 15 USB20_P13 102 87
0.1U_0402_10V6K 2 1 C623 R_DPB_TXN0 157 32 R_DPC_TXN0 C624 1 2 0.1U_0402_10V6K 101 88
23 DPB_TXN0 157 32 DPC_TXN0 23 101 88 DOCK_LINE_IN_L 34
156 156 33 33 12 SATA_PTX_C_DRX_P3 100 100 89 89 DOCK_LINE_IN_R 34
0.1U_0402_10V6K 2 1 C625 R_DPB_TXP1 155 34 R_DPC_TXP1 C626 1 2 0.1U_0402_10V6K 12 SATA_PTX_C_DRX_N3 99 90
23 DPB_TXP1 155 34 DPC_TXP1 23 99 90
23 DPB_TXN1
0.1U_0402_10V6K 2 1 C627 R_DPB_TXN1 154 154 35 35 R_DPC_TXN1 C628 1 2 0.1U_0402_10V6K DPC_TXN1 23
R523 0_0402_5% 98 98 91 91 DLINE_OUT_L
DLINE_OUT_L 34
153 36 1 2 SATA_PRX_DTX_P3_R 97 92 DLINE_OUT_R
153 36 12 SATA_PRX_DTX_P3 97 92 DLINE_OUT_R 34
0.1U_0402_10V6K 2 1 C629 R_DPB_TXP2 152 37 R_DPC_TXP2 C630 1 2 0.1U_0402_10V6K 1 2 SATA_PRX_DTX_N3_R 96 93
23 DPB_TXP2 152 37 DPC_TXP2 23 12 SATA_PRX_DTX_N3 96 93
0.1U_0402_10V6K 2 1 C631 R_DPB_TXN2 151 38 R_DPC_TXN2 C632 1 2 0.1U_0402_10V6K R522 0_0402_5% 95 94 DETECT
23 DPB_TXN2 151 38 DPC_TXN2 23 95 94
150 150 39 39
23 DPB_TXP3
0.1U_0402_10V6K 2 1 C633 R_DPB_TXP3 149 149 40 40 R_DPC_TXP3 C634 1 2 0.1U_0402_10V6K DPC_TXP3 23
0.1U_0402_10V6K 2 1 C635 R_DPB_TXN3 148 41 R_DPC_TXN3 C636 1 2 0.1U_0402_10V6K
23 DPB_TXN3 148 41 DPC_TXN3 23
147 147 42 42
0.1U_0402_10V6K 2 1 C637 R_DPB_AUX 146 43 R_DPC_AUX C638 1 2 0.1U_0402_10V6K 192 191
23 DPB_AUX 146 43 DPC_AUX 23 G2 G1
0.1U_0402_10V6K 2 1 C639 R_DPB_AUX# 145 44 R_DPC_AUX# C640 1 2 0.1U_0402_10V6K 194 193
23 DPB_AUX# 145 44 DPC_AUX# 23 G4 G3
144 144 45 45 196 G6 G5 195
198 G8 G7 197
200 G10 G9 199
FOX_QL0094L-D26601-5H 10/04 HP 10/14 HP
FOX_QL0094L-D26601-5H

DOCK_RED R677 2 1@ 150_0402_1%

DOCK_GRN R680 2 1@ 150_0402_1%
DOCK_BLU R687 2 1@ 150_0402_1%
+3VS
10/17 HP DOCK_RED C665 1 2 @ 0.1U_0402_10V6K
R_DPC_AUX# R528 1 2 100K_0402_5% DOCK_GRN C698 1 2 @ 0.1U_0402_10V6K
R_DPB_AUX# R530 1 2 100K_0402_5% DOCK_BLU C699 1 2 @ 0.1U_0402_10V6K
R_DPC_AUX R529 1 2 100K_0402_5%
R_DPB_AUX R531 1 2 100K_0402_5% 09/25 HP 09/30 HP

09/17 HP

U25 09/30 HP U26 09/30 HP U27 09/30 HP

1 6 DOCK_ID 1 6 DOCK_ID 1 6 DOCK_ID

19 VGA_RED NO IN 19 VGA_GRN NO IN 19 VGA_BLU NO IN
+3VS C691 +3VS C692 +3VS C693
2 GND VCC 5 2 1 2 GND VCC 5 2 1 2 GND VCC 5 2 1

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

DOCK_RED 3 4 RED_R 19 DOCK_GRN 3 4 GREEN_R 19 DOCK_BLU 3 4 BLUE_R 19
NC COM NC COM NC COM

TS5A3157_SC70-6 TS5A3157_SC70-6 TS5A3157_SC70-6

IN NC<-->COM NO<-->COM

L ON OFF Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
H OFF ON
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 33 of 50

wWw.Laptopfix.vn
www.vinafix.vn
 5 4 3 2 1

C739
Audio/Express Card/TP/LEDs Connector @ 0.1U_0402_10V6K
1 2

JP27
DOCK_LINE_IN_L 1 2 DLINE_OUT_L
33 DOCK_LINE_IN_L
33 DOCK_LINE_IN_R
33 LINE_IN_SENSE
DOCK_LINE_IN_R
LINE_IN_SENSE
3
5
1
3
5
2
4
6
4
6
DLINE_OUT_R
DOCK_HPS#
DLINE_OUT_L 33
DLINE_OUT_R 33
DOCK_HPS# 33
Serial Port CONN
7 8
7 8 +5VS
9 9 10 10
HDA_BIT_CLK_CODEC 11 12 A_SD +3VL +3VALW +5VS +3VS +1.5VS
12 HDA_BIT_CLK_CODEC 11 12 A_SD 35
HDA_SDOUT_CODEC 13 14 EAPD JP23
D 12 HDA_SDOUT_CODEC 13 14 EAPD 35 D
HDA_RST#_CODEC 15 16 HDA_SPKR 1
12 HDA_RST#_CODEC 15 16 HDA_SPKR 12 1
HDA_SYNC_CODEC 17 18 DCD#1 2
12 HDA_SYNC_CODEC 17 18 33,36 DCD#1 2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
HDA_SDIN0 19 20 CLK_PCIE_EXP# DSR#1 3
12 HDA_SDIN0 19 20 33,36 DSR#1 3
+3VL 21 22 CLK_PCIE_EXP 33,36 RXD1 RXD1 4
21 22 RTS#1 4
+3VALW 23 24 1 1 1 1 1 33,36 RTS#1 5
23 24 PCIE_PTX_C_DRX_N2 TXD1 5
+5VS 25 25 26 26 PCIE_PTX_C_DRX_N2 13 33,36 TXD1 6 6

C646

C647

C648

C649

C650
27 28 PCIE_PTX_C_DRX_P2 CTS#1 7
+3VS 27 28 PCIE_PTX_C_DRX_P2 13 33,36 CTS#1 7
29 30 RI#1 8
+1.5VS 29 30 2 2 2 2 2 33,36 RI#1 8
SLP_S3# 31 32 PCIE_PRX_DTX_N2 DTR#1 9
14,27,35,37,38,41,43,44,45,46,49 SLP_S3# 31 32 PCIE_PRX_DTX_N2 13 33,36 DTR#1 9
14,27,29 PCIE_WAKE# PCIE_WAKE# 33 34 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 13 33,36 SER_SHD SER_SHD 10
PLT_RST# 33 34 10
4,12,15,21,27,29,32 PLT_RST# 35 35 36 36 11 11
CLKREQ_EXP# 37 38 USB20_N4 12
13 CLKREQ_EXP# 37 38 USB20_N4 15 12
AMBER_BATLED# 39 40 USB20_P4
35 AMBER_BATLED# 39 40 USB20_P4 15
AQUAWHITE_BATLED# 41 42 ACES 87213-1200G 12P P1
35 AQUAWHITE_BATLED# SATA_LED# 41 42 TP_CLK
43 44 TP_CLK 35 CONN@
12,33 SATA_LED# 43 44
HDD_HALTLED 45 46 TP_DATA TP_DATA 35
12 HDD_HALTLED STB_LED# 45 46
30,33 STB_LED# 47 47 48 48
WL/BT_LED# 49 50
30 WL/BT_LED# 49 50
09/23 HP
51 52
51 52 CLK_PCIE_EXP
13 CLK_PCIE_EXP_PCH 1 4 RP31
ACES_88075-05071_50P-T 2 3 CLK_PCIE_EXP#
13 CLK_PCIE_EXP_PCH#
CONN@ 0_4P2R_5%
CK32@

Remove after DB2

+3VS

C C

1
R532
47K_0402_5%

2
+3VS

WL/BT_LED#
3

47K
Q37
DTA114YKAT146_SOT23-3 Q38A
2 10K BT_LED 2 2N7002DW T/R7_SOT-363-6
29 WL_LED# 31 BT_LED 10/07
1

3
1

Q38B
WL_LED 5 2N7002DW T/R7_SOT-363-6
4
1

29 WW_LED# 2 10K
BT_LED R533 1 2 100K_0402_5%

B
47K B
Q39 WL_LED R534 1 2 100K_0402_5%
3

DTA114YKAT146_SOT23-3

+3VS
Card Reader 7 in 1 + 2 Port USB Connector
+3VS
JP28
1 2 +5VALW
1 2
3 3 4 4
CLK_PCIE_CARD# 5 6
5 6 SLP_S4 31,38
CLK_PCIE_CARD 7 8 PLT_RST#
7 8
9 10
9 10
13 PCIE_PTX_C_DRX_N3 11 12 USB20_N2 15
11 12 +3VS
13 PCIE_PTX_C_DRX_P3 13 14 USB20_P2 15
13 14
15 16
15 16
13 PCIE_PRX_DTX_N3 17 18 USB20_N3 15
17 18
13 PCIE_PRX_DTX_P3 19 20 USB20_P3 15
19 20

0.1U_0402_10V6K
21 G1 G2 22

ACES_88075-02071_20P-T 1
CONN@

C651
2

1 4 RP33 CLK_PCIE_CARD
13 CLK_PCIE_CARD_PCH CLK_PCIE_CARD#
13 CLK_PCIE_CARD_PCH# 2 3
A 0_4P2R_5% A
CK32@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CR&LEDS&PW&Audio&Exp Conn

wWw.Laptopfix.vn
www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 34 of 50
5 4 3 2 1
 +3VL System Board ID Detect Q57A ID R645 R647 R648 R649
2N7002DW T/R7_SOT-363-6
0_0402_5% 6 1 05h X X
RP21 +3VL R645 1 2
1 8 KSI0 R647 1 2 06h X X
2 7 KSI3 @ 0_0402_5%

2
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_0805_10V4Z
3 6 KSI2 0_0402_5% 07h X
+3VL

C653

C654

C655

C656

C657
4 5 KSI1 1 1 1 1 1 1 2 +3VS R648 1 2

0.1U_0402_10V6K
R548 0_0402_5% R649 1 2 09h X X
10K_0804_8P4R_5% RP30 @ 0_0402_5%

C658
1 1 8 KSO4 3 4 0Ah X X
RP22 2 2 2 2 2 KSO2
2 7
1 8 KSI7 3 6 KSO1 Q57B 0Bh X
2 7 KSI6 4 5 KSO0 2N7002DW T/R7_SOT-363-6

5
KSI5 2 ADP_EN
3 6 0Dh X
4 5 KSI4 10K_0804_8P4R_5%
09/18 0Eh X

106

119
10K_0804_8P4R_5%

39
58
84

14

49

1
U29 0Fh
128 15 CAP C659 1 2 4.7U_0805_10V4Z R690

VCC1
VCC1
VCC1
VCC1
VCC1

VCC1

VCC2
32 SPI_SI FLDATAOUT CAP
12 KBC_SPI_SI_R 127 HSTDATAOUT/GPIO45 47K_0402_5%
32 SPI_CS0# 97 FLCS0# GPIO28 93
12 KBC_SPI_CS0#_R 96 98

2
HSTCS0#/GPIO44 GPIO29
32 SPI_SO 95 FLDATAIN GPIO30 99 AC_PRESENT 14,23,38
94 100 R550 1 2 0_0402_5%
12 KBC_SPI_SO HSTDATAIN/GPIO43 GPIO31 EAPD 34
GPIO32 126 PCI_SERR# 15,32 10/15 HP
30 KSO[0..13]
KSO0 21 124 KBC_PWR_ON
KSO0 OUT0/(SCI) KBC_PWR_ON 43
KSO1 20 125 AQUAWHITE_BATLED#
KSO1 OUT1/IRQ8# AQUAWHITE_BATLED# 34
KSO2 19 R552 1 2 1091@ 0_0402_5%
KSO2 BATSELB_A# 42
KSO3 18 123 R554 1 2 1098@ 0_0402_5%
KSO3 CFETA/OUT7/nSMI FET_A 42
KSO4 17 122 KBRST# CH751H-40PT_SOD323-2 1 2 D32 10/01 HP
KSO4 OUT8/KBRST KB_RST# 15

Keyboard/Mouse Interface
KSO5 16 121

SMSC_1098-NU_TQFP-128P
KSO5 OUT9/PWM2 FAN_PWM 4

General Purpose I/O Interface

KSO6 13 120 2 R678 1
KSO6 OUT10/PWM0 BAT_PWM_OUT 41 LOW_BAT# 14
KSO7 12 118 1091@ 0_0402_5%
KSO7 PWM_CHRGCTL CHGCTRL 41
KSO8 10 P80 2 R679 1
KSO8 ADP_DET# 48
KSO9 9 107 THM_TRAVEL# 1098@ 0_0402_5%
KSO9 GPIO01 THM_TRAVEL# 40
KSO10 8 79
KSO10 GPIO02 ON/OFFBTN_KBC# 30
KSO11 7 80 P80
+5VS KSO12 KSO11 GPIO03
6 KSO12/GPIO00/KBRST GPIO04/KSO14 81 SLP_S3# 14,27,34,37,38,41,43,44,45,46,49
KSO13 5 83 10/03 HP +3VL
RP34 KSO13/GPIO18 GPIO05/KSO15 8051_RECOVER# 32
1 8 TP_CLK 30 KSI[0..7] 85 PM_RSMRST# BATCON R558 1 2
GPIO07/PWM3 PM_RSMRST# 14
2 7 TP_DATA KSI0 29 86 CRACK_BGA @ 10K_0402_5%
KSI0 GPIO08/RXD CRACK_BGA 17,25
3 6 KBD_CLK KSI1 28 87 KBRST# 1 2
KBD_DATA KSI2 KSI1 GPIO09/TXD R549 10K_0402_5%
4 5 27 KSI2
KSI3 26 88 AB2A_DATA R560 1 2 0_0402_5% VCC1_PWRGD 1 2
KSI3 GPIO11/AB2A_DATA CAP_DAT 13,23,30
10K_0804_8P4R_5% KSI4 25 89 AB2A_CLK R561 1 2 0_0402_5% R551 10K_0402_5%
KSI4 GPIO12/AB2A_CLK CAP_CLK 13,23,30
KSI5 24 90 R562 1 2 0_0402_5% CRACK_BGA 1 2
KSI5 GPIO13/AB2B_DATA CELLS 41
KSI6 23 91 R563 1 2 0_0402_5% R553 100K_0402_5%
RP23 KSI6 GPIO14/AB2B_CLK A_SD 34
KSI7 22 92 BATCON
KSI7 GPIO15/FAN_TACH1 BATCON 42
1 8 SP_CLK 101
GPIO16/FAN_TACH2 THM_MAIN# 40
2 7 SP_DATA 102 09/28 HP
GPIO17/A20M GATEA20 15
3 6 PS2_CLK TP_CLK 35
34 TP_CLK IMCLK
4 5 PS2_DATA TP_DATA 36 103
34 TP_DATA IMDAT GPIO20/PS2CLK KBD_CLK 33
P61 61 105
KCLK GPIO21/PS2DAT KBD_DATA 33
10K_0804_8P4R_5% P62 62 4 KBC_PWR_ON 1 2
KDAT GPIO24/KSO16 LANLINK_STATUS# 15,27,28,33
PS2_CLK 66 74 R557 10K_0402_5%
33 PS2_CLK EMCLK ADP_PRES[CKT#2]/GPIO27/WK_SE05 ADP_PRES 27,41,42,48
PS2_DATA 67 LATCH 1 2
33 PS2_DATA EMDAT
09/22 HP R559 10K_0402_5%
10/07 HP FET_A 1 2
111 AB1A_DATA AB1A_DATA 40 R575 10K_0402_5%
AB1A_DATA AB1A_CLK FET_B
AB1A_CLK 112 AB1A_CLK 40 1 2
Access Bus Interface R576 10K_0402_5%
14,32,36 PM_CLKRUN# 55 109 AB1B_DATA
CLKRUN# AB1B_DATA AB1B_DATA 40
57 110 AB1B_CLK
12,32,36 SIRQ SER_IRQ AB1B_CLK AB1B_CLK 40 +3VL
CLK_PCI_KBC
RUNSCI_EC#
54
76
PCI_CLK Power Mgmt/SIRQ 73 R564 1 2 0_0402_5% RP24
15 RUNSCI_EC# EC_SCI# GPIO25 CAP_INT 30
4.7K_0804_8P4R_5%
108 R566 1 2@ 10_0402_5% C660 1 2 @ 10P_0402_50V8J AB1A_CLK 1 8
GPIO26/KSO17 1091@ CLK_14M_KBC AB1A_DATA
12,29,32,36 LPC_LAD3 51 LAD[3] NC_CLOCKI 59 1 R567 2 0_0402_5% 2 7
32K_CLK R568 1 2 0_0402_5% AB1B_CLK

Miscellaneous
12,29,32,36 LPC_LAD2 50 LAD[2] 32KHZ_OUT/GPIO22/WK_SE01 75 ADP_EN 48 3 6
48 60 PGD_IN R569 1 2 10K_0402_5% The Timing from PWR_GD to AB1B_DATA 4 5
12,29,32,36 LPC_LAD1 LAD[1] RESET_OUT#/GPIO06 PM_PWROK 12,14,47
46 LPC 78 PWR_GD
12,29,32,36 LPC_LAD0 LAD[0] PWRGD PWR_GD 37,47 PM_PWROK should be more than
77 P77 R570 1 2 0_0402_5%
52
Bus VCC1_RST#
38 R597 2 1
VCC1_PWRGD 43,48
12,29,32,36 LPC_LFRAME# LFRAME# ADC_TO_PWM_OUT/GPIO19 1098@ 0_0402_5%
OCP 48 99ms.
15,36 NPCI_RST# 53 LRESET#
69 R593 2 1 1091@ 0_0402_5% SP_CLK 1091@ 0_0402_5%
TEST PIN TEST R572 1 1K_0402_5% P77
2 1 R573 2 1091_VCC1_RST# 37
R642 2 1 1091@ 0_0402_5% ADP_ID 10/01 HP
ADP_ID 48
CRY1 70 116 R641 2 1 1098@ 0_0402_5%
XTAL1 CFETB/GPIO10 FET_B 42
CRY2 71 113
XTAL2 BAT_LED# AMBER_BATLED# 34
PWR_LED#/8051TX 115 8051TX 32
+VCC0 68 114 PM_PWROK 2 1 VCC1_PWRGD
VCC0 FDD_LED#/8051RX 8051RX 32
09/22 HP 1 2 +3VL D34 CH751H-40PT_SOD323-2
42 BAT_ALARM 1 R574 100K_0402_5%
Alarm [CKT#2]/GPIO36 P41
12 KBC_SPI_CLK_R 2 HSTCLK/GPIO41 AC[CKT#2]/GPIO23 41
P42 PGD_IN
32.768KHZ 1TJS125DJ4A420P

32 SPI_CLK 3 FLCLK ADC2/GPIO40 42 1 2

30 65 P65 R577 10K_0402_5%
29 MC2_DISABLE GPIO39 Q/GPIO33
1

12 PCH_SPI_CS1#_R 31 64 R579 1 2 0_0402_5%

HSTCS1#/GPIO42 GPIO34 LID_SW# 12,20,30
33P_0402_50V8J

33P_0402_50V8J

Y7 32 63 R581 1 2 @ 0_0402_5%
OUT
IN

32 KBC_SPI_CS1#_R FLCS1# GPIO35 CAP_RST_EC 30

C661

C662

29 MC1_DISABLE 33 GPIO38 AVCC 40

1 1 34 R601 2 1 1098@ 0_0402_5% +3VL
GPIO37
AGND

AVSS

1098@ 0_0402_5% 1 R592 2 P43 43 R599 2 1 1091@ 0_0402_5% SP_DATA

41 PMC
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ADC1/GPIO46
2 P44
NC

NC

48 OCP_A_IN 1 44 ADC_TO_PWM_IN
R595 1098@ 0_0402_5%
2 2 KBC1098-NU_VTQFP_128P
2

72

11
37
47
56
104
82
117

45

1098@
09/22 Change to R644 1 2 0_0402_5% LATCH 42
1098 symbol 2 R587 1
ADP_PS1 48
33pF only for 1070/1091 0_0402_5% P65 R578 1 2 0_0402_5% LANLINK_STATUS#
1091@ 1091@
2

1091@ 1 R583 2 P43

0_0402_5% R589
+RTCVCC 1091@ 1 R584 2 P44 0_0402_5% 2 R594 1 PS2_CLK
1 0_0402_5% 1098@ SP_CLK 1098@ 1 R585 2 P61 1091@ 0_0402_5%
30 SP_CLK
C663 0_0402_5% P41 2 R598 1
AC_AND_CHG 41,42
1
1

4.7U_0805_10V4Z SP_DATA 1098@ 1 R590 2 P62 1098@ 0_0402_5%

30 SP_DATA
1091@ 0_0402_5%
R591 2
0_0402_5% ADP_PS0 1091@ 0_0402_5% 2 R571 1 P61 2 R600 1 PS2_DATA
48 ADP_PS0
1091@ 0_0402_5%
2

SLP_S3# 1091@ 0_0402_5% 2 R582 1 P62 P42 2 R602 1 ADP_A_ID

Remove after DB2 ADP_A_ID 48
R596 1 2 +VCC0 1098@ 0_0402_5%
@ 0_0402_5% 10/01 HP
C664

1U_0603_10V4Z

C666

0.1U_0402_10V6K

CK32@ 0_0402_5% 2 1 R760 CLK_PCI_KBC

15 CLK_PCI_KBC_PCH
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

13 CLK_14M_KBC_PCH
CK32@ 0_0402_5% 2 1 R762 CLK_14M_KBC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBC1091
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 35 of 50

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 5 4 3 2 1

+3VS
+3V_PLL RP25
RI#1 1 8
+3VS CTS#1 2 7
DSR#1 3 6
+3VS +3V_PLL DCD#1 4 5
L48 0.1U_0402_10V6K
D 1 2 4.7K_0804_8P4R_5% D
1 1
FCM1608KF-601T02_2P_0603 C689 C690

C667

C668
1 1 0.1U_0402_10V6K 2 1
2 2 0_0402_5% R603

15
36
48

13
34
46
1000P_0402_50V7K

0.1U_0402_10V6K

1
2 2 U30

VSTBY

AVSS
AVCC
VCC_1
VCC_2

VSS_1
VSS_2
VSS_3
33 LPTERR#
2 @1 LPTERR# 16 33 LPC_LDRQ#0 LPC_LDRQ#0 12
C669 180P_0402_50V9 LPTSLCT ERR# / GPIO34 LDRQ# CLK_PCI_SIO
33 LPTSLCT 17 SLCT / GPIO35 LPCCLK 35
33 LPTSTB# LPTSTB# 18 POWER/GND 37 LPC_LFRAME# LPC_LFRAME# 12,29,32,35
LPD0 STB# / GPIO00 LFRAME# LPC_LAD0
33 LPD0 19 PD0 / GPIO01 LAD0 38 LPC_LAD0 12,29,32,35
33 LPD1 LPD1 20 39 LPC_LAD1 LPC_LAD1 12,29,32,35
LPD2 PD1 / GPIO02 LAD1 LPC_LAD2
21 40

LPC I/F
33 LPD2 LPC_LAD2 12,29,32,35

PARALLEL I/F
LPD3 PD2 / GPIO03 LAD2 LPC_LAD3
33 LPD3 22 PD3 / GPIO04 LAD3 41 LPC_LAD3 12,29,32,35
33 LPD4 LPD4 23 42 NPCI_RST#
PD4 / GPIO05 LPCRST# NPCI_RST# 15,35
33 LPD5 LPD5 24 43 SIRQ SIRQ 12,32,35
LPD6 PD5 / GPIO06 SERIRQ SIO_PD#
33 LPD6 25 PD6 / GPIO07 LPCPD# / GPIO17 44 1 2 +3VS
33 LPD7 LPD7 26 45 PM_CLKRUN# PM_CLKRUN# 14,32,35 R604 10K_0402_5%
LPTINIT# PD7 / GPIO10 CLKRUN# / GPIO20
33 LPTINIT# 27 INIT# / GPIO11
33 LPTAFD# LPTAFD# 28 47 CLK_48M_SIO
LPTSLCTIN# AFD# / GPIO12 CLOCK CLKIN
33 LPTSLCTIN# 29 SLIN# / GPIO13
LPTACK# 30 3 DCD#1
33 LPTACK# ACK # / GPIO14 DCD# / GPIO21 / CIR1TX DCD#1 33,34
LPTBUSY 31 4 DSR#1
33 LPTBUSY DSR#1 33,34

SERIAL I/F
LPTPE BUSY / GPIO15 DSR# / GPIO22 / CIR1RX RXD1
33 LPTPE 32 PE / GPIO16 SIN / CIR0TX / GPIO23 5 RXD1 33,34
6 RTS#1
RTS# / CIR0RX / GPIO24 RTS#1 33,34
7 TXD1
SOUT / WUINTR# / GPIO25 TXD1 33,34
33,34 SER_SHD 11 8 CTS#1
FIRRX / GPIO31 CTS# / GPIO26 / ED1 CTS#1 33,34
12 9 RI#1
C FIRTX / GPIO32 RI# / GPIO27 / ED0 RI#1 33,34 C

FIR
14 10 DTR#1 2 1 +3VS
FIRRX2(BW)/ GPIO33 DTR# / GPIO30 / BADDR R605 4.7K_0402_5%

2
DTR#1 33,34
R606
@ 560_0402_5%
CK32@ 0_0402_5% 2 1 R764 CLK_48M_SIO IT8305E-L_LQFP48_7X7 DTR#1:
13 CLK_48M_SIO_PCH

1
1: Base I/O address 4E/4F
0: Base I/O address 2E/2F
Remove after DB3

CK32@ 0_0402_5% 2 1 R766 CLK_PCI_SIO

15 CLK_PCI_SIO_PCH

CLK_PCI_SIO CLK_48M_SIO Parallel Port +5VS

1

2
R607 R608
@ 10_0402_5% @ 10_0402_5% D35
TO IT8305
CH751H-40PT_SOD323-2
2

1 1

1
C670 C671
+5VS_PRN
@ 18P_0402_50V8J @ 10P_0402_50V8J
2 2 LPTERR# 1 R609 2
4.7K_0402_5%

B B
RP27
LPD1 1 8
LPD0 2 7
LPTSTB# 3 6
LPTSLCT 4 5

2.2K_0804_8P4R_5%
RP28
LPD5 1 8
LPD4 2 7
LPD3 3 6
LPD2 4 5

2.2K_0804_8P4R_5%
RP29
LPTAFD# 1 8
LPTINIT# 2 7
LPD7 3 6
LPD6 4 5

2.2K_0804_8P4R_5%
RP26
LPTPE 1 8
LPTBUSY 2 7
LPTACK# 3 6
LPTSLCTIN# 4 5

2.2K_0804_8P4R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Super I/O IT8305E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 36 of 50
5 4 3 2 1

wWw.Laptopfix.vn
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 +3VS

R610
1 2

1
1 2 1M_0402_5%
46 1.05VS_POK
R668 3.3K_0402_5% R611
+5VALW 10K_0402_5%
46 1.5V_POK 1 2
R612 3.3K_0402_5%

2
8
U31A
1 2 1 2 3

P
+5VS +
R613 76.8K_0402_1% R614 10K_0402_5% 1 1 2
O VCCP_EN 44
2VREF_51125 1 2 2VREF_393 2 -
J4 SHORT PADS

G
+0.75VS 1 2 R615 34.8K_0402_1%
R616 11.5K_0402_1% LM393DR2G_SO8

4
D36 1 2
1 2 1 2 R617 49.9K_0402_1%
25,45 1.1VS_POK +3VL
R618 3.3K_0402_5%
CH751H-40PT_SOD323-2 1
D37 C672
14,27,34,35,38,41,43,44,45,46,49 SLP_S3# 1 2 1 2 1000P_0402_50V7K

5
R619 3.3K_0402_5% U28
CH751H-40PT_SOD323-2 2
1

P
IN1
1 O 4 PWR_GD 35,47
C673 2
44 VCCP_POK IN2

1
3300P_0402_25V7K MC74AHC1G08DFT2G SC70 5P

3
2 R620 R674
1 2 4.99K_0402_1%
1M_0402_5%

2
1 2 +5VALW
49 1.8VS_POK
R669 3.3K_0402_5%
VTTPWRGOOD 4

8
U31B
1 2 1 2 5

P
49 NVVDD_POK +

1
R670 3.3K_0402_5% R621 10K_0402_5% 7
2VREF_393 O R675
2VREF_393 6 -

G
+3VS 1 2 2.49K_0402_1%
R671 49.9K_0402_1% LM393DR2G_SO8

2
+1.5VS 1 2
R672 22.6K_0402_1%

2
R673
1
C687
26.7K_0402_1%
3300P_0402_25V7K
1

H1 H2 H3 H7 H8
HOLEA HOLEA HOLEA HOLEA HOLEA

1
H9 H10 H11 H12 H13
HOLEA HOLEA HOLEA HOLEA HOLEA

1
+3VL
1091@ 1091@
R622 2 1 1M_0402_5% R623 1 2 10K_0402_5% +3VL
1

VL
R624
1091@ 23.7K_0402_1%
H14 H15 H17 H16 H20 H19 H18
2

1091@ U32A HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

R625 1 2 23.7K_0402_1% 3
KBC Power OK
P

+
O 1 1091_VCC1_RST# 35
2200P_0402_50V7K

update KBC power good. 9/19 2

1
-
1

G
C674

1 VL VL
LM393DR2G_SO8
4
1091@ 100K_0402_5%

R626
1

1091@ 51.1K_0402_1%
1

2
R627

R628
2

1M_0402_5%
1091@
ZZZ1
2

9/21
2

FM2 FM3 FM1 FM4

1091@ 1 1 1 1
C675
1

1091@ 0.1U_0402_10V6K D 10/01 HP

1 2 2 Q43 PCB-LA-4891P
G 2N7002_SOT23-3
S 1091@
3

2VREF_51125

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 37 of 50

wWw.Laptopfix.vn
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 A B C D E

+3VALW to +3VS Transfer +1.5V to +1.5VS Transfer

+5VALW to +5VS Transfer +1.5V +1.5VS
B+ +3VALW +3VS
SI7326DN-T1-E3_PAK1212-8 +5VALW +5VS Q44
U33 SI7326DN-T1-E3_PAK1212-8 AO4430 1N SOIC-8
1 U34 8 1

1
2 1 7 2

0.1U_0402_10V6K

10U_0805_10V4K

0.1U_0402_10V6K
1 5 3 2 6 3 1
1

C677

C679
R629 1 1 5 3 5

C680

C682

10U_0805_10V4K

C683

0.1U_0402_10V6K

C684

0.1U_0402_10V6K

C685

10U_0805_10V4K
330K_0402_5% C676 1 1 1
C681 1 1 1 1
2

4
2 10U_0805_10V4K C678 10U_0805_10V4K

4
2 2 10U_0805_10V4K
RUNON 2 2 2
RUNON 2 2 2 2
1

1
RUNON
J5
SHORT PADS R630 R631
62

820K_0402_5% 470_0402_5%
2

2
1
SLP_S3 2 C686
Q1A 0.01U_0402_16V7K
2N7002DW T/R7_SOT-363-6
1

14,23,35 AC_PRESENT 5
Q1B
2N7002DW T/R7_SOT-363-6
4

2 2

+3VL +3VL
1

1
R632 R633
100K_0402_5% 100K_0402_5%
2

2
31,34 SLP_S4 SLP_S4 SLP_S3
6

3
14,46 SLP_S4# 2 14,27,34,35,37,41,43,44,45,46,49 SLP_S3# 5
Q63A Q63B
2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6
1

4
3 3

Discharge circuit-1
+1.05VS +3VS +1.5VS +5VS
1

R634 R635 R636 R637

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
2

2
6

D
SLP_S3 2
G Q50
SLP_S3 2 S 2N7002_SOT23-3 SLP_S3 2 SLP_S3 5
3

Q45A Q64A Q45B

2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6
1

+1.5V +0.75VS +1.8VS

1

4 4
R650 R651 R638
470_0402_5% 470_0402_5% 470_0402_5%
2

2
6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
SLP_S4 2 SLP_S3 5 SLP_S3 5
Q65A Q65B Q64B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6 2N7002DW T/R7_SOT-363-6 Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 38 of 50
A B C D E

wWw.Laptopfix.vn
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 5 4 3 2 1

D D

+1.5V
AC VIN LM331 +0.75VSP 2A
G2992
Adapter Thermal
LDO(0.75V)
in Protector
Page39 SLP_S3# Page44
Page39 +1.5V
+1.1VSP 3A
APL5913 +5VALW
ADP_EN# SWITCH LDO(1.1V) PWR_GD
EN0 2VREF_51125
B+
SLP_S3# Page44

VDD VR_ON
EN0
+3VALWP 3A
B+ B+
TPS51125 +1.05V_VCCP 18A ISL62883&ISL6208
C ISL6269A C
DC/DC DC/DC
(1.05V)
(3V/5V) SLP_S3# (CPU_CORE)
+5VALWP 4.5A
51125_PWR VCCP_EN Page43 Page46
Page42

CPU_CORE
( 48A)
BQ24740 TPS51124
Charger DC/DC +1.8VSP 3A
B+ (1.8V/VGA)
Page40
B+
+1.5VSP 8A
B VGA_COREP 10A TPS51117 B
SLP_S3# EN1/EN2 Page48 (1.05V)
BATSELB_A
Battery SLP_S3# EN_PSV
Page45
Selector
Circuit BATSELB_A# B+
Battery A Battery B +1.5VP 8A
Page41 TPS51117
6 Cell 8 Cell
(1.5V)

SLP_S4# EN_PSV
Page45

SWITCH SWITCH SWITCH Battery Battery

Connector Connector
A Page39 B Page39
A A
BATT
BATT_A Title

BATT_B
POWER BLOCK DIAGRAM
Size Document Number Rev

5 4 wWw.Laptopfix.vn
www.vinafix.vn 3
Date:
2
Monday, October 27, 2008 Sheet
1
39 of 50
 A B C D

ADP_SIGNAL
PJP1
6 GND ID 1

7 GND V+ 2
VIN
8 GND V+ 3 ADPIN PL1
1 9 4 SMB3025500YA_2P 1
GND V- ADPIN 1 2
10 GND V- 5

3
11

100P_0402_50V8J

1000P_0402_50V7K
GND

1
PC3

1
PC1

PC4
FOX_JPD113D-NBA50-7F 100P_0402_50V8J PR1
@15K_0402_5%
PD1 PC2

2
PJSOT24C_SOT23 1000P_0402_50V7K

2
VMB_A BATT_A
PJP2 PL2
1 SMB3025500YA_2P
1
2 2 1 2
3 3
4 4

1
5 5 2 1
6 PR2 1M_0402_1%
6 PC5 PC6
7

2
7 1000P_0402_50V7K 0.01U_0402_50V4Z
8 8

SUYIN_200046MR008G102ZR

100_0402_5%
100P_0402_50V8J

100P_0402_50V8J
1

1
1K_0402_5%

100_0402_5%
2 2
1

1
PR6
PR3

PC7

PR5

PC8
PC9
100P_0402_50V8J
2

2
+3VL VL PR88
2

2
69.8K_0402_1%
1 2
1

PR4
100K_0402_5%
PR89 AB1A_DATA 35
PQ29 100K_0402_1%
2

E
MMBT3906_SOT23-3
35 THM_MAIN#
2

B
2 AB1A_CLK 35
1

D C
PD15 PD16 PD17
1

2 BAV99W T1G_SC70-3 BAV99W T1G_SC70-3 BAV99W T1G_SC70-3

G
1

S
3

PQ30
SSM3K7002FU_SC70-3 PR91 PR90 VL
220K_0402_5% 150K_0402_1% +3VL
2

PH1 under CPU botten side :

2

CPU thermal protection at 90 +-3 degree C

PR92
294K_0402_1%
(Need to be checked)
48 OCP_ADJ 1 2
3 3

VMB_B BATT_B 2VREF_51125

PCN1 PL3
SMB3025500YA_2P
1 1 2 PR8
BATT+
470K_0402_1%

1
2 PR7 1 2 VL
SMD
1

3 1K_0402_5% PH1
SMC 100K_0603_1%_TSM1A104F4361RZ
B/I 4 1 2 Close to CPU
5 PC11 PC10
2

TS 1000P_0402_50V7K 0.01U_0402_50V4Z PR12 VL

PR10

2
6 150K_0603_1% PU1
GND 100K_0402_5%
1 2 1 +IN EN0 43
SUYIN_20163S-06G1-K
100P_0402_50V8J

1
100_0402_5%

5
100P_0402_50V8J

V+
2

1
100_0402_5%

1
V-
1

1
PC12 PR16 D
PR14

PC28

PR15

51.1K_0402_1%
PC27

PR11 PC29 0.022U_0603_25V7K 4 2 PQ1

2

100P_0402_50V8J OUTPUT G SSM3K7002FU_SC70-3

1K_0402_5% 1 2 3
2

2
-IN
2VREF_51125 PR13 S
1

3
+3VL
75K_0402_1%

1
LMV331M5X-NOPB_SOT23-5

1
2

PR17 PC13
PR9 150K_0402_1% 1000P_0402_50V7K

2
100K_0402_5%

2
AB1B_DATA 35
1

35 THM_TRAVEL# AB1B_CLK 35
4 4

PD19
1

BAV99W T1G_SC70-3

0.1
PD18
BAV99W T1G_SC70-3
PD20
BAV99W T1G_SC70-3 +3VL
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-IN/ BATTERY CONN

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 40 of 50
A B C D
 A B C D

B+
VIN P2 P4 P4

PQ101 PQ102 PQ103

AO4433_SO8 AO4433_SO8 PR102 PL101 AO4407A_SO8
1 8 8 1 0.01_2512_1% HCB2012KF-121T50_0805 1 8
2 7 7 2 1 4 1 2 CHG_B+ 2 7
3 6 6 3 3 6
5 5 2 3 5

4.7U_0805_25V6M

4.7U_0805_25V6M

4.7U_0805_25V6M
4

4
1

1
ACN
ACP
ACDET
+3VL PC105

PC102

PC103

PC104
1 1 2 1 2 PR104 1

PR103 1 2 1U_0603_6.3V6M

0.1U_0603_50V7K

2
1

2
PC101 47K_0402_5% 56K_0402_1% 1 2
0.22U_0603_10V7K

1
1 2 PR105 PR106

PC108
PR101 15K_0402_5% 0_0402_5%
1

200K_0402_5% PC107 +3VL PC106

1 2

1
PR111 0.01U_0402_16V7K @0.1U_0603_25V7K
D CHGEN# P2
150K_0402_5%
2
G CHG_B+
2

1
S PQ104

3
48 ADP_EN# VL SSM3K7002FU_SC70-3 PR110

LPMD

ACN

CHGEN
ACP
LPREF

ACSET

ACDET
29 10_0805_5%
PR109 TP
PR138 1 2
1 2 0_0402_5%

5
6
7
8
100K_0402_5% 1 2 8 28 1 2
BATT P2 14,27,34,35,37,38,43,44,45,46,49 SLP_S3# IADSLP PVCC
PC109 PC110

D
D
D
D
PR139 1U_0805_25V6K 0.1U_0402_10V7K
1 2 9 27 BST_CHG 1 2 1 2
PR135 1M_0402_5% AGND BTST PR121 PQ106

G
8

BQ24740VREF

S
S
S
100K_0402_1% PU101 0_0402_5% AO4466_SO8
1 2 3 1 2 10 BQ24740RHDR_QFN28_5X5 26 DH_CHG 1 2 BATT
P

4
3
2
1
+ PC111 VREF HIDRV PR145 PL102 PR112
O 1
1 2 2 1U_0603_6.3V6M +3VL 0_0402_5% 10U_LF919AS-100M-P3_4.5A_20% 0.01_1206_1%
-
G

PR136 PU10A 11 25 LX_CHG 1 2 1 2

100K_0402_1% LM393DG_SO8 VDAC PH
23.7K_0402_1%

4
1

5
6
7
8
PD102

2
PR113 VADJ 12 24 REGN 2 1
VADJ REGN PR141
PR140

2 2
453K_0402_1%
RLS4148_LL34-2 @4.7_1206_5%

4.7U_0805_25V6M

4.7U_0805_25V6M

4.7U_0805_25V6M

4.7U_0805_25V6M
PR137 13 23 DL_CHG
2

2
EXTPWR LODRV

1
24K_0603_1% 35 BAT_PW M_OUT 1 2 4

1 1
PR114

PC112

PC113

PC114

PC115
1 2
422K_0402_1% 1 14 22 PQ107

2
ISYNSET PGND
1

PR115 AO4468_SO8 PC126

DPMDET
1

IADAPT
PC116 1M_0402_1% PC118 @680P_0603_50V8J 1 2

SRSET

CELLS

3
2
1

2
1
1U_0603_6.3V6M 1U_0603_10V6K PC117

SRN

SRP
2

BAT
PR116 CELLS 35 0.1U_0402_10V7K
2

22.6K_0402_1%

2
2

15

16

17

18

19

20

21
PR117
100K_0402_5%

BATT
IADAPT
PR118

1
P2
1 2
+3VL 48 IADAPT

1
499K_0402_1%
PC119
AC Detector
1

100P_0402_50V8J

2
PR119
200K_0402_1% PR120
High 11.85
SRSET 48
22K_0402_5% Low 10.55
8
2

1
5 2 1 CHGCTRL 35
P

+ PR122
O 7
1

1
6 ADP_PRES 27,35,42,48 210K_0402_1% PC120 PC121

2
-
G

1
PU103B PR124 0.1U_0603_50V7K @0.1U_0603_25V7K
PR123
44.2K_0402_1% LM393DG_SO8 147K_0402_1%
4

3 PC122 3

2
1U_0603_6.3V6M
2

2VREF_51125
+3VL

1 2
PR125 PR142
Charge Detector
2

255K_0402_1% 100_0402_5% VL
470K_0402_5%
1

+3VL
High 17.588 IADAPT
PR126

1 2 1 +IN
P2 VL PC123

1
Low 17.292 0.047U_0402_16V7K 5
2

5 V+
1
Note: X7R type 2
1

V-
1

PC127
NC
P

2
1

PR127 2 4 CHG 1 2 1U_0603_10V6K 4

75K_0402_1%
A Y PR128 AC_AND_CHG 35,42 3
OUTPUT PMC 35
-IN
G

PC124 10K_0402_5%
2

0.1U_0402_10V7K PU102
2

3
8

PR130 74LVC1G14GW _SOT353-5 PU104

1

1K_0402_5% D
3 LMV321M5X-NOPB_SOT23-5
P

+ AC_AND_CHG ACDET CHGCTRL 1

O 1 1 2 2 1 2 2
1

2 PR129 PC125 G
-
G

PU103A BQ24740VREF 47K_0402_5% 1000P_0402_50V7K S PQ108

PR131 1 2
3

LM393DG_SO8 PR132 SSM3K7002FU_SC70-3

4

1
10K_0603_0.1% PR143
300K_0402_5%
1

PR144 33.2K_0402_1%
2

PR134 49.9K_0402_1%
PR133
2

2VREF_51125 220K_0402_5% 470K_0402_5%

4 PD103 4
2

2
1SS355_SOD323-2
2

CHGEN#
1

D
2
G
S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

PQ109 2008/10/24 2009/10/24 Title

Issued Date Deciphered Date
SSM3K7002FU_SC70-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 41 of 50
A B C D
 A B C D

B++ PR37 51125_PWR

0_0402_5%
1 2 2 1 1 2
PR18 Vin PD12

1
1M_0402_5% PD22
2VREF_51125 2 1 1SS355_SOD323-2

1
VL +3VL +3VL PD8
BATT 1SS355_SOD323-2
PR34 RLZ27V
1 0_0402_5%

2
1
BATT_A

1
PR93 PD2

2
1

10K_0402_5% PR20 RB715F_SOT323-3 PR23 PQ2A

PC30 100K_0402_5% PC14 BATT_B 2 100_0805_5% @2N7002KDW-2N_SOT363-6
2

2
8

5
PR19 0.1U_0603_50V4Z @0.1U_0402_10V6K 1 1 2 6 1 1 2 BATT_IN

2
1 1
93.1K_0603_1% 5 1 3

P
+ ALARM 1 INB PR24
7 4

P
2

O INB O @0_0402_5%
6 4 2

2
- O INA

G
PU10B 2 PR25 PD3
INA

G
1

1
LM393DG_SO8 PU3 @1.5M_0402_5% @1SS355_SOD323-2
4

1
PR21 PU2 74LVC1G02_04_SOT353 PC15

1
20K_0402_1% 74LVC1G02_04_SOT353 0.1U_0603_50V4Z
BAT_ALARM 35

2
PD4
2

@RLZ6.2C_LL34
PQ2B

2
1

@2N7002KDW-2N_SOT363-6
1

PR94 D LATCH 4 3
8.06K_0402_1% 2 CFET_B
G +3VL +3VL
S PQ31
2

5
SSM3K7002FU_SC70-3

2
PR22 35 LATCH PQ27 PR40
47K_0402_5% 0_0402_5%

S
2BATT_IN

D
3 1 1

1
BSS84LT1G_SOT23-3

G
2
6

PQ4A
PC16
2N7002KDW-2N_SOT363-6
BATSELB_A 1 2 2
2

1000P_0402_50V7K BATT
1

+3VL
PR26
2 22K_0402_5% 2

1
1

NC
2 A Y 4

1
G
3

6
PQ4B PU4 PR28
2N7002KDW-2N_SOT363-6 74LVC1G14GW_SOT353-5 470K_0402_5% PQ7A

3
PC17
6

2
PQ6A 2N7002KDW-2N_SOT363-6
BATSELB_A# 1 2 5 2N7002KDW-2N_SOT363-6 BATT_IN2

1
PR29
2

1000P_0402_50V7K 2 ADP_PRES 27,35,41,48 2 470K_0402_5%

4

1
PQ8

1
1
PR27 PMBT2222A_SOT23-3
1

3
22K_0402_5% PR30
+3VL +3VL 10K_0402_5% PQ7B
1

3
PU5 2N7002KDW-2N_SOT363-6

1
74LVC1G14GW_SOT353-5 48 CFET_A 1 2

6 2
CFET_A PR31
5

PD5 PD6 5 4.7K_0402_5%

5
PR32 1SS355_SOD323-2 SX34-40_SMA
P

NC

BATSELB_A# 2 4 BATSELB_A 1 10K_0402_5% 1 2

P
35 BATSELB_A#

2
A Y IN1

BATT_A_P
O 4 1 2 2
G

2 PQ10A
IN2

G
2N7002KDW-2N_SOT363-6
3

1
3

4
3 PU6

1
SN74AHC1G08DCKR_SC70 PQ10B 5 5
2N7002KDW-2N_SOT363-6 3 6 6 3 PR33
1

BATT_IN 5 2 7 7 2 470K_0402_5%
1 8 8 1
PC18 BATT BATT_A
2

2
220P_0402_50V7K PQ12 PQ13
AO4407A_SO8 AO4407A_SO8
3
FET_A 35 3

PQ15 PQ14
+3VL AO4407A_SO8 AO4407A_SO8 BATT_B

1
1 8 8 1

PMBT2222A_SOT23-3
2 7 7 2 PR35

470K_0402_5%
3 6 6 3 470K_0402_5%
PR36 5 5
2

2
470K_0402_5%

2
BATT_B_P
4

4
PR39
PR38

1
220K_0402_5% PU8
5

PQ17
SN74AHC1G08DCKR_SC70 2
1

1
1 1 2
P

IN1 PR41
4

3
PQ6B O
1
BATSELB_A# 2 PD7 4.7K_0402_5%
IN2
G

2N7002KDW-2N_SOT363-6 FET_B 35 PR42 SX34-40_SMA

35,41 AC_AND_CHG 4 3 10K_0402_5% 1 2
3

2
PD9
6 2

6
1SS355_SOD323-2
5

PQ20A
ADP_PRES PQ19A 2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6 2
1 2 2
PR44

1
10K_0402_5%
1

+3VL
CFET_B
CFET_B

3
3

PQ20B
PQ19B 2N7002KDW-2N_SOT363-6
4 2N7002KDW-2N_SOT363-6 BATT_IN5 4
PD10 BATT_IN 5
5

RB715F_SOT323-3

4
CFET_A 2
P

1 2 I O 4
CFET_B 3 1 BATCON 35
NC
G
1

PU9
3

PR45 SN74LVC1G17DBVR_SOT23-5
100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
Battery selector
2

wWw.Laptopfix.vn
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 42 of 50
A B C D
 A B C D E

2VREF_51125

1
PC302
0.22U_0603_10V7K

2
1 1

PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
+3VALWP 1 2 1 2 +5VALWP

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
1 PR305 PR306
@0.1U_0402_25V6

4.7U_0805_25V6-K

105K_0402_1% 113K_0402_1%

@2200P_0402_50V7K
@0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

+ PC316 1 2 1 2

1
@100U_25V_M

PC318

PC304

PC305

PC306
PC301
PC303
2

PC3172

2 @2200P_0402_50V7K

2
5

5
PC307
1U_0805_25V6K PQ302

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
PQ301 25 SI7326DN-T1-E3_PAK1212-8

2
SI7326DN-T1-E3_PAK1212-8 P PAD

4UG1_3V 7 VO2 VO1 24 4

2 8 23 PR308 PC309 2
VREG3 PGOOD 0_0402_5% 0.1U_0402_10V7K
PR307
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310
1
2
3

3
2
1
0_0402_5% VBST2 VBST1 0_0402_5%
PC308 0_0402_5%
PL302 1 2 0.1U_0402_10V7K UG_3V 10 DRVH2 DRVH1 21 UG_5V 1 2 PL303
4.7UH_SIQB74B-4R7PF_4A_20% 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
8
7
6
5

5
6
7
8
LG_3V 12 19 LG_5V
DRVL2 DRVL1

1
SKIPSEL
1

PR312

VREG5

VCLK
1 PR311 PR313 +3VL @4.7_1206_5% 1

GND
EN0

VIN
@4.7_1206_5% @1M_0402_1%
+ 4 1 2 4 +
B++

2
PR318 PU301
2

13

14

15

16

17

18

1
PC310 PQ304 @0_0402_5% TPS51125RGER_QFN24_4X4 PC311

1
220U_6.3VM_R152 AO4468_SO8 EN0 1 2 +5VLP
2 220U_6.3VM_R15
1

PR314 PQ303
1
2
3

3
2
1
PC312 @100K_0402_5% IRF8707_SO8 PC313

2
@680P_0603_50V8J 2 1 @680P_0603_50V8J
14,27,34,35,37,38,41,44,45,46,49 SLP_S3#
2

2
RPGOOD 14
PD302 51125_PW R
1SS355_SOD323-2

1
1 2 B++

1
PR319
PR315 2VREF_51125 @0_0402_5%
6 ENTRIP1

3 ENTRIP2

620K_0402_5% PC315

2
PC314 10U_0805_10V6K
2

0.1U_0603_25V7K +3VEXTLP
3 3

+5VLP
PQ305A PQ305B

1
2N7002KDW -2N_SOT363-6 2N7002KDW -2N_SOT363-6 PU303

1
2 5 1 PC320
PJP301 VIN PR322

1
(4.5A,180mils ,Via NO.= 9) PC319 64.9K_0402_1% 10U_0805_6.3V6M

220K_0402_5%
+5VALW P 1 2 +5VALW 5
1

2
1U_0603_10V6K VOUT
2

2
GND

PR325
PAD-OPEN 4x4m

2
FB 4
PR316 PJP303
(3A,120mils ,Via NO.= 6) 3

2
EN

1
100K_0402_5% 1 2 +3VALW
+3VALW P DEBUG_KBCRST
1 2
VL

1
PR317 P2 APL5317 PR323
PAD-OPEN 4x4m
1

D 330K_0402_5% 20K_0402_1%
2 2 1 +5VLP PR326
KBC_PWR_ON 35

2
1
G PJP304 470K_0402_5%

1
S 2 1 PU302
+5VLP VL
3

2
PQ307 2 1 PR320 1 PR324
DEBUG_KBCRST 32 +IN
SSM3K7002FU_SC70-3 PD305 PAD-OPEN 2x2m 301K_0402_1% 16.9K_0402_1%
1SS355_SOD323-2 5

2
V+
2

2
V-
2 1
VCC1_PWRGD 35,48

1
PD301 no install PC321
OUT 4 2 1
1SS355_SOD323-2 PJP302 3 PD304

13.7K_0402_1%
1U_0603_16V6K -IN 1SS355_SOD323-2

PR321
2 1
+3VLP +3VL 2
PAD-OPEN 2x2m LMV321AS5X_SOT23-5

2
EN0 40
4 4
PJP305
PR148 2 1
PR146 @0_0402_5% +3VEXTLP +3VL
8

@0_0402_5% 1 2 ENTRIP1 PAD-OPEN 2x2m

1 2 5
P

+ PR149
7
2VREF_393
6 -
O @0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
G

1 2 ENTRIP2 Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

1 2 PU15B
3.3VALWP/5VALWP
4

PR147 LM393DG_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@10K_0402_5% Size Document Number Rev

wWw.Laptopfix.vn
www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 43 of 50
A B C D E
 A B C D

1 1

B+ PL401
HCB2012KF-121T50_0805
1 2 VCCP_B+

@2200P_0402_50V7K
@0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
+3VS +VCCP
1

1
PC416

PC401 1 2
PR427 PR401 PR417

PC402

PC403

PC404
2

2
10K_0402_5% @10K_0402_5% 1 2 1 2 0_0603_5%
PR402
0_0603_5% PC405

BST_VCCP
2

DH_VCCP
LX_VCCP
0.22U_0603_16V7K
+5VALW
37 VCCP_POK

DH_VCCP1

5
6
7
8
PR403
0_0402_5% PR404 PQ401

17

16

15

14

13
PU401 2.2_0603_5% AO4474_SO8
1 2

UG
GND

PGOOD

PHASE

BOOT
+6269_VCC

2
4
1 VIN PVCC 12 1 2 PC406
+6269_VCC 2.2U_0603_6.3V6K

3
2
1
2 11 DL_VCCP PL402
VCC LG 0.47UH_FDV0630-R47M-P3_18A_20%
1

PC407 PR405 1 2
2

2.2U_0603_6.3V6K
+1.05V_VCCP 2

0_0402_5%
1 2 3 10
2

FCCM PGND
1 1 1

330U_D2E_2.5VM_R6

330U_D2E_2.5VM_R6

330U_D2E_2.5VM_R6
5

1
PR408 + + +

PC408

PC409

PC410
1 2 4 9 SE_VCCP 1 2 @4.7_1206_5%
14,27,34,35,37,38,41,43,45,46,49 SLP_S3# EN ISEN PR407
PR406
COMP
2 2 2

FSET
6.04K_0402_1%
@0_0402_5%

2
VO
FB
4
1

2
1 2 ISL6269ACRZ-T_QFN16
37 VCCP_EN
5

8
PR428 PC412
PC411 PQ402
0_0402_5%
2

3
2
1

1
@0.1U_0402_25V4K +1.05V_VCCP TPCA8028_PSO8 @680P_0603_50V7K
FB_VCCP
90.9K_0402_1%

0.01U_0402_16V7K
1

1
PR409

49.9K_0402_1%
PR410

PC413
2
1

2
6800P_0603_50V7K

PC414
22P_0402_50V8J PJP401
2

+1.05V_VCCP 1 2 +VCCP (18A,720mils ,Via NO.= 36)

PAD-OPEN 4x4m
PC415
2

3
PJP402 3

1 2 1 2 1 2+1.05V_VCCP 1 2
7 H_VTTVID1 PR416 PR411 PR413
35.7K_0402_1% 1.58K_0402_1% 10_0402_5% PAD-OPEN 4x4m
1

H_VTTVID1= Low, 1.1V PR412 1 2

1.96K_0402_1% PR414 VTT_SENSE 7
H_VTTVID1= High, 1.05V 0_0402_5%
2

1 2
PR415 VSS_SENSE_VTT 7
10_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V_VCCP

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 44 of 50
A B C D
 A B C D

+5VALW

1
PC613 +1.5V
+3VS 1U_0603_10V6K

2
1 1

+1.5V

1
+1.5V

1
PU601 PR609
1 6 10K_0402_1% PC614
VIN VCNTL +5VALW

6
10U_0805_6.3V6M

10U_0805_6.3V6M

@10U_0805_10V4Z

2
2 5 5

VCNTL
2
GND NC VIN
25,37 1.1VS_POK 7 POK

1
3 VREF NC 7 VIN 9

1
PC601

PC602
+5VALW PR601
4 8 PC603 3

2
1K_0402_1% VOUT NC 1U_0603_10V6K VOUT
+1.1VSP

2
9 SLP_S3# 1 2 8 4

2
TP EN VOUT
1

1
PR604 PR610

GND

1
0_0402_5% PR602 G2992F1U_SO8 0_0402_5% 2
FB PR611 PC615
1 2
44,46,49 SLP_S3#

1
10K_0402_5% PC616 49.9K_0402_1% PC617 22U_0805_6.3VAM

2
PQ601A @0.1U_0402_16V7K 47P_0402_50V8J

0.1U_0402_10V7K
+0.75VSP
2

2
1
2N7002KDW -2N_SOT363-6

2
2 PR603 PU603
3

1K_0402_1% APL5913-KAC-TRL_SO8

1
PQ601B

1
2N7002KDW -2N_SOT363-6 PC605

2
10U_0805_6.3V6M PJP603

PC604
5

2
+1.1VSP 1 2 +1.1VS
1

1
4

PAD-OPEN 3x3m
PC606 PR612
2

@0.1U_0402_16V7K 100K_0402_1% (3A,120mils ,Via NO.= 6)

2
PJP601 2

2
+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 3x3m

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VSP/PCIE

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 45 of 50
A B C D
 A B C D

PR516 PL501
2 1 1.05VS_B+
14,27,34,35,37,38,41,43,44,45,49 SLP_S3# HCB1608KF-121T30_0603
0_0402_5% PC519 1 2 B+

1
@1000P_0402_50V7K

@1000P_0402_50V7K

@0.1U_0402_25V6

4.7U_0805_25V6M

4.7U_0805_25V6M
2

1
PC504

PC505

PC506

PC507
1 1

PR511 PC511

2
5
6
7
8
0_0402_5% 0.1U_0402_10V7K
BST_1.05V 1 2 1 2

15

14
1
PU501 4
PR716 PR509

EN_PSV

TP

VBST
255K_0402_1% 0_0402_5% PQ502
1 2 2 13 UG_1.05V 1 2 UG1_1.05V PL503 +1.05VSP
TON DRVH AO4466_SO8 2.2UH_PCMC063T-2R2MN_8A_20%

3
2
1
+1.05VSP 1 2 3 12 LX_1.05V 1 2
PR519 0_0402_5% VOUT LL
+5VALW 1 PR517 15.4K_0402_1%
+5VALW 2 4 V5FILT TRIP 11 1 2

5
6
7
8

1
PR518 PR503
+1.05VSP 1 2 5 10 +5VALW
316_0402_1% VFB V5DRV PR513
4.12K_0402_1% 1 1
1

1
6 9 LG_1.05V @4.7_1206_5%
PGOOD DRVL

PGND
PC520 PC521 + +

GND

220U_B2_2.5VM_R25M
2
1U_0603_10V6K 1 2 4.7U_0805_10V6K 4
2

2
PC526 PC518

1
@10P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 PQ504 2 2 @330U_B2_2.5VM_R15M

8
1
IRF8707_SO8 PC517

PC515
PR504 @680P_0603_50V8J

3
2
1

2
10.2K_0402_1%

2
2 2

1.05VS_POK 37

PJP501

+1.05VSP 1 2 +1.05VS (8A,320mils ,Via NO.= 16)

PAD-OPEN 4x4m

PR521 PL504
2 1 1.5V_B+
14,38 SLP_S4# HCB1608KF-121T30_0603
0_0402_5% PC524 1 2 B+
1

@1000P_0402_50V7K

@1000P_0402_50V7K

@0.1U_0402_25V6

4.7U_0805_25V6M

4.7U_0805_25V6M
2

1
5
6
7
8

PC501

PC502

PC508

PC509
PR510 PC510

2
0_0402_5% 0.1U_0402_10V7K
BST_1.5V 1 2 1 2

4
15

14
1

3 PU502 PQ501 3

PR715 PR508
EN_PSV

TP

VBST

255K_0402_1% 0_0402_5% AO4466_SO8 +1.5VP

3
2
1
1 2 2 13 UG_1.5V 1 2 UG1_1.5V PL502
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
+1.5VP 1 2 3 12 LX_1.5V 1 2
PR520 0_0402_5% VOUT LL
+5VALW 1 PR515 5.9K_0402_1%
+5VALW 2 4 V5FILT TRIP 11 1 2

5
6
7
8

1
PR522 PR501
+1.5VP 1 2 5 10 +5VALW PQ503
316_0402_1% VFB V5DRV PR512
10.2K_0603_0.1% 1
1

6 9 LG_1.5V @4.7_1206_5%
PGOOD DRVL

1
PGND

PC522 PC523 +
GND

2
1U_0603_10V6K 1 2 4.7U_0805_10V6K 4 PC513
2

PC525 4.7U_0805_6.3V6K PC512

2
1
@10P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 2 330U_B2_2.5VM_R15M
7

8
1

PC516
PR502 AO4714_SO8 @680P_0603_50V8J

3
2
1

2
10K_0603_0.1%
2

1.5V_POK 37

PJP502

+1.5VP 1 2 +1.5V (8A,320mils ,Via NO.= 16)

4 4

PAD-OPEN 4x4m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/1.05VSP

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 46 of 50
A B C D
 8 7 6 5 4 3 2 1

+VCCP

H_VID0 2 1 PR266 10K_0402_5% H_VID0 2 1 PR280 @10K_0402_5%

H_VID1 2 1 PR267 10K_0402_5% H_VID1 2 1 PR281 @10K_0402_5%

CPU_B+ PL201
H_VID2 2 1 PR268 10K_0402_5% H_VID2 2 1 PR282 @10K_0402_5% SMB3025500YA_2P
2 1 B+
H H_VID3 2 1 PR269 @10K_0402_5% H_VID3 2 1 PR275 10K_0402_5% H

H_VID4 2 1 PR270 @10K_0402_5% H_VID4 2 1 PR276 10K_0402_5%

@100U_25V_M

@100U_25V_M
2200P_0402_50V7K
@0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
H_VID0 2 PR201 0_0402_5% H_VID5 1 PR271 10K_0402_5% H_VID5 1 PR277 @10K_0402_5%

PC205

PC206
7 H_VID0 1 2 2

1
+ +

PC201

PC203

PC204
1

1
H_VID1 2 PR202 0_0402_5% H_VID6 1 PR272 @10K_0402_5% H_VID6 1 PR278 10K_0402_5%

PC202

PC207

PC208
7 H_VID1 1 2 2

2
H_VID2 1 2 PR203 0_0402_5% PROC_DPRSLPVR 2 1 PR273 10K_0402_5% PROC_DPRSLPVR 2 1 PR279 @10K_0402_5% 2 2
7 H_VID2

2
5
6
7
8
7 H_VID3 H_VID3 1 2 PR204 0_0402_5% PQ201
AO4474_SO8
7 H_VID4 H_VID4 1 2 PR205 0_0402_5%

7 H_VID5 H_VID5 1 2 PR206 0_0402_5% PR208 PC209 UGATE1_CPU2 4

0_0603_5% 0.22U_0603_10V7K
7 H_VID6 H_VID6 1 2 PR207 0_0402_5% BOOST_CPU2 2 1 1 2 PR249
0_0603_5%
12,14,35 PM_PWROK 1 2 PR209 0_0402_5% UGATE_CPU2 2 1 PL202

3
2
1
G 0.36UH_PCMC104T-R36MN1R17_30A_20% G

7 PROC_DPRSLPVR PROC_DPRSLPVR 1 2 PR210 0_0402_5% PHASE_CPU2 2 1 +CPU_CORE

5
11 CLK_EN#

10K_0402_5%
3.65K_0402_1%
1

1
+3VALW PQ202

@4.7_1206_5%

1
PR215 TPCA8028_PSO8

PR211
1.91K_0402_1% PR216

PR213

PR214
35,37 PWR_GD PWR_GD 1 2 CLK_EN# 1_0402_5%
LGATE_CPU2 4 PR218

2
1

@0_0402_5%

2
1 2+CPU_CORE VSUM-
PR217

@1000P_0603_50V7K
1
PR219 1.91K_0402_1% PR220

3
2
1
0_0402_5% @0_0402_5%

PC210
2

1 2 1 2+CPU_CORE

2
14 VGATE ISEN2
VSUM+
+VCCP 1 2 PR221 @10K_0402_5%
F F
PSI#1 2 PR222 0_0402_5% CPU_B+
7 PSI#
2 1 PR283 10K_0402_5%

1 2
PR223 147K_0402_1%

@0.1U_0402_25V6

2200P_0402_50V7K
5
6
7
8
PC211 +5VALW

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1U_0603_10V6K PQ203
40
39
38
37
36
35
34
33
32
31

+VCCP 1 2

1
PR224 PU201 AO4474_SO8

PC212
1 2
68_0402_5%

PC213

PC214

PC215

PC216

PC217
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

1U_0603_10V6K
1 2 PR226

2
1
4 H_PROCHOT# PR225 0_0603_5% PC219 UGATE1_CPU3 4

PC218
30
0_0402_5% BOOT2 PU202 0.22U_0603_10V7K
29
UGATE2 BOOST_CPU3 PR264
1 28 5 1 1 2 1 2

2
PC220 @56P_0402_50V8 PGOOD PHASE2 VCC BOOT 0_0603_5%
2 27
PSI# VSSP2 UGATE_CPU3
1 2 3 26 6 8 1 2

3
2
1
RBIAS LGATE2 FCCM UGATE
4 25 +5VALW
PR227 @4.02K_0402_1% VR_TT# VCCP PHASE_CPU3 PL203
E 5 24 2 7 E
NTC PWM3 PWM PHASE 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2 1 2 6 23
PH202 VW LGATE1 LGATE_CPU3
7 22 3 4 2 1 +CPU_CORE
@470K_0402_5%_TSM0B474J4702RE COMP VSSP1 GND LGATE
8 21
FB PHASE1 PR228 ISL6208CRZ-T_QFN8
1 2 9

1
ISEN3
UGATE1

10 @0_0402_5%
BOOT1

10K_0402_5%
@4.7_1206_5%
ISUM+

ISEN2

1
ISEN1

ISUM-
VSEN

IMON

PC221 PQ204

PR229
1 2
@249K_0402_1%

8.06K_0402_1%

3.65K_0402_1%
VDD
1000P_0402_50V7K

RTN

VIN

@22P_0402_50V8J TPCA8028_PSO8 PR233

PR231

PR232
41
AGND
1

1_0402_5%
PC222

ISL62883HRZ-T_QFN40_5X5
PR234

PR235

11
12
13
14
15
16
17
18
19
20

2
4 PR237
2

2
390P_0402_50V7K PC223 @0_0402_5%
2

1 2 1 2 1U_0603_10V6K 1 2+CPU_CORE VSUM-

2

PR236

@1000P_0603_50V7K
562_0402_1% PC224 PR240

3
2
1

1
PR239 0_0402_5% @0_0402_5%
2+CPU_CORE

PC226
1 2 1 2 1 2 1
PC225 ISEN3

2
33P_0402_50V8K PR238 PR242 0_0402_5% IMVP_IMON 7 VSUM+
D 2.37K_0402_1% 1 2 CPU_B+ D
1 2 1 2
0.22U_0603_25V7K

PC227 PR241
150P_0402_50V8J 324K_0402_1% PR244 1_0402_5%
1 2 CPU_B+
+5VALW
ISEN3
1

1
PC228

PC229

PC230
1U_0603_10V6K

0.22U_0603_25V7K

ISEN2
PR246
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

ISEN1 8.25K_0402_1%

@0.1U_0402_25V6

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2

PQ205

1
BOOST_CPU1

VSSSENSE AO4474_SO8

PC231
PR274

PC232

PC233

PC234

PC238

PC239
1

0_0603_5%
PC235

PC236

PC237

2
UGATE_CPU1 2 1 UGATE1_CPU1 4
2

PR248 PC240
C 0_0603_5% 0.22U_0603_10V7K C

3
2
1
VSUM+ 2 1 1 2

PL204
82.5_0402_1%

0.36UH_PCMC104T-R36MN1R17_30A_20%
PHASE_CPU1 2 1 +CPU_CORE
1
2.61K_0402_1%
0.01U_0603_16V7K

1
PR252

10K_0402_5%
@4.7_1206_5%

3.65K_0402_1%
0.33U_0603_10V7K

1
PR250

PR253

PR255
0.022U_0402_25V7K
1

PQ206 PR257
PC241

PR256
7 VCCSENSE 1 2
0.01U_0402_25V7K

TPCA8028_PSO8 1_0402_5%
2

PR251 0_0402_5%
2

2
1

PR258

2
1

PC244 LGATE_CPU1 @0_0402_5%

PC242

PC243

4
330P_0402_50V7K 2+CPU_CORE VSUM-
PC245

1
2

@1000P_0603_50V7K
2

1
PR259

PC246
3
2
1
@0_0402_5%
330P_0402_50V7K

2
1

B B
PR260 1 2+CPU_CORE
11K_0402_1%
1

PC247 464_0402_1% PH201 ISEN1

PC248

PR262

1000P_0402_50V7K 1 2 VSUM+
PR263 0_0402_5% 0_0402_5% 10KB_0603_5%_ERTJ1VR103J
2

1 2 PR261
7 VSSSENSE
2

Iccmax= 48A
2

PC249 100_0402_1%
I_TDC=TDB
1 21 2 VSUM- OCP=TDBA, Intel spec=TDBA
1200P_0402_50V7K PR265
0.1U_0402_16V7K
1

PC250
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
CPU_CORE

wWw.Laptopfix.vn
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 47 of 50
8 7 6 5 4 3 2 1
 5 4 3 2 1

+3VS
BQ24740VREF

1
+3VS
PR50 PR47

1
165K_0402_1% 100K_0402_5%
PR46 1 2

1
PC21 133K_0402_1%

2
0.22U_0603_10V7K PR48
1 2 10K_0402_5%

8
+5VS
3

2
+
1 2 1 1

0.01U_0402_16V7K
41 IADAPT PR51 +IN O
D 2 - D

G
1
10K_0402_1% 5 PU11A
V+ LM393DG_SO8
42 CFET_A 1 2 2

4
V-

PC31
PR95 PR53
150K_0402_5% 4 80.6K_0402_1%
OUTPUT +3VS
3 1 2

2
-IN

2
G
PQ33 PR54

1
BSS138_SOT23-3 604K_0603_1%

0.027U_0402_16V7K
1 3 3 1 PU12

2
PR52

D
D LMV321M5X-NOPB_SOT23-5

S
1

1
D

PC22
PQ32 2K_0402_5%
2 BSS138_SOT23-3 PR49 PR55
1,42 ADP_PRES

2
G 105K_0402_1% +3VS 10K_0402_5%
OCP_ADJ 40

2
S PQ34
3

1
2
SSM3K7002FU_SC70-3

1
1 2 OCP# 15
PD11 PR56 PR57
1SS355_SOD323-2 10K_0402_5% 0_0402_5%

4
PD21

1
1SS355_SOD323-2 D
6

G
ADP_SIGNAL

2
-
O 7 1 2 2

D
1 2 3 1 2 1 1 2 5 PR63 G
+

P
PR58 PQ24 PR96 PU11B 0_0402_5%

3.9K_0402_5%
S

3
1
100_0402_5% NDS0610_NL_SOT23-3 VIN 3.9K_0402_5% LM393DG_SO8 PQ25
1

8
PR59
SSM3K7002FU_SC70-3

3900P_0402_50V7K
2
1 2

1
PR97
2

PC23
PR87 330K_0402_5%

2
1_0805_1%
C C
SRSET 41
OCP 35

1
C
1 1 2 2 PQ26

2
@0_0805_5% PD14 PR60 B MMBT3904W _SOT323-3
RLS4148_LL34-2 +3VL 100K_0402_5% E
PR98

3
VIN VIN

1
1U_0805_25V6K +3VS
1 2OCP_A_IN OCP_A_IN 35
2

1
1

1
PR100 +3VS
1 2
PR70 PR61 PR72 PC26 PR62 100_0402_5%
8

68K_0402_5% 137K_0402_1% 22.6K_0402_1% 10K_0402_5% PD24

1
RLZ4.7B_LL34 PR64 +5VS
3
P

ADP_ID 35

2
PR99 + PR65 1M_0402_5% PR66
1
2

2
O 71.5K_0402_1% 10K_0402_5%
1 2 2 - 1 2
G

@0_0402_5%
1

PU14A PR68
4

2
8
PR80 PR79 LM393DG_SO8 10K_0402_5%
33K_0402_5% 1 2 5

P
10K_0402_1% + ADP_PS0 35
ADP_EN# 41 O 7
1

1
6
2

G
PR43 PR75 PU13B
@21K_0402_1% PR73 21K_0603_1% LM393DG_SO8

4
1M_0402_5% +3VS
4.7K_0402_5%

1 2
2

2
1

PR77 +5VS
PR81

1
+3VL 1M_0402_5%
1

+3VL PQ28A PR76 1 2

3

B E VIN 3.48K_0402_1% PR78 B

1 2
4.12K_0402_1%

2N7002KDW -2N_SOT363-6
2

10K_0402_5%
B
PR83
PR1001

2 2 VCC1_PW RGD 35,43

8
1M_0402_5% 21K_0603_1%

2
1

C
PQ35 PR84 1 2 3

P
2

1
+
1

MMBT3906_SOT23-3 PR69 1
29.4K_0402_1% PR74 O
PR67 1 2 2 1 2 - ADP_PS1 35

G
10K_0402_1% 47K_0402_5% PR85 PR86 PU13A
8

2 1 ADP_A_ID LM393DG_SO8 47K_0402_5% 470K_0402_5% LM393DG_SO8

2

4
5
P
2

1
PD23 7 1 2
O
1

1SS355_SOD323-2 6 PR107 PC25

-
G

PR1002 PR82 0_0402_5% PC24 0.1U_0603_16V7K

2
3

10K_0402_1% PU14B @1091 1U_0603_10V6K

24.9K_0402_1%
4
2

PQ28B 5 ADP_EN 35
2N7002KDW -2N_SOT363-6
2 4

2VREF_51125
1 2
PR1005
1M_0402_5% +3VL PR108
0_0402_5%
1

@1098
1

VL
PR1003
1

130K_0402_1% PR1006
22K_0402_5%
8
2

3
P

+
A O 1 ADP_DET# 35 A
1

2 -
G

PR1004 PU15A
10K_0402_1%
4

LM393DG_SO8
2

1 2ADP_A_ID ADP_A_ID 35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title
PR1007
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
Size Document Number Rev

wWw.Laptopfix.vn
www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4891
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 48 of 50
5 4 3 2 1
 A B C D

+3VS

1
PR701
10K_0402_5% PR702
10K_0402_1%
1
High: VGA_CORE 0.9V 1

2
2 1
Low: VGA_CORE 1.0V

1
PC701

5
0.022U_0402_16V7K PR703 PQ701B
2 100K_0402_1% 2N7002KDW -2N_SOT363-6
23 VGA_PWRSEL

2
PQ701A 1 2 3 4

1
2N7002KDW -2N_SOT363-6

1
PR704
10K_0402_5% PR705 PR706 PR707 PR708
14.7K_0402_1% 75K_0402_1% 10K_0402_1% 13.7K_0402_1%
+VGA_COREP 1 2 1 2 1 2 1 2 +1.8VSP

2
1 2
PC702

2
@10P_0402_50V8J PR709 VGA_1.8V_B+ B+
VGA_1.8V_B+ 0_0402_5% PL701
HCB2012KF-121T50_0805
2 1

1
+VGA_COREP +1.8VSP
2200P_0402_50V7K

@0.1U_0402_25V4K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

37 NVVDD_POK
PC703

PC704

PC705

PC706

2200P_0402_50V7K

@0.1U_0402_25V4K
1.8VS_POK 37

1
PC707

4.7U_0805_25V6-K
2 2
2

1
@0.1U_0402_16V7K PU701 PC708

1
PQ703 @0.1U_0402_16V7K

PC710

PC711
VO2

VFB2

TONSEL

VFB1

VO1
GND
SI7326DN-T1-E3_PAK1212-8 PQ706

PC709
25

2
P PAD

2
SI7326DN-T1-E3_PAK1212-8
4 7 PGOOD2 PGOOD1 24 4
PC713
PC712 PR710 8 23 PR711
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+VGA_COREP 2 1 2 1 BST_VGA 9 22 BST_1.8V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
+1.8VSP
PL702 UG1_VGA 2 1 UG_VGA 10 21 UG_1.8V 2 1 UG1_1.8V PL703
1UH_PCMC063T-1R0MN_11A_20% 0_0402_5% PR712 DR VH2 DR VH1 PR713 4.7UH 30% MSCDRI-7030AB-4R7N 3.3A
2 1 LX_VGA 11 20 LX_1.8V 0_0402_5% 1 2
LL2 LL1
LG_VGA 12 19 LG_1.8V
DR VL2 DR VL1
8
7
6
5

5
PQ704

PGND2

PGND1
1 1

V5FILT
330U_D2E_2.5VM_R9

1
TRIP2

TRIP1
IRF8707_SO8 PR714 PQ705 1

V5IN
+ + @4.7_1206_5% PR721 SI7230DN-T1-E3_PAK1212-8
PC714

220U_B2_2.5VM
PC715 @4.7_1206_5% +

PC717
@330U_D2E_2.5VM_R9 4 TPS51124RGER_QFN24_4x4
1 2

13

14

15

16

17

18
2 2
4

1 2
2

2
PC718
1
2
3

@680P_0603_50V7K PR717 PR722 PC719

3
2
1
3 14.7K_0402_1% 4.99K_0402_1% @680P_0603_50V7K 3

1 2
1

PR718
0_0402_5% PR720
2 1 0_0402_5%
14,27,34,35,37,38,41,43,44,45,46 SLP_S3# 1 2 SLP_S3#
1 2 +5VALW
PR719
3.3_0402_5%
1

1
PC721 PC722 PC723
1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K PJP703
PC720 1 2 +1.8VS
+1.8VSP
2

@0.1U_0402_16V7K 2
PAD-OPEN 3x3m
(3A,80mils ,Via NO.= 6)
PJP701

+VGA_COREP 1 2 +NVVDD (10A,400mils ,Via NO.= 20)

PAD-OPEN 4x4m
PJP702
1 2
4 4

PAD-OPEN 4x4m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE/ 1.8VSP

wWw.Laptopfix.vn
www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 49 of 50
A B C D
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date Phase

D D

3
4

C C

B B

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24
Changed-List History

wWw.Laptopfix.vn
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-4891 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 50 of 50
5 4 3 2 1