A Mini-Project Report

On

“DESIGN OF ASYNCHRONOUS COUNTER USING SG GATE”

Submitted for partial fulfillment of the requirements for the award of the degree

of

MASTER OF TECHNOLOGY
IN

VLSI SYSTEM DESIGN

BY

Ms.B.SOUMYA SREE (20641D5722)

Under the Guidance of

Mr.M. DEVADAS

Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VAAGDEVI COLLEGE OF ENGINEERING

(Autonomous, Affiliated to JNTUH, NAAC ‘A’ Grade and NBA Accredited)

BOLLIKUNTA, WARANGAL - 506 005

2020-2021
 VAAGDEVI COLLEGE OF ENGINEERING
(Autonomous, Affiliated to JNTUH, NAAC ‘A’ Grade and NBA Accredited)

BOLLIKUNTA, WARANGAL - 506 005

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the mini-project work entitled “DESIGN OF
ASYNCHRONOUS COUNTER USING SG GATE” is a bonafide work carried out
by Ms.B.SOUMYA SREE (20641D5722) in partial fulfillment of the requirements for
the award of degree of Master of Technology in VLSI System Design from Vaagdevi
College of Engineering, (Autonomous) during the academic year 2020-2021.

Project Guide Head of the Department

Mr.M .DEVADAS Dr. M. SHASHIDHAR

Assistant Professor Associate Professor

 DECLARATION

I declare that the work reported in the mini project entitled “DESIGN OF
ASYNCHRONOUS COUNTER USING SG GATE” is a record of work done by me
in the partial fulfillment for the award of the degree of Master of Technology in VLSI
System Design VAAGDEVI COLLEGE OF ENGINEERING (Autonomous),
Affiliated to JNTUH, Accredited By NAAC, under the guidance of Mr.M .DEVADAS,
Assistant Professor, ECE Department, I hereby declare that this mini-project work
bears no resemblance to any other project submitted at Vaagdevi College of Engineering
or any other university/college for the award of the degree.

Ms.B.SOUMYA SREE (20641D5722)

 ACKNOWLEDGEMENT

The development of the project though it was an arduous task, it has been made
by the help of many people. I am pleased to express my thanks to the people whose
suggestions, comments, criticisms greatly encouraged me in betterment of the project.

I would like to express my sincere gratitude and indebtedness to my project

Guide Mr.M. DEVADAS, Associate Professor, for him valuable suggestions and
interest throughout the course of this project.

I would like to express my sincere thanks and profound gratitude to

Dr. K. PRAKASH, Principal of Vaagdevi College of Engineering, for his support,
guidance and encouragement in the course of our project.

I am also thankful to the Head of the Department Dr. M. SHASHIDHAR,

Associate Professor for providing excellent infrastructure and a nice atmosphere for
completing this project successfully.

I am highly thankful to the Project Coordinators for their valuable

suggestions, encouragement and motivations for completing this project successfully.

I am thankful to all other faculty members for their encouragement

I convey my heartfelt thanks to the lab staff for allowing me to use the required
equipment whenever needed.

Finally, I would like to take this opportunity to thank my family for their
support through the work. I sincerely acknowledge and thank all those who gave
directly or indirectly their support in completion of this work.

Ms.B.SOUMYA SREE (20641D5722)

 TABLE OF CONTENTS
PAGE NOS.
ABSTRACT i
LIST OF FIGURES ii
LIST OF TABLES iv
LIST OF ACRONYMS v
CHAPTER-1
INTRODUCTION TO REVERSIBLE GATES 1
1.1 Problem Specification 1
1.2 Reversible Circuits 2
1.3Nomenclature 4
1. 3. 1 Gate Count 4
1. 3. 2 Garbage Outputs 4
1. 3. 3 Ancilla Inputs (Constant Inputs) 4
1. 3. 4 Quantum Cost 4
1. 3. 5 Balanced Circuits 5
1. 3. 6 Conservative Circuits 5
1. 3. 7 Transistor Cost 5
1.4 Basic Reversible Logic Gates 5
1.4. 1 Feynman Gate 5
1. 4. 2 Toffoli Gate 6
1.4. 3 Fredkin Gate 8
1. 4. 4 Peres Gate 9
1. 5 The Elimination of Garbage Bits in Reversible Circuits 10
1.6 Challenges and Motivation 11
1.7 Motivation 11
1.8 Design Methodology 12
1.9 Applications 14
1.10 Outline of the Report 15
CHAPTER 2
LITERATURE REVIEW 16
2.1 Theoretical Back Ground 16
2.2 Existed Method 16
CHAPTER 3
PROPOSED A SYNCHRONOUS COUNTER 28
CHAPTER 4
RESULTS 33
CHAPTER 5
CONCLUSION AND FUTURE SCOPE 37
5.1 Conclusion 37
5.2 Future Scope 37
REFERENCES 38
 ABSTRACT

In today’s world power dissipation is one of the major concern as the complexity of
the chip is increasing and more devices are being integrated on a single chip. Thus this high
density of chip and increased power dissipation demands for better power optimization
methods. Reversible logic is one of the method to reduce power dissipation. Reversible
computing has a wide number of applications in areas of advance computing such as low
power CMOS VLSI design, nanotechnology, cryptography, optical computing, DNA
computing and quantum computing. This paper presents reversible T- flip flop using “SGG”
gate and Feynman gate and then a novel design of asynchronous reversible counter is also
proposed.

i
 LIST OF FIGURES
Fig.No. Figure Name Page No.

Fig:1.1 Block diagram of Reversible circuit 2

Fig:1.2 Conventional XOR and Reversible XORgate 3
Fig:1.3 Feynman gate 6
Fig:1. 4 Application of Feynman gate 6
Fig: 1. 5 Toffoli gate 7
Fig:1.6 Representation of Toffoli gate 7
Fig:1. 7 Block diagram of Fredkin gate 8
Fig:1. 8 Representation of Fredkin gate 9
Fig:1. 9 Peres gate 10
Fig:1.10 The reversible circuit and its reversible mirror to 10
eliminate garbage bits
Fig:1,11 Design flow of reversible logic circuits 13
Fig:2.1 Asynchronous Counter[Up mode] 19
Fig:2.2 Asynchronous Counter[Down mode] 21
Fig:1.3 A3-bitasynchronousup-downcounter 22
Fig.2.4 A3-bit synchronous counter 22
Fig.2.5 A4-Bit Synchronous up-Down Counter 23
Fig:2.6 Count Down Waveforms 24
Fig.2.7 Mod5 Counter 25
Fig:2.8 IC54/7490A [ Decade Counter] 26
Fig:3.1 Block Diagram 28
Fig:3.2 4-bit asynchronous Up- Counter 29
Fig:3.3 Proposed 4-bit Reversible Asynchronous Up Counter 30
Fig:3.4 Simulated waveform of t flip flop 31
Fig:3.5 Asynchronous Counter counting Up 31
Fig:3.6 Asynchronous Counter counting Down 32
Fig:3.7 Asynchronous Counter counting both Up and Down 32
Fig:4.1 SG gate Schematic 33
Fig:4.2 SG gate block diagram 33
Fig:4.3 Fredkin schematic diagram 34
Fig:4.4 Fedkin block diagram 34

ii
Fig:4.5 Counter with SG gate 35
Fig:4.6 Counter block diagram 35
Fig:4.7 Counter output waveform 36

iii
 LIST OF TABLES

Table No. Table Name Page No.

Table : 1.1 Truth tables of conventional XOR and reversible XOR gates 3
Table 1. 2 Truth table of Feynman gate 5
Table1. 3 Truth table of Toffoli gate 7
Table 1. 4 Truth table of Fredkin gate 8
Table 1.5 Truth table of Peres gate 9
Table:2.1 Truth table of up-down counter 25
Table:3.1 Positive Edge Triggered T Flip Flop 28
Table:3.2 Comparison of Different T Flip Flops with only Q Output 29

iv
 LIST OF ACRONYMS

S.NO ACRONYM FULL FORM

1 MOSFET Metal-Oxide Semiconductor Field Effect Transistor

2 VLSI Very Large Scale Integration
3 ALU Arithmetic Logic Unit
4 CNOT Controlled NOT gate
5. CMOS Complementary Metal-Oxide Semiconductor
6. QMUX Quantum Multiplexers
7 QDe-MUX Quantum Demultiplexers
8 ASICs Application Specific Integrated Circuits
9. QC Quantum Cost
10 DSP Digital Signal Processing
11 FPGA Field Programmable Gate Arrays
12. CPLD Complex Programmable Logic Device
13. VHDL Verilog Hardware Description Language
14 Xilinx ISE Xilinx Integrated Synthesis Environment
15 RTL Register Transfer Level

v
 CHAPTER-1

INTRODUCTION TO REVERSIBLE GATES

For the past 50 years the semiconductor technology has marched at the pace as
expressed in Moore‟s law. Transistor scaling associated with doubling the number of
transistors every two years has been and continues to be the unique feature of the
technology. In the process as transistors became smaller they could also be switched
from OFF to ON state at faster rates and also became cheaper to manufacture. The past
editions of technology concentrated on forecasting the rate of transistor scaling and how
transistor density and performance affected the evolution of integrated circuits. Through
the years nobody paid attention to the fact that power consumption of integrated circuits
kept on increasing with every new technology generation since motto of the
semiconductor industry was : “Performance at any cost!”. This approach came to an end
at the beginning of the last decade when fundamental thermal limits were reached by
someICs.

Minimal power consumption of a transistor has become the main requirement for
the future technology.

1.1 PROBLEM SPECIFICATION

Reversible computing is the path to future computing technologies and will

become mandatory because of the necessity to decrease power consumption. The main
drawback of irreversible hardware computation is energy dissipation due to information
loss. As a fundamental contribution in [2], Landauer has demonstrated that high
technology circuits and systems constructed using irreversible hardware results in
energy dissipation due to information loss. According to Landauer‟sprinciple, the loss of
one bit of information dissipates K*T*ln2 joules of energy where K is the Boltzmann‟s
constant (2.3807×20-23 JK-2) and T is the absolute temperatureat which the operation is
performed. At room temperature (3000 K), KT ln2 is approximately 2.8×20-22 joules.
The heat generated due to the loss of one bit of information is very small but non-
negligible at room temperature, but when the number of bits are more as in the case of
high speed computational systems, the heat dissipated by them will be so large that it
affects the performance and results in the reduction of life time of the components.

1
 As the Moore‟s law [65, 66] continues to hold, the processing power doubles
every 28 months. If the current trend continues, there will be intolerable amount of heat
generated by computer systems. Definitely, one should be looking for revolutionary
technologies that permit extremely low power consumption and heat dissipation in
computing.

Later, Bennett [2] showed that K*T*ln2 joules of energy dissipation in a circuit
would not occur, if a computation is carried out from reversible circuit, since the amount
of energy dissipated in a system bears a direct relationship to the number of bits erased
during computation.

1.2 REVERSIBLE CIRCUITS

Reversible circuits are those circuits that do not lose information during
computation and reversible computation in a system can be performed only when the
system comprises of reversible logic gates. Reversible logic circuits have the same
number of inputs and outputs, and have one-to-one mapping between vectors of inputs
and outputs; thus the vector of input states can be always reconstructed from the vector
of output states and vice versa. Thus an N × N (N inputs and N outputs) reversible
circuit can be representedas

Iv= I2, I2, I3,I4,...................IN (2.2)

Ov = O2, O2, O3,O4,..........ON (2.2)

where Iv and Ov represent input and output vectors respectively. The block diagram of
reversible circuit is shown in figure 2.2.

Figure 1.1: Block diagram of Reversible circuit

Classical logic gates are irreversible since input vector states cannot be uniquely
reconstructed from the output vector states.
2
 (a) ConventionalXORgate (b) Reversible XOR gate

Figure 1.2: Conventional XOR and Reversible XORgate

As an example, considering conventional irreversible XOR gate as shown in

figure 2. 2 (a), it is obvious from the truth table illustrated in table 1.1 (a) that a unique
input vector cannot be constructed from the output vector. This is because for
output„0‟,therearetwoinputvectorsAB=(00,22)thatgiverisetoit.Considering figure 1.2(b), a
reversible XOR gate, it is evident from the truth table illustrated in table 1.1(b) that a
unique input vector can be constructed for every outputvector.

Table : 1.1 Truth tables of conventional XOR and reversible XOR gates

A B Q A B P Q

0 0 0 0 0 0 0

0 2 2 0 2 0 2

2 0 2 2 0 2 2

2 2 0 2 2 2 0

(a) XORgate (b) R-XORgate

Consequently, a computation is reversible, if it is always possible to uniquely

recover the input, given the output. Each gate can be made reversible by adding some
additional input and output wires if necessary. The synthesis of reversible logic differs
significantly from traditional irreversible logic approaches.

Two constraints for reversible logic synthesis are:

(i) Fan-out is not allowed (i.e., fan-out = 2).

(ii) Feedback is notallowed

3
 Fan-out is not allowed in reversible logic since fan-out (one to many) structure
itself is not reversible. This results in high degree of interdependence among gates. Also
feedbacks from gate outputs to inputs are not allowed.

1.3 NOMENCLATURE

1. 3. 1 Gate Count

Gate count is the total number of reversible gates in a circuit. It is a quantitative

measure of quality of a circuit and often referred to as circuit cost. It is not unique. If
allowed to introduce a new gate or a complex gate library then the gate count can be
reducedconsiderably.

1. 3. 2 Garbage Outputs

Garbage outputs are the additional outputs that make a function reversible and
are not used for further computations. Garbage outputs increase the width of the circuit.
It is not possible to avoid the garbage outputs as these are very essential to achieve the
reversibility. Since the garbage bits are not used for further computation, large numbers
of garbage bits are not desirable in a reversible circuit.

1. 3. 3 Ancilla Inputs (Constant Inputs)

Ancilla inputs or constant inputs refer to the number of inputs, set at a constant
value logic „0‟ or logic „2‟ to get the required output. The relation between garbage bits
and constant inputs is the algebraic sum of inputs and constant inputs is equal to the
algebraic sum of outputs and garbage outputs. Mathematically,

Inputs + Constant inputs = Outputs +Garbageoutputs (2. 3)

1. 3. 4 Quantum Cost

Quantum cost refers to the number of elementary quantum gates required for the
construction of reversible function. Using elementary quantum or primitive gates any
reversible gate can be constructed. Therefore the number of quantum gates used is
referred to as quantum cost.

4
1. 3. 5 Balanced Circuits

Balanced circuits are circuits for which each output value appears a number of
times which is equal to the number of times that each of the other output values appears.
For example, in balanced binary logic the circuit has half of minterms with value 2.
While in balanced ternary logic one third of minterms have value 0, one third have value
2 and one third have value2.

1. 3. 6 Conservative Circuits

Conservative circuits are circuits that have the same number of values in inputs
and outputs, i.e. a conservative circuit preserves the number of logic values in all
combinations.

1. 3. 7 Transistor Cost

Transistor Cost is the total number of transistors required to implement a

reversible logic circuit if CMOS technology is adapted for the design.

1.4 BASIC REVERSIBLE LOGIC GATES

1.4. 1 Feynman Gate

Feynman gate [3] is a 2x2 gate, also called as controlled-not (C-NOT) gate.

The Feynman gate is shown in figure 2. 3. The outputs of Feynman gate are:

P=A

Q = A⊕B

A B P Q
0 0 0 0
0 2 0 2
2 0 2 2
2 2 2 0

Table 1. 2: Truth table of Feynman gate

5
 Figure 1.3: Feynman gate

where A and B are the inputs, while P and Q are the outputs. The truth table of the
Feynman gate is shown in table 2. 2. When A = 0 then Q = B, and when A = 2 then Q

= this is why it is called controlled not gate. With B = 0 Feynman gate is used as a fan-
out gate or a copying gate (P = A and Q = A). This feature is illustrated in the figure 2. 4
(a). Further, it can be also be used for generating the complement of a signal when B = 2
which is as shown in figure 2. 4 (b).

(a) Directoutput (b) Complemented output

Figure 1. 4: Application of Feynman gate

1. 4. 2 Toffoli Gate

The 3x3 Toffoli gate [4] is also known as two-through reversible gate or
controlled-controlled-not gate. It is described by the following equations:

P = A, Q = B,

R = AB⊕C.

The Toffoli gate is shown in figure 2. 5 and table 2. 3 represents truth table of
Toffoli gate.

6
Table1. 3: Truth table of Toffoli gate

A B C P Q R
0 0 0 0 0 0
0 0 2 0 0 2
0 2 0 0 2 0
0 2 2 0 2 2
2 0 0 2 0 0
2 0 2 2 0 2
2 2 0 2 2 2
2 2 2 2 2 0

Figure 1. 5: Toffoli gate

From the truth table, it can be seen that when A and B are equal to one then R= ,
this is why this gate is called controlled-controlled-not, because it has two control inputs
A and B to invert the third input C. Toffoli gate is an example of two through gates,
because two of its inputs are given to the output. This is shown in figure 1. 6.

Figure 1.6: Representation of Toffoli gate

7
1.4. 3 Fredkin Gate

The 3x3 Fredkin gate [5] is also called controlled SWAP (CSWAP). It is
described by the following equations:

P=A P=A

Q = C if A = 2 else B or Q= B +AC

R = B if A = 2 else C R =AB+ C

Table1. 4:Truth table of Fredkin gate

A B C P Q R
0 0 0 0 0 0
0 0 2 0 0 2
0 2 0 0 2 0
0 2 2 0 2 2
2 0 0 2 0 0
2 0 2 2 2 0
2 2 0 2 0 2
2 2 2 2 2 2

Figure 1. 7: Block diagram of Fredkin gate

8
Figure 1. 7 shows the block diagram of the Fredkin gate, while its truth table is shown in
table 1. 4. In terms of classical logic this gate is just two multiplexers in a flipped
(permuted) way from the same control input A. This is illustrated in figure 1. 8 (a) and
its simplified diagram is shown in figure 1. 8 (b). It permutes the data inputs of its two
multiplexers under control of the control input of these multiplexers. This control input
is also an output from the Fredkin gate. Fredkin gates are called one through gates,
which means that gates in which one input variable is also anoutput

(a) Fredkin gate usingtwo multiplexers (b) Simplifieddiagram

Figure 1. 8: Representation of Fredkin gate

1. 4. 4 Peres Gate

The Peres gate [6] is a 3-input, 3- output (3x3) reversible gate. The equations are
described by:

P = A,

Q = A⊕B, R = AB⊕C,

where A, B, C are the inputs and P, Q, R are the outputs respectively. Figure 2. 9 shows
the Peres gate and truth table of Peres gate is shown in table 2. 5.

Table 1. 5: Truth table of Peres gate

A B C P Q R
0 0 0 0 0 0
0 0 2 0 0 2
0 2 0 0 2 0
0 2 2 0 2 2
2 0 0 2 2 0
2 0 2 2 2 2
2 2 0 2 0 2
2 2 2 2 0 0

9
 Figure 1. 9: Peres gate

The Toffoli gate, the Peres gate and the Fredkin gate are the three standard 3x3
reversible gates used for designing the reversible logic circuits and Feynman gate is
used for avoiding the fan-outproblem

1. 5 THE ELIMINATION OF GARBAGE BITS IN REVERSIBLE

CIRCUITS

In reversible logic circuits, where number of inputs is equal to the number of

outputs, reversibility of computation has been achieved at the cost of introducing the
constant inputs and garbage outputs (information that are not needed for the
computation) [7, 8]. To eliminate the garbage outputs, for avoiding energy loss due to
garbage accumulation, it is important to construct the inverse of the circuit. This is
achieved by taking the outputs of the reversible circuit and producing “inverse” inputs
from them. This is important especially in quantum computing where garbage is not
allowed. Figure 1.9shows reversible circuit called “forward” (the block on the left), and
its reversible inverse, called “mirror”, (the block on the right).

Figure 1.10: The reversible circuit and its reversible mirror to eliminate garbage bits

10
 Each reversible gate realizes a reversible function. That is, for each input pattern
a unique output pattern, i.e. a one-to-one mapping, exists. Thus, calculating the inverse
of the function F for an output pattern is essentially the same operation as propagating
this pattern backwards through the circuit. Hence, if the cascade of n reversible gates G
= g0 g2 … gn−2 realizes a reversible function F, then the reverse cascade G=gn−
2gn−2…g0realizestheinversefunctionF−2.Theforwardcircuitis composed by using
reversible gates, while the mirror circuit is composed by replacing each gate in the
forward circuit by its inverse. It has been shown [9] that each of Fredkin, Toffoli, and
Feynman gates is the inverse of itself. To measure the state of the hidden functions
within the total network of the forward reversible part and the inverse reversible part,
the “spy” circuit is used. The “spy” circuit is Feynman gate which is used as a copier by
setting the value of the control input to value„0‟.The disadvantage of this approach of
eliminating garbage signals is that it causes the duplication of the circuit‟s delay and the
count of gates.

1.6 CHALLENGES AND MOTIVATION

The real challenge in system design today and also in the future is to design
reliable systems that consume as little power as possible and in which the signals are
processed and transmitted with very high signal integrity. Logically reversible devices
have to be used to reduce (theoretically eliminate) power consumption. Since fan-out is
not permitted, and assuming an appropriate technology, then a reversible logic circuit
can realize the inverse specification simply by applying the gates in the reverse order.
Hence, synthesis can be carried out from the inputs toward the outputs or from the
outputs toward the inputs.

1.7 MOTIVATION

The motivation for reversible computing comes from the fact that these models
are information preserving. Reversible logic can be useful to design non- dissipative
circuits if the physical implementation of the logic is also physically reversible. One of
the primary motivations for adopting reversible logic lies in the fact that it can provide a
logic design methodology for designing ultra-low power circuits beyond K*T*ln2 limit
for those emerging nanotechnologies in which the energy dissipated due to information
destruction will be a significant factor of the overall heat dissipation.

11
 Most gates used in digital design are not reversible. Of the commonly used
gates, only the NOT gate is reversible, and the gates like AND, OR and EX-OR gates do
not perform reversible operations. A set of reversible gates is needed to design
reversible circuits. Our main motivation to pursue further research in design, synthesis
and test of reversible logic circuits is owing to their wide spread applications in
emerging technologies. In reversible logic based circuit design, parameters such as
number of reversible gates, ancilla inputs, garbage outputs, quantum cost and delay are
radically different from the traditional parameters suchas speed, power and chip area
that are used in conventional computing. This multitude of parameters need be
optimized [64] in order to build effective reversible logic based circuits. This warrants
extensive research towards developing new design and synthesis methods for realization
of reversible circuits and a synthesis framework in which multiple parameters can be
optimized.

Design and synthesis of reversible logic circuits is quite different from that of
conventional, irreversible logic as fan-out and feedback are not allowed in reversible
logic circuits. The designed circuits need to be optimized which is a challenging task in
reversible logic.

The objectives of this thesis are statedas follows: To redesign the reversible
logiccircuit

To simulate the reversiblelogiccircuit To synthesize the reversible logic circuit

1.8 DESIGN METHODOLOGY

The design methodology is as described in the figure 2. 22. The design flow is
divided into the following steps:

· The designer specifies the design requirement such as the parameters to optimize
(number of gates, number of ancilla inputs, garbage outputs, quantum cost,
delay, etc.) along with the designscheme.
· Create a library of all the reversible gates coded in HDL [53] such as the Fredkin
gate, the Toffoli gate, the Peres gate, the Feynman gate etc. If a new reversible
gate is proposed in the literature, it can be easily added to thelibrary.
· The HDL code of the desired design is generated. The test benches needs to
verify the functional correctness of the design are also generated.

12
 · The functional verification of HDL codes are done using standard HDL
simulators such as ModelSim/ ISim simulators. The waveforms are to
begenerated.
Synthesis of the HDL code is generated by the Xilinx XST synthesizer/Leonardo
Spectrum synthesizer from Mentor Graphics. The RTL schematic of the design is
generated by the synthesizer with various reports such as delay, number of slices
occupied and power dissipation.

Figure 1,11: Design flow of reversible logic circuits

References to related work is listed in Bibliography section and Papers published

are listed in Publication section.

Appendix A contains the typical snapshots of 2 to 2 multiplexer. This section

shows the design flow of front-end to back-end design. Appendix B presents the HDL
descriptions of few reversible systems. Test Benches to test the functionality of the
systems are also presented in thissection.

13
1.9 APPILICATIONS

Reversible computing may have applications in computer security and

transaction processing, but the main Long-term benefit will be felt very well in those
areas which require high energy efficiency, speed and performance .it include the area
like

· Low power CMOS

· Quantum computer.
· Nanotechnology.
· Optical computing.
· DNA computing.
· Computer graphics.
· Communication.
· Design of low power arithmetic and data path for digital signal processing
(DSP).
· Field Programmable Gate Arrays (FPGAs) in CMOS technology.

The potential application areas of reversible computing include the following

· Nano computing
· Bio Molecular Computations
· Laptop/Handheld/Wearable Computers
· Spacecraft
· Implanted Medical Devices
· Wallet “smart cards”
· “ Smart tags” on inventory
· Prominent application of reversible logic lies in quantum computers.
· Quantum gates perform an elementary unitary operation on one, two or more
two–state quantum systems called qubits.
· Any unitary operation is reversible and hence quantum networks also.
· Quantum networks effecting elementary arithmetic operations cannot be directly
deduced from their classical Boolean counterparts (classical logic gates such as
AND or OR are clearly irreversible).

14
1.10 OUTLINE OF THE REPORT

Reversible logic gates form the building blocks of quantum computing. Efficient
and lossless digital circuits are demand of current electronic devices. Reversible logic
concept is the result of this need of improved efficiency and performance of digital
systems. In this, we have proposed an approach to design optimized reversible
realization of 8-bit adder subtractor circuit. The optimization is achieved on some
selected factors such as number of gates, garbage outputs and quantum cost as compared
to the existing designs. This proposed adder-subtractor circuit is designed using only 8
gates, generates 26 garbage outputs and total quantum cost of the circuit is equal to 56.
This adder-subtractor circuit may be utilized in various computational devices for
designing low power loss electronic systems.

15
 CHAPTER 2

LITERATURE REVIEW
2.1 THEORETICAL BACK GROUND
2.1.1 Irreversibility and Heat Generation in the Computing Process, IBM Journal
of Research and Development: It is argued that computing machines inevitably
involve devices which perform logical functions that do not have a single-valued
inverse. This logical irreversibility is associated with physical irreversibility and
requires a minimal heat generation, per machine cycle, typically of the order of kT for
each irreversible function. This dissipation serves the purpose of standardizing signals
and making them independent of their exact logical history. Two simple, but
representative, models of bistable devices are subjected to a more detailed analysis of
switching kinetics to yield the relationship between speed and energy dissipation, and to
estimate the effects of errors induced by thermal fluctuations.

2.1.2 Logical reversibility of Computation, IBM Journal of Research and

Development: The usual general-purpose computing automaton (e.g., a Turing
machine) is logically irreversible—its transition function lacks a single-valued inverse.
Here it is shown that such machines may be made logically reversible at every step,
while retaining their simplicity and their ability to do general computations. This result
is of great physical interest because it makes plausible the existence of
thermodynamically reversible computers which could perform useful computations at
useful speed while dissipating considerably less than kT of energy per logical step. In
the first stage of its computation the logically reversible automaton parallels the
corresponding irreversible automaton, except that it saves all intermediate results,
thereby avoiding the irreversible operation of erasure. The second stage consists of
printing out the desired output. The third stage then reversibly disposes of all the
undesired intermediate results by retracing the steps of the first stage in backward order
(a process which is only possible because the first stage has been carried out reversibly),
thereby restoring the machine (except for the now-written output tape) to its original
condition. The final machine configuration thus contains the desired output and a
reconstructed copy of the input, but no other undesired data.

16
 The foregoing results are demonstrated explicitly using a type of three-tape
Turing machine. The biosynthesis of messenger RNA is discussed as a physical example
of reversible computation.

2.1.3. Digital Electronics. Principles, Devices and Applications :The fundamentals

and implementation of digital electronics are essential to understanding the design and
working of consumer/industrial electronics, communications, embedded systems,
computers, security and military equipment. Devices used in applications such as these
are constantly decreasing in size and employing more complex technology. It is
therefore essential for engineers and students to understand the fundamentals,
implementation and application principles of digital electronics, devices and integrated
circuits. This is so that they can use the most appropriate and effective technique to suit
their technical need.

2.2 EXISTED METHOD

In 2020, V. Ganesh Raja has proposed the Design Approach of specific

Sequential circuits using Reversible gates [1]. They designed a D Flipflop, JK Flipflop,
T Flipflop, and linear feedback shift register and priority encoder using reversible logic
gates. They intend to decrease delay, power consumption and garbage outputs. They
proposed priority encoder, it shows great improvement than other designs. In upcoming,
they want to realize reversible 4 and 8 bit LFSR and PROMs.

In 2018, C. Venkata sudhakar has designed and Synthesis of Combinational

Circuits using Reversible logic [2]. They designed combinational circuits like decoders,
comparator, full adder and multiplexer with reversible logic gates are fredkin gate,
CNOT, Peres gate and R-I gate [2]. They designed 3 to 8 decoder using 2 to4 decoder
followed by 4 R-I gates [2] and also designed the 4 to 16 decoder using 3 to 8 decoder
followed by 8 RI gates with quantum cost 56.

In 2018, Harish Naik K. P has proposed design of Asynchronous Counter using

Reversible logic gates [4]. They designed Reversible D-latch and four bit asynchronous
counter using reversible T Flipflop. Two SG [4] gates and one Feynman gate[2] are used
for design of T Flip-flop with less garbage outputs and number of gates as 3 and 3. 4-bit
asynchronous counter[4] are proposed with reversible T Flipflop contains Reversible
Gates are 15, Constant Inputs are 11 and produce Garbage Outputs is 12

17
COUNTERS

A counter driven by clock can be used to count the number of pulses. Since
clock pulses occur at known intervals, the counter can be used as an instrument for
measuring time and therefore period or frequency.

There are basically two different types of counters

1. Asynchronous counters

2. Synchronous counters

The ripple counter is simple and straightforward in operation and construction

usuallyrequiresaminimumhardware.Itdoes,howeverithasspeedlimitations.Eachflipistrigg
ered by the previous flip flop, and thus the counter has a cumulative settling time.
Counterssuc has these a recalled serial, orasynchronous.

An increase in speed of operation can be achieved by use of a parallel or

synchronous counter. Here, every flip-flop is triggered by the clock (in synchronism),
and thus settling time is simply equal to the delay time of a single flip-flop. The increase
in speed is usually obtained at the price of increased hardware.

Serial and parallel counters are used in combination to compromise between

speed of operation and hardware count. Serial, parallel, or combination counters can be
designed such that each clock transition advances the contents of the counter by one; it
is then operating in a count-up mode. The opposite is also possible; the counter then
operates in the count-down mode.

ASYNCHRONOUSCOUNTERS

A binary ripple counter can be constructed using clocked JK flip-flops. Figure

1showthree negative edge-triggered, JK flip-flops connected in cascade. The system
clock, a square wave, drives flip-flop A. The output of A drives B, and the output of B
drives flip-flop C. Allthe] and K inputs are tied to +VCC. This means that each flip-flop
will change state (toggle) with a negative transition at its clock input.

18
 Fig:2.1 Asynchronous Counter[Up mode]

When the output of a flip-flop is used as the clock input for the next flip-flop, we
call the counter a ripple counter, or asynchronous counter. The A flip-flop must change
state before it can trigger the Bflip-flop, and the Bflip-floph as to change state before it
can trigger the C flip-flop. The triggers move through the flip-flops like a ripple in
water. Because of this, the overall propagation delay time is the sum of the individual
delays. For instance, ifeach flip-flop in this three-flip-flop counter has a propagation
delay time of 10 ns, the overall propagation delay time for the counter is 30ns.

The waveforms given in Fig. 1(b) show the action of the counter as the clock
runs. Let's assume that the flip-flops are all initially reset to produce O outputs. If
weconsiderA to be the least-significant bit(LSB) and C the most-significant bit (MSB),
we can say the contents of the counter is CEA = 000.Every time there is a clock NT,
flip-flop A will change state. This is indicated by the small arrows () on the time line.
Thus at point a on the timeline, A goes high, at point b it goes back low, at c it goes back
high, and so on. The wave form at the output of flip-flopA is one-half the clock
frequency.

Since A acts as the clock for B, each time the waveform at A goes low, flip-flop
B willtoggle. Thus at point b on the time line, B goes high; it then goes low at point d
and toggles back high again at point f. The wave format the output of flip-flopBisone-
half the frequencyofAand one-fourth the clock frequency.

19
 Since B acts as the clock for C, each time the waveform at B goes low, flip-flop
C will toggle. Thus C goes high at point don the time line and goes back low again at
point h. The frequency of the waveform at C is one-half that at B, but it is only one-
eighth the clock frequency.

The output condition of the flip-flops is a binary number equivalent to the

number of clock NTs that have occurred. The counter content advances one count with
each clock NT in a "straight binary progression” that is summarized in the truth table in
Fig. 1(c).Becau seeach output condition shown in the truth table is the binary equivalent
of the number of clock NTs, the three cascaded flip-flops in Fig. 1 comprises a 3-bit
binary ripple counter. This counter cans be used to count the number of clock transitions
up to a maximum of seven. The counter begins at count 000 and advances one count for
each clock transition until it reaches count 111. At this point it resets back to 000 and
begins the count cycle all over again. Thus this ripple counter is operating in a count-up
mode.

Since a binary ripple counter counts in a straight binary sequence, it is easy to

seeth at a counter having n flip-flops will have 2noutput conditions. For instance, the
three-flip-flop counter just discussed has 23 = 8output conditions (000 through 111).
Five flip-flops would have 25=32output conditions(00000through11111), and soon.

The largest binary number that can be represented by n cascaded flip-flops has
adecimal equivalent of 2n- 1. For example, the three-flip-flop counter reaches a
maximum decimal number of 23- 1.The maximum decimal number for five flip-flops is
25 - l = 31, while six flip-flops haveamaximumcountof63.

A three-flip-flop counter is often referred to as a modulus-8 (or mod-8) counter

sinceit has eight states. Similarly, a four-flip-flop counter is a mod-16 counter, and a six-
flip-flop counter is a mod-64 counter. The modulus of a counter is the total number of
states through which the counter can progress.

20
Adown counter

In down counter[fig.2], the system clock is used at the clock input to flip-flop A,
but the complement ofA,A, is used to driveflipflop B,like wise; B is used to drive flip-
flop C.

Fig:2.2 Asynchronous Counter[Down mode]

Flip-flop A simply toggles with each negative clock transition as before. But flip-
flop B will toggle each time A goes high! Notice that each time A goes high, A goes low,
and it isthis negative transition on A that triggers B. On the timeline, B toggles at
pointsa, c, e, g and i. Similarly, flip-flop C is triggered by B and so C will toggle each
time B goes high. Thus Ctoggles high at point a on the time line, toggles back low at
point e and goes back high again at pointi.

The counter contents become ABC= 111 at point a on the time line, change to
110 atpoint b, and change to101 at point c. Notice that the counter contents are reduced
by one count with each clock transition! In other words, the counter is operating in a
count-down mode. The results are summarized in the truth table in Fig.2[c]. This is still
a mod-8 counter, since it has eight discrete states, but it is connected as adown counter.

3-bitasynchronous up-down counter

A 3-bit asynchronous up-down counter that counts in a straight binary sequence
is shown inFig.1.3. It is simply a combination of the two counters up and down counter.
For this counter to progress through a count-up sequence, it is necessary to trigger each
flip-flop with the true side of the previous flip-flop (as opposed to the complement
side.).
21
 If the count-down control line is low and the count-up control line high, this will
be the case, and the counter will have count- up wave forms suchasthoseshowninFig.1.3.

Fig:1.3 A3-bitasynchronousup-downcounter

On the other hand, if count-down is high and count-up is low, each flip-flop will
be triggered from the complement side of the previous flip-flop. The counter will then
be in a count-down mode and will progress through the waveforms as shown in Fig.1.3.

SYNCHRONOUS[PARALLEL]COUNTERS

The ripple counter is the simplest to build, but there is a limit to its highest
operating frequency. Each flip-flop has a delay time. In a ripple counter these delay
times are additive, and the total "settling" time for the counter is approximately the
delay time times the total number of flip-flops. Furthermore, there is the possibility of
glitches occurring at the output of decoding gates used with a ripple counter. The first
problem fully and the second problem, to some extent can be overcome by the use of a
synchronous parallel counter. The main difference here is that every flip-flop is
triggered in synchronism with the clock.

Fig.2.4:A3-bit synchronous counter

22
 The construction of one type of parallel binary counter is shown in Fig.4, along
withthetruthtableandthewaveformsforthenaturalcountsequence.Sinceeachstatecorrespon
ds to an equivalent binary number (or count). The J and K inputs of each flip-flopare
high; therefore each flip-flop will toggle with any clock NT at its clock input. AND
gates are used to gate every second clock to flip-flop B, every fourth clock to flip-flop
C, and so on. This logic configuration is often referred to as "steering logic" since the
clock pulses are gate do steered to each individual flip-flop.

The clock is applied directly to flip-flop A. Since the JK flip-flop used responds
to a negative transition at the clock input and toggles when both the J and K inputs are
high, flip-flop A will change state with each clock NT. Whenever A is high, AND gate X
is enabled and a clock pulse is passed through the gate to the clock input of flip-flop B.
Thus B changes state with every other clock NT at point’sb,d, f and h on the timeline.

Since, there is an additional AND gate delay for the clock at B flip-flop in
comparison to A flip-flop, it is not a parallel counter in a strict sense of the term. Since
AND gate Y is enabled and will transmit the clock to flip-flop C only when both A and B
are high, flip-flop C changes state with every fourth clock NT at points d and h on the
timeline. Examination of the waveforms and the truth table shows that this counter
progresses upward in a natural binary sequence from count 000 up to count111, advance
in gone count with each clock NT; This is a mod-8parallel or synchronous binary
counter operating in the count- up mode.

Aparallelup-down counter

Fig.2.5:A4-Bit Synchronous up-Down Counter

23
 Figure 2.5 shows a 4 bit parallel up-down counter. In any parallel counter, the
time at which any flip-flop changes state is determined by the states of all previous flip
flops in the counter. In the count-up mode, a flip-flop must toggle every time all
previous flip-flops areina1state,and the clock makes a transition.

In the count-down mode, flip-flop toggles must occur when all prior flip-flops
are in a O state. The counter in Fig.5 is a synchronous 4-bit up-down counter. To
operate in the count-up mode, the system clock is applied at the count-up input, while
the count-down input is held low. To operate in the countdown mode, the system clock
is applied at the count-down in put while holding the count-up in put low.

Holding the count-down input low (at ground) will disable AND gates Y1, Y2,
andY3.The clock applied at count-up will then go directly into flip-flop A and will be
steered into the other flip-flops by AND gates X1,X2, and X3. This counter will then
function exactly as parallel counter. The only difference here is that this is a mod-
16counter that advances one count with each clock NT, beginning with 0000 and ending
with1111.The correct wave forms are shown in Fig.2.6.

Fig:2.6 Count Down Waveforms

If the count-up line is held low, the upper AND gates X1, X2, and X3 are
disabled. The clock applied at input count-down will go directly into flip-flop A and be
steered into the following flip-flops by AND gatesY1, Y2, and Y3.Flip-flop A will toggle
each time there is a clock NT as shown in Fig. 5[c]. Each time A is high, AND gate Y1
will be enabled and the clock NT will toggle flip-flop Bat points a, c, e, g, and so on.
Whenever both A and B are high, AND gate Y2 is enabled, and thus a clock will be
steered into flip-flop Cat points a, e, i, m, and q. Similarly, AND gate Y3 will steer a
clock into flip-flop D only when A, B, and C are all high. Thus flip-flop D will toggle at
points aand i on the time line. The waveforms in Fig.
24
 Table:2.1 Truth table of up-down counter
AMod-5Counter

Fig.2.7:Mod5 Counter

The three- flip- flop counter shown in Fig.1.7 has a S natural count of 8,butitis
connected in such a way that it will skip over three counts. It will, in fact, advance one
count at a time, through has tract binary sequence, beginning with 000 and ending
with100; therefore, it is amod-5counter. The wave forms show that flip-flop A changes
state each time the clock goes negative, except during the transition from count 4 to
count 0. Thus, flip-flop A should be triggered by the clock and must have an inhibit
during count 4-that is, some signal must be provided during the transition from count 4

25
to count 0. Notice that C is high during all counts except count 4.

If C is connected to the J input of flip-flop A, we will have the desired inhibit

signal. This is true since the J and K inputs to flip-flop Aare both true for all counts
except count4; thus the flip-flop triggers each time the clock goes negative. However,
during count 4, theJ side is low and the next time the clock goes negative the flip-flop
will be prevented from being set. The connections which cause flip-flop A to progress
through the desired sequence are shown inFig.1.7[a].

The7490 [Decade Counter]

The 54/7490A is a TTL MSI decade counter. Its logic diagram, truth table, and
pin out are given in Fig.7.A careful examination will shows that flip-flops QB, Qc, and
QD form amod-5 counter. The flip-flop QD in the '90A is an RS flip-flop that has a
direct connection from its Q output back to its R input. The net result in this case is that
QD behaves exactly like a JKflip-flop.

Fig:2.8 IC54/7490A [ Decade Counter]

26
 If the system clock is applied at input A and QA is connected to input B, we have
a true binary decade counter. On the other hand, if the system clock is applied at input B
and Q Disconnected to input A, we have the biquinary counter.Fig7(b) shows truth table
andfig.7(c)shows pindiagramofIC7490

27
 CHAPTER 3

PROPOSED A SYNCHRONOUS COUNTER

T-FLIP FLOP

A flip flop has two stable states and can be used as a one bit memory device that
stores either 0 or 1. This section illustrates the master slave T flip flop construction. The
positive edge triggered T flip flop truth table is given in Table I. The reversible clocked
T flip flop design is shown in fig 2. And the block diagram of asynchronous clocked T
flip flop can be represented as black box as shown in fig.3.The reversible design of
clocked T flip flop consists of one Feynman gate and two SG gates.It has three constant
inputs and five garbage outputs for designing asynchronous counter.

Table:3.1 Positive Edge Triggered T Flip Flop

Positive edge triggered reversible Asynchronous T- flip flop using SGG gate

Fig:3.1Block Diagram

28
Table:3.2 Comparison of Different T Flip Flops with only Q Output

Counters are a very commonly used functional elements in digital circuits.Also

counters are either manufactured apart of integrated circuits or incorporated as parts of
larger integrated circuits. A counter circuit is basically constructed of a number of flip
flops connected one after another in cascade such that a counting operation is performed
by the combined output. Asynchronous counters obtained its name from the point that
the output of the counter is not directly dependent on the applied clock.In asynchronous
or ripple counter, a source for triggering for next flip flop is served by the output
transition of previous flip flop In other words, the clocking signal is provided only to
one flip flop and the remaining flip flops clock pins are derived by the output of the
previous flip flop.

Proposed 4-bit Asynchronous Up Counter The typical circuit diagram of

asynchronous 4 bit up counter and it’s truth table is shown as under in Fig.4[12].

Fig:3.2 4-bit asynchronous Up- Counter

29
 The reversible T flip flop,has the complemented output Q produced using
Feynman gate with its second input as 1.The subsequent flip flops are triggered by the
inverted Q output and the Upcounter operation is performed by the reversible
design.[13]. Each reversible T flip flop contains 3 reversible gates(2 SG gates and 1
Feynman gate), 3 constant inputs(0,1 and 0) and 5 garbage outputs.Hence the proposed
reversible asynchronous Up counter design comprises of 15 reversible gates,15 constant
inputs and produces 20 garbage outputs.

Fig:3.3 Proposed 4-bit Reversible Asynchronous Up Counter

Proposed 4-bit Asynchronous Down Counter The 4-bit reversible asynchronous

down counter is shown below in fig.6. The fan out of output Q is produced using
Feynman gate with the second input as 0 at the output of each reversible T flip flop. The
subsequent flip flops are triggered by the Q output and the Down-counter operation is
performed by the reversible design. The proposed reversible asynchronous counter
design consists of 15 reversible gates, 15 constant inputs and 20 garbage outputs.

Proposed Asynchronous Up/Down Counter The proposed design of reversible

asynchronous 4-bit Up/Down counter is shown in fig.3.3 . The Up/Down control input
signal is used to perform Up/Down operation of this reversible design.

30
 When Proposed 4-bit Asynchronous Down Counter this control signal is 1 then
the reversible design performs Up counter operation. When this control signal is 0 then
the reversible design performs Down counter operation. The Up/Down counter
reversible design consists of 15 reversible gates, 15 constant inputs and 20 garbage
outputs.

Fig:3.4 Simulated waveform of t flip flop

Fig:3.5 Asynchronous Counter counting Up

31
 Fig:3.6 Asynchronous Counter counting Down

Fig:3.7 Asynchronous Counter counting both Up and Down

32
 CHAPTER 4

RESULTS

Fig:4.1 SG gate Schematic

Fig:4.2 SG gate block diagram

33
Fig:4.3 Fredkin schematic diagram

Fig:4.4 Fedkin block diagram

34
Fig:4.5 Counter with SG gate

Fig:4.6 Counter block diagram

35
Fig:4.7 Counter output waveform

36
 CHAPTER 5

CONCLUSION AND FUTURE SCOPE

5.1 CONCLUSION

The key contribution of this paper were carried out for the reversible realization
of T flip flop and asynchronous counter using proposed reversible SG gate and Feynman
gate. The proposed asynchronous counter designs find its use in building reversible
processor, reversible ALU, etc. Also in quantum computers, this work plays a
significant step towards making more complex reversible sequential circuits so as to
minimize the power consumption and build more improved applications. Asynchronous
counter are designed with reversible logic gates which gives low power consumption,
less delay and less

5.2 FUTURE SCOPE

In future work, could be to develop efficient reversible counters and controller

circuits to minimize the power consumption and area

37
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39